WO2006013698A1 - Nitride semiconductor device and method for fabricating same - Google Patents

Nitride semiconductor device and method for fabricating same Download PDF

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WO2006013698A1
WO2006013698A1 PCT/JP2005/012663 JP2005012663W WO2006013698A1 WO 2006013698 A1 WO2006013698 A1 WO 2006013698A1 JP 2005012663 W JP2005012663 W JP 2005012663W WO 2006013698 A1 WO2006013698 A1 WO 2006013698A1
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layer
semiconductor device
nitride semiconductor
polarity
semiconductor
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PCT/JP2005/012663
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French (fr)
Japanese (ja)
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Masayoshi Sumino
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Nec Corporation
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0083—Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2054—Methods of obtaining the confinement
    • H01S5/2081—Methods of obtaining the confinement using special etching techniques
    • H01S5/209—Methods of obtaining the confinement using special etching techniques special etch stop layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/32308—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm
    • H01S5/32341—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm blue laser based on GaN or GaP

Definitions

  • the present invention relates to a nitride semiconductor device such as a semiconductor laser, a light emitting device, and a light emitting diode, and a method for manufacturing the same.
  • FIG. 15 is a cross-sectional view of a ridge-type GaN-based semiconductor laser according to a first conventional example (Non-Patent Document 1).
  • the semiconductor laser 2000 is formed on a sapphire substrate 200 1 [0.5 [/ ⁇ ⁇ ] ⁇ 3 ⁇ 4 ⁇ ] ⁇ ⁇ — ⁇ & ⁇ 2002, 1.0 [, um] (n-AlGaNji2003, 0. 1 [; zm] n—GaN guide layer 2004, Ga In N (3.5 [nm]) / Ga In N
  • the p layer of this semiconductor laser 2000 is covered in a ridge stripe shape with a mesa width of 2.3 [m] by reactive ion etching (hereinafter abbreviated as “RIE”).
  • RIE reactive ion etching
  • the thickness of the p-layer beside the mesa is adjusted to 0.15 [m] for lateral light confinement.
  • Both sides of the ridge stripe are covered with SiO.
  • the n-GaN layer up to 2002 was deposited by RIE.
  • the thickness of the semiconductor laser is 100 [m] and the cavity length is 600 [m]. This semiconductor laser has reported a lifetime of 1000 hours at an output of 30 [mW] in an environment of 50 [° C].
  • a wet etching method is known as a method for processing a semiconductor layer in a semiconductor element. It is one of the constituent layers of the semiconductor layer and does not damage the active layer that is the light emitting layer. Therefore, it can be said that it is the most excellent cache method.
  • the GaN-based semiconductor device has a problem that it cannot be formed into an edge shape by the wet etching method. This is because the epilayer surface is usually an inactive (0 001) plane. Therefore, a method of performing a wet etching method using a (000-1) plane with the epilayer surface not the (0001) plane is conceivable.
  • the (000 1) plane when used, when an InAlGaN-based material is grown on a GaN substrate by a metal organic vapor phase thin film growth method (hereinafter abbreviated as “MOVPE method”), flat growth is performed at the atomic level. It is difficult. Therefore, there is a problem that the optical quality of the active layer is inferior to that using the (0001) plane. Therefore, so far, GaN-based semiconductor devices have been formed using optical etching structures or current confinement structures using dry etching or selective growth.
  • MOVPE method metal organic vapor phase thin film growth method
  • Patent Document 1 A technique related to a nitride semiconductor laser capable of wet etching that solves the above problems has been proposed (hereinafter referred to as "second conventional example") (Patent Document 1).
  • This second conventional nitride semiconductor laser has an internal current confinement layer.
  • This current confinement layer is composed of an amorphous A1N layer having a thickness of 10 nm to 80 nm deposited at a low temperature of 400 [° C] to 600 [° C].
  • the current confinement layer can be patterned by wet etching.
  • LEDs semiconductor light emitting devices
  • Non-patent Document 2 a technique related to a semiconductor light emitting device capable of improving the light extraction efficiency has been proposed (hereinafter referred to as “third conventional example”) (Non-patent Document 2).
  • the third conventional example uses a photonic crystal to improve the light extraction efficiency.
  • a semiconductor light-emitting device with an InGaAsP-based material with a wavelength of 1.5 [/ ⁇ ⁇ ] band is attached to a two-dimensional surface-diffractive lattice photonic crystal to demonstrate improved LED light extraction efficiency.
  • the surface diffraction grating photonic crystal used in this semiconductor light emitting device has a triangular lattice with a cylindrical hole with a depth of 0.6 [m] and a diameter of 1 [; zm] above the active layer of the semiconductor light emitting device. It is produced by two-dimensional arrangement with a period of about 2 [m].
  • GaN-based semiconductor elements are also being applied to electronic devices. Since GaN has a breakdown voltage 10 times that of Si and a saturation electron velocity 2.5 times that of Si, it can be applied to high-frequency, high-voltage operation power devices.
  • High electron transfer in AlGaNZGaN heterostructure A high electron mobility transistor (HEMT) is obtained that produces a two-dimensional electron gas of a certain degree and uses it as channel electrons. Furthermore, due to the piezo effect generated by crystal distortion, the concentration of the two-dimensional electron gas is 10 times that of GaAs HEMT, and high transconductance characteristics and high-frequency operation can be expected.
  • HEMT high electron mobility transistor
  • the AlGaNZGaN recess gate structure is a structure in which the source electrode and drain electrode force are in ohmic contact with the SGaN layer, so that the A1 concentration is increased to form a high-concentration two-dimensional electron gas while keeping the parasitic resistance small.
  • FIG. 16 is a cross-sectional view of a GaN-based semiconductor laser diode according to a fourth conventional example.
  • the recess gate type HEM T is composed of a (0001) sapphire substrate 2101, a 30 [nm] thick GaN nucleation layer 2102, and a 2.5 [ ⁇ m] thick i-GaN. Buffer layer 2103, 10 [nm] thick and i-A1
  • N layer 2106 Ti (25 [nm]) ZAl (150 [nm]) drain electrode 2107, Ti (25 [nm]) Z Al (150 [nm]) source electrode 1108, Pt (10 [nm]) / Ti (40 [nm]) / Au (100 [nm]) gate electrode 2109.
  • Spacer layer 2104 is provided to reduce Coulomb scattering of two-dimensional electrons in the channel layer.
  • the gate recess etching is performed by reactive ion etching using BC1 plasma.
  • the chamber pressure during etching is 3 [Pa], and the high-frequency power is 10 [W].
  • the depth of the recess etching is 30 [nm].
  • the ohmic contacts of the drain electrode 2107 and the source electrode 2108 of Ti (25 [nm]) / Al (l 50 [nm]) were obtained by heat treatment at 900 [° C.] for 60 seconds.
  • the gate length is 2.1 [/ ⁇ ⁇ ], the width is 15 [/ ⁇ ⁇ ], and the length between the source and drain is 10 [m].
  • Patent Document 2 and Patent Document 3 describe conventional techniques related to "polarity control" limited by means for solving the problems described later. These will be described later.
  • Non-patent document 1 "GaN-based high-power blue-violet laser diode” Japanese 'Journal' Ob 'Applied' Physics magazine 2001 40 pp. 3206-3210
  • Non-Patent Document 2 “Increased Efficiency in Light-Emitting Diodes with Two-Dimensional Surface Grating Photonic Crystals” Applied 'Physics' Letter magazine, 2004, 84 pp. 457-459 AlGaNZGaN modulation-doped field-effect transistor "Applied 'Physics' Letter, 2000, 76-121-123 Patent Document 1: JP 2002-314203
  • Patent Document 2 Japanese Patent Laid-Open No. 2001-148532
  • Patent Document 3 Japanese Patent Publication No. 2003-527745
  • GaN-based semiconductor elements (hereinafter also referred to as “LEDs”) are expected to be put to practical use in various fields.
  • LEDs semiconductor laser diode
  • LD semiconductor laser diode
  • a processing technique that does not cause crystal defects or damage in the active layer that is the light emitting layer is required.
  • high device yield and processing technology are required.
  • GaN-based semiconductor elements are also expected to be practical for illumination.
  • white light-emitting elements using GaN-based semiconductor light-emitting elements (LEDs) are expected to have a large market as alternative lighting for fluorescent lamps.
  • LEDs GaN-based semiconductor light-emitting elements
  • research and development for this purpose is ongoing.
  • the first problem with the semiconductor laser of the first conventional example is that the dry etching method uses a ridge. This is the point that the depth of the head cannot be controlled with high accuracy. For this reason, a high yield cannot be obtained.
  • the depth of the ridge In the case of a mesa width of 1.7 [m], which is normally used, the depth of the ridge must be adjusted to achieve the horizontal emission angle of 8 [°] or higher and the kink level of 50 [mW] or higher required for semiconductor lasers. It is necessary to control with high accuracy of 5 [nm]. The reason is as follows.
  • this laser has an actual refractive index guide structure, and if the lateral refractive index difference An is increased in order to strengthen the lateral optical confinement, a higher-order mode is easily generated, and the current-voltage characteristics are kinked. Arise. If An is made smaller, the optical confinement becomes weaker and the horizontal radiation angle decreases, which increases the aspect ratio of the light spot.
  • the range of ⁇ that realizes the horizontal radiation angle of 8 [°] or more and the kink level of 50 [mW] or more required for LD is very narrow as 0.0068 ⁇ 0.0072. This is equivalent to controlling the ridge depth with high accuracy of ⁇ 5 [nm].
  • a second problem with the semiconductor laser of the first conventional example is that damage during dry etching reduces the device lifetime. There are two reasons for this.
  • the first cause is that the operating voltage rises due to the high resistance of the p-cladding layer which enters the side of the dry etching damage stripe.
  • the second cause is that when the dry etching damage reaches the active layer, a non-emission center is introduced into the active layer, and the current threshold and operating current of the device rise. This is because the element lifetime is strongly dependent on the operating current and operating voltage.
  • the damage to the active layer is large, and the device life is significantly reduced.
  • a third problem in the first conventional semiconductor laser is that it is difficult to keep the state of the dry etching apparatus stable.
  • the dry etching system is affected by acid contamination of the mask material, metal contamination from the electrode, and organic contamination of the resist power. The reason is that these contaminants are brought into the apparatus and adhere to the inner wall of the apparatus after dry etching, and the contaminants are detached and adhered to the wafer at the next etching. As a result, ridge mesa shape defects and processing It is difficult to maintain high device yield as soon as reliability is reduced due to damage.
  • the nitride semiconductor laser of the internal current confinement type according to the second conventional example has many problems.
  • the amorphous A1N layer which is the internal current confinement layer, tends to have uneven surfaces that make it difficult to obtain a flat film.
  • the amorphous A1N layer crystallizes and causes lattice mismatch with GaN, which causes many defects and dislocations in the surrounding crystals, limiting the device lifetime.
  • the thickness of the A1N layer is increased, dislocation increases, and when the thickness of the A1N layer is decreased, a current leak is generated from the recess.
  • the control of the A1 composition of the AlGaN cladding layer in the opening and the control of the Mg concentration are unstable.
  • the A1N mask is amorphous, the film quality becomes non-uniform and the stripe formed by wet etching is not straight, and its width fluctuates and the stripe width becomes larger than the design value. As a result, problems such as the fact that the desired light spot shape cannot be obtained during high-power operation, the waveguide loss of light increases, and the current threshold value rises arise.
  • the third conventional example also has the following problems.
  • the recess gate type HEMT of the fourth conventional example also has the following problems.
  • the distance from the bottom of the gate electrode to the n-AlGaNZi-AlGaN interface is The thickness is d [nm].
  • the thickness d of the film was 20 [nm].
  • the thickness d of the electron supply layer is 10 [nm] or less
  • the carrier concentration decreases, the sheet resistance increases, and high-frequency operation is limited.
  • the mobility decreases, the mutual conductance decreases, and high-frequency operation becomes difficult.
  • the n-doping concentration of the electron supply layer is increased to increase the carrier concentration, the Schottky barrier becomes thin and the breakdown voltage cannot be obtained, and high voltage operation cannot be performed. If a voltage is applied forcibly, a leak current is generated, increasing the noise generated inside the device.
  • the differential coefficient (d VthZ dd) of the threshold gate voltage Vth with respect to the thickness d of the electron supply layer (d VthZ dd) is proportional to the product of the donor concentration of the electron supply layer and the thickness d of the electron supply layer.
  • the doping concentration is high, the variation of the threshold gate voltage Vth increases with respect to the distribution of the thickness d of the electron supply layer.
  • the thickness d of the electron supply layer exceeds 20 [nm], the capacity of the electron supply layer is reduced, the mutual conductance is reduced, and the high frequency operation is restricted. If the n-GaN layer with a high n concentration remains without being completely etched, the carrier concentration increases and the threshold gate voltage Vth changes greatly.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide the following nitride semiconductor device and a method for manufacturing the same. That is, the first object is to provide (1) a semiconductor element that can increase the reliability during output operation and (2) can be manufactured at low cost. The second object is to obtain (3) an active layer with high luminous efficiency while satisfying the above (1) and (2). The third object is to satisfy (1) and (2) above, and (4) a semiconductor device with high light extraction efficiency. Etc. is to provide.
  • the nitride semiconductor device is a nitride semiconductor device in which a substrate and a plurality of semiconductor layers are formed on the substrate, and is formed on the substrate.
  • At least one stacked body comprising two semiconductor layers, the second semiconductor layer having a polarity that is etched by wet etching, and the first semiconductor layer being the wet etching of the second semiconductor layer.
  • the above polarity refers to elements that are predominantly arranged on the surface during crystal growth, and are used as an index representing the crystal growth direction.
  • Single-crystal GaN has two types of crystal planes (polarity): Ga (gallium) plane and N (nitrogen) plane.
  • the Ga plane is a polar plane in which Ga atoms are formed on the crystal growth surface, with one of the four bonds of Ga atoms facing the outside of the film and the remaining three bonds facing the inside of the film.
  • the N-plane is a polar plane in which N atoms are formed on the crystal growth surface and three bonds of N atoms are directed toward the inside of the film.
  • the surface orientation of a GaN crystal with a Ga surface is (0001)
  • the surface orientation of a GaN crystal with an N surface is (000-1).
  • Ga-polar crystal a GaN crystal whose surface during growth was a Ga plane
  • N-polar crystal a GaN crystal whose growth surface was an N-plane
  • Group IV polarity when the surface of the crystal is grown by a group III element, it is called Group IV polarity
  • Group V element when the surface of the crystal is grown by a Group V element, it is called Group V polarity.
  • the nitride semiconductor device of the first aspect of the present invention it is possible to use a wet etching method when forming the pattern of the second semiconductor layer.
  • the reason is that the crystal growth direction polarity of the first stacked body and the second stacked body is selected so that the first semiconductor layer is not etched by wet etching of the second semiconductor layer.
  • the semiconductor element controlled with high precision can be obtained.
  • the device yield can be improved. Therefore, low cost can be realized.
  • the wet etching method can be used, the first semiconductor layer and its lower layer
  • Patent Document 2 discloses a technique related to a nitride semiconductor device in which a polarity inversion layer is formed in a p-contact layer (for example, see FIG. 1) (hereinafter referred to as “fifth conventional example”). "") According to the fifth conventional example, by stacking a high-concentration Mg GaN layer in the p-contact layer, the polarities of the two layers sandwiched between the layers can be reversed. As a result, by forming a p-electrode on the N-polar surface, the contact resistance can be reduced and the operating voltage can be improved.
  • Patent Document 3 discloses a technique in which a polarity inversion layer is formed in an active layer (for example, see Fig. 1) (hereinafter referred to as "sixth conventional example"). According to the sixth conventional example, a technique is disclosed in which an Mg monomolecular layer is deposited in an active layer and the active layer as a subsequent layer is inverted.
  • the present invention is consistent with the fifth and sixth conventional examples in that a polarity inversion layer is provided in the nitride semiconductor device.
  • the polarity inversion layer according to the present invention is such that the first semiconductor layer is not etched during the wet etching in the pattern formation of the second semiconductor layer. It is provided in order to reverse the polarity of the second semiconductor layer. Therefore, there is no suggestion to the present invention from the fifth and sixth conventional examples.
  • the nitride semiconductor device according to the second aspect of the present invention is the nitride semiconductor device according to the first aspect, wherein the polarity inversion layer is any one of the following (1) to (5): It is characterized by being a layer of
  • the nitride semiconductor device according to the third aspect of the present invention is the nitride semiconductor device according to the first or second aspect, wherein the polarity inversion layer includes the following (1) to (5): It is characterized by being a deviation.
  • a nitride semiconductor device includes an active layer on the substrate and below the first semiconductor layer or above the second semiconductor layer. RU
  • the nitride semiconductor device of the fourth aspect of the present invention since the patterning is performed using the wet etching method, crystal defects occur in the first semiconductor layer and its lower layer, as well as in the first. It does not reach the upper layer of the two semiconductor layers. Therefore, the subsequent regrowth does not diffuse the defect into the active layer and introduce a non-light emitting center into the active layer. As a result, light It is possible to improve the reliability during output operation and to improve the yield of devices by preventing deterioration of the physical characteristics.
  • the nitride semiconductor device is the nitride semiconductor device according to the first to fourth aspects, wherein the active layer is provided below the first semiconductor layer, and the first semiconductor layer includes the active layer.
  • the ridge type is characterized in that the second semiconductor layer is patterned into a ridge shape.
  • the second semiconductor layer is etched into a ridge shape by wet etching, and the first semiconductor layer is etched. Since it functions as a stop layer, when the ridge mesa stripe is formed, the thickness of the mesa side can be controlled with high accuracy. As a result, a structure as designed can be obtained. In addition, even if high-power operation is performed, the basic transverse mode is maintained and a small aspect ratio can be realized. In addition, a nitride semiconductor device having excellent reliability as compared with the dry etching method can be obtained.
  • the nitride semiconductor device according to the sixth aspect of the present invention is the nitride semiconductor device according to any one of the first to fourth aspects, wherein the second semiconductor layer is an internal current confinement layer.
  • the internal current confinement layer type is characterized in that the active layer is provided under the semiconductor layer 1.
  • the internal current confinement layer is made of crystal, the problem caused by non-crystal can be solved.
  • the internal current confinement layer is patterned by the wet etching method, processing damage such as crystal defects does not occur in the first semiconductor layer and its lower layer. Therefore, the high luminous efficiency of the active layer is maintained even after regrowth.
  • a nitride semiconductor device is the nitride semiconductor device according to the sixth aspect, wherein the internal current confinement layer is any of the following (1) to (3): It is characterized by satisfying these conditions.
  • the refractive index of the internal current confinement layer can be kept low by satisfying the above condition (1) force (3). Therefore, light can be more effectively confined in the active layer.
  • the value of X in (2) is more preferably 0.1 ⁇ X ⁇ 0.25, and more preferably 0.15 ⁇ X ⁇ 0.2.
  • the nitride semiconductor device according to the eighth aspect of the present invention is the same as the nitride semiconductor device according to the fourth aspect, laminated on the second semiconductor layer and the second semiconductor layer.
  • the semiconductor layer is patterned, and an embedded layer is formed in a portion opened by the pattern.
  • a high threshold is achieved due to the feature that the refractive index distribution and the gain distribution coincide with each other. Reliability can be obtained. In addition, the lifetime of the semiconductor element can be increased.
  • the nitride semiconductor device is the nitride semiconductor device according to any one of the fourth to eighth aspects, wherein the first semiconductor layer is a separated light confinement heterostructure layer.
  • the active layer is provided below the first semiconductor layer.
  • the nitride semiconductor device according to the tenth aspect of the present invention is the nitride semiconductor device according to any one of the first to ninth aspects, wherein the semiconductor layer is formed of a GaN-based semiconductor layer. It is a life characterized by scolding.
  • the nitride semiconductor device according to the eleventh aspect of the present invention is the nitride semiconductor device according to any one of the first to tenth aspects, wherein the crystal plane orientation of the second semiconductor layer is (000 — 1) or V group polarity.
  • a nitride semiconductor device is the nitride semiconductor device according to any one of the first to ninth aspects, further comprising a nitride photonic crystal. It is characterized by this. By providing a nitride photonic crystal, the light extraction efficiency can be improved.
  • a nitride semiconductor device is characterized by including an n-type superlattice light reflecting layer.
  • an n-type superlattice light reflecting layer Since the emitted light can be reflected, the light extraction efficiency can be further increased.
  • a nitride semiconductor device is the nitride semiconductor device according to any one of the first to thirteenth aspects, wherein a p electrode and a p connected to the p electrode are provided.
  • a nitride semiconductor device is the nitride semiconductor device according to any one of the first to fourteenth aspects, wherein a p electrode and a p connected to the p electrode are provided.
  • a p-contact layer, and the p-contact layer is N-polar and is made of a material containing at least the p-electrode force SPd.
  • P electrode contains at least Pd, it reacts with p contact layer and is easily alloyed. Therefore, the annealing temperature can be lowered.
  • the nitride semiconductor device according to the sixteenth aspect of the present invention is the nitride semiconductor device according to the first, second or third aspect, wherein the first semiconductor layer is an electrode connected to a gate electrode.
  • the second semiconductor layer is a contact layer that is in ohmic contact with the source electrode and the drain electrode.
  • a nitride semiconductor device is the nitride semiconductor device according to the sixteenth aspect, wherein the contact layer has a plane orientation in the growth direction of the contact layer of (00 00- 1) a group V polar n-type semiconductor layer, wherein the electron supply layer is a group III polar n-type semiconductor layer whose growth direction plane orientation is (0001). It is a life.
  • the nitride semiconductor device includes, as the semiconductor layer, a semiconductor layer formed by laminating a channel layer and a spacer layer in that order under the first semiconductor layer.
  • the channel layer is an undoped GaN layer having a group III polarity
  • the spacer layer is an undoped AlGaN layer (where 0 ⁇ X ⁇ 1)
  • the electron supply layer is an n-type layer.
  • the contact layer is an n-type Al Ga N layer with group V polarity (however, 0 ⁇ Y ⁇ X) or ⁇ -type InGaN layer (however, 0 ⁇ Z ⁇ 0.2)
  • the nitride semiconductor device is the nitride semiconductor device according to the eighteenth aspect, wherein the spacer layer has group III polarity, and the spacer layer
  • the sum of the layer thicknesses of the electron supply layer and the electron supply layer is 10 [nm] or more and 25 [nm] or less, and the value of the composition ratio X of the electron supply layer and the spacer layer is 0.25. As described above, it is characterized by being 0.45 or less.
  • the nitride semiconductor device is the nitride semiconductor element according to any one of the fifteenth to eighteenth aspects, wherein the substrate is a semiconductor insulating SiC substrate or a semiconductor. It is an insulating GaN substrate. In this way, a high quality flat interface can be obtained. As a result, high electron mobility can be obtained.
  • the nitride semiconductor device includes a first semiconductor layer on a substrate, a polarity inversion layer formed immediately above the first semiconductor layer, and A method for manufacturing a nitride semiconductor device comprising a plurality of semiconductor layers formed immediately above and including a stack of at least one second semiconductor layer having a polarity different from that of the first semiconductor layer, Forming the first semiconductor layer to be an etching stop layer during wet etching in patterning of the second semiconductor layer, forming the polarity inversion layer, forming the second semiconductor layer, and forming the second semiconductor layer; The semiconductor layer is etched by a wet etching method to form a pattern of the second semiconductor layer.
  • the nitride semiconductor device of the twenty-first aspect of the present invention it is possible to use a wet etching method when forming the second semiconductor layer pattern.
  • the reason is that the polarities of the crystal growth directions of the first stacked body and the second stacked body are selected so that the first semiconductor layer is not etched by wet etching of the second semiconductor layer.
  • a semiconductor element controlled with high accuracy can be manufactured.
  • the device yield can be improved. Therefore, cost reduction can be realized.
  • a wet etching method can be used, crystal defects and damage of the first semiconductor layer, its lower layer, and the upper layer of the second semiconductor layer do not occur. Therefore, the reliability during the output operation can be improved.
  • the wet etching method eliminates the need for expensive equipment used for the dry etching method, thereby reducing the production cost.
  • the nitride semiconductor device according to the twenty-second aspect of the present invention is the method for producing a nitride semiconductor device according to the twenty-second aspect, wherein the wet etching uses a mixed solution of phosphoric acid and sulfuric acid. Etching is performed at a temperature of 80 [° C] or higher and 300 [° C] or lower.
  • a method for manufacturing a nitride semiconductor device according to the twenty-third aspect of the present invention is the method for manufacturing a nitride semiconductor device according to the twenty-first or twenty-second aspect, wherein the plurality of semiconductor layers are: To (3).
  • the manufacturing method of (1) of the nitride semiconductor device according to the twenty-third aspect of the present invention, a stable device yield can be obtained in the device processing step, and the device cost can be reduced. wear.
  • the manufacturing method of (2) above since the source and dopant supply can be switched rapidly while observing the growth surface by reflection high energy electron diffraction, it is easy to control the polarity inversion. It is also easy to optimize the growth temperature and nitrogen pressure. In addition, since NH and H are not used, hydrogen is not taken into the crystal. For this reason, Mg
  • Hydrogen inactivation of the dopant can be prevented.
  • sharp control is possible, it is advantageous for improving the characteristics and reliability of the element.
  • the nitride semiconductor device according to the present invention has an excellent effect of being able to provide the following nitride semiconductor device and manufacturing method thereof. That is, (1) it is possible to provide a semiconductor element or the like that can improve reliability during output operation and can be manufactured at low cost. In addition, (2) high reliability during output operation, low cost and high luminous efficiency. A semiconductor element or the like capable of obtaining an active layer can be provided. Furthermore, (3) it is possible to provide a semiconductor element or the like with high light extraction efficiency, which can increase the reliability during output operation and can be manufactured at low cost.
  • FIG. 1 is a cross-sectional view of a nitride semiconductor laser according to a first embodiment.
  • FIG. 2 is a cross-sectional view of a nitride semiconductor laser according to Embodiment 2.
  • FIG. 3 is a cross-sectional view of a nitride semiconductor laser according to a third embodiment.
  • FIG. 4 is a cross-sectional view of a nitride semiconductor laser according to Embodiment 4.
  • FIG. 5 is a cross-sectional view of a nitride semiconductor laser according to a fifth embodiment.
  • FIG. 6 is a cross-sectional view of a nitride semiconductor light emitting device according to Embodiment 6.
  • FIG. 7 is a top view of a nitride semiconductor light emitting device according to Embodiment 6.
  • FIG. 8 is a cross-sectional view of a nitride semiconductor light emitting device according to Embodiment 7.
  • FIG. 9 is a sectional view of a nitride semiconductor high electron mobility transistor according to the eighth embodiment.
  • FIG. 10 is a cross-sectional view of a nitride semiconductor high electron mobility transistor according to the ninth embodiment.
  • FIG. 11 is an explanatory view of the action of the nitride semiconductor light emitting device according to the sixth embodiment.
  • FIG. 12 shows an emission spectrum of the ultraviolet LED of Embodiment 7.
  • FIG. 13 is a graph showing the relationship between the band gap and the a-axis length in an A1 Ga In N mixed crystal.
  • FIG. 14 shows characteristics of the semiconductor laser according to the first embodiment.
  • FIG. 15 is a cross-sectional view of a nitride semiconductor laser according to a first conventional example.
  • FIG. 16 is a cross-sectional view of a nitride semiconductor field effect transistor according to a fourth conventional example.
  • FIG. 1 is a cross-sectional view of nitride semiconductor laser 100 according to the first embodiment.
  • an n-type GaN (0001) substrate 101 having a thickness of 110 [m] was used as the substrate.
  • n-type GaN (OOOl) substrate 101 was used as the substrate.
  • a noffer layer 102 a first cladding layer 103, a first separated light confinement heterostructure (hereinafter abbreviated as rsCHj (Separete confinement Getero-structure)) layer 104, and a quantum well active layer comprising three layers 105, current overflow prevention (hereinafter abbreviated as “OFP”) layer 106, second SCH layer 107, polarity inversion layer 108, third SCH layer 109, second cladding layer 110
  • the contact layers 111 are laminated in this order (hereinafter, these layers are collectively referred to as a laminate 150).
  • the SCH layer is a layer for confining light strongly in the active layer.
  • the first semiconductor layer is the second SCH layer 107
  • the second semiconductor layer is the third SCH layer 109.
  • the buffer layer 102 is configured to have a thickness of 1 1 0 & ⁇ with a layer thickness of 0.3 111].
  • the first cladding layer 103 is made of n-AlGaN having a layer thickness of 1.5 [m].
  • the first SCH layer is an n-GaN layer with a layer thickness of 100 [nm]
  • the quantum well active layer 105 with three layers is made of InGaN (2.5 [nm]) ZGaN (10 [nm]). Composed.
  • the FP layer is 8 [nm] thick p-AlGaN, and the second SCH layer 107 is 100 [nm] thick
  • P— consists of GaN.
  • the polarity from the n-GaN (0001) substrate 101 to the second SCH layer 107 is configured to be the Ga polarity 120 described above.
  • Ga polarity refers to a GaN crystal whose growth surface was a Ga plane
  • N polarity refers to a GaN crystal whose growth surface was an N plane !, #2.
  • the polarity inversion layer 108 is composed of an Mg monoatomic layer.
  • the third SCH layer 109 is contacted by p-GaN with a layer thickness of 20 [nm]
  • the second cladding layer 110 is contacted by a ridge type p-AlGaN with a layer thickness of 0.6 [m].
  • the layer 111 is composed of p-GaN with a layer thickness of 20 nm.
  • the polarity from the third SCH layer 109 to the contact layer 111 is formed to be N polarity 121.
  • the ridge mesa width is preferably in the range of 1.5 [/ ⁇ ⁇ ] to 2.2 [m]. This is because a light distribution of a single transverse mode can be obtained within this range. In Embodiment 1, the ridge mesa width is set to 1.8 [m].
  • a current confinement mask 113 and a P electrode 112 are formed on the upper surface of the multilayer body 150.
  • back surface a surface on the back side with respect to the surface (hereinafter referred to as “main surface”) on which the multilayer body 150 is formed on the n-GaN (0001) substrate 101 has N Electrode 114 is formed.
  • the P electrode 112 is made of 10 [nm] Ni and 10 [nm] Au, and the N electrode 114 is made of TiZAl.
  • Semiconductor laser device according to Embodiment 1 The oscillation wavelength was 405 [nm].
  • Embodiment 1 the laminate was formed by metal organic vapor phase epitaxy (hereinafter abbreviated as “MOVPE method”).
  • MOVPE method metal organic vapor phase epitaxy
  • TMG trimethylgallium
  • T [MA] trimethylaluminum
  • T I trimethylindium
  • Ammonia NH 3 was used as the N raw material. Also, n-type punch
  • Silane (SiH) p-type dopants include biscyclopentagenenyl magnesium (hereinafter “
  • Mg magnesium
  • n Si silicon
  • 0 oxygen
  • the atomic concentration of Mg is 1 x 10 20 [cm " 3 ] for the contact layer 111 that also has p-GaN force, 2 x 10 19 [cm _ 3 ] otherwise, and the atomic concentration of Si is all 2 x 10 18 [cm _3 ].
  • the temperature of the substrate is raised while supplying NH.
  • the growth was started when the growth temperature was reached.
  • a buffer layer 102 having a layer thickness of 0.3 [m]
  • a first cladding layer 103 having a layer thickness of 1.5 [ ⁇ m]
  • a first layer having a layer thickness of 100 [nm]
  • the SCH layer 104, the active layer 105 of the quantum well consisting of three layers, the OFP layer 106 with a thickness of 8 [nm], and the second SCH layer 107 with Ga polarity are formed in this order.
  • the Mg monoatomic layer which is the polarity inversion layer 108, lowers the substrate temperature to 850 [° C], stops the TMG supply, and supplies a small amount of NH. ,
  • N-polar p-GaN having several molecular layers was formed.
  • the substrate temperature was raised to 1000 [° C], and an N-polarity third SCH layer 109, an N-polarity second cladding layer 110, and a contact layer (N-polarity) 111 were laminated.
  • the formation of the buffer layer 102 is 600 [in]
  • the first cladding layer 103 and the second cladding The layer 110 was formed at 1050 [° C]
  • the active layer 105 was formed at 800 [° C].
  • the substrate on which the nitride semiconductor has been grown as described above is taken out by the growth apparatus force, and the surface of the contact layer 111 is maintained on the surface of the contact layer 111 by thermal CVD (chemical vapor deposition) using a predetermined mask.
  • thermal CVD chemical vapor deposition
  • a protective film was formed. Then, a stripe shape having a layer thickness of 300 nm and a width of 3 [m] was formed using a resist exposure technique so as to be parallel to the orientation flat of the substrate.
  • the obtained wafer was immersed in a mixed solution of 200 [° C] phosphoric nitric acid (2: 1) for 30 [s] to perform wet etching to obtain a mesa stripe structure.
  • the etching solution was heated sufficiently to evaporate and remove the internal moisture.
  • the etching rate of the second cladding layer 110 was 1.8 [/ ⁇ ⁇ ].
  • the surface after etching was flat, and the surface of the second SCH layer 107 was exposed.
  • the mesa shape does not change even if additional etching is performed V. Therefore, it can be seen that the second SCH layer 107 serves as an etching stop layer.
  • the distance h from the third well layer of the active layer to the etching surface is preferably 100 [nm] or more. This is because when the current is smaller than 100 [nm], the current-voltage characteristics become linear. This is because the difference in refractive index An in the horizontal direction is large and higher modes are allowed. In the first embodiment, the distance h is 118 [nm].
  • a Zr 2 O layer having a layer thickness of 300 [nm] was first formed on the upper surface of the laminate 150 by a sputtering method. Then, immerse for 70 [s] in notched hydrofluoric acid (BHF).
  • the ZrO layer has a mesa stripe due to its low etching rate.
  • the obtained mesa width was 2 [m].
  • ohmic contact was formed by rapid thermal annealing between 600 [30] and 30 [s] in a nitrogen gas environment containing oxygen.
  • the back surface of the obtained wafer was polished to obtain a 1 10 [m] thick wafer.
  • an n-electrode was formed, and an n-side ohmic contact was formed by alloying between 400 [in] and 5 [min].
  • 300 [nm] thick gold was deposited on the p side.
  • the wafer that has undergone the above steps is cleaved perpendicular to the stripe direction, and the LD resonator A plane (1-100) was obtained.
  • ARZHR reflective coating film was attached to the cavity end face.
  • the last obtained LD chip was assembled by fusing to the heat sink of A1N with p side up
  • the first embodiment uses a structure in which the side walls of the mesa stripe are covered with a ZrO layer.
  • SiO layer can be used instead. In that case, shape a striped mesa
  • an SiO layer is formed on the upper surface of the laminate 150, and a resist is further applied to the surface.
  • the resist is removed by dry etching to expose the SiO layer in the stripe mesa, and
  • Stripe mesa SiO layer is removed, resist is removed, and electrodes are deposited.
  • a P-AlGaN cladding layer is used as the P-type cladding layer.
  • both the clad layer made of p-AlGaN and the SCH layer made of P-GaN in contact with the clad layer have Ga polarity. For this reason, an energy barrier that becomes an obstacle when a hole passes from the clad layer to the SCH layer in contact therewith has been formed. This is because the clad layer composed of p-AlGaN is subjected to tensile strain, and a large piezoelectric field is generated in the C-axis direction of the crystal. Positive piezoelectric charges are generated at the interface, and a hole injection barrier is formed. It is because it becomes.
  • the SCH layer in contact with the second cladding layer is divided into the second SCH layer and the third SCH layer via the Mg monoatomic layer, and the polarity is inverted.
  • Both the SCH layer in contact with the cladding layer 110 (third SCH layer 109) are N-polar. Therefore, it does not form a hole energy barrier.
  • FIG. 14 shows current-voltage characteristics and current-light output characteristics of the semiconductor laser according to the first embodiment.
  • the operating voltage during oscillation was 4.5 [V], a drop of more than 2.5 [V] compared to the conventional one.
  • the band gap corresponding to the oscillation wavelength is 3. l [eV].
  • a voltage of 3.1 [V] is required for carrier injection.
  • the operating voltage rise that can be estimated for the contact resistance of the p electrode, the resistance of the p layer, and the current density force during oscillation is about 1.4 [V], and as a result, an operating voltage of 4.5 [V] is realized. Yes.
  • the structure of the first embodiment the operating voltage rise due to the energy barrier of the hall is eliminated.
  • the polarity of the SCH layer can be inverted through this polarity inversion layer.
  • the third SCH layer 109 is N-polarized and the second SCH layer 107 is Ga-polarized by stacking the polarity inversion layer 108, which is an Mg monoatomic layer, on the Ga-polarized second SCH layer 107. It can be. Since the third SCH layer 109 is N-polar, it is well etched by wet etching. On the other hand, the second SCH layer 107 serves as an etching stop layer because it has Ga polarity.
  • the second SCH layer 107 can be used as an etching stop layer while the third SCH layer 109 is systematically etched by the wet etching method. it can.
  • the second SCH layer 107 serves as an etching stop layer, no crystal defects were generated in the second SCH layer and its lower layer by wet etching. Therefore, no diffusion of defects occurred during regrowth, and the active layer was not damaged. Moreover, when forming the mesa stripe, the 100 [nm] third SCH layer 109 beside the mesa could be controlled with high accuracy of ⁇ 2 [nm]. As a result, we were able to obtain the structure as designed. As a result, it was possible to provide a nitride semiconductor device having superior reliability as compared with the dry etching method.
  • the p-contact can be formed at a low wheel temperature.
  • the N-polar P-GaN surface is chemically active, and the P-electrode formed on the contact layer 111 made of N-polar p-GaN is easily alloyed by heating.
  • Ga atoms bonded to N atoms on the surface of N-polar PGaN have three bonds on the surface side and are likely to react with the metal of the p electrode, which also has surface forces.
  • the annealing temperature can be lowered by using a metal having a high work function and GaN as the p-electrode.
  • the hole barrier of the second SCH layer 109 and the second cladding layer 110 caused by piezo is eliminated, and the voltage during operation at 25 [in] and 30 [mW] is set to 4.8 [V]. It was possible to reduce. Thirdly, by reducing the voltage, DC current operation for over 2000 hours was achieved at 70 [° C] and 70 [mW], greatly improving reliability.
  • the oscillation wavelength of the laser device of Embodiment 1 is that the In composition of the InGaN active layer is increased, and Si is doped into the active layer 105 at a concentration of 1 ⁇ 10 18 [cm ⁇ 3 ].
  • the quantum well width By increasing the quantum well width to 3 [nm], it was possible to change it to 487 [nm] without a significant decrease in luminous efficiency.
  • a 480 [nm] band LD that emits greenish-blue light can also be obtained.
  • the laminate 150 is formed by the MOVPE method.
  • the crystal growth is a molecular beam epitaxy method (hereinafter abbreviated as “MBE method”), the MOVPE method, It differs in that it is manufactured by combining. More specifically, crystal growth of Ga-polar semiconductor layers is performed using MOVPE (metal organic vapor phase epitaxy), and crystal growth of N-polar semiconductor layers is performed using MBE (molecular beam epitaxy). went.
  • MBE method molecular beam epitaxy method
  • the polarity inversion layer 108 which is an Mg monoatomic layer, is used as the polarity inversion layer 108, whereas in the first modification, 0.1 [%] Mg is included.
  • the difference is that two atomic layers of Ga are used. This is because, in the MBE method, a high-quality polarity reversal crystal was obtained by using the A1 or Ga diatomic layer rather than the Mg monoatomic layer.
  • the second SCH layer 107 is laminated on the GaN (0001) substrate 100 by the MOVPE method in the same manner as in the first embodiment. Thereafter, a polarity inversion layer 108 composed of a Ga atomic layer containing 0.1 [%] Mg was laminated. After forming the polarity inversion layer 108, the above The polarity inversion layer 108 to the contact layer 111 described in the first embodiment are stacked by the MBE method.
  • Metal sources were used for the Ga, A1, and Mg sources in the MBE method.
  • the Ga cell temperature was set to 970 [in]
  • the A1 cell temperature was set to 1100 [° C].
  • the N source used was active nitrogen in a plasma state at a high frequency of 13.56 [MHz].
  • the nitrogen flow rate was set to 1.5 [ S ccm]
  • the high-frequency plasma was set to 350 [W]
  • the substrate temperature was raised while supplying active nitrogen.
  • the N flux strength at this time was 5 X 10 _5 [torr].
  • the oxide film was evaporated, and the growth surface was observed by reflection-enhanced energy electron diffraction (hereinafter referred to as “RHEED”), confirming the surface reconstruction pattern of (1 X 1). Then, a small amount of Ga was supplied, the temperature was lowered to 700 [° C], and the (5 ⁇ 5) Ga surface was confirmed.
  • RHEED reflection-enhanced energy electron diffraction
  • Ga, N, and Mg are simultaneously supplied to form an N-polar p-GaN layer
  • the growth of 109 was started and the temperature was immediately raised to 800 [° C].
  • the N flux strength at that time was 8 X 10 _5 [torr].
  • the p-cladding and p-contact layers were grown in the (1 X 1) state.
  • the growth of the p-AlGaN cladding layer was performed at 870 [° C].
  • the substrate temperature was lowered to 300 [° C] after the growth was completed and the N supply was stopped, it was confirmed that the (3 X 3) N face could be obtained.
  • the p-concentration of the p-cladding layer was 6 X 10 17 [cm _3 ], the specific resistance of the p-cladding layer was 0.8 [Q cm], and the p-contact resistivity was 4 X 10 _5 [Q cm 2 ]. .
  • the MBE method since the MBE method is used, it is possible to sharply switch the supply of raw materials and dopants with a shirter while observing the growth surface with RHEED. Therefore, polarity inversion can be controlled and high-quality N-polar GaN crystals can be obtained immediately. In addition, optimization of growth temperature and nitrogen pressure is difficult. Furthermore, since NH and H are not used, hydrogen is taken into the crystal.
  • the MBE method since the MBE method is used, there is an advantage that the superlattice structure of the second cladding layer 110 in the short period can be accurately set.
  • the Mg distribution in the vicinity of the active layer can be controlled more rapidly than in the MOVPE method, which is advantageous for improving device characteristics and reliability.
  • the basic configuration of the second modification is the same as that of the first embodiment except for the following points. That is, in the first embodiment, all the semiconductor layers are formed by the MOVPE method, whereas in the first modification, all the semiconductor layers are manufactured by the MBE method. .
  • the temperature of the GaN (0001) substrate 100 is increased from 780 [° C] to 800 [° C] while supplying active nitrogen having a flux strength of 5 X 10 _5 [torr].
  • the acid capsule was evaporated.
  • the growth of n-GaN constituting the noffer layer 102 was started.
  • Si was used for n-GaN constituting the buffer layer 102 and the first SCH layer or n-AlGaN constituting the first cladding layer.
  • n-AlGaN constituting the first cladding layer 103 was grown at 870 [° C].
  • the InGaN layer composing the active layer 105 the In cell temperature was set to 740 [in] and the substrate temperature was set to 700 [° C].
  • the conditions for N can be the same.
  • the subsequent formation method of the laminated body is the same as the manufacturing method of Modification 1 described above.
  • the growth rate of the InGaN active layer does not decrease by adopting the MBE method for forming the stacked body. This is because the MBE method does not take in hydrogen, so there is no problem of inhibition of In uptake by hydrogen. Therefore, by using the MBE method, even a crystal having a high In composition can be obtained a high-quality crystal having a small In composition fluctuation.
  • FIG. 2 is a cross-sectional view of the nitride semiconductor laser 200 according to the second embodiment.
  • the same reference numerals as those described above are used, and description thereof is omitted.
  • an n-type GaN (0001) substrate 101 having a thickness of 110 [m] was used as the substrate.
  • the following layers are stacked as shown in FIG. That is, a quantum well comprising a buffer layer 102, a first cladding layer 103, a first SCH layer 104, and three layers. Active layer 105, OFP layer 106, second SCH layer 207, first superlattice cladding layer 208, polarity inversion layer 209, second superlattice cladding layer 210, and contact layer 111 are laminated in this order. (Hereinafter, these layers are collectively referred to as a laminate 250).
  • the first semiconductor layer according to the second embodiment is the first superlattice cladding layer 208
  • the second semiconductor layer is the second superlattice cladding layer 210.
  • the second SCH layer 207 is formed of a p-GaN (SCH) layer having a layer thickness of 80 [nm].
  • the first superlattice cladding layer 208 is composed of p- [GaN (2.5 [nm]) / AlGaN (2.5 [nm]) X 4] having a layer thickness of 20 [nm]. .
  • the polarity from the substrate 101 to the first superlattice cladding layer 208 is configured to be the Ga polarity 220 described above.
  • the polarity inversion layer 209 is composed of a Mg +: GaN layer having a layer thickness of 2 [nm] that is highly doped with an Mg concentration of 3 X 10 2G [cm- 3 ], and the second superlattice cladding layer 210 Ridge type p— [GaN (2.5 [nm]) ZAl Ga N (2.5 [nm]) X 120] with a layer thickness of 0.6 [/ ⁇ ⁇ ]
  • the polarity from the second superlattice cladding layer 210 to the contact layer 111 is configured to be N polarity 221.
  • a current confinement mask 113 and a P electrode 212 are formed on the top surface of the laminate 250.
  • An N electrode 114 is formed on the back surface of the n-GaN (0001) substrate 101.
  • the P electrode 212 is formed of 20 [nm] Pd and 20 [nm] Pt.
  • An ohmic contact was formed by performing a keyhole between 400 [° C] and 10 [min] in a nitrogen gas environment.
  • the second embodiment differs from the first embodiment in the following points. That is, in Embodiment 1 above, the polarity reversal interface was inside the SCH layer (the surface of the polarity reversal layer 108 formed on the second SCH layer 107) composed of p-GaN. However, the second embodiment is different in that the polarity inversion interface is inside the superlattice cladding layer (the surface of the polarity inversion layer 209 formed on the first superlattice cladding layer 208).
  • a force using an Mg monoatomic layer is used as the polarity inversion layer 108.
  • a Mg +: GaN layer having a layer thickness of 2 [nm] is used as the polarity inversion layer 209. The point is different.
  • Embodiment 1 above p-AlGaN is used as the second cladding layer.
  • the superlattice clad layer described above was used.
  • the average A1 concentration of the superlattice cladding layer is 0.07, which is the same as in the first embodiment.
  • the polarity of the superlattice cladding layer can be inverted through this polarity inversion layer.
  • the N-polarity second superlattice cladding layer 210 can be stacked on the Ga-polarity first superlattice cladding layer 208 via the polarity inversion layer 209. Since the second superlattice cladding layer 210 is N-polar, it is etched well by wet etching.
  • the first superlattice cladding layer 208 functions as an etching stop layer because it has Ga polarity. Therefore, by inverting the polarity of the superlattice cladding layer using the polarity inversion layer 209, the first superlattice cladding layer could be used as an etching stop layer.
  • the first superlattice cladding layer 208 serves as an etching stop layer, so that no crystal defects are generated.
  • the active layer 105 was not damaged during the regrowth without any defects diffusing.
  • a semiconductor element in which the mesa side was controlled with high precision could be obtained. As a result, the structure as designed was obtained.
  • the p-AlGaN (2.5 [nm]) of the superlattice cladding layer is used.
  • the effective carrier concentration of the p-clad can be increased to about IX 10 18 [cm _3 ]. For this reason, there is an advantage that the element resistance is reduced.
  • the p-electrode 212 can be in contact with the N-plane (N-polar surface), so that a p-contact is formed at a low mark temperature as in the first embodiment. be able to.
  • the contact surface since Pd is included as a constituent element of the layer electrode 212, if the contact surface is clean, it has a contact resistance of 10 _3 [ ⁇ « ⁇ 2 ] on the N plane. An electrode can be formed. This is because an alloy such as PdGa is formed at the contact interface.
  • the contact resistance is 10 _5 [Q cm 2 ] to 10 _4 [ ⁇ by a cable of 400 [° C] or less. ⁇ 2 ] level.
  • FIG. 3 is a cross-sectional view of the nitride semiconductor laser element 300 according to the third embodiment.
  • the dislocation density of the substrate is preferably 5 ⁇ 10 6 [cm — 2 ] or less.
  • the average dislocation interval is not strongly affected by dislocations of 5 [ ⁇ m] or more, so a flat growth surface can be obtained. It is.
  • the following layers are stacked as shown in FIG. That is, the first notch layer 302, the polarity inversion layer 303, the second buffer layer 304, the first cladding layer 305, the first SCH layer 306, the active layer 307, the OFP layer 308, and the second SCH layer 309
  • the superlattice cladding layer 310 and the contact layer 111 are laminated in this order (hereinafter, these layers are collectively referred to as a laminated body 350).
  • the first semiconductor layer in Embodiment 3 is the first buffer layer 302
  • the second semiconductor layer is the second buffer layer 304.
  • the first buffer layer 302 according to the third embodiment is made of n-GaN having a layer thickness of 0.2 [m].
  • the polarity inversion layer 303 is composed of an Mg monoatomic layer.
  • the polarity from the n-GaN (0001) substrate 301 to the first buffer layer 302 is configured to be Ga polarity 320.
  • the second buffer layer 304 is made of n-GaN having a layer thickness of 0.1 [m]
  • the first cladding layer 305 is made of n-AlGaN having a layer thickness of 1.5 [m]. It is configured.
  • SCH layer 306 is n-GaN, and active layer 307 is InGaN (2.5 [nm]) / GaN (10 [n
  • OFP layer 308 is composed of p—Al Ga
  • the second SCH layer is composed of p-GaN with a layer thickness of 100 [nm]. Furthermore, the superlattice cladding layer 310 is made of p-AlGa NZGaN with a layer thickness of 0.6 [m], and the contact layer 111
  • the second noffer layer 304 force is also configured so that the polarity up to the contact layer 111 is N polarity 321! RU
  • a buried layer 313 and a P-electrode 212 are formed on the upper surface of the laminate 350.
  • An N electrode 114 is formed on the back surface of the n-GaN (0001) substrate 301.
  • the buried layer 313 was formed by the following method. First, a striped SiO mask having a thickness of 300 [nm] is formed on an epoxy wafer, and wet etching is performed in the same manner as in the first embodiment. Perform. Then, on the first buffer layer 302, undoped i-Al Ga In N
  • the buried layer 313 was grown in a selected region, and a ridge mesa was buried.
  • the ridge width is 1.6 [m].
  • the buried layer 313 functions as a current constriction because of its high resistance. Further, since the buried layer 313 has a refractive index smaller than that of the active layer, it functions to confine light in the lateral direction.
  • the growth temperature can be lowered to 800 [° C.] or lower.
  • the growth temperature of the buried layer 313 is 780 [° C.].
  • the polarity of the notch layer can be inverted through this polarity inversion layer.
  • the N-polar second buffer layer 304 can be laminated on the Ga-polar first notch layer 302 via the polarity inversion layer 303 which is an Mg monoatomic layer.
  • the second buffer layer 304 and the layers from the first clad layer 305 to the contact layer 111 stacked on the second buffer layer 304 are N-polar, so that they are satisfactorily etched by wet etching.
  • the first buffer layer 302 is Ga-polar, it is not etched by wet etching. Therefore, by inverting the polarity of the buffer layer using the polarity inversion layer 303, the first buffer layer could be used as an etching stop layer. As a result, it has been possible to obtain a semiconductor element controlled with high accuracy.
  • the buried layer 313 can be buried and regrown using a low refractive index semiconductor at a growth temperature approximately equal to or lower than the growth temperature of the active layer. As a result, an embedded structure could be obtained without degrading the quality of the active layer.
  • the characteristics of the refractive index distribution and the gain distribution coincide with each other, so that the low threshold, the stable transverse mode at high output, and the heat dissipation are improved. Reliability was obtained. In addition, a long life could be realized.
  • the N-polar active layer had a flat interface, and the light emission efficiency was equivalent to that of the Ga-polar one.
  • FIG. 4 is a cross-sectional view of the nitride semiconductor laser according to the fourth embodiment.
  • an n-GaN (OOOl) substrate 101 having a layer thickness of 110 [/ ⁇ ⁇ ] was used.
  • the following layers are stacked as shown in FIG.
  • buffer layer 102, first cladding layer 103, first SCH layer 104, three-layer quantum well active layer 105, OFP layer 106, second SCH layer 107, polarity inversion layer 108, current A constricting layer 409, a superlattice cladding layer 410, and a contact layer 111 are laminated in this order (hereinafter, these layers are collectively referred to as a laminated body 450).
  • the first semiconductor layer is the second SCH layer 107
  • the second semiconductor layer is the current confinement layer 409.
  • the nitride semiconductor laser according to Embodiment 4 is of an internal current confinement type.
  • the current confinement layer 409 also has an n—In Al N force having a layer thickness of 80 [nm]. Also, superlattice class
  • the lead layer 410 is composed of p-AlGaN (2.5 [nm]) / p-GaN (2.5 [m] with a layer thickness of 0.5 [m].
  • the current confinement layer 409 is an N-polar crystal (the crystal plane direction is (000-1) plane), and the other stacked body 450 is a Ga-polar crystal.
  • the current confinement layer 409 is lattice-matched with p-AlGaN and has a concentration of 2 X 10 18 [cm_ 3 ].
  • the surface of the current confinement layer 409 is covered with a SiO insulating film,
  • a disc was formed. Then, it was immersed in a mixed solution of 150 [° C.] phosphoric acid sulfuric acid (2: 1) for 10 seconds. Thereafter, the N-polarity current confinement layer 409 under the surface of the stripe-shaped opening was removed by wet etching. The etching rate of the current confinement layer 409 was 1. Ot ⁇ m / min]. The surface after etching was flat, and the surface of the second SCH layer 107 was exposed. Due to the lateral etching, the opening width of the current confinement layer became larger than 1.4 [/ z m]. The insulating film (SiO 2) is removed with buffered hydrofluoric acid (BHF), and the current confinement is 1.7 [m]
  • Layer 409 was obtained. Then, using this current confinement layer 409 as a mask, the superconductivity is formed on the second SCH layer. The child cladding layer 410 was regrown.
  • the concentration of Si contained in the n-type InAIN layer constituting the current confinement layer 409 is a doping level, which is 5 or more orders of magnitude lower than the concentration of Si contained in the SiO mask. Therefore, high temperature
  • the p-AlGaN cladding layer is grown, the influence of Si contamination at the regrowth interface is small, and the operating voltage is hardly affected. If the mask thickness is 100 [nm] or less, the surface after embedding becomes almost flat.
  • the element surface after embedding the current confinement layer 409 was flat.
  • the pitch was 300 [m]
  • the chip was separated by placing a marking line parallel to the stripes using a graduation marking device. The resulting device was fused to the heat sink with the P electrode side down.
  • the semiconductor laser 400 manufactured in this way had a cavity length of 650 [m], a threshold current value of 40 [mA], and a good aspect ratio of 1.9.
  • the operating voltage at 40 [mA] was 4.5 [V]. This is thought to be due to the PdZPt P electrode 212 force 3 ⁇ 4 contact layer 411 formed over the entire surface, reducing the contact resistance, and the p-type superlattice cladding layer (Ga polarity) 410 reducing the hole barrier.
  • Ga polarity p-type superlattice cladding layer
  • the temperature change power of the oscillation wavelength is estimated at 70 [mW]
  • the temperature rise of the active layer is 15 [K] which is half of the current 30 [K] o
  • the polarity of the second SCH layer 107 and the current confinement layer 409 can be inverted via this polarity inversion layer.
  • the N-polarity current confinement layer 409 can be stacked on the Ga-polar second SCH layer 107 via the polarity inversion layer 108 as an Mg monoatomic layer.
  • Current confinement layer 409 Since N polarity, it is etched well by wet etching.
  • the second SCH layer 107 is not etched by wet etching because it has Ga polarity. Therefore, by inverting the polarity of the SCH layer using the polarity inversion layer 108, the second SCH layer 107 could be used as an etching stop layer.
  • the current confinement layer 409 is removed by wet etching, processing damage such as crystal defects does not occur in the active layer therebelow. Therefore, the high luminous efficiency of the active layer is maintained even after regrowth.
  • the InAIN composition is adopted as the current confinement layer 409 and the In composition ratio is about 0.2, a low refractive index can be realized. As a result, the laser light can be effectively confined by the active layer.
  • the current blocking effect is high because the InAIN layer is n-type. Note that the undoped InAIN layer has a high resistance and may be used.
  • the active layer was not damaged by wet etching.
  • the patterning of the current confinement layer 409 was performed with high accuracy. As a result, the structure as designed was obtained.
  • the n-type InAIN layer configured as the current confinement layer 409 is not a crystal like the conventional A1N layer, and is not a crystal. It has the characteristic that there is almost no lattice mismatch. Therefore, all problems caused by non-crystals are solved. Since the n-type InAIN layer of Embodiment 4 is flat, there is no current leakage. Since there are no dislocations due to the block layer, it does not limit the lifetime. The control of the stripe width of the opening also makes the waveguide loss very small due to scattering because the straight stripe is straight.
  • FIG. 13 shows the relationship between the band gap and the a-axis length in Al Ga In N mixed crystals.
  • the current confinement layer is In Ga Al N (where 0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1, 0 ⁇ X +
  • the current confinement layer 409 is InAlN, and the In group
  • the value of the composition X may be 0.05.X ⁇ X ⁇ 0.3. A more preferable range of the range of X is 0.1 ⁇ X ⁇ 0.25, and a more preferable range is 0.15 ⁇ X ⁇ 0.2.
  • the current confinement layer 40 9 is a lattice matching layer of (In Al) Ga N and the value of its Ga composition Z is 0.2 ⁇ Z ⁇ 1
  • FIG. 5 is a cross-sectional view of the nitride semiconductor laser according to the fifth embodiment.
  • an n-GaN (0001) substrate 101 having a layer thickness of l lO ⁇ m] was used as the substrate.
  • the following layers are stacked as shown in FIG. That is, the nofer layer 102, the first cladding layer 103, the first SCH layer 104, the quantum well active layer 105 that also has a three-layer force, the OFP layer 106, the second SCH layer 507, the polarity inversion layer 508, the current A constriction layer 409, a second lattice cladding layer 510, and a contact layer 111 are laminated in this order.
  • the first semiconductor layer is the second SCH layer 507
  • the second semiconductor layer is the current confinement layer 409.
  • the nitride semiconductor laser according to Embodiment 5 is of the internal current confinement type.
  • the second SCH layer is composed of p-GaN having a layer thickness of 50 [nm].
  • the polarity inversion layer 508 is composed of a Ga atomic layer containing 0.1 [%] Mg.
  • the third SCH layer 509 has a layer thickness P-GaN of 50 [nm] makes the current confinement layer (N polarity) 409 n-In with a layer thickness of 80 [nm]
  • the second cladding layer 510 is made of p—Al Ga N with a layer thickness of 0.5 [/ ⁇ ⁇ ].
  • the current confinement layer 409 of Embodiment 5 has an etching rate that is an order of magnitude higher than that of the third SCH layer 509, only the current confinement layer 409 can be selectively etched. Even if the third SCH layer 509 is etched, if the third SCH layer 509 is grown by the etched thickness during regrowth, the original thickness can be recovered. it can.
  • the polarity inversion layer 508 is composed of an atomic layer having a double layer force of Ga containing 0.1 [%] Mg.
  • Laminate 550 was manufactured by the manufacturing method described in Modification 1 above. In other words, the Ga polar crystal including the active layer was formed by the MOVPE method, and the polarity inversion layer and the subsequent N-polar crystal growth were formed by the MBE method.
  • a constriction layer (N polarity) 409 is obtained. If there is a part with a large In composition in the crystal, it will result in a loss of light absorption and the laser threshold will increase. However, in the manufacturing method of the fifth embodiment, an n-In Al N current confinement layer (N polarity) 409 having no blue light absorption loss can be obtained.
  • the polarity of the SCH layer can be inverted through this polarity inversion layer.
  • the N-polarity third SCH layer 509 can be stacked on the Ga-polarity second SCH layer 507 via the polarity inversion layer 508. Since the third SCH layer 509 is N-polar, it is etched well by wet etching. On the other hand, since the second SCH layer 507 is Ga-polar, it is not etched by wet etching. Therefore, by inverting the polarity of the SCH layer using the polarity inversion layer 508, the second SCH layer 507 could be used as an etching stop layer.
  • the active layer was not damaged by wet etching.
  • the current confinement layer 409 it was possible to form a pattern with high accuracy. As a result, it was possible to obtain the structure as designed.
  • the third SCH layer 509 and the second cladding layer 510 are in contact with each other, there is no hole injection barrier, and there is a feature of PdZPt on the N-polar p-GaN contact layer 111.
  • P electrode 21 In order to form 2 the p-contact voltage has small characteristics and characteristics.
  • FIG. 6 is a cross-sectional view of the nitride semiconductor light emitting device (LED) according to the sixth embodiment.
  • a substrate As the substrate, an n-type GaN (0001) substrate 101 having a thickness of 110 [/ z m] was used.
  • the following layers are stacked as shown in FIG.
  • the nofer layer 102, the first cladding layer 103, the first SCH layer 104, the single quantum well active layer 605, the OFP layer 606, the second SCH layer 607, the first contact layer 608, the polarity inversion A layer 609, a third SCH layer 610, and a second contact layer 611 are stacked in this order (hereinafter, these layers are collectively referred to as a stacked body 650).
  • the first semiconductor layer is the first contact layer 608, and the second semiconductor layer is the third SCH layer 610.
  • the active layer 605 of the single quantum well according to the sixth embodiment is composed of In Ga ON (2.5 [nm]).
  • the OFP layer 606 is a 10 nm thick p-A1 o
  • the second SCH layer 607 is composed of p-GaN with a layer thickness of 50 [nm].
  • the first contact layer 608 is made of p-GaN having a layer thickness of 20 [nm].
  • the polarity from the n — GaN (0001) substrate 101 to the first contact layer 608 is configured to be the Ga polarity 619 described above! Speak.
  • the polarity inversion layer 609 is composed of an Mg monoatomic layer.
  • the third SCH layer 610 is composed of p-GaN having a layer thickness of 230 [nm]
  • the second contact layer 611 is composed of p-GaN having a layer thickness of 20 [nm].
  • the polarities of the third SCH layer 610 and the second contact layer 611 are configured to be N polarities.
  • a transparent electrode 612 having a layer thickness of 70 [nm] is formed on the polarity inversion layer 609, the third SCH layer 610, and the second contact layer 611 as shown in FIG. .
  • a p-electrode 613 is formed on the left side of the transparent electrode 612 in the figure.
  • the transparent electrode 612 is a film in which ITO (refractive index 1.5) having a thickness of 50 [nm] is formed on Ni (l 0 [nm]) / Au (10 [nm]).
  • TiZPtZAu was used for the rho electrode 613.
  • Mg (magnesium) was used for the p-type punch.
  • Si was used as the n dopant.
  • the atomic concentration of Mg is l X 10 2G [cm _3 ] for the first contact layer 608 and the second contact layer 611, and 2 X 10 19 [cm _3 ] for the other, and the atomic concentration of Si is All were set to 2 X 10 18 [cm " d ].
  • the photonic crystal 614 formed on the top of the semiconductor element according to the sixth embodiment has a third SCH layer 610 and a second contact layer 611 that are processed into a cylindrical shape with a period b617 of 1.6. They are arranged two-dimensionally at triangular lattice positions at intervals of [m].
  • the height h615 of the cylinder composed of the third SCH layer 610 and the second contact layer 611 is 250 [nm]
  • the diameter a618 of the upper surface of the cylinder is 800 [nm].
  • the photonic crystal 614 is N-pole '.
  • FIG. 7 is a top view of the semiconductor element with a photonic crystal according to the sixth embodiment. Cylindrical photonic crystals are arranged in a triangular lattice arrangement 650 as shown in the figure.
  • FIG. 11 is a diagram for explaining the operation of the nitride semiconductor light emitting device according to the sixth embodiment.
  • the nitride semiconductor light emitting device of Embodiment 6 has a two-dimensional photonic crystal in which cylinders are arranged in a triangular lattice pattern on a p-contact layer.
  • the light emitted from the active layer 1200 can be extracted from the top surface only from the upper surface of the escape cone 1205 having a critical angle of 23.6 [°].
  • the critical angle 1206 is determined by the ratio of the refractive index 2.5 of GaN and the refractive index 1 of air. In this case, the extraction efficiency is as low as 8.3 [%].
  • the photonic crystal 614 When the photonic crystal 614 is present as in Embodiment 6, the sum of the wave vector kl 201 of light from the active layer and the diffraction vector d 1202 by the photonic crystal 614 due to the action of the two-dimensional diffraction grating.
  • the diameter a of the cylinder is optimized to 0.80 [/ ⁇ ⁇ ] and the period b is optimized to 1.6 [/ zm], and the critical angle is 42 [°] and the efficiency is 25 [%]. Was obtained. This efficiency is equivalent to three times 8.3 [%].
  • the LED of Embodiment 6 has a three-fold increase in efficiency compared to the conventional LED, which is about the same as or better than the luminous efficiency of fluorescent lamps. Since the LED of Embodiment 6 is manufactured by wet etching, it can be manufactured at low cost. Considering the lifetime and cost, the LED of Embodiment 6 can sufficiently replace the fluorescent lamp.
  • the emission wavelength peak of the semiconductor device configured as described above was 405 [nm].
  • the feature of Embodiment 6 is that the distance d from the active layer 705 to the surface of the first contact layer 608 is 9 It is as small as 0 [nm].
  • the optimum period b of the columnar photonic crystal at this time is 1.6 [ ⁇ m], and at this time, the light extraction efficiency of the semiconductor device according to the sixth embodiment has been maximized.
  • the light extraction efficiency of the semiconductor device of Embodiment 6 was about twice as large as that of the semiconductor device having a distance of 1 [; zm] from the active layer to the surface.
  • the reason why the distance from the active layer to the surface can be 0.2 [; z m] or less is that the manufacturing method of Embodiment 6 uses less etching damage and / or wet etching. Since the manufacturing method of Embodiment 6 has a complete etching stop layer, a p-electrode can be formed on the p-contact layer having a layer thickness of 20 [nm] and a high Mg concentration.
  • the emission wavelength peak of the semiconductor device of this Embodiment 6 shows remarkable emission efficiency up to 490 [nm] by increasing the In composition of the InGaN active layer and increasing the quantum well width to 3 [nm]. It was possible to change without degradation.
  • a 48 0 [nm] band LED that emits greenish blue light was also obtained.
  • FIG. 8 is a cross-sectional view of the nitride semiconductor light emitting device (LED) according to the seventh embodiment.
  • a substrate As the substrate, an n-type GaN (0001) substrate 101 having a thickness of 110 [/ z m] was used.
  • the following layers are laminated as shown in FIG.
  • the nofer layer 102, the first superlattice light reflecting layer 703, the first SCH layer 704, the single quantum well active layer 705, the OFP layer 706, the second SCH layer 707, and the first contact layer 708, a polarity inversion layer 709, a third SCH layer 710, and a second contact layer 711 are laminated in this order (hereinafter, these layers are collectively referred to as a laminate 750).
  • the first semiconductor layer is the first contact layer 708, and the second semiconductor layer is the third SCH layer 710.
  • the superlattice light reflecting layer 703 according to Embodiment 7 includes n- [GaN (32.2 [nm]) AlGaN (37 [nm])] (12 periods) having a layer thickness of 830 [nm]. It is composed of The first SCH
  • the layer consists of n-AlGaN with a layer thickness of 100 [nm], and the active layer 705 of a single quantum well is
  • So 706 is p-AlGaN with a thickness of 10 [nm]
  • the second SCH layer is p- with a thickness of 50 [nm].
  • Al Ga N force is also constructed. Furthermore, a first contact layer is formed on the layer with a thickness of 20 [ nm] p—AlGaN. N-GaN (0001) substrate 101
  • the first contact layer 708 is configured to have the above-mentioned Ga polarity 619.
  • the polarity inversion layer 709 is composed of an Mg monoatomic layer.
  • the third SCH layer 710 is a p-AlGaN layer with a layer thickness of 230 [nm], and the second contact layer 711 has a layer thickness of 20
  • the contact layer 711 has a polarity of N polarity! RU
  • a transparent electrode 612 having a layer thickness of 70 [nm] is formed on the polarity inversion layer 709, the third SCH layer 710, and the second contact layer 711 as shown in FIG. .
  • a p-electrode 613 is formed on the left side of the transparent electrode 612 in the drawing.
  • the third SCH layer 610 and the second contact layer 611 processed into a cylindrical shape have a period b617 of 1.6. They are arranged two-dimensionally at triangular lattice positions at intervals of [m].
  • the height h615 of the cylinder composed of the third SCH layer 710 and the second contact layer 711 is 250 [nm]
  • the diameter a618 of the upper surface of the cylinder is 800 [nm].
  • the photonic crystal 614 is N-pole '.
  • n-type superlattice light reflection layer 703 is 32.2 [11111] thick 0 &? ⁇ and 37 [11111] thick 8
  • the refractive indices of GaN and AlGaN are 2.70 and 2.35, respectively.
  • the 1Z4 wavelength in these crystals is 32.2 [nm] and 37.0 [nm], respectively.
  • the maximum reflectivity reached 95 [%] with a 12-period superlattice, and the width giving a reflectivity of 90 [%] or more was 40 [nm].
  • the strain of Al Ga N is equivalent to the strain of the Al Ga N cladding layer of 2.2 [zm].
  • the n-type superlattice light reflecting layer is composed of InGaN and AlGaN with a 1Z4 wavelength thickness, the amount of strain in the entire crystal can be reduced and higher reflectivity can be obtained with the same number of layers.
  • FIG. 12 shows an emission spectrum of the ultraviolet LED according to the seventh embodiment.
  • the peak wavelength of light emission at 25 [° C] and light output of 5 [mW] was 348 [nm], and 98 [%] of the light emission amount was within the wavelength width of 35 [nm].
  • the ultraviolet light emitted to the GaN substrate side is 90%.
  • UV LED can be used in a small and long-life exposure apparatus.
  • UV LED can be used as a light source for hardening kidnapping lamps, germicidal lamps and dental UV-curing resins.
  • Nitride LEDs can be used as detectors for blue light and ultraviolet light as they flow when they receive blue or ultraviolet light. Since flames contain more ultraviolet light than sunlight, a flame detector can be created by combining blue and ultraviolet LEDs to detect changes in the intensity ratio of blue and ultraviolet light. Can do.
  • FIG. 9 is a cross-sectional view of the high electron mobility transistor according to the eighth embodiment.
  • the high electron mobility transistor according to the eighth embodiment is a recess gate type high electron mobility transistor (HEM). T), and the following semiconductor layers are stacked on a semi-insulating SiC substrate 800. That is, a nucleation layer 801, a channel layer 802, a spacer layer 803, an electron supply layer 804, a polar half-rotation layer 805, and a contact layer 806 are laminated in this order.
  • the first semiconductor layer is the electron supply layer 804, and the second semiconductor layer is the contact layer 806.
  • the nucleation layer 801 is made of GaN having a layer thickness of 40 nm.
  • the channel layer 802 is made of i GaN (Ga polarity) having a thickness of 2.6 [m]
  • the spacer layer 803 is made of i A1 Ga N with a thickness of 5 [nm]
  • the electron supply layer 804 is made of a layer It is composed of n-AlGaN with a thickness of 15 nm.
  • the polarity from the nucleation layer 801 to the electron supply layer 804 is configured to be the Ga polarity described above.
  • the polarity inversion layer 805 is composed of an atomic layer composed of two layers of 0.1% Si-doped A1.
  • the contact layer 806 is composed of n-GaN having a layer thickness of 40 [nm]. This contact layer 806 is configured to be N-polar! RU
  • the semiconductor element according to the eighth embodiment includes a drain electrode 807, a source electrode 808, a recess gate electrode 809, and an element isolation layer 810.
  • the carrier concentration of the electron supply layer 804 is a 1 X 10 18 [cm_ 3]
  • the wire carrier rear concentration of the contact layer 806 is a 1 X 10 19 [cm _3] .
  • the above structure is grown on a semi-insulating SiC substrate 800 using MOVPE.
  • the nucleation layer 801 was formed by growing it in a relatively low temperature environment of 500 [° C.].
  • the channel layer 802 was grown at 1000 [° C.] and the spacer layer 803 was grown at 1080 [° C.] to form the layer.
  • the polarity inversion layer 805 was formed by setting the growth temperature to 850 [° C], decreasing the ammonia flow rate, and supplying the A1 raw material by the thickness of the bimolecular layer by estimating the growth rate while flowing disilane. Thereafter, the contact layer 806 was grown while the growth temperature was raised to 950 [° C].
  • the channel depth h from the contact surface of the recess gate electrode 809 to the interface between the i-GaN (Ga polarity) channel layer 802 and the spacer layer 803 is 20 [nm].
  • the element isolation layer 810 is covered with a photoresist in other regions, and nitrogen with ion energy of 20 [keV] and 100 [keV] is applied. The ion implantation was performed twice to form. The injection volume is 10 [cm].
  • the drain electrode 807 and the source electrode 808 were Ti (25 [nm]) / Al (150 [nm]), and they were made ohmic by carrying out a 30 second roll at 600 [° C].
  • the contact resistance on the contact layer 806 is 5 ⁇ 10 _6 [Q cm 2 ], which is one digit lower than that formed on n- AlGaN .
  • the n-GaN (N-polarity) layer 806 is etched by wet etching of phosphoric acid sulfuric acid to expose the surface of the electron supply layer 804, and a recess gate electrode 809 is formed thereon. It was formed by vapor deposition. The distance between the source and the drain was 3 [m].
  • the gate electrode 809 is Ni (20 [nm]) ZAu (130 [nm]), and the gate length is 0.2 [/ ⁇ ⁇ ].
  • the polarity inversion layer 805 may be left during wet etching, it is preferable to remove the polarity inversion layer 805 and directly contact the electron supply layer 804 and the gate electrode 809 LV. This is because the Schottky barrier can be set high.
  • the obtained device showed a high characteristic of a maximum transconductance of 550 [mS / mm] and a maximum drain current IDS of 1.3 [AZmm] at a gate voltage of 4 [V] and 25 [° C]. .
  • FIG. 10 is a cross-sectional view of the high electron mobility transistor according to the ninth embodiment.
  • the high electron mobility transistor of Embodiment 9 is a recessed gate type high electron mobility transistor (HEM T), and the following layers are stacked on a semi-insulating GaN substrate 900 having a layer thickness of 110 [ ⁇ m]. ⁇ . That is, a nofer layer 901, a channel layer 802, a spacer layer 803, an electron supply layer 804, a polarity inversion layer 805, a source layer, and a contact layer 806 forming a drain region are laminated in this order.
  • the nitride semiconductor element includes a drain electrode 807, a source electrode 808, a recess gate electrode 809, and an element isolation layer 810.
  • the first semiconductor layer is the electron supply layer 804, and the second semiconductor layer is the contact layer 806.
  • the buffer layer 901 is composed of iGaN having a layer thickness of 100 [nm].
  • the polarity from the buffer layer 901 to the electron supply layer 804 is the Ga polarity described above. It is configured as follows.
  • Semi-insulating GaN substrate 900 is a substrate in which Fe, Ni, or platinum-based metal is doped on GaN at a concentration of about 1 X 10 18 [cm "3]. Not included! /, High-resistance GaN substrate
  • the other structure has the structure described in Embodiment 8.
  • the GaN crystal of the semi-insulating GaN substrate 900 is lattice-matched. A flat interface with high quality is obtained, resulting in high electron mobility.
  • the 400 [nm] band can be used for optical discs, and the 480 [nm] band can be substituted for an argon / gas laser.
  • the 400 nm band is mainly used for illumination light sources.
  • Other applications include UV light sources, full-color display light sources, and 480 [nm] band fishlight source.
  • Heterojunction field-effect transistors can be used as microwave power transmitters in third-generation mobile phone base stations and high-efficiency amplifiers in subscriber wireless access and satellite Internet access. .

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Abstract

A semiconductor device capable of enhancing reliability at the time of output operation while reducing the fabrication cost. The nitride semiconductor device comprising a substrate (101), and a plurality of semiconductor layers formed on the substrate (101) is provided with at least one multilayer body consisting of a first semiconductor layer (107) formed on the substrate (101), a polarity reversal layer (108) formed directly on top of the first semiconductor layer (107), and a second semiconductor layer (109) formed directly on top of the polarity reversal layer (108) and patterned. The second semiconductor layer (109) is arranged with a polarity to be etched by wet etching and the first semiconductor layer (107) is arranged with a polarity to be an etching stopper layer by wet etching of the second semiconductor layer (109).

Description

窒化物半導体素子、及びその製造方法  Nitride semiconductor device and manufacturing method thereof
技術分野  Technical field
[0001] 本発明は、半導体レーザ、発光素子、発光ダイオード等の窒化物半導体素子、及 びその製造方法に関する。  The present invention relates to a nitride semiconductor device such as a semiconductor laser, a light emitting device, and a light emitting diode, and a method for manufacturing the same.
背景技術  Background art
[0002] 従来より、窒化物半導体素子の構造や製造方法ついて、さかんに研究開発が続け られている。とりわけ、 GaN系の窒化物半導体発光素子は、次世代の照明や半導体 レーザなどの用途への実用化に向けて研究開発が進められて!/、る。  [0002] Conventionally, research and development has been continued on the structure and manufacturing method of nitride semiconductor devices. In particular, GaN-based nitride semiconductor light-emitting devices are being researched and developed for practical use in applications such as next-generation lighting and semiconductor lasers!
[0003] 図 15は、第 1の従来例に係るリッジ型の GaN系の半導体レーザの断面図である（ 非特許文献 1)。この半導体レーザ 2000は、同図に示すように、サファイア基板 200 1上【こ、 0. 5 [ /ζ πι] η¾Ε]^Ο— Ο&Νϋ2002、 1. 0[ ,u m] ( n-AlGaNji2003, 0. 1 [； z m]の n— GaNガイド層 2004、 Ga In N (3. 5 [nm]) /Ga In N  FIG. 15 is a cross-sectional view of a ridge-type GaN-based semiconductor laser according to a first conventional example (Non-Patent Document 1). As shown in the figure, the semiconductor laser 2000 is formed on a sapphire substrate 200 1 [0.5 [/ ζ πι] η¾Ε] ^ Ο— Ο & Νϋ2002, 1.0 [, um] (n-AlGaNji2003, 0. 1 [; zm] n—GaN guide layer 2004, Ga In N (3.5 [nm]) / Ga In N
0. 90 0. 10 0. 98 0. 02 0. 90 0. 10 0. 98 0. 02
(7. 0[nm])の 3層量子井戸活性層 2005、 20[nm]の p— Al Ga N層 2006、 (7.0 [nm]) 3-layer quantum well active layer 2005, 20 [nm] p-AlGaN layer 2006,
0. 16 0. 84  0. 16 0. 84
0. 1 [ /ζ πι]の p— GaNガイド層 2007、 0. 5 [ /z m]の p— [GaN (2. 5 [nm]) /Al  0.1 [/ ζ πι] p— GaN guide layer 2007, 0.5 [/ z m] p— [GaN (2.5 [nm]) / Al
0. 1 0. 1
Ga N (2. 5 [nm] ) X 100]の超格子クラッド層 2008、 0. 1 [ m]の p— GaN層 2Ga N (2.5 [nm]) X 100] superlattice cladding layer 2008, 0.1 [m] p-GaN layer 2
5 0. 85 5 0. 85
009、 PdZPtZAu—電極 2010、電流狭窄用 SiOマスク層 2011、 Ti/Pt/Au- 009, PdZPtZAu—Electrode 2010, SiO mask layer for current confinement 2011, Ti / Pt / Au-
2 2
n電極 2012を備えている。  Equipped with n-electrode 2012.
[0004] この半導体レーザ 2000の p層は、反応性イオンエッチング（以下、「RIE」と略記す る）によりメサ幅 2. 3 [ m]のリッジストライプ形状にカ卩ェされている。メサ脇の p層の 厚さは、横方向の光閉じ込めのために 0. 15 [ m]に調整されている。リッジストライ プの両側は、 SiOで覆われている。 n電極 2012は、 RIEで n— GaN層 2002までをド [0004] The p layer of this semiconductor laser 2000 is covered in a ridge stripe shape with a mesa width of 2.3 [m] by reactive ion etching (hereinafter abbreviated as “RIE”). The thickness of the p-layer beside the mesa is adjusted to 0.15 [m] for lateral light confinement. Both sides of the ridge stripe are covered with SiO. For n-electrode 2012, the n-GaN layer up to 2002 was deposited by RIE.
2  2
ライエッチングして、 n— GaN層の表面上に蒸着して形成されている。半導体レーザ の厚みは 100 [ m]で、共振器長は 600 [ m]である。この半導体レーザにおいて 、 50 [°C]の環境下、 30 [mW]の出力で 1000時間の寿命を報告している。  It is formed by ly etching and vapor-depositing on the surface of the n-GaN layer. The thickness of the semiconductor laser is 100 [m] and the cavity length is 600 [m]. This semiconductor laser has reported a lifetime of 1000 hours at an output of 30 [mW] in an environment of 50 [° C].
[0005] 半導体素子における半導体層の加工方法として、ウエットエッチング法が知られて いる。半導体層の構成層の一つであり、発光層である活性層に加工損傷を与えない ため、最も優れたカ卩ェ方法といえる。 A wet etching method is known as a method for processing a semiconductor layer in a semiconductor element. It is one of the constituent layers of the semiconductor layer and does not damage the active layer that is the light emitting layer. Therefore, it can be said that it is the most excellent cache method.
しかしながら、 GaN系の半導体素子では、上記ウエットエッチング法ではエッジ形 状などにカ卩ェすることができないという問題がある。通常、ェピ層表面が不活性な (0 001)面であるためである。そこで、ェピ層表面を（0001)面ではなぐ（000— 1)面 のものを用いて、ウエットエッチング法を行う方法が考えられる。しかしながら、（000 1)面を用いると、有機金属気相薄膜成長法 (以下、「MOVPE法」と略記する)で GaN基板上に InAlGaN系材料を成長させる場合、原子レベルで平坦な成長を行う ことが難しい。そのため、活性層の光学的品質が（0001)面を用いたものに比して劣 るという問題がある。従って、これまで GaN系の半導体素子では、ドライエッチング法 あるいは選択成長法を用いて、光導波路構造や電流狭窄構造などを形成して!/ヽた。  However, the GaN-based semiconductor device has a problem that it cannot be formed into an edge shape by the wet etching method. This is because the epilayer surface is usually an inactive (0 001) plane. Therefore, a method of performing a wet etching method using a (000-1) plane with the epilayer surface not the (0001) plane is conceivable. However, when the (000 1) plane is used, when an InAlGaN-based material is grown on a GaN substrate by a metal organic vapor phase thin film growth method (hereinafter abbreviated as “MOVPE method”), flat growth is performed at the atomic level. It is difficult. Therefore, there is a problem that the optical quality of the active layer is inferior to that using the (0001) plane. Therefore, so far, GaN-based semiconductor devices have been formed using optical etching structures or current confinement structures using dry etching or selective growth.
[0006] 上記問題点を解決すベぐウエットエッチングが可能な窒化物半導体レーザに関す る技術が提案されている（以下、「第 2の従来例」という）（特許文献 1)。この第 2の従 来例の窒化物半導体レーザは、内部型の電流狭窄層を備えている。この電流狭窄 層は、 400 [°C]〜600 [°C]の低温で堆積させた厚さ 10 [nm]〜80 [nm]の非晶質 の A1N層により構成されている。この第 2の従来例によれば、電流狭窄層のパター- ングをウエットエッチングにより行うことが可能であるとしている。 [0006] A technique related to a nitride semiconductor laser capable of wet etching that solves the above problems has been proposed (hereinafter referred to as "second conventional example") (Patent Document 1). This second conventional nitride semiconductor laser has an internal current confinement layer. This current confinement layer is composed of an amorphous A1N layer having a thickness of 10 nm to 80 nm deposited at a low temperature of 400 [° C] to 600 [° C]. According to the second conventional example, the current confinement layer can be patterned by wet etching.
[0007] 半導体発光素子 (LED)においては、光の取り出し効率の向上が重要である。  [0007] In semiconductor light emitting devices (LEDs), it is important to improve light extraction efficiency.
従来例として、光の取り出し効率の向上が可能な半導体発光素子に関する技術が 提案されている (以下、「第 3の従来例」という）（非特許文献 2)。  As a conventional example, a technique related to a semiconductor light emitting device capable of improving the light extraction efficiency has been proposed (hereinafter referred to as “third conventional example”) (Non-patent Document 2).
第 3の従来例は、フォトニック結晶を用いて、光の取り出し効率の向上を図ったもの である。波長 1. 5 [ /ζ πι]帯の InGaAsP系材料の半導体発光素子で 2次元の表面回 折格子フォトニック結晶を取り付けて、 LEDの光の取り出し効率の向上を実証してい る。この半導体発光素子に用いられる表面回折格子フォトニック結晶は、半導体発光 素子の活性層の上部に、深さ 0. 6 [ m]、直径 1 [； z m]の円筒形の孔を三角格子状 に約 2[ m]周期で 2次元配列させて作製されているものである。  The third conventional example uses a photonic crystal to improve the light extraction efficiency. A semiconductor light-emitting device with an InGaAsP-based material with a wavelength of 1.5 [/ ζ πι] band is attached to a two-dimensional surface-diffractive lattice photonic crystal to demonstrate improved LED light extraction efficiency. The surface diffraction grating photonic crystal used in this semiconductor light emitting device has a triangular lattice with a cylindrical hole with a depth of 0.6 [m] and a diameter of 1 [; zm] above the active layer of the semiconductor light emitting device. It is produced by two-dimensional arrangement with a period of about 2 [m].
[0008] GaN系の半導体素子は、電子デバイスへの応用も進められている。 GaNは Siの 1 0倍の破壊電圧と、 Siの 2. 5倍の飽和電子速度を有するため、高周波'高耐圧動作 の電力素子への応用が可能である。 AlGaNZGaNのへテロ構造では高電子移動 度の 2次元電子ガスが生成され、それをチャネル電子として利用する高電子移動度ト ランジスタ (HEMT)が得られる。さらに結晶歪によって発生するピエゾ効果によって 、 2次元電子ガスの濃度は GaAs系 HEMTの 10倍になり、高い相互コンダクタンス特 性や高周波動作が期待できる。中でも AlGaNZGaNのリセスゲート構造は、ソース 電極とドレイン電極力 SGaN層にォ一ミックに接触した構造のため、寄生抵抗を小さく 保ったまま、 A1濃度を上げて高濃度の 2次元電子ガスを形成することができる利点を 有する。 [0008] GaN-based semiconductor elements are also being applied to electronic devices. Since GaN has a breakdown voltage 10 times that of Si and a saturation electron velocity 2.5 times that of Si, it can be applied to high-frequency, high-voltage operation power devices. High electron transfer in AlGaNZGaN heterostructure A high electron mobility transistor (HEMT) is obtained that produces a two-dimensional electron gas of a certain degree and uses it as channel electrons. Furthermore, due to the piezo effect generated by crystal distortion, the concentration of the two-dimensional electron gas is 10 times that of GaAs HEMT, and high transconductance characteristics and high-frequency operation can be expected. Among them, the AlGaNZGaN recess gate structure is a structure in which the source electrode and drain electrode force are in ohmic contact with the SGaN layer, so that the A1 concentration is increased to form a high-concentration two-dimensional electron gas while keeping the parasitic resistance small. Has the advantage of being able to
[0009] 従来例として、 GaN系の半導体素子を電子デバイスに応用した例を説明する（以 下、「第 4の従来例」という）（非特許文献 3)。図 16は、第 4の従来例に係る GaN系の 半導体レーザーダイオードの断面図である。同図に示すように、リセスゲート型 HEM Tは、（0001)面のサファイア基板 2101、 30[nm]厚の GaN核形成層 2102、 2. 5 [ μ m]厚のアンド—プの i— GaNバッファ層 2103、 10[nm]厚のアンド—プの i— A1  [0009] As a conventional example, an example in which a GaN-based semiconductor element is applied to an electronic device will be described (hereinafter referred to as "fourth conventional example") (Non-patent Document 3). FIG. 16 is a cross-sectional view of a GaN-based semiconductor laser diode according to a fourth conventional example. As shown in the figure, the recess gate type HEM T is composed of a (0001) sapphire substrate 2101, a 30 [nm] thick GaN nucleation layer 2102, and a 2.5 [μm] thick i-GaN. Buffer layer 2103, 10 [nm] thick and i-A1
0. 0.
Ga Nスぺーサ層 2104、 Siドーピング濃度 1 X 1018[cm_3]の 20[nm]厚の n—Ga N spacer layer 2104, Si doping concentration 1 X 10 18 [cm_ 3 ], 20 [nm] thick n—
26 0. 74 26 0. 74
Al Ga N層 2105、 Siドーピング濃度 l X 1019[cm_3]の 20[nm]厚の n— GaAl Ga N layer 2105, Si doping concentration l X 10 19 [cm_ 3 ] 20 [nm] thick n-Ga
0. 26 0. 74 0. 26 0. 74
N層 2106、 Ti(25 [nm]) ZAl (150[nm])のドレイン電極 2107、Ti (25 [nm]) Z Al ( 150 [nm] )のソース電極 1108、 Pt ( 10 [nm] ) /Ti (40 [nm] ) /Au (100 [nm] )ゲート電極 2109からなる。  N layer 2106, Ti (25 [nm]) ZAl (150 [nm]) drain electrode 2107, Ti (25 [nm]) Z Al (150 [nm]) source electrode 1108, Pt (10 [nm]) / Ti (40 [nm]) / Au (100 [nm]) gate electrode 2109.
[0010] スぺーサ層 2104は、チャネル層の 2次元電子のクーロン散乱を低減させるために 設けられている。ゲートリセスのエッチングは、 BC1プラズマを用いた反応性イオンェ [0010] Spacer layer 2104 is provided to reduce Coulomb scattering of two-dimensional electrons in the channel layer. The gate recess etching is performed by reactive ion etching using BC1 plasma.
3  Three
ツチング (RIE)により行っている。エッチング時のチャンバ圧力は 3 [Pa]、高周波電 力は 10[W]である。リセスエッチングの深さは 30 [nm]である。 Ti (25 [nm]) /Al(l 50 [nm])のドレイン電極 2107及びソース電極 2108のォ一ミックコンタクトは、 900[ °C]で 60秒間の熱処理で得た。ゲート長は 2. 1 [ /ζ πι]、幅は 15 [ /ζ πι]、ソースとドレ イン間の長さは 10 [ m]である。ゲ一トに正の電圧をかけるとソ一スとドレイン間の電 流 IDSがドレイン電圧に比例して増加し、飽和する I—V特性が得られる。 4. 6 [K]で シ―トキャリア密度 4. 8 X 1012 [cm—2]での 2次元電子ガスの移動度は 9260 [cm2Z Vs]であった。 25 [°C]での最大相互コンダクタンスは 146 [mSZmm]、 IDSは 900[ mAz mm]であつ 7こ。 [0011] なお、後述する課題を解決する手段で限定する「極性制御」に関する従来技術が 特許文献 2及び特許文献 3に記載されている。これらについては、後述する。 This is done by tsuching (RIE). The chamber pressure during etching is 3 [Pa], and the high-frequency power is 10 [W]. The depth of the recess etching is 30 [nm]. The ohmic contacts of the drain electrode 2107 and the source electrode 2108 of Ti (25 [nm]) / Al (l 50 [nm]) were obtained by heat treatment at 900 [° C.] for 60 seconds. The gate length is 2.1 [/ ζ πι], the width is 15 [/ ζ πι], and the length between the source and drain is 10 [m]. When a positive voltage is applied to the gate, the source-drain current IDS increases in proportion to the drain voltage, and a saturated IV characteristic is obtained. At 6 [K], the sheet carrier density at 4.8 X 10 12 [cm- 2 ] was 9260 [cm 2 Z Vs]. The maximum transconductance at 25 [° C] is 146 [mSZmm] and IDS is 900 [mAz mm]. [0011] Note that Patent Document 2 and Patent Document 3 describe conventional techniques related to "polarity control" limited by means for solving the problems described later. These will be described later.
非特許文献 1：「GaN系高出力の青紫色レーザダイオード」ジャパニーズ 'ジャーナル 'ォブ 'アプライド 'フィジックス誌 2001年 40卷 3206〜3210頁  Non-patent document 1: "GaN-based high-power blue-violet laser diode" Japanese 'Journal' Ob 'Applied' Physics magazine 2001 40 pp. 3206-3210
非特許文献 2：「2次元の表面回折格子フォトニック結晶を備えた発光ダイオードにお ける効率増加」 アプライド 'フィジックス 'レター誌 2004年 84卷 457〜459頁 非特許文献 3：「サファイア上のリセスゲート AlGaNZGaN変調ドープ電界効果トラン ジスタ」 アプライド 'フィジックス'レター誌 2000年 76卷 121〜123頁 特許文献 1 :特開 2002— 314203号公報  Non-Patent Document 2: “Increased Efficiency in Light-Emitting Diodes with Two-Dimensional Surface Grating Photonic Crystals” Applied 'Physics' Letter magazine, 2004, 84 pp. 457-459 AlGaNZGaN modulation-doped field-effect transistor "Applied 'Physics' Letter, 2000, 76-121-123 Patent Document 1: JP 2002-314203
特許文献 2：特開 2001— 148532号公報  Patent Document 2: Japanese Patent Laid-Open No. 2001-148532
特許文献 3：特表 2003 - 527745号公報  Patent Document 3: Japanese Patent Publication No. 2003-527745
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0012] 近年の技術の発展に伴い GaN系の半導体素子（以下、「LED」とも言う）は、様々 な分野でその実用化が期待されている。例えば、光ディスク用の半導体レーザーダイ ォ―ド (以下、「LD」と略記する）光源への実用化が期待されている。そのためには、 半導体発光素子の（1)出力動作時の信頼性を高めること、（2)低コストィ匕を実現する ことが極めて重要な課題である。上記（1)の出力動作時の信頼性を高めるためには 、発光層である活性層に結晶欠陥や損傷を生じさせない加工技術が必要である。上 記（2)の低コストィ匕を実現するためには、素子歩留まりの高 、加工技術が必要である With the recent development of technology, GaN-based semiconductor elements (hereinafter also referred to as “LEDs”) are expected to be put to practical use in various fields. For example, it is expected to be put to practical use as a semiconductor laser diode (hereinafter abbreviated as “LD”) light source for optical disks. For this purpose, it is extremely important to (1) improve the reliability of the semiconductor light emitting device during output operation, and (2) realize low cost. In order to improve the reliability during the output operation described in (1) above, a processing technique that does not cause crystal defects or damage in the active layer that is the light emitting layer is required. In order to realize the low cost (2) above, high device yield and processing technology are required.
[0013] GaN系の半導体素子は、照明への実用ィ匕も期待されている。とりわけ、 GaN系の 半導体発光素子 (LED)を用いた白色発光素子は、蛍光灯の代替照明として大きな 市場が期待されている。しかしながら、照明として実用化するためには、（3)活性層に お!、て高 、発光効率を得ること、（4)光取り出し効率を向上させることが重要な課題 となっている。現在、そのための研究開発が続けられているところである。 [0013] GaN-based semiconductor elements are also expected to be practical for illumination. In particular, white light-emitting elements using GaN-based semiconductor light-emitting elements (LEDs) are expected to have a large market as alternative lighting for fluorescent lamps. However, in order to put it into practical use as illumination, it is important to (3) obtain high luminous efficiency in the active layer and (4) improve light extraction efficiency. Currently, research and development for this purpose is ongoing.
[0014] ところが、上記第 1〜4の従来例においては、以下のような問題点があった。  However, the first to fourth conventional examples have the following problems.
第 1従来例の半導体レーザにおける第 1の問題点は、ドライエッチング法ではリッジ の深さの高精度な制御ができない点である。このため、高い歩留まりが得られない。 通常用いられるメサ幅 1. 7 [ m]の場合、半導体レーザに要求される 8 [° ]以上 の水平放射角と 50 [mW]以上のキンクレベルを実現するには、リッジの深さを士 5 [n m]の高い精度で制御する必要がある。その理由は、以下の通りである。まず、このレ ザは実屈折率ガイド構造であり、横方向の光閉じ込めを強くするために横方向の 屈折率差 Anを大きくすると、容易に高次モードが発生し、電流電圧特性にキンクが 生じる。 Anを小さくすると光閉じ込めが弱くなり、水平放射角が減少するため、光ス ポットのアスペクト比が増大してしまう。 LDに要求される 8[° ]以上の水平放射角と 5 0[mW]以上のキンクレベルを実現する Δηの範囲は、 0. 0068≤Δη≤0. 0072と 非常に狭くなる。これは、リッジの深さを ±5 [nm]の高い精度で制御することに相当 するのである。 The first problem with the semiconductor laser of the first conventional example is that the dry etching method uses a ridge. This is the point that the depth of the head cannot be controlled with high accuracy. For this reason, a high yield cannot be obtained. In the case of a mesa width of 1.7 [m], which is normally used, the depth of the ridge must be adjusted to achieve the horizontal emission angle of 8 [°] or higher and the kink level of 50 [mW] or higher required for semiconductor lasers. It is necessary to control with high accuracy of 5 [nm]. The reason is as follows. First, this laser has an actual refractive index guide structure, and if the lateral refractive index difference An is increased in order to strengthen the lateral optical confinement, a higher-order mode is easily generated, and the current-voltage characteristics are kinked. Arise. If An is made smaller, the optical confinement becomes weaker and the horizontal radiation angle decreases, which increases the aspect ratio of the light spot. The range of Δη that realizes the horizontal radiation angle of 8 [°] or more and the kink level of 50 [mW] or more required for LD is very narrow as 0.0068≤Δη≤0.0072. This is equivalent to controlling the ridge depth with high accuracy of ± 5 [nm].
結局、ドライエッチング法では、損失の小さい実屈折率ガイド構造である限りこのよう な高精度の膜厚制御は難しい。そして、膜厚の面内分布を考慮すると、高い歩留まり は望めない。  After all, in the dry etching method, it is difficult to control the film thickness with such high accuracy as long as the actual refractive index guide structure has a small loss. Considering the in-plane distribution of film thickness, a high yield cannot be expected.
[0015] 第 1の従来例の半導体レーザにおける第 2の問題点は、ドライエッチング時の損傷 が素子寿命を低下させる点である。この原因は、 2つある。第 1の原因は、ドライエツ チングの損傷力 サストライプの側面に入り、 pクラッド層が高抵抗ィ匕するために、動 作電圧が上昇することに起因する。第 2の原因は、ドライエッチングの損傷が活性層 に及ぶと、活性層に非発光センタが導入され、素子の電流閾値と動作電流が上昇す ることに起因する。素子寿命は、動作電流と動作電圧に強く依存しているためである 。特に電流狭窄に優れた内部電流狭窄型の半導体素子においては、活性層への損 傷が大きぐ素子寿命の低下が顕著となる。  [0015] A second problem with the semiconductor laser of the first conventional example is that damage during dry etching reduces the device lifetime. There are two reasons for this. The first cause is that the operating voltage rises due to the high resistance of the p-cladding layer which enters the side of the dry etching damage stripe. The second cause is that when the dry etching damage reaches the active layer, a non-emission center is introduced into the active layer, and the current threshold and operating current of the device rise. This is because the element lifetime is strongly dependent on the operating current and operating voltage. In particular, in an internal current confinement type semiconductor device excellent in current confinement, the damage to the active layer is large, and the device life is significantly reduced.
[0016] 第 1の従来例の半導体レーザにおける第 3の問題点は、ドライエッチング装置の状 態を安定に保つのが難 Uヽ点である。  [0016] A third problem in the first conventional semiconductor laser is that it is difficult to keep the state of the dry etching apparatus stable.
ドライエッチング装置はマスク材カ の酸ィ匕物汚染、電極からの金属汚染、レジスト 力 の有機物汚染などの影響を受ける。その理由は、それらの汚染物質が装置内に 持ち込まれ、ドライエッチング後に装置内壁に付着し、次のエッチング時に汚染物質 が離脱して、ウェハに付着するからである。その結果、リッジメサ形状の不良や加工 損傷による信頼性の低下が発生しやすぐ高い素子歩留まりを維持するのが難しい。 The dry etching system is affected by acid contamination of the mask material, metal contamination from the electrode, and organic contamination of the resist power. The reason is that these contaminants are brought into the apparatus and adhere to the inner wall of the apparatus after dry etching, and the contaminants are detached and adhered to the wafer at the next etching. As a result, ridge mesa shape defects and processing It is difficult to maintain high device yield as soon as reliability is reduced due to damage.
[0017] 一方、ドライエッチング以外にメサ脇の厚さを制御する方法として選択成長法がある 。し力しながら、選択成長法は、上記問題点はないものの実用化が困難である。それ は、 GaNの高温成長のために、 SiOなどのマスク材から蒸発した Siや酸素などの不  On the other hand, there is a selective growth method as a method for controlling the thickness of the mesa side other than the dry etching. However, although the selective growth method does not have the above problems, it is difficult to put it into practical use. This is because of the high temperature growth of GaN, such as Si and oxygen evaporated from the mask material such as SiO.
2  2
純物が再成長界面に堆積し、素子の動作電圧を安定に制御できな!ヽからである。  This is because the pure material is deposited on the regrowth interface and the operating voltage of the device cannot be stably controlled.
[0018] 第 2の従来例に係る内部電流狭窄型の窒化物半導体レーザに関しても多くの課題 力 Sある。内部電流狭窄層たる非晶質の A1N層は、平坦な膜を得るのが難しぐ表面 が凸凹になりやすい。再成長中に非晶質の A1N層は、結晶化して GaNとの格子不 整合を生じ、周囲の結晶に欠陥や転位を多く発生させて素子寿命を制限する。 A1N 層の厚さを大きくすると転位が増加し、 A1N層の厚さを小さくすると、凹部から電流リ —クが発生する。また、非晶質 A1Nマスクのため、開口部の AlGaNクラッド層の A1組 成の制御や Mg濃度の制御が不安定である。さらに、 A1Nマスクは、非晶質のため、 膜質が不均一になりやすぐウエットエッチングで形成したストライプが直線ではなく て、その幅が揺らいだり、ストライプ幅が設計値より大きくなる。それによつて、高出力 動作時に所望の光スポット形状が得られな 、、光の導波損失が増加して電流閾値が 上昇する、などの問題が生じる。  [0018] The nitride semiconductor laser of the internal current confinement type according to the second conventional example has many problems. The amorphous A1N layer, which is the internal current confinement layer, tends to have uneven surfaces that make it difficult to obtain a flat film. During the re-growth, the amorphous A1N layer crystallizes and causes lattice mismatch with GaN, which causes many defects and dislocations in the surrounding crystals, limiting the device lifetime. When the thickness of the A1N layer is increased, dislocation increases, and when the thickness of the A1N layer is decreased, a current leak is generated from the recess. Also, because of the amorphous A1N mask, the control of the A1 composition of the AlGaN cladding layer in the opening and the control of the Mg concentration are unstable. Furthermore, since the A1N mask is amorphous, the film quality becomes non-uniform and the stripe formed by wet etching is not straight, and its width fluctuates and the stripe width becomes larger than the design value. As a result, problems such as the fact that the desired light spot shape cannot be obtained during high-power operation, the waveguide loss of light increases, and the current threshold value rises arise.
[0019] 第 3の従来例に関しても以下のような問題点がある。  [0019] The third conventional example also has the following problems.
取り出し効率をさらに向上させるためには、表面回折格子フォトニック結晶と活性層 の距離を近づけるのが効果的である。し力しながら、フォトニック結晶と活性層の距離 を近づけるとドライエッチング損傷が活性層に入り、発光効率が低下するという問題 がある。  In order to further improve the extraction efficiency, it is effective to reduce the distance between the surface diffraction grating photonic crystal and the active layer. However, if the distance between the photonic crystal and the active layer is reduced, dry etching damage enters the active layer, resulting in a problem that the light emission efficiency decreases.
また、 LEDの寿命が小さくなつてしまうという問題が生じる。その理由は、ドライエツ チングした p— GaN面に、コンタクト抵抗の小さい p電極を形成できないためである。 これは、ドライエッチング損傷で pドーパントの活性ィ匕率が低減すること、 pドーピング 濃度の高い 20 [nm]厚の p— GaN層でドライエッチングを停止させられないことに起 因する。  In addition, there is a problem that the lifetime of the LED is shortened. This is because a p-electrode having a low contact resistance cannot be formed on the dry-etched p-GaN surface. This is due to the fact that the active ratio of the p-dopant is reduced by dry etching damage and that the dry etching cannot be stopped by a 20-nm thick p-GaN layer with a high p-doping concentration.
[0020] 第 4の従来例のリセスゲ—ト型 HEMTに関しても以下のような問題点がある。  [0020] The recess gate type HEMT of the fourth conventional example also has the following problems.
ここで、ゲート電極下から n—AlGaNZi— AlGaN界面までの距離を電子供給層の 厚さ d[nm]とする。第 4の従来例ではゲート電極下の n— Al Ga N電子供給層 Here, the distance from the bottom of the gate electrode to the n-AlGaNZi-AlGaN interface is The thickness is d [nm]. In the fourth conventional example, the n-AlGaN electron supply layer under the gate electrode
0. 26 0. 74  0. 26 0. 74
の厚さ dは、 20 [nm]であった。  The thickness d of the film was 20 [nm].
電子供給層の厚さ dが 10[nm]以下になると、キャリア濃度が減少してシート抵抗が 増大し、高周波動作が制限される。また、 AlGaNZGaN界面にドライエッチングの損 傷が及ぶと移動度が減少し、相互コンダクタンスが減少して高周波動作が難しくなる 。キャリア濃度を上げるために電子供給層の nドーピング濃度を高めると、ショットキー 障壁が薄くなつて耐圧が取れなくなり、高電圧動作ができなくなる。無理に電圧をか けるとリーク電流が発生して、素子内部で発生する雑音が増大してしまう。閾ゲート電 圧 Vthの電子供給層の厚さ dに対する微分係数（ d VthZ d d)は、電子供給層のド ナ 濃度と電子供給層の厚さ dの積に比例するので、電子供給層の nドーピング濃 度が高いと電子供給層の厚さ dの分布に対して閾ゲート電圧 Vthの変動が増加する 。電子供給層の厚さ dが 20 [nm]を越えると、電子供給層の容量が低減し相互コンダ クタンスが減少して高周波動作が制限される。また、 n濃度の高い n—GaN層が完全 にエッチングされずに残留するとキャリア濃度が増加し、閾ゲート電圧 Vthが大きく変 動する。電子供給層の厚さ dが変動すると、チャネル層のシートキャリア濃度が変化 するので、閾ゲート電圧 Vthが大きく変動する。その結果、散乱パラメータの分布が 増大し、高周波 ICを作製する上で入出力整合が取りに《なる。  When the thickness d of the electron supply layer is 10 [nm] or less, the carrier concentration decreases, the sheet resistance increases, and high-frequency operation is limited. In addition, when dry etching damages the AlGaNZGaN interface, the mobility decreases, the mutual conductance decreases, and high-frequency operation becomes difficult. If the n-doping concentration of the electron supply layer is increased to increase the carrier concentration, the Schottky barrier becomes thin and the breakdown voltage cannot be obtained, and high voltage operation cannot be performed. If a voltage is applied forcibly, a leak current is generated, increasing the noise generated inside the device. The differential coefficient (d VthZ dd) of the threshold gate voltage Vth with respect to the thickness d of the electron supply layer (d VthZ dd) is proportional to the product of the donor concentration of the electron supply layer and the thickness d of the electron supply layer. When the doping concentration is high, the variation of the threshold gate voltage Vth increases with respect to the distribution of the thickness d of the electron supply layer. When the thickness d of the electron supply layer exceeds 20 [nm], the capacity of the electron supply layer is reduced, the mutual conductance is reduced, and the high frequency operation is restricted. If the n-GaN layer with a high n concentration remains without being completely etched, the carrier concentration increases and the threshold gate voltage Vth changes greatly. When the thickness d of the electron supply layer changes, the sheet carrier concentration of the channel layer changes, so that the threshold gate voltage Vth changes greatly. As a result, the distribution of scattering parameters increases, and input / output matching is difficult to achieve when fabricating high-frequency ICs.
しかしながら、従来のドライエッチング法では、直径 50 [mm]以上のウェハの面内 のゲート電極下の電子供給層の厚さ dを 15 [nm]士 5 [nm]の精度で制御するのは 困難であった。  However, with the conventional dry etching method, it is difficult to control the thickness d of the electron supply layer under the gate electrode within the surface of a wafer having a diameter of 50 [mm] or more with an accuracy of 15 [nm] to 5 [nm]. Met.
[0021] なお、上記問題点は GaN系の半導体素子特有の問題ではなぐ他の窒化物半導 体素子においても同様の問題が生じ得るものである。  [0021] Note that the above problem is not a problem peculiar to a GaN-based semiconductor element, and a similar problem may occur in other nitride semiconductor elements.
[0022] 本発明は、上記問題点に鑑みてなされたものであり、その目的とするところは、以下 のような窒化物半導体素子、及びその製造方法を提供することである。すなわち、第 1の目的とするところは、（1)出力動作時の信頼性を高め、（2)低コストィ匕の可能な半 導体素子等を提供することである。また、第 2の目的とするところは、上記（1)及び (2 )を満足しつつ、（3)発光効率の高い活性層を得ることである。また、第 3の目的とす るところは、上記（1)及び (2)を満足しつつ、（4)光取り出し効率の高い半導体素子 等を提供することである。 [0022] The present invention has been made in view of the above problems, and an object of the present invention is to provide the following nitride semiconductor device and a method for manufacturing the same. That is, the first object is to provide (1) a semiconductor element that can increase the reliability during output operation and (2) can be manufactured at low cost. The second object is to obtain (3) an active layer with high luminous efficiency while satisfying the above (1) and (2). The third object is to satisfy (1) and (2) above, and (4) a semiconductor device with high light extraction efficiency. Etc. is to provide.
課題を解決するための手段  Means for solving the problem
[0023] 本発明者は、上記目的を達成すべく鋭意検討を重ねた。その結果、以下に示す態 様において、本件発明の目的を達成し得ることを見出し、本件発明を完成するに至 つた o  [0023] The present inventor has intensively studied to achieve the above object. As a result, it was found that the object of the present invention could be achieved in the following manner, and the present invention was completed.
[0024] 本発明の第 1の態様に係る窒化物半導体素子は、基板と、該基板上に複数の半導 体層が形成されている窒化物半導体素子であって、該基板上に形成される第 1の半 導体層と、該第 1の半導体層の直上に積層される極性反転層と、該極性反転層の直 上に積層されて、少なくとも一部がウエットエッチングによりパターユングされる第 2の 半導体層とからなる積層体を少なくとも一つ備え、該第 2の半導体層は、ウエットエツ チングによりエッチングされる極性、該第 1の半導体層は、該第 2の半導体層の該ゥ エツトエッチングによるエッチング停止層となる極性に配設されたものである。  The nitride semiconductor device according to the first aspect of the present invention is a nitride semiconductor device in which a substrate and a plurality of semiconductor layers are formed on the substrate, and is formed on the substrate. A first semiconductor layer, a polarity reversal layer stacked immediately above the first semiconductor layer, and a first reversal layer stacked immediately above the polarity reversal layer and patterned at least partially by wet etching. At least one stacked body comprising two semiconductor layers, the second semiconductor layer having a polarity that is etched by wet etching, and the first semiconductor layer being the wet etching of the second semiconductor layer. Are arranged in a polarity to be an etching stop layer.
[0025] なお、上記極性とは、結晶の成長時の表面に支配的に配列されている元素のこと を 、 、、結晶の成長方向を表す指標として用いて 、る。  [0025] Note that the above polarity refers to elements that are predominantly arranged on the surface during crystal growth, and are used as an index representing the crystal growth direction.
一例として、 GaN結晶の極性について説明する。単結晶 GaNには、 2種類の結晶 面 (極性）、すなわち Ga (ガリウム）面と、 N (窒素）面とがある。 Ga面とは、 Ga原子が 結晶の成長面に形成されており、 Ga原子の 4つの結合のうち 1つが膜外部に、残り 3 本の結合が膜内部を向いた極性面のことをいう。 N面とは、 N原子が結晶の成長面に 形成されており、 N原子の 3本の結合が膜内部に向かっている極性面のことをいう。 一般的に、表面が Ga面の GaN結晶の面方位は（0001)、表面が N面の GaN結晶の 面方位は（000—1)と表される。ここでは、成長時の表面が Ga面であった GaN結晶 を Ga極性の結晶、成長時の表面が N面であった GaN結晶を N極性の結晶と呼ぶ。 同様にして、結晶の成長時の表面が III族元素によるものを ΠΙ族極性、結晶の成長 時の表面が V族元素によるものを V族極性という。  As an example, the polarity of a GaN crystal will be described. Single-crystal GaN has two types of crystal planes (polarity): Ga (gallium) plane and N (nitrogen) plane. The Ga plane is a polar plane in which Ga atoms are formed on the crystal growth surface, with one of the four bonds of Ga atoms facing the outside of the film and the remaining three bonds facing the inside of the film. The N-plane is a polar plane in which N atoms are formed on the crystal growth surface and three bonds of N atoms are directed toward the inside of the film. In general, the surface orientation of a GaN crystal with a Ga surface is (0001), and the surface orientation of a GaN crystal with an N surface is (000-1). Here, a GaN crystal whose surface during growth was a Ga plane is called a Ga-polar crystal, and a GaN crystal whose growth surface was an N-plane is called an N-polar crystal. Similarly, when the surface of the crystal is grown by a group III element, it is called Group IV polarity, and when the surface of the crystal is grown by a Group V element, it is called Group V polarity.
[0026] 本発明の第 1の態様に係る窒化物半導体素子によれば、第 2の半導体層のパター ユング形成に際して、ウエットエッチング法を用いることが可能である。その理由は、 第 2の半導体層のウエットエッチングにより第 1の半導体層がエッチングされないよう に第 1の積層体と第 2の積層体との結晶の成長方向の極性を選択しているためであ る。このようにすることにより、高精度に制御された半導体素子を得ることができる。そ の結果、素子の歩留まりを向上させることができる。従って、低コストィ匕を実現できる。 また、ウエットエッチング法を用いることができるので、第 1の半導体層及びその下層[0026] According to the nitride semiconductor device of the first aspect of the present invention, it is possible to use a wet etching method when forming the pattern of the second semiconductor layer. The reason is that the crystal growth direction polarity of the first stacked body and the second stacked body is selected so that the first semiconductor layer is not etched by wet etching of the second semiconductor layer. The By doing in this way, the semiconductor element controlled with high precision can be obtained. As a result, the device yield can be improved. Therefore, low cost can be realized. In addition, since the wet etching method can be used, the first semiconductor layer and its lower layer
、並びに第 2の半導体層の上層にある層の結晶欠陥や損傷が生じない。従って、出 力動作時の信頼性を向上させることができる。さらに、ウエットエッチング法によれば、 ドライエッチング法に用いられる高価な装置が不要となるので生産コストを低減するこ とがでさる。 In addition, crystal defects and damage of the upper layer of the second semiconductor layer do not occur. Therefore, the reliability during the output operation can be improved. Furthermore, according to the wet etching method, an expensive apparatus used for the dry etching method is not necessary, so that the production cost can be reduced.
[0027] なお、上記特許文献 2においては、 pコンタクト層（例えば、図 1参照）に極性反転層 が形成された窒化物半導体素子に関する技術が開示されている（以下、「第 5の従来 例」と 、う）。この第 5の従来例によれば pコンタクト層中に高濃度の Mgの GaN層を積 層させることにより、当該層に挟まれる二つの層の極性を反転させることができる。こ れによって、 N極性面に p電極を形成することで、コンタクト抵抗を低減し、動作電圧 を改善できるとしている。  [0027] It should be noted that Patent Document 2 discloses a technique related to a nitride semiconductor device in which a polarity inversion layer is formed in a p-contact layer (for example, see FIG. 1) (hereinafter referred to as “fifth conventional example”). "") According to the fifth conventional example, by stacking a high-concentration Mg GaN layer in the p-contact layer, the polarities of the two layers sandwiched between the layers can be reversed. As a result, by forming a p-electrode on the N-polar surface, the contact resistance can be reduced and the operating voltage can be improved.
[0028] また、上記特許文献 3においては、活性層（例えば、図 1参照）に極性反転層が形 成された技術が開示されている（以下、「第 6の従来例」という）。この第 6の従来例に よれば、活性層中に Mg単分子層を堆積させ、後続層たる活性層を反転させる技術 が開示されている。  [0028] Further, Patent Document 3 discloses a technique in which a polarity inversion layer is formed in an active layer (for example, see Fig. 1) (hereinafter referred to as "sixth conventional example"). According to the sixth conventional example, a technique is disclosed in which an Mg monomolecular layer is deposited in an active layer and the active layer as a subsequent layer is inverted.
[0029] 本件発明は、窒化物半導体素子中に極性反転層を備える点において、上記第 5及 び第 6の従来例と一致する。しカゝしながら、本件発明に係る極性反転層は、第 2の半 導体層のパター-ング形成におけるウエットエッチング時に、第 1の半導体層がエツ チングされな 、ように、第 1の半導体層と第 2の半導体層との極性を反転させるため に設けるものである。従って、上記第 5及び第 6の従来例からは、本件発明への示唆 はない。  The present invention is consistent with the fifth and sixth conventional examples in that a polarity inversion layer is provided in the nitride semiconductor device. However, the polarity inversion layer according to the present invention is such that the first semiconductor layer is not etched during the wet etching in the pattern formation of the second semiconductor layer. It is provided in order to reverse the polarity of the second semiconductor layer. Therefore, there is no suggestion to the present invention from the fifth and sixth conventional examples.
[0030] なお、上記第 5の従来例のように極性反転層を pコンタクト層中に形成すると、 pコン タクト層の厚さを 60[nm]以上にする必要があり、その結果、 GaNZAlGaN界面にホ ールが蓄積して動作電圧が上昇してしまう。また、上記第 6の従来例のように活性層 中に極性反転層を設けると、極性反転層は非発光センタを含むので発光効率が著し く減少してしまう。 [0031] 本発明の第 2の態様に係る窒化物半導体素子は、上記第 1の態様の窒化物半導 体素子において、上記極性反転層は、以下の（1)から（5)のいずれかの層であること を特徴とするものである。 [0030] When the polarity inversion layer is formed in the p contact layer as in the fifth conventional example, the thickness of the p contact layer needs to be 60 [nm] or more. As a result, the GaNZAlGaN interface As a result, holes accumulate and the operating voltage rises. If a polarity inversion layer is provided in the active layer as in the sixth conventional example, the light emission efficiency is significantly reduced because the polarity inversion layer includes a non-light emission center. [0031] The nitride semiconductor device according to the second aspect of the present invention is the nitride semiconductor device according to the first aspect, wherein the polarity inversion layer is any one of the following (1) to (5): It is characterized by being a layer of
(1) II族原子が 102°[cm_3]以上、 1023[cm_3]以下の濃度でドーピングされた 2 [n m]以下の層 (1) A layer of 2 [nm] or less doped with a group II atom at a concentration of 10 2 ° [cm_ 3 ] or more and 10 23 [cm_ 3 ] or less
(2) II原子の単原子層  (2) II atomic monolayer
(3) II族原子と V族原子とを含む単原子層、又は単分子層  (3) Monoatomic layer or monomolecular layer containing group II and group V atoms
(4) II族原子と ΠΙ族原子とを含む単原子層、又は単分子層  (4) Monoatomic layer or monomolecular layer containing group II atoms and group IV atoms
(5) ΠΙ族原子、又は Ζ及び、 V族原子の 2原子層  (5) V-group atoms or bi-layers of V and V-group atoms
[0032] 本発明の第 3の態様に係る窒化物半導体素子は、上記第 1又は第 2の態様の窒化 物半導体素子にお 、て、上記極性反転層は下記（1)から（5)の 、ずれかであること を特徴とするものである。  [0032] The nitride semiconductor device according to the third aspect of the present invention is the nitride semiconductor device according to the first or second aspect, wherein the polarity inversion layer includes the following (1) to (5): It is characterized by being a deviation.
(1) η型不純物原子が 102°[cm_3]以上、 1023 [cm—3]以下の濃度でドーピングされ た 2 [nm]以下の層 (1) A layer of 2 nm or less doped with η-type impurity atoms at a concentration of 10 2 ° [cm_ 3 ] or more and 10 23 [cm- 3 ] or less
(2) n型不純物原子の単原子層  (2) Monolayer of n-type impurity atoms
(3) n型不純物原子と ΠΙ族原子とを含む単原子層、又は単分子層  (3) Monoatomic layer or monomolecular layer containing n-type impurity atoms and ΠΙ group atoms
(4) n型不純物原子と V族原子とを含む単原子層、又は単分子層  (4) Monoatomic layer or monomolecular layer containing n-type impurity atoms and group V atoms
(5) n型不純物原子と III族原子と V族原子とを含む単原子層、又は単分子層  (5) Monoatomic layer or monomolecular layer containing n-type impurity atoms, group III atoms and group V atoms
[0033] 本発明の第 4の態様に係る窒化物半導体素子は、上記基板上であって、上記第 1 の半導体層の下層、又は上記第 2の半導体層の上層に活性層を備えて 1、る。 [0033] A nitride semiconductor device according to a fourth aspect of the present invention includes an active layer on the substrate and below the first semiconductor layer or above the second semiconductor layer. RU
[0034] 半導体素子における半導体層を、ドライエッチング法で除去すると、結晶欠陥が第 [0034] When the semiconductor layer in the semiconductor element is removed by a dry etching method, crystal defects are
1の半導体層及びその下層、若しくは、第 2の半導体層の上層に及ぶ。従って、その 後の再成長により欠陥が活性層に拡散し、活性層に非発光センタが導入される場合 がある。  It covers one semiconductor layer and its lower layer, or the second semiconductor layer. Therefore, subsequent regrowth may cause defects to diffuse into the active layer and introduce a non-light emitting center into the active layer.
[0035] 本発明の第 4の態様に係る窒化物半導体素子によれば、ウエットエッチング法を用 いてパター-ングを行っているので、結晶欠陥が第 1の半導体層及びその下層、並 びに第 2の半導体層の上層には及ばない。従って、その後の再成長により上記欠陥 が活性層に拡散して活性層に非発光センタが導入されることがない。その結果、光 学的特性の低下を防止して出力動作時の信頼性を向上させ、かつ素子の歩留まりを 高めることができる。 [0035] According to the nitride semiconductor device of the fourth aspect of the present invention, since the patterning is performed using the wet etching method, crystal defects occur in the first semiconductor layer and its lower layer, as well as in the first. It does not reach the upper layer of the two semiconductor layers. Therefore, the subsequent regrowth does not diffuse the defect into the active layer and introduce a non-light emitting center into the active layer. As a result, light It is possible to improve the reliability during output operation and to improve the yield of devices by preventing deterioration of the physical characteristics.
[0036] 本発明の第 5の態様に係る窒化物半導体素子は、上記第 1から第 4の態様の窒化 物半導体素子において、上記第 1の半導体層の下層に上記活性層を備え、上記第 2の半導体層がリッジ形状にパター-ングされることを特徴とするリッジ型のものであ る。  The nitride semiconductor device according to the fifth aspect of the present invention is the nitride semiconductor device according to the first to fourth aspects, wherein the active layer is provided below the first semiconductor layer, and the first semiconductor layer includes the active layer. The ridge type is characterized in that the second semiconductor layer is patterned into a ridge shape.
[0037] 本発明の第 5の態様に係る窒化物半導体素子によれば、ウエットエッチング法によ り第 2の半導体層をリッジ形状となるようにエッチングを行い、第 1の半導体層がエツ チング停止層として機能しているので、リッジメサストライプを形成するに際して、メサ 脇の厚み等を高精度に制御することができる。その結果、設計どおりの構造を得るこ とができる。また、高出力動作を行っても、基本横モードが保たれ、小さいアスペクト 比が実現できるという利点が得られる。また、ドライエッチング法に比して、優れた信 頼性を有する窒化物半導体素子を得ることができる。  [0037] According to the nitride semiconductor device of the fifth aspect of the present invention, the second semiconductor layer is etched into a ridge shape by wet etching, and the first semiconductor layer is etched. Since it functions as a stop layer, when the ridge mesa stripe is formed, the thickness of the mesa side can be controlled with high accuracy. As a result, a structure as designed can be obtained. In addition, even if high-power operation is performed, the basic transverse mode is maintained and a small aspect ratio can be realized. In addition, a nitride semiconductor device having excellent reliability as compared with the dry etching method can be obtained.
[0038] 本発明の第 6の態様に係る窒化物半導体素子は、上記第 1から第 4の態様の窒化 物半導体素子において、上記第 2の半導体層が、内部電流狭窄層であり、上記第 1 の半導体層の下層に上記活性層を備えることを特徴とする内部電流狭窄層型のもの である。  [0038] The nitride semiconductor device according to the sixth aspect of the present invention is the nitride semiconductor device according to any one of the first to fourth aspects, wherein the second semiconductor layer is an internal current confinement layer. The internal current confinement layer type is characterized in that the active layer is provided under the semiconductor layer 1.
[0039] 本発明の第 6の態様に係る窒化物半導体素子によれば、内部電流狭窄層を結晶と したので、非結晶に起因する問題を解決することができる。また、ウエットエッチング 法により内部電流狭窄層のパターユングを行ったので、第 1の半導体層及びその下 層に結晶欠陥などの加工損傷が生じない。従って、再成長後も活性層の高い発光 効率が維持される。  [0039] According to the nitride semiconductor device of the sixth aspect of the present invention, since the internal current confinement layer is made of crystal, the problem caused by non-crystal can be solved. In addition, since the internal current confinement layer is patterned by the wet etching method, processing damage such as crystal defects does not occur in the first semiconductor layer and its lower layer. Therefore, the high luminous efficiency of the active layer is maintained even after regrowth.
[0040] 本発明に係る第 7の態様の窒化物半導体素子は、上記第 6の態様の窒化物半導 体素子において、上記内部電流狭窄層は、以下の（1)から（3)のいずれかの条件を 満たすことを特徴とするものである。  [0040] A nitride semiconductor device according to a seventh aspect of the present invention is the nitride semiconductor device according to the sixth aspect, wherein the internal current confinement layer is any of the following (1) to (3): It is characterized by satisfying these conditions.
(1) ln Ga Al N (0≤X≤1、 0≤Y≤1、 0≤X+Y≤1)、  (1) ln Ga Al N (0≤X≤1, 0≤Y≤1, 0≤X + Y≤1),
X Υ 1 -Χ-Υ  X Υ 1 -Χ-Υ
(2) In Al Ν (0. 05≤Χ≤0. 3)、  (2) In Al Ν (0. 05≤Χ≤0.3.),
X 1 -Χ  X 1 -Χ
(3) (In Al ) Ga Ν (0. 2≤Ζ≤1) [0041] 本発明の第 7の態様に係る窒化物半導体素子によれば、上記（1)力 (3)の条件 を満たすことにより、内部電流狭窄層の屈折率を低く抑えることができる。よって、光 を活性層に、より効果的に閉じ込めることができる。上記（2)における Xの値は、より 好ましくは、 0. 1≤X≤0. 25であり、さらに好ましくは 0. 15≤X≤0. 2である。 (3) (In Al) Ga Ν (0. 2≤Ζ≤1) [0041] According to the nitride semiconductor device of the seventh aspect of the present invention, the refractive index of the internal current confinement layer can be kept low by satisfying the above condition (1) force (3). Therefore, light can be more effectively confined in the active layer. The value of X in (2) is more preferably 0.1≤X≤0.25, and more preferably 0.15≤X≤0.2.
[0042] 本発明の第 8の態様に係る窒化物半導体素子は、上記第 4の態様の窒化物半導 体素子において、上記第 2の半導体層、及び該第 2の半導体層上に積層される半導 体層がパター-ングされ、当該パター-ングにより開口した部位に埋め込み層を形 成することを特徴とする埋め込み型のものである。  [0042] The nitride semiconductor device according to the eighth aspect of the present invention is the same as the nitride semiconductor device according to the fourth aspect, laminated on the second semiconductor layer and the second semiconductor layer. The semiconductor layer is patterned, and an embedded layer is formed in a portion opened by the pattern.
[0043] 本発明の第 8の態様に係る窒化物半導体素子によれば、屈折率分布と利得分布が 一致した特長により低閾値、高出力時の安定横モード、放熱性の向上により、高い信 頼性を得ることができる。また、半導体素子の長寿命化を達成することができる。  [0043] According to the nitride semiconductor device of the eighth aspect of the present invention, a high threshold is achieved due to the feature that the refractive index distribution and the gain distribution coincide with each other. Reliability can be obtained. In addition, the lifetime of the semiconductor element can be increased.
[0044] 本発明の第 9の態様に係る窒化物半導体素子は、上記第 4〜8のいずれかの態様 の窒化物半導体素子において、上記第 1の半導体層が分離光閉じ込めヘテロ構造 層であり、該第 1の半導体層の下層に上記活性層を備えて ヽることを特徴とするもの である。このように構成することにより、高出力動作を行っても、基本横モードが保た れて、小さいアスペクト比を実現することができる。  [0044] The nitride semiconductor device according to the ninth aspect of the present invention is the nitride semiconductor device according to any one of the fourth to eighth aspects, wherein the first semiconductor layer is a separated light confinement heterostructure layer. The active layer is provided below the first semiconductor layer. With this configuration, the basic transverse mode is maintained even when high output operation is performed, and a small aspect ratio can be realized.
[0045] 本発明の第 10の態様に係る窒化物半導体素子は、上記第 1〜9のいずれかの態 様の窒化物半導体素子において、上記半導体層は、 GaN系の半導体層により形成 されて ヽることを特徴とするちのである。  [0045] The nitride semiconductor device according to the tenth aspect of the present invention is the nitride semiconductor device according to any one of the first to ninth aspects, wherein the semiconductor layer is formed of a GaN-based semiconductor layer. It is a life characterized by scolding.
[0046] 本発明の第 11の態様に係る窒化物半導体素子は、上記第 1〜10のいずれかの態 様の窒化物半導体素子において、上記第 2の半導体層の結晶の面方位が (000— 1 )、又は V族極性であることを特徴とするものである。  [0046] The nitride semiconductor device according to the eleventh aspect of the present invention is the nitride semiconductor device according to any one of the first to tenth aspects, wherein the crystal plane orientation of the second semiconductor layer is (000 — 1) or V group polarity.
[0047] 本発明の第 12の態様に係る窒化物半導体素子は、上記第 1〜9のいずれかの態 様の窒化物半導体素子にお!、て、窒化物フォトニック結晶を備えて 、ることを特徴と するものである。窒化物フォトニック結晶を備えることにより、光の取り出し効率を向上 させることがでさる。  [0047] A nitride semiconductor device according to a twelfth aspect of the present invention is the nitride semiconductor device according to any one of the first to ninth aspects, further comprising a nitride photonic crystal. It is characterized by this. By providing a nitride photonic crystal, the light extraction efficiency can be improved.
[0048] 本発明の第 13の態様に係る窒化物半導体素子は、 n型超格子光反射層を備えて いることを特徴とするものである。 n型超格子光反射層を備えることにより、基板に放 射された光を反射させることができるので、光取り出し効率をさらに高めることができる [0048] A nitride semiconductor device according to a thirteenth aspect of the present invention is characterized by including an n-type superlattice light reflecting layer. By providing an n-type superlattice light reflecting layer, Since the emitted light can be reflected, the light extraction efficiency can be further increased.
[0049] 本発明の第 14の態様に係る窒化物半導体素子は、上記第 1〜13のいずれかに記 載の態様の窒化物半導体素子において、 p電極と、該 p電極に接続される pコンタクト 層とを備え、該 pコンタクト層は、 N極性であり、その層厚が 10[nm]以上、 50[nm]以 下であることを特徴とするものである。このように構成することにより、 p電極と接する p コンタクト層を N極性とすることができるため、低いァニール温度で pコンタクトを形成 することができる。 [0049] A nitride semiconductor device according to a fourteenth aspect of the present invention is the nitride semiconductor device according to any one of the first to thirteenth aspects, wherein a p electrode and a p connected to the p electrode are provided. A p-contact layer having N polarity and a layer thickness of 10 [nm] or more and 50 [nm] or less. With this configuration, the p-contact layer in contact with the p-electrode can be made N-polar, so that the p-contact can be formed at a low annealing temperature.
[0050] 本発明の第 15の態様に係る窒化物半導体素子は、上記第 1〜14のいずれかに記 載の態様の窒化物半導体素子において、 p電極と、該 p電極に接続される pコンタクト 層とを備え、該 pコンタクト層は、 N極性であり、該 p電極力 SPdを少なくとも含む材料に より構成されていることを特徴とするものである。 p電極として Pdを少なくとも含んでい るので、 pコンタクト層と反応して合金化しやすい。従って、ァニール温度を低くするこ とがでさる。  [0050] A nitride semiconductor device according to a fifteenth aspect of the present invention is the nitride semiconductor device according to any one of the first to fourteenth aspects, wherein a p electrode and a p connected to the p electrode are provided. A p-contact layer, and the p-contact layer is N-polar and is made of a material containing at least the p-electrode force SPd. As P electrode contains at least Pd, it reacts with p contact layer and is easily alloyed. Therefore, the annealing temperature can be lowered.
[0051] 本発明の第 16の態様に係る窒化物半導体素子は、上記第 1、 2又は 3の態様の窒 化物半導体素子において、上記第 1の半導体層は、ゲート電極に接続される電子供 給層であり、上記第 2の半導体層は、ソース電極、及びドレイン電極にォーミックに接 するコンタクト層であることを特徴とするものである。  [0051] The nitride semiconductor device according to the sixteenth aspect of the present invention is the nitride semiconductor device according to the first, second or third aspect, wherein the first semiconductor layer is an electrode connected to a gate electrode. The second semiconductor layer is a contact layer that is in ohmic contact with the source electrode and the drain electrode.
[0052] 本発明の第 17の態様に係る窒化物半導体素子は、上記第 16の態様の窒化物半 導体素子において、上記コンタクト層は、当該コンタクト層の成長方向の面方位が（0 00— 1)である V族極性の n型半導体層であり、上記電子供給層は、当該電子供給 層の成長方向の面方位が（0001)である III族極性の n型半導体層であることを特徴 とするちのである。  [0052] A nitride semiconductor device according to a seventeenth aspect of the present invention is the nitride semiconductor device according to the sixteenth aspect, wherein the contact layer has a plane orientation in the growth direction of the contact layer of (00 00- 1) a group V polar n-type semiconductor layer, wherein the electron supply layer is a group III polar n-type semiconductor layer whose growth direction plane orientation is (0001). It is a life.
[0053] 本発明の第 18の態様に係る窒化物半導体素子は、上記半導体層として、上記第 1 の半導体層の下層にチャネル層、スぺーサ層の順に積層されて ヽる半導体層を含 み、該チャネル層は、 III族極性のアンドープの GaN層、該スぺーサ層は、アンド一 プの Al Ga N層（ただし、 0<X≤ 1)、上記電子供給層は、 n型の Al Ga N層（ [0053] The nitride semiconductor device according to the eighteenth aspect of the present invention includes, as the semiconductor layer, a semiconductor layer formed by laminating a channel layer and a spacer layer in that order under the first semiconductor layer. The channel layer is an undoped GaN layer having a group III polarity, the spacer layer is an undoped AlGaN layer (where 0 <X≤1), and the electron supply layer is an n-type layer. Al Ga N layer (
X 1 -X X 1 -X ただし、 0<X≤ 1)、上記コンタクト層は、 V族極性の n型の Al Ga N層（ただし、 0 ≤Y<X)、又は、 η型の In Ga N層（ただし、 0≤Z≤0. 2)であることを特徴とする X 1 -XX 1 -X where 0 <X≤ 1), the contact layer is an n-type Al Ga N layer with group V polarity (however, 0 ≤Y <X) or η-type InGaN layer (however, 0≤Z≤0.2)
Z 1 -Z  Z 1 -Z
ものである。  Is.
[0054] 本発明の第 19の態様に係る窒化物半導体素子は、上記第 18の態様の窒化物半 導体素子において、上記スぺーサ層は、 III族極性であって、該スぺーサ層と上記電 子供給層との層厚の和は、 10[nm]以上、 25[nm]以下であり、かつ、該電子供給層 及び該スぺーサ層の組成比 Xの値力 0. 25以上、 0. 45以下であることを特徴とす るものである。  [0054] The nitride semiconductor device according to the nineteenth aspect of the present invention is the nitride semiconductor device according to the eighteenth aspect, wherein the spacer layer has group III polarity, and the spacer layer The sum of the layer thicknesses of the electron supply layer and the electron supply layer is 10 [nm] or more and 25 [nm] or less, and the value of the composition ratio X of the electron supply layer and the spacer layer is 0.25. As described above, it is characterized by being 0.45 or less.
[0055] 本発明の第 20の態様に係る窒化物半導体素子は、上記第 15〜18のいずれかに 記載の態様の窒化物半導体素子において、上記基板が、半導体絶縁性の SiC基板 、又は半導体絶縁性の GaN基板であることを特徴とするものである。このようにするこ とにより、品質の高い平坦な界面が得られる。その結果、高い電子移動度を得ること ができる。  [0055] The nitride semiconductor device according to the twentieth aspect of the present invention is the nitride semiconductor element according to any one of the fifteenth to eighteenth aspects, wherein the substrate is a semiconductor insulating SiC substrate or a semiconductor. It is an insulating GaN substrate. In this way, a high quality flat interface can be obtained. As a result, high electron mobility can be obtained.
[0056] 本発明の第 21の態様に係る窒化物半導体素子は、基板上に第 1の半導体層と、 該第 1の半導体層の直上に形成される極性反転層と、該極性反転層の直上に形成 され、該第 1の半導体層とは極性の異なる第 2の半導体層とからなる積層体を少なく とも一つ含む複数の半導体層を備える窒化物半導体素子の製造方法であって、該 第 2の半導体層のパターユング形成におけるウエットエッチング時にエッチング停止 層となる該第 1の半導体層を形成し、該極性反転層を形成し、該第 2の半導体層を 形成し、該第 2の半導体層をウエットエッチング法によりエッチングし、該第 2の半導 体層のパターンを形成するものである。  [0056] The nitride semiconductor device according to the twenty-first aspect of the present invention includes a first semiconductor layer on a substrate, a polarity inversion layer formed immediately above the first semiconductor layer, and A method for manufacturing a nitride semiconductor device comprising a plurality of semiconductor layers formed immediately above and including a stack of at least one second semiconductor layer having a polarity different from that of the first semiconductor layer, Forming the first semiconductor layer to be an etching stop layer during wet etching in patterning of the second semiconductor layer, forming the polarity inversion layer, forming the second semiconductor layer, and forming the second semiconductor layer; The semiconductor layer is etched by a wet etching method to form a pattern of the second semiconductor layer.
[0057] 本発明の第 21の態様に係る窒化物半導体素子によれば、第 2の半導体層のバタ 一-ング形成に際して、ウエットエッチング法を用いることが可能である。その理由は 、第 2の半導体層のウエットエッチングにより第 1の半導体層がエッチングされないよう に第 1の積層体と第 2の積層体との結晶の成長方向の極性を選択しているためであ る。このようにすることにより、高精度に制御された半導体素子を製造することができ る。その結果、素子の歩留まりを向上させることができる。従って、低コスト化を実現で きる。また、ウエットエッチング法を用いることができるので、第 1の半導体層及びその 下層、並びに第 2の半導体層の上層にある層の結晶欠陥や損傷が生じない。従って 、出力動作時の信頼性を向上させることができる。さらに、ウエットエッチング法によれ ば、ドライエッチング法に用いられる高価な装置が不要となるので生産コストを低減す ることがでさる。 [0057] According to the nitride semiconductor device of the twenty-first aspect of the present invention, it is possible to use a wet etching method when forming the second semiconductor layer pattern. The reason is that the polarities of the crystal growth directions of the first stacked body and the second stacked body are selected so that the first semiconductor layer is not etched by wet etching of the second semiconductor layer. The By doing so, a semiconductor element controlled with high accuracy can be manufactured. As a result, the device yield can be improved. Therefore, cost reduction can be realized. In addition, since a wet etching method can be used, crystal defects and damage of the first semiconductor layer, its lower layer, and the upper layer of the second semiconductor layer do not occur. Therefore Therefore, the reliability during the output operation can be improved. Furthermore, the wet etching method eliminates the need for expensive equipment used for the dry etching method, thereby reducing the production cost.
[0058] 本発明の第 22の態様に係る窒化物半導体素子は、上記第 22の態様の窒化物半 導体素子の製造方法において、上記ウエットエッチングは、燐酸と硫酸の混合液を 用い、該ウエットエッチングを 80 [°C]以上、 300 [°C]以下の温度で行うことを特徴と するものである。  [0058] The nitride semiconductor device according to the twenty-second aspect of the present invention is the method for producing a nitride semiconductor device according to the twenty-second aspect, wherein the wet etching uses a mixed solution of phosphoric acid and sulfuric acid. Etching is performed at a temperature of 80 [° C] or higher and 300 [° C] or lower.
[0059] 本発明の第 23の態様に係る窒化物半導体素子の製造方法は、上記第 21又は 22 の態様の窒化物半導体素子の製造方法において、上記複数の半導体層は、以下の (1)から（3)の方法により製造されることを特徴とするものである。  [0059] A method for manufacturing a nitride semiconductor device according to the twenty-third aspect of the present invention is the method for manufacturing a nitride semiconductor device according to the twenty-first or twenty-second aspect, wherein the plurality of semiconductor layers are: To (3).
(1)有機金属気相成長法  (1) Metalorganic vapor phase epitaxy
(2)分子線ェピタキシ法  (2) Molecular beam epitaxy
(3) V族極性、又は (000— 1)面の該半導体層を形成するときは、有機金属気相成 長法により、 III族極性、又は (0001)面の該半導体層を形成するときは、分子線ェピ タキシ法  (3) When forming the semiconductor layer of Group V polarity or (000-1) plane, when forming the semiconductor layer of Group III polarity or (0001) plane by metalorganic vapor phase growth method The molecular beam epitaxy method
[0060] 本発明の第 23の態様に係る窒化物半導体素子の上記（1)の製造方法によれば、 素子加工工程で安定な素子歩留まりを得ることができ、素子コストを低減することがで きる。また、上記（2)の製造方法によれば、反射高エネルギー電子線回折により成長 表面を観察しながら、原料やドーパント供給の切り替えを急峻に行うことができるため 、極性反転の制御が行いやすい。また、成長温度と窒素圧の最適化が行いやすい。 さらに、 NHや Hを用いないので、結晶中に水素が取り込まれない。このため、 Mg  [0060] According to the manufacturing method of (1) of the nitride semiconductor device according to the twenty-third aspect of the present invention, a stable device yield can be obtained in the device processing step, and the device cost can be reduced. wear. In addition, according to the manufacturing method of (2) above, since the source and dopant supply can be switched rapidly while observing the growth surface by reflection high energy electron diffraction, it is easy to control the polarity inversion. It is also easy to optimize the growth temperature and nitrogen pressure. In addition, since NH and H are not used, hydrogen is not taken into the crystal. For this reason, Mg
3 2  3 2
ドーパントの水素不活性化を防止できる。また、急峻な制御が可能なので、素子の特 性と信頼性向上に有利である。  Hydrogen inactivation of the dopant can be prevented. In addition, since sharp control is possible, it is advantageous for improving the characteristics and reliability of the element.
発明の効果  The invention's effect
[0061] 本発明に係る窒化物半導体素子においては、以下のような窒化物半導体素子、及 びその製造方法を提供することができるという優れた効果がある。すなわち、（1)出力 動作時の信頼性を高め、低コストィ匕が可能な半導体素子等を提供することができる。 また、 (2)出力動作時の信頼性を高め、低コストィ匕が可能であって、高い発光効率の 活性層を得ることができる半導体素子等を提供することができる。さらに、（3)出力動 作時の信頼性を高め、低コストィ匕が可能であって、光取り出し効率の高い半導体素 子等を提供することができる。 [0061] The nitride semiconductor device according to the present invention has an excellent effect of being able to provide the following nitride semiconductor device and manufacturing method thereof. That is, (1) it is possible to provide a semiconductor element or the like that can improve reliability during output operation and can be manufactured at low cost. In addition, (2) high reliability during output operation, low cost and high luminous efficiency. A semiconductor element or the like capable of obtaining an active layer can be provided. Furthermore, (3) it is possible to provide a semiconductor element or the like with high light extraction efficiency, which can increase the reliability during output operation and can be manufactured at low cost.
図面の簡単な説明  Brief Description of Drawings
[0062] [図 1]実施形態 1に係る窒化物半導体レーザの断面図。 FIG. 1 is a cross-sectional view of a nitride semiconductor laser according to a first embodiment.
[図 2]実施形態 2に係る窒化物半導体レーザの断面図。  FIG. 2 is a cross-sectional view of a nitride semiconductor laser according to Embodiment 2.
[図 3]実施形態 3に係る窒化物半導体レーザの断面図。  FIG. 3 is a cross-sectional view of a nitride semiconductor laser according to a third embodiment.
[図 4]実施形態 4に係る窒化物半導体レーザの断面図。  FIG. 4 is a cross-sectional view of a nitride semiconductor laser according to Embodiment 4.
[図 5]実施形態 5に係る窒化物半導体レーザの断面図。  FIG. 5 is a cross-sectional view of a nitride semiconductor laser according to a fifth embodiment.
[図 6]実施形態 6に係る窒化物半導体発光素子の断面図。  FIG. 6 is a cross-sectional view of a nitride semiconductor light emitting device according to Embodiment 6.
[図 7]実施形態 6に係る窒化物半導体発光素子の上面図。  FIG. 7 is a top view of a nitride semiconductor light emitting device according to Embodiment 6.
[図 8]実施形態 7に係る窒化物半導体発光素子の断面図。  FIG. 8 is a cross-sectional view of a nitride semiconductor light emitting device according to Embodiment 7.
[図 9]実施形態 8に係る窒化物半導体の高電子移動度トランジスタの断面図。  FIG. 9 is a sectional view of a nitride semiconductor high electron mobility transistor according to the eighth embodiment.
[図 10]実施形態 9に係る窒化物半導体の高電子移動度トランジスタの断面図。  FIG. 10 is a cross-sectional view of a nitride semiconductor high electron mobility transistor according to the ninth embodiment.
[図 11]実施形態 6に係る窒化物半導体発光素子の作用の説明図。  FIG. 11 is an explanatory view of the action of the nitride semiconductor light emitting device according to the sixth embodiment.
[図 12]実施形態 7の紫外光 LEDの発光スペクトル。  FIG. 12 shows an emission spectrum of the ultraviolet LED of Embodiment 7.
[図 13]A1 Ga In N系混晶におけるバンドギャップと a軸長の関係を示す図。  FIG. 13 is a graph showing the relationship between the band gap and the a-axis length in an A1 Ga In N mixed crystal.
[図 14]実施形態 1に係る半導体レーザの特性を示す図。  FIG. 14 shows characteristics of the semiconductor laser according to the first embodiment.
[図 15]第 1の従来例に係る窒化物半導体レーザの断面図。  FIG. 15 is a cross-sectional view of a nitride semiconductor laser according to a first conventional example.
[図 16]第 4の従来例に係る窒化物半導体電界効果トランジスタの断面図。  FIG. 16 is a cross-sectional view of a nitride semiconductor field effect transistor according to a fourth conventional example.
符号の説明  Explanation of symbols
[0063] 100、 200、 300、 400 窒化物半導体レーザ [0063] 100, 200, 300, 400 Nitride semiconductor laser
101、 301 基板  101, 301 substrate
104 第 1の SCH層  104 First SCH layer
105、 307、 605、 705 活性層  105, 307, 605, 705 active layer
106 第 2の SCH層  106 Second SCH layer
108、 209、 303、 508、 609、 709 極性反転層  108, 209, 303, 508, 609, 709 Polarity inversion layer
111、 411、 611 コンタクト層 112、 212、 312、 412、 512 p電極 111, 411, 611 Contact layer 112, 212, 312, 412, 512 p electrodes
113 電流狭窄マスク  113 Current confinement mask
114 n電極  114 n electrode
150、 250、 350、 450、 550、 650 積層体  150, 250, 350, 450, 550, 650 Laminate
409 電流狭窄層  409 Current confinement layer
614 フォトニック結晶  614 Photonic Crystal
703 超格子光反射層  703 Superlattice light reflection layer
714 フォトニック結晶  714 photonic crystal
801 核形成層  801 Nucleation layer
802 チャネル層  802 channel layer
803 スぺーサ層  803 Spacer layer
804 電子供給層  804 Electron supply layer
805 極性半転層  805 Polar half-rotation layer
806 コンタクト層  806 Contact layer
807 ドレイン電極  807 Drain electrode
808 ソース電極  808 source electrode
809 ゲート電極  809 Gate electrode
809 リセスゲート電極  809 Recessed gate electrode
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0064] 以下、本発明を窒化物半導体レーザ等に適用した実施形態の一例について説明 する。なお、本発明の趣旨に合致する限り他の実施形態も本発明の範疇に属し得る ことは言うまでもない。 Hereinafter, an example of an embodiment in which the present invention is applied to a nitride semiconductor laser or the like will be described. It goes without saying that other embodiments may also belong to the category of the present invention as long as they match the gist of the present invention.
[実施形態 1]  [Embodiment 1]
[0065] 図 1は、実施形態 1に係る窒化物半導体レーザ 100の断面図である。基板としては 、厚さ 110 [ m]の n型 GaN (0001)基板 101を用いた。この n型 GaN (OOOl)基板 101上には、図 1に示すように、以下の層が積層されている。すなわち、ノッファ層 10 2、第 1のクラッド層 103、第 1の分離光閉じ込めヘテロ構造 (以下、 rsCHj (Separete confinement Getero- structure)と略記する）層 104、 3層からなる量子井戸の活性層 105、電流ォ—バ―フ口—防止（以下、「OFP」と略記する）層 106、第 2の SCH層 1 07、極性反転層 108、第 3の SCH層 109、第 2のクラッド層 110、コンタクト層 111が 、この順に積層されている（以下、これらの層をまとめて積層体 150という）。なお、 SC H層とは、光を活性層に強く閉じ込めるための層をいう。本実施形態 1においては、 第 1の半導体層は第 2の SCH層 107であり、第 2の半導体層は第 3の SCH層 109で ある。 FIG. 1 is a cross-sectional view of nitride semiconductor laser 100 according to the first embodiment. As the substrate, an n-type GaN (0001) substrate 101 having a thickness of 110 [m] was used. On this n-type GaN (OOOl) substrate 101, as shown in FIG. That is, a noffer layer 102, a first cladding layer 103, a first separated light confinement heterostructure (hereinafter abbreviated as rsCHj (Separete confinement Getero-structure)) layer 104, and a quantum well active layer comprising three layers 105, current overflow prevention (hereinafter abbreviated as “OFP”) layer 106, second SCH layer 107, polarity inversion layer 108, third SCH layer 109, second cladding layer 110 The contact layers 111 are laminated in this order (hereinafter, these layers are collectively referred to as a laminate 150). The SCH layer is a layer for confining light strongly in the active layer. In the first embodiment, the first semiconductor layer is the second SCH layer 107, and the second semiconductor layer is the third SCH layer 109.
[0066] 本実施形態 1に係るバッファ層 102は、層厚 0. 3 111]の11 0&^こょり構成され る。また、第 1のクラッド層 103は、層厚 1. 5 [ m]の n— Al Ga Nにより構成さ  [0066] The buffer layer 102 according to the first embodiment is configured to have a thickness of 1 1 0 & ^ with a layer thickness of 0.3 111]. The first cladding layer 103 is made of n-AlGaN having a layer thickness of 1.5 [m].
0. 07 0. 93  0. 07 0. 93
れる。第 1の SCH層は、層厚 100[nm]の n—GaN層、 3層からなる量子井戸の活性 層 105は、 In Ga N (2. 5 [nm]) ZGaN (10 [nm])により構成される。さらに、 O  It is. The first SCH layer is an n-GaN layer with a layer thickness of 100 [nm], and the quantum well active layer 105 with three layers is made of InGaN (2.5 [nm]) ZGaN (10 [nm]). Composed. In addition, O
0. 2 0. 8  0. 2 0. 8
FP層は、 8 [nm]厚の p— Al Ga N、第 2の SCH層 107層は、層厚 100[nm]  The FP layer is 8 [nm] thick p-AlGaN, and the second SCH layer 107 is 100 [nm] thick
0. 14 0. 86  0. 14 0. 86
の p— GaNから構成される。上記 n—GaN (0001)基板 101から第 2の SCH層 107 までの極性は、上述した Ga極性 120となるように構成されている。なお、上述したと おり Ga極性とは、成長時の表面が Ga面であった GaN結晶のことをいい、 N極性とは 、成長時の表面が N面であった GaN結晶のことを!、う。  P— consists of GaN. The polarity from the n-GaN (0001) substrate 101 to the second SCH layer 107 is configured to be the Ga polarity 120 described above. As described above, Ga polarity refers to a GaN crystal whose growth surface was a Ga plane, and N polarity refers to a GaN crystal whose growth surface was an N plane !, Yeah.
[0067] 極性反転層 108は、 Mg単原子層により構成されて 、る。また、第 3の SCH層 109 は、層厚 20 [nm]の p— GaNにより、第 2のクラッド層 110は、層厚 0. 6 [ m]のリツ ジ型 p— Al Ga Nにより、コンタクト層 111は、層厚 20 [nm]の p— GaNにより構 The polarity inversion layer 108 is composed of an Mg monoatomic layer. The third SCH layer 109 is contacted by p-GaN with a layer thickness of 20 [nm], and the second cladding layer 110 is contacted by a ridge type p-AlGaN with a layer thickness of 0.6 [m]. The layer 111 is composed of p-GaN with a layer thickness of 20 nm.
0. 07 0. 93  0. 07 0. 93
成されている。第 3の SCH層 109からコンタクト層 111までの極性は、 N極性 121とな るように形成されている。  It is made. The polarity from the third SCH layer 109 to the contact layer 111 is formed to be N polarity 121.
[0068] リッジメサ幅は、 1. 5 [ /ζ πι]〜2. 2 [ m]の範囲にすることが好ましい。当該範囲 にすれば、単一横モードの光分布が得られるからである。本実施形態 1においては、 リッジメサ幅を 1. 8 [ m]とした。  [0068] The ridge mesa width is preferably in the range of 1.5 [/ ζ πι] to 2.2 [m]. This is because a light distribution of a single transverse mode can be obtained within this range. In Embodiment 1, the ridge mesa width is set to 1.8 [m].
[0069] 上記積層体 150の上面には、電流狭窄マスク 113、 P電極 112が形成されている。  A current confinement mask 113 and a P electrode 112 are formed on the upper surface of the multilayer body 150.
また、 n—GaN (0001)基板 101上の上記積層体 150が形成されている面（以下、「 主面」という）に対して裏側の面（以下、単に「裏面」という）には、 N電極 114が形成さ れている。 P電極 112は、 10[nm]の Niと 10[nm]の Auにより形成されており、 N電 極 114は、 TiZAlにより形成されている。本実施形態 1における半導体レーザ素子 の発振波長は 405 [nm]であった。 In addition, a surface on the back side (hereinafter simply referred to as “back surface”) with respect to the surface (hereinafter referred to as “main surface”) on which the multilayer body 150 is formed on the n-GaN (0001) substrate 101 has N Electrode 114 is formed. The P electrode 112 is made of 10 [nm] Ni and 10 [nm] Au, and the N electrode 114 is made of TiZAl. Semiconductor laser device according to Embodiment 1 The oscillation wavelength was 405 [nm].
[0070] 次に、上記窒化物半導体レーザ 100の製造方法について説明する。本実施形態 1 においては、上記積層体は、有機金属気相成長法 (以下、「MOVPE法」と略記する )により形成した。 Next, a method for manufacturing the nitride semiconductor laser 100 will be described. In Embodiment 1, the laminate was formed by metal organic vapor phase epitaxy (hereinafter abbreviated as “MOVPE method”).
Ga, Al、 In原料として、それぞれトリメチルガリウム（以下、「TMG」と略記する）、トリ メチルアルミニウム（以下、「T[MA]」と略記する）、トリメチルインジウム（以下、「TMI 」と略記する）を、 N原料としては、アンモニア (NH )を用いた。また、 n型ド一パントに  As raw materials for Ga, Al, and In, trimethylgallium (hereinafter abbreviated as “TMG”), trimethylaluminum (hereinafter abbreviated as “T [MA]”), trimethylindium (hereinafter abbreviated as “TMI”), respectively. Ammonia (NH 3) was used as the N raw material. Also, n-type punch
3  Three
はシラン（SiH ) p型ドーパントには、ビスシクロペンタジェニルマグネシウム（以下、 「  Silane (SiH) p-type dopants include biscyclopentagenenyl magnesium (hereinafter “
4  Four
Cp Mg」という）を用いた。  Cp Mg ”).
2  2
キャリアガスには、活性層 105の形成には窒素を、活性層 105以外の相の形成に は水素と窒素の混合ガスを用いた。 pドーパントには、 Mg (マグネシウム）を用いた。 n ド—パントには、 Si (シリコン)を用いたが、 0 (酸素）を用いてもよい。 Mgの原子濃度 は p— GaN力もなるコンタクト層 111には 1 X 1020 [cm"3]、それ以外は 2 X 1019 [cm _ 3]、 Siの原子濃度はすべて 2 X 1018 [cm_ 3]とした。 As the carrier gas, nitrogen was used to form the active layer 105, and a mixed gas of hydrogen and nitrogen was used to form phases other than the active layer 105. Mg (magnesium) was used as the p dopant. n Si (silicon) was used for the dopant, but 0 (oxygen) may be used. The atomic concentration of Mg is 1 x 10 20 [cm " 3 ] for the contact layer 111 that also has p-GaN force, 2 x 10 19 [cm _ 3 ] otherwise, and the atomic concentration of Si is all 2 x 10 18 [cm _3 ].
[0071] n—GaN (0001)基板 101を成長装置に投入後、 NHを供給しながら基板を昇温 [0071] After introducing the n-GaN (0001) substrate 101 into the growth apparatus, the temperature of the substrate is raised while supplying NH.
3  Three
し、成長温度まで到達した時点で成長を開始した。  The growth was started when the growth temperature was reached.
n— GaN (OOOl)基板 101上に、層厚 0. 3 [ m]のバッファ層 102、層厚 1. 5 [ μ m]の第 1のクラッド層 103、層厚 100 [nm]の第 1の SCH層 104、 3層からなる量子 井戸の活性層 105、 8 [nm]厚の OFP層 106、 Ga極性の第 2の SCH層 107をこの順 に禾貝層し 7こ。  n— On a GaN (OOOl) substrate 101, a buffer layer 102 having a layer thickness of 0.3 [m], a first cladding layer 103 having a layer thickness of 1.5 [μm], and a first layer having a layer thickness of 100 [nm] The SCH layer 104, the active layer 105 of the quantum well consisting of three layers, the OFP layer 106 with a thickness of 8 [nm], and the second SCH layer 107 with Ga polarity are formed in this order.
[0072] 極性反転層 108たる Mg単原子層は、 Ga極性の第 2の SCH層 107を形成した後、 基板温度を 850 [°C]に下げ、 TMGの供給を停止して少量の NHと、上記キャリアガ  [0072] After the formation of the Ga-polar second SCH layer 107, the Mg monoatomic layer, which is the polarity inversion layer 108, lowers the substrate temperature to 850 [° C], stops the TMG supply, and supplies a small amount of NH. , The above carrier
3  Three
スと、 10 [sccm]の Cp Mgを流すことにより積層した。  And 10 [sccm] Cp Mg.
2  2
続いて、 450 [ /ζ πι]厚、 40 [mm]径の GaN基板の Ga極性面（0001)上に TMGを 少量供給して、数分子層の N極性の p— GaNを形成した後、基板温度を 1000 [°C] に上げて、 N極性の第 3の SCH層 109、 N極性の第 2のクラッド層 110、コンタクト層（ N極性） 111を積層した。  Subsequently, after a small amount of TMG was supplied onto the Ga polar face (0001) of a GaN substrate having a thickness of 450 [/ ζ πι] and a diameter of 40 [mm], N-polar p-GaN having several molecular layers was formed. The substrate temperature was raised to 1000 [° C], and an N-polarity third SCH layer 109, an N-polarity second cladding layer 110, and a contact layer (N-polarity) 111 were laminated.
なお、バッファ—層 102の形成を 600 [で]、第 1のクラッド層 103及び第 2のクラッド 層 110の形成を 1050 [°C]、活性層 105の形成を 800 [°C]の条件化にて行った。 In addition, the formation of the buffer layer 102 is 600 [in], the first cladding layer 103 and the second cladding The layer 110 was formed at 1050 [° C], and the active layer 105 was formed at 800 [° C].
[0073] 以上のようにして窒化物半導体を成長させた基板を成長装置力 取り出し、所定の マスクを用いてコンタクト層 111の表面に熱 CVD (化学気相堆積)で SiO力もなる保 [0073] The substrate on which the nitride semiconductor has been grown as described above is taken out by the growth apparatus force, and the surface of the contact layer 111 is maintained on the surface of the contact layer 111 by thermal CVD (chemical vapor deposition) using a predetermined mask.
2 護膜を形成した。そして、基板のオリフラに平行となるようにレジスト露光技術を用い て層厚 300 [nm]、幅 3 [ m]のストライプ形状を形成した。  2 A protective film was formed. Then, a stripe shape having a layer thickness of 300 nm and a width of 3 [m] was formed using a resist exposure technique so as to be parallel to the orientation flat of the substrate.
[0074] 得られたウェハーを 200 [°C]の燐酸硝酸（2 : 1)の混合溶液中に 30 [s]間浸漬する ことにより、ウエットエッチングを行ってメサストライプ構造を得た。エッチング溶液は、 十分加熱し、内部の水分を蒸発除去したものを使用した。第 2のクラッド層 110のエツ チングレートは 1. 8 [ /ζ πιΖπΰη]であった。エッチング後の表面は平坦であり、第 2の SCH層 107の表面が露出して 、た。追加エッチングを行ってもメサ形状が変化しな V、ことから、第 2の SCH層 107がエッチング停止層の役割を果たして 、ることが分か つた ο [0074] The obtained wafer was immersed in a mixed solution of 200 [° C] phosphoric nitric acid (2: 1) for 30 [s] to perform wet etching to obtain a mesa stripe structure. The etching solution was heated sufficiently to evaporate and remove the internal moisture. The etching rate of the second cladding layer 110 was 1.8 [/ ζ πιΖπΰη]. The surface after etching was flat, and the surface of the second SCH layer 107 was exposed. The mesa shape does not change even if additional etching is performed V. Therefore, it can be seen that the second SCH layer 107 serves as an etching stop layer.
[0075] なお、メサ幅 1. 8 [ m]の場合、活性層の第 3番目の井戸層からエッチング表面ま での距離 hは 100 [nm]以上であることが好ましい。 100 [nm]より小さくなると、電流 電圧特性が線形関係にならな力つたためである。これは水平方向の屈折率差 Anが 大きくなり、高次モ―ドが許容されたためである。本実施形態 1においては、上記距 離 hは、 118 [nm]とした。  [0075] When the mesa width is 1.8 [m], the distance h from the third well layer of the active layer to the etching surface is preferably 100 [nm] or more. This is because when the current is smaller than 100 [nm], the current-voltage characteristics become linear. This is because the difference in refractive index An in the horizontal direction is large and higher modes are allowed. In the first embodiment, the distance h is 118 [nm].
[0076] 続いて、メサ側壁を絶縁層で覆うため、まず積層体 150上面に層厚 300[nm]の Zr O層をスパッタリング法で形成した。その後、ノ ッファードフッ酸 (BHF)に 70 [s]浸し Subsequently, in order to cover the mesa side wall with an insulating layer, a Zr 2 O layer having a layer thickness of 300 [nm] was first formed on the upper surface of the laminate 150 by a sputtering method. Then, immerse for 70 [s] in notched hydrofluoric acid (BHF).
2 2
て、リッジ上の SiOマスクパタ一ンをリフトオフし、 p— GaNコンタクト層（N極性） 111  Lift off the SiO mask pattern on the ridge, and p-GaN contact layer (N polarity) 111
2  2
の表面を露出させた。一方、 ZrO層は、エッチング速度が小さいためメサストライプ  The surface of was exposed. On the other hand, the ZrO layer has a mesa stripe due to its low etching rate.
2  2
の側壁を覆った状態で残っていた。得られたメサ幅は 2 [ m]であった。 NiZAuの p コンタクト電極を蒸着した後、酸素を含む窒素ガス環境で 600 [で]、 30 [s]間の高速 熱ァニールを行って、ォーミック接触を形成した。得られたウェハの裏面を研磨して 1 10 [ m]厚のウェハを得た。次いで、 n電極を形成して 400 [で]、 5 [min]間のァロ ィをして n側のォーミック接触を形成した。最後に p側に 300 [nm]厚の金を蒸着した  It remained with the side wall covered. The obtained mesa width was 2 [m]. After vapor deposition of NiZAu p-contact electrode, ohmic contact was formed by rapid thermal annealing between 600 [30] and 30 [s] in a nitrogen gas environment containing oxygen. The back surface of the obtained wafer was polished to obtain a 1 10 [m] thick wafer. Next, an n-electrode was formed, and an n-side ohmic contact was formed by alloying between 400 [in] and 5 [min]. Finally, 300 [nm] thick gold was deposited on the p side.
[0077] 上記工程を経たウェハは、ストライプ方向に対して垂直に劈開を行い、 LD共振器 面（1— 100)を得た。共振器端面には ARZHRの反射コ—ティング膜をつけた。最 後に得られた LDチップは p側を上にして、 A1Nのヒートシンクに融着して組み立てた The wafer that has undergone the above steps is cleaved perpendicular to the stripe direction, and the LD resonator A plane (1-100) was obtained. ARZHR reflective coating film was attached to the cavity end face. The last obtained LD chip was assembled by fusing to the heat sink of A1N with p side up
[0078] なお、本実施形態 1にお ヽては、メサストライプの側壁を ZrO層で覆った構造を用 Note that the first embodiment uses a structure in which the side walls of the mesa stripe are covered with a ZrO layer.
2  2
いたが、これに代えて SiO層を用いることもできる。その場合は、ストライプメサを形  However, a SiO layer can be used instead. In that case, shape a striped mesa
2  2
成した後に、積層体 150上面に SiO層を形成し、レジストをさらにその表面につけ、  After the formation, an SiO layer is formed on the upper surface of the laminate 150, and a resist is further applied to the surface.
2  2
ドライエッチングでレジストを除去してストライプメサ部の SiO層を露出させ、 BHFで  The resist is removed by dry etching to expose the SiO layer in the stripe mesa, and
2  2
ストライプメサ部の SiO層を除去して、レジストを除去し、電極を蒸着する。  Stripe mesa SiO layer is removed, resist is removed, and electrodes are deposited.
2  2
また、本実施形態 1においては、 P型クラッド層に P—Al Ga Nクラッド層を用  In Embodiment 1, a P-AlGaN cladding layer is used as the P-type cladding layer.
0. 07 0. 93  0. 07 0. 93
いたが、これに代えて p— [GaN (2. 5 [nm]) /Al Ga N (2. 5 [nm]) ]の超格  However, instead of this, super-p- [GaN (2.5 [nm]) / Al Ga N (2.5 [nm])]
0. 15 0. 85  0. 15 0. 85
子クラッド層（N極性)を用！/、ることもできる。  Uses a clad layer (N polarity)! / You can also.
[0079] 従来、 GaN系半導体レーザでは、 p— AlGaNにより構成されるクラッド層と、これと 接する P— GaNから構成される SCH層とはいずれも Ga極性であった。このため、ホ ールが上記クラッド層からこれと接する上記 SCH層を経過するときに、障害となるェ ネルギ障壁を形成していた。これは、 p— AlGaNにより構成されるクラッド層が引っ張 り歪を受けるために結晶の C軸方向に大きなピエゾ電界が生じ、その界面に正のピエ ゾ電荷が発生してホ一ルの注入障壁となるためである。  Conventionally, in the GaN-based semiconductor laser, both the clad layer made of p-AlGaN and the SCH layer made of P-GaN in contact with the clad layer have Ga polarity. For this reason, an energy barrier that becomes an obstacle when a hole passes from the clad layer to the SCH layer in contact therewith has been formed. This is because the clad layer composed of p-AlGaN is subjected to tensile strain, and a large piezoelectric field is generated in the C-axis direction of the crystal. Positive piezoelectric charges are generated at the interface, and a hole injection barrier is formed. It is because it becomes.
[0080] 本実施形態 1では、第 2のクラッド層と接する SCH層を Mg単原子層を介して第 2の SCH層と第 3の SCH層に分け、極性反転をさせているため、第 2のクラッド層 110と 接する SCH層（第 3の SCH層 109)とは、ともに N極性となる。従って、ホールのエネ ルギ障壁を形成しない。  In Embodiment 1, the SCH layer in contact with the second cladding layer is divided into the second SCH layer and the third SCH layer via the Mg monoatomic layer, and the polarity is inverted. Both the SCH layer in contact with the cladding layer 110 (third SCH layer 109) are N-polar. Therefore, it does not form a hole energy barrier.
[0081] 図 14は、本実施形態 1にかかる半導体レーザの電流 電圧特性と電流一光出力 特性を示したものである。発振時の動作電圧は 4. 5 [V]であり、従来のものに較べて 2. 5 [V]以上低下した。発振波長に相当するバンドギャップは 3. l [eV]である。す なわち、キャリア注入には、 3. 1 [V]の電圧が必要である。 p電極のコンタクト抵抗と p 層の抵抗と発振時の電流密度力も見積もられる動作電圧上昇分は約 1. 4[V]であり 、それによつて 4. 5 [V]の動作電圧が実現している。本実施形態 1の構造により、ホ ールのエネルギ障壁による動作電圧上昇は解消された。 [0082] 本実施形態 1によれば、極性反転層 108を設けることにより、 SCH層の極性を、こ の極性反転層を介して反転させることができる。具体的には、 Ga極性の第 2の SCH 層 107上に Mg単原子層たる極性反転層 108を積層せしめることにより、第 3の SCH 層 109を N極性、第 2の SCH層 107を Ga極性とすることができる。第 3の SCH層 10 9は、 N極性なのでウエットエッチングにより良好にエッチングされる。一方、第 2の SC H層 107は、 Ga極性なのでエッチング停止層の役割を果たす。従って、極性反転層 108を用いて SCH層の極性を反転させることにより、第 3の SCH層 109をウエットェ ツチング法により制度よくエッチングしつつ、第 2の SCH層 107をエッチング停止層と することができる。 FIG. 14 shows current-voltage characteristics and current-light output characteristics of the semiconductor laser according to the first embodiment. The operating voltage during oscillation was 4.5 [V], a drop of more than 2.5 [V] compared to the conventional one. The band gap corresponding to the oscillation wavelength is 3. l [eV]. In other words, a voltage of 3.1 [V] is required for carrier injection. The operating voltage rise that can be estimated for the contact resistance of the p electrode, the resistance of the p layer, and the current density force during oscillation is about 1.4 [V], and as a result, an operating voltage of 4.5 [V] is realized. Yes. With the structure of the first embodiment, the operating voltage rise due to the energy barrier of the hall is eliminated. According to the first embodiment, by providing the polarity inversion layer 108, the polarity of the SCH layer can be inverted through this polarity inversion layer. Specifically, the third SCH layer 109 is N-polarized and the second SCH layer 107 is Ga-polarized by stacking the polarity inversion layer 108, which is an Mg monoatomic layer, on the Ga-polarized second SCH layer 107. It can be. Since the third SCH layer 109 is N-polar, it is well etched by wet etching. On the other hand, the second SCH layer 107 serves as an etching stop layer because it has Ga polarity. Therefore, by inverting the polarity of the SCH layer using the polarity inversion layer 108, the second SCH layer 107 can be used as an etching stop layer while the third SCH layer 109 is systematically etched by the wet etching method. it can.
[0083] 本実施形態 1によれば、第 2の SCH層 107がエッチング停止層の役目を果たして いるので、ウエットエッチングにより第 2の SCH層、及びその下層に結晶欠陥が生じ なかった。従って、再成長時に欠陥の拡散が起こらず、活性層への損傷がな力つた。 また、メサストライプを形成するに際して、メサ脇の 100 [nm]の第 3の SCH層 109を ± 2 [nm]の高精度に制御することができた。その結果、設計どおりの構造を得ること ができた。その結果、ドライエッチング法に比して、優れた信頼性を有する窒化物半 導体素子を提供することができた。  According to the first embodiment, since the second SCH layer 107 serves as an etching stop layer, no crystal defects were generated in the second SCH layer and its lower layer by wet etching. Therefore, no diffusion of defects occurred during regrowth, and the active layer was not damaged. Moreover, when forming the mesa stripe, the 100 [nm] third SCH layer 109 beside the mesa could be controlled with high accuracy of ± 2 [nm]. As a result, we were able to obtain the structure as designed. As a result, it was possible to provide a nitride semiconductor device having superior reliability as compared with the dry etching method.
[0084] また、本実施形態 1によれば、 p電極 112を N面 (N極性表面）に形成することができ るため、低いァ-—ル温度で pコンタクトを形成することができる。これは、 N極性の P - GaN表面は化学的に活性なため、 N極性の p - GaNからなるコンタクト層 111上 に形成された P電極は、加熱により合金化しやすいためである。すなわち、 N極性の P GaN表面の N原子に結合している Ga原子は、表面側に 3本の結合手を持ってお り、表面力も来る p電極の金属と反応しやすい。特に、 p電極として、仕事関数が大き ぐ GaNと反応性の高い金属を用いるとァニール温度を低くできる。  [0084] Further, according to the first embodiment, since the p-electrode 112 can be formed on the N-plane (N-polar surface), the p-contact can be formed at a low wheel temperature. This is because the N-polar P-GaN surface is chemically active, and the P-electrode formed on the contact layer 111 made of N-polar p-GaN is easily alloyed by heating. In other words, Ga atoms bonded to N atoms on the surface of N-polar PGaN have three bonds on the surface side and are likely to react with the metal of the p electrode, which also has surface forces. In particular, the annealing temperature can be lowered by using a metal having a high work function and GaN as the p-electrode.
[0085] さらに、以下のような効果を得ることもできた。  [0085] Further, the following effects could be obtained.
第 1に、 200 [mW]の高出力動作を行っても、基本横モードが保たれ、 2. 0の小さ V、アスペクト比が実現できると 、う利点が得られた。  First, even if high power operation of 200 [mW] is performed, the basic transverse mode is maintained, and a small V of 2.0 and an aspect ratio can be realized.
第 2に、ピエゾに起因する第 2の SCH層 109と第 2のクラッド層 110のホ―ル障壁を なくし、 25 [で]、 30 [mW]動作時の電圧を 4. 8 [V]に低減させることができた。 第 3に、電圧の低減により、 70 [°C] , 70 [mW]で 2000時間以上の直流電流動作 を実現し、信頼性を大きく向上させることができた。 Secondly, the hole barrier of the second SCH layer 109 and the second cladding layer 110 caused by piezo is eliminated, and the voltage during operation at 25 [in] and 30 [mW] is set to 4.8 [V]. It was possible to reduce. Thirdly, by reducing the voltage, DC current operation for over 2000 hours was achieved at 70 [° C] and 70 [mW], greatly improving reliability.
第 4に、素子加工工程で、 90[%]以上の安定な素子歩留まりが実現でき、素子コ ストが低下した。  Fourth, in the element processing process, a stable element yield of 90 [%] or more was realized, and the element cost was reduced.
第 5に、ドライエッチング装置などの高価な装置が不必要なため、素子の生産コスト を低く抑えることができた。  Fifth, since expensive equipment such as dry etching equipment is unnecessary, the production cost of the element could be kept low.
[0086] なお、本実施形態 1のレーザ素子の発振波長は、 InGaN活性層の In組成を増加さ せ、活性層 105に Siを 1 X 1018 [cm—3]の濃度でド—ビングし、量子井戸幅を 3 [nm] に大きくすることで 487 [nm]まで、発光効率の顕著な低下なしに、変化させることが できた。本実施形態 1においては、緑青色の発光である 480 [nm]帯の LDも得ること ができた。 Note that the oscillation wavelength of the laser device of Embodiment 1 is that the In composition of the InGaN active layer is increased, and Si is doped into the active layer 105 at a concentration of 1 × 10 18 [cm −3 ]. By increasing the quantum well width to 3 [nm], it was possible to change it to 487 [nm] without a significant decrease in luminous efficiency. In Embodiment 1, a 480 [nm] band LD that emits greenish-blue light can also be obtained.
[0087] [変形例 1]  [0087] [Modification 1]
次に、上記実施形態 1に係る窒化物半導体レーザの製造方法とは異なる例につい て説明する。  Next, an example different from the nitride semiconductor laser manufacturing method according to the first embodiment will be described.
[0088] 本変形例 1は、基本的な構成は上記実施形態 1と同様であるが、以下の点が異な つている。すなわち、上記実施形態 1においては、 MOVPE法により積層体 150を形 成したが、本変形例 1においては、結晶成長を分子線ェピタキシ法 (以下、「MBE法 」と略記する）と MOVPE法とを組み合わせることにより製造している点が異なる。より 具体的には、 Ga極性の半導体層を結晶成長を MOVPE (有機金属気相成長）法を 用いて行!、、 N極性の半導体層を結晶成長を MBE (分子線ェピタキシ)法を用いて 行った。また、上記実施形態 1においては、極性反転層 108として、 Mg単原子層た る極性反転層 108を用いているのに対し、本変形例 1においては、 0. 1 [%]の Mgを 含む Gaの 2原子層を用いている点が異なる。このようにしたのは、 MBE法において は、 Mg単原子層より A1又は Gaの 2原子層を用 、たほうが高品質の極性反転結晶が 得られたためである。  [0088] Although the basic configuration of the first modification is the same as that of the first embodiment, the following points are different. That is, in the first embodiment, the laminate 150 is formed by the MOVPE method. However, in the first modification, the crystal growth is a molecular beam epitaxy method (hereinafter abbreviated as “MBE method”), the MOVPE method, It differs in that it is manufactured by combining. More specifically, crystal growth of Ga-polar semiconductor layers is performed using MOVPE (metal organic vapor phase epitaxy), and crystal growth of N-polar semiconductor layers is performed using MBE (molecular beam epitaxy). went. In the first embodiment, the polarity inversion layer 108, which is an Mg monoatomic layer, is used as the polarity inversion layer 108, whereas in the first modification, 0.1 [%] Mg is included. The difference is that two atomic layers of Ga are used. This is because, in the MBE method, a high-quality polarity reversal crystal was obtained by using the A1 or Ga diatomic layer rather than the Mg monoatomic layer.
[0089] 本変形例 1においては、 GaN (0001)基板 100上に第 2の SCH層 107までを上記 実施形態 1と同様にして MOVPE法により積層した。その後、 0. 1 [%]の Mgを含む Gaの 2原子層からなる極性反転層 108を積層した。極性反転層 108を形成後、上記 実施形態 1にお ヽて説明した極性反転層 108からコンタクト層 111までを MBE法に より積層した。 In the first modification, up to the second SCH layer 107 is laminated on the GaN (0001) substrate 100 by the MOVPE method in the same manner as in the first embodiment. Thereafter, a polarity inversion layer 108 composed of a Ga atomic layer containing 0.1 [%] Mg was laminated. After forming the polarity inversion layer 108, the above The polarity inversion layer 108 to the contact layer 111 described in the first embodiment are stacked by the MBE method.
[0090] MBE法における Gaと A1と Mgソースは、金属原料を用いた。 Gaセル温度は、 970 [ で]、 A1セル温度は、 1100[°C]に設定した。また、 N源には、 13. 56 [MHz]の高周 波でプラズマ状態にした活性窒素を用いた。窒素流量を 1. 5 [Sccm]、高周波プラズ マを 350[W]に設定し、活性窒素を供給しながら基板温度を上げた。この時の Nフラ ックス強度は 5 X 10_5[torr]であった。基板温度 780 [で]〜 800 [。C]で酸ィ匕膜を蒸 発させ、反射高工ネルギ電子線回折 (以下、「RHEED」という）により成長表面を観 察し、（1 X 1)の表面再構成バタ—ンを確認した。その後、 Gaを少量供給し、 700 [ °C]に温度を下げ、（5 X 5)の Ga面を確認した。 [0090] Metal sources were used for the Ga, A1, and Mg sources in the MBE method. The Ga cell temperature was set to 970 [in], and the A1 cell temperature was set to 1100 [° C]. The N source used was active nitrogen in a plasma state at a high frequency of 13.56 [MHz]. The nitrogen flow rate was set to 1.5 [ S ccm], the high-frequency plasma was set to 350 [W], and the substrate temperature was raised while supplying active nitrogen. The N flux strength at this time was 5 X 10 _5 [torr]. Substrate temperature 780 [in] ~ 800 [. In [C], the oxide film was evaporated, and the growth surface was observed by reflection-enhanced energy electron diffraction (hereinafter referred to as “RHEED”), confirming the surface reconstruction pattern of (1 X 1). Then, a small amount of Ga was supplied, the temperature was lowered to 700 [° C], and the (5 × 5) Ga surface was confirmed.
[0091] さらに、 0. 1 [%]の Mgを含む Gaを 1原子層供給し（1 X 1)に変化させた後、 Gaと Nと Mgを同時に供給して N極性の p - GaN層 109の成長を開始し、直ちに 800 [°C] に温度を上げた。そのときの Nフラックス強度は 8 X 10_5[torr]であった。（1 X 1)の 状態で、 pクラッドと pコンタクト層の成長を行った。 p— AlGaNクラッド層の成長は 87 0[°C]で行った。成長終了後に基板温度を 300[°C]に下げて N供給を止めると、 (3 X 3)の N面が得られることを確認した。 pクラッド層の p濃度は 6 X 1017[cm_3]、 pクラ ッド層の比抵抗は 0. 8 [ Q cm]、 pコンタクト抵抗率は 4 X 10_5[ Q cm2]であった。 [0091] Further, after supplying Ga containing 0.1 [%] Mg to one atomic layer and changing it to (1 X 1), Ga, N, and Mg are simultaneously supplied to form an N-polar p-GaN layer The growth of 109 was started and the temperature was immediately raised to 800 [° C]. The N flux strength at that time was 8 X 10 _5 [torr]. The p-cladding and p-contact layers were grown in the (1 X 1) state. The growth of the p-AlGaN cladding layer was performed at 870 [° C]. When the substrate temperature was lowered to 300 [° C] after the growth was completed and the N supply was stopped, it was confirmed that the (3 X 3) N face could be obtained. The p-concentration of the p-cladding layer was 6 X 10 17 [cm _3 ], the specific resistance of the p-cladding layer was 0.8 [Q cm], and the p-contact resistivity was 4 X 10 _5 [Q cm 2 ]. .
[0092] 本変形例 1によれば、 MBE法を用いているので、 RHEEDにより成長表面を観察し ながらシャツタで原料やドーパント供給の切り替えが急峻にできる。このため、極性反 転の制御が行いやすぐ高品質の N極性の GaN結晶が得られる。また、成長温度と 窒素圧の最適化がしゃすい。さらに NHや Hを用いないので、結晶中に水素が取り  [0092] According to the first modification, since the MBE method is used, it is possible to sharply switch the supply of raw materials and dopants with a shirter while observing the growth surface with RHEED. Therefore, polarity inversion can be controlled and high-quality N-polar GaN crystals can be obtained immediately. In addition, optimization of growth temperature and nitrogen pressure is difficult. Furthermore, since NH and H are not used, hydrogen is taken into the crystal.
3 2  3 2
込まれない。このため、 Mgドーパントの水素不活性ィ匕を防止できる。  Not included. For this reason, the hydrogen inertness of Mg dopant can be prevented.
また、本変形例 1によれば、 MBE法を用いているので第 2のクラッド層 110の短周 期の超格子構造が正確にできる利点を有する。 MBE法では活性層近傍の Mg分布 が MOVPE法より急峻に制御できるため、素子の特性と信頼性向上にも有利である  Further, according to the present modification 1, since the MBE method is used, there is an advantage that the superlattice structure of the second cladding layer 110 in the short period can be accurately set. In the MBE method, the Mg distribution in the vicinity of the active layer can be controlled more rapidly than in the MOVPE method, which is advantageous for improving device characteristics and reliability.
[0093] [変形例 2] [0093] [Modification 2]
次に、上記実施形態 1及び上記変形例 1に係る窒化物半導体レーザの製造方法と は異なる変形例 2につ 、て説明する。 Next, a method for manufacturing a nitride semiconductor laser according to the first embodiment and the first modification example and A different modification 2 will be described.
本変形例 2は、基本的な構成は上記実施形態 1と同様であるが、以下の点が異な つている。すなわち、上記実施形態 1においては、すべての半導体層を MOVPE法 により積層体を形成したのに対し、本変形例 1においては、すべての半導体層を MB E法により製造して 、る点が異なる。  The basic configuration of the second modification is the same as that of the first embodiment except for the following points. That is, in the first embodiment, all the semiconductor layers are formed by the MOVPE method, whereas in the first modification, all the semiconductor layers are manufactured by the MBE method. .
[0094] 本変形例 2においては、まず、フラックス強度 5 X 10_5[torr]の活性窒素を供給し ながら GaN (0001)基板 100の温度を 780 [で]〜 800 [°C]まで上げて酸ィ匕膜を蒸 発させた。そして、（1 X 1)の表面再構成に対応する RHEEDバタ—ンを確認した後 、ノッファ層 102を構成する n—GaNの成長を始めた。バッファ層 102や第 1の SCH 層を構成する n— GaN、あるいは、第 1のクラッド層を構成する n— AlGaNの nド一パ ントには Siを用いた。 RHEEDパタ一ンのストリ一クが安定した後、第 1のクラッド層 10 3を構成する n— AlGaNを 870 [°C]で成長させた。活性層 105を構成する InGaN層 の成長では、 Inセル温度を 740 [で]、基板温度を 700 [°C]に設定して。 Nの条件は 同じでよい。 [0094] In the second modification, first, the temperature of the GaN (0001) substrate 100 is increased from 780 [° C] to 800 [° C] while supplying active nitrogen having a flux strength of 5 X 10 _5 [torr]. The acid capsule was evaporated. Then, after confirming the RHEED pattern corresponding to the surface reconstruction of (1 X 1), the growth of n-GaN constituting the noffer layer 102 was started. Si was used for n-GaN constituting the buffer layer 102 and the first SCH layer or n-AlGaN constituting the first cladding layer. After the RHEED pattern was stabilized, n-AlGaN constituting the first cladding layer 103 was grown at 870 [° C]. In the growth of the InGaN layer composing the active layer 105, the In cell temperature was set to 740 [in] and the substrate temperature was set to 700 [° C]. The conditions for N can be the same.
その後の積層体の形成法は、上記変形例 1の製造方法と同じである。  The subsequent formation method of the laminated body is the same as the manufacturing method of Modification 1 described above.
[0095] 本変形例 2によれば、積層体の形成に MBE法を採用することにより、 InGaN活性 層の成長レートが低下しない。これは、 MBE法では水素が取り込まれることがないの で、水素による Inの取り込み阻害の問題が発生しないからである。従って、 MBE法を 用いることにより、 In組成の高い結晶でも、 In組成揺らぎの小さい高品質な結晶が得 られる。 [0095] According to the second modification, the growth rate of the InGaN active layer does not decrease by adopting the MBE method for forming the stacked body. This is because the MBE method does not take in hydrogen, so there is no problem of inhibition of In uptake by hydrogen. Therefore, by using the MBE method, even a crystal having a high In composition can be obtained a high-quality crystal having a small In composition fluctuation.
[実施形態 2]  [Embodiment 2]
[0096] 次に、上記実施形態 1の窒化物半導体レーザ 100とは異なる例について説明する 。図 2は、実施形態 2に係る窒化物半導体レーザ 200の断面図である。なお、以降の 説明において、説明の便宜上、層厚、組成、機能が同一の層構造の場合には、前述 した符号と同一のものを使用し、その説明を省略する。  Next, an example different from the nitride semiconductor laser 100 of the first embodiment will be described. FIG. 2 is a cross-sectional view of the nitride semiconductor laser 200 according to the second embodiment. In the following description, for convenience of description, in the case of a layer structure having the same layer thickness, composition, and function, the same reference numerals as those described above are used, and description thereof is omitted.
[0097] 基板としては、厚さ 110 [ m]の n型 GaN (0001)基板 101を用いた。この n型 Ga N (0001)基板 101上には、図 2に示すように、以下の層が積層されている。すなわ ち、バッファ層 102、第 1のクラッド層 103、第 1の SCH層 104、 3層からなる量子井戸 の活性層 105、 OFP層 106、第 2の SCH層 207、第 1の超格子クラッド層 208、極性 反転層 209、第 2の超格子クラッド層 210、コンタクト層 111が、この順に積層されて いる（以下、これらの層をまとめて積層体 250という）。なお、本実施形態 2に係る第 1 の半導体層は第 1の超格子クラッド層 208であり、第 2の半導体層は第 2の超格子ク ラッド層 210である。 As the substrate, an n-type GaN (0001) substrate 101 having a thickness of 110 [m] was used. On the n-type Ga N (0001) substrate 101, the following layers are stacked as shown in FIG. That is, a quantum well comprising a buffer layer 102, a first cladding layer 103, a first SCH layer 104, and three layers. Active layer 105, OFP layer 106, second SCH layer 207, first superlattice cladding layer 208, polarity inversion layer 209, second superlattice cladding layer 210, and contact layer 111 are laminated in this order. (Hereinafter, these layers are collectively referred to as a laminate 250). Note that the first semiconductor layer according to the second embodiment is the first superlattice cladding layer 208, and the second semiconductor layer is the second superlattice cladding layer 210.
[0098] 本実施形態 2に係る第 2の SCH層 207は、層厚 80[nm]の p— GaN (SCH)層によ り構成される。また、第 1の超格子クラッド層 208は、層厚 20[nm]の p— [GaN (2. 5 [nm]) /Al Ga N (2. 5 [nm]) X 4]により構成される。上記 n— GaN (OOOl)  [0098] The second SCH layer 207 according to the second embodiment is formed of a p-GaN (SCH) layer having a layer thickness of 80 [nm]. The first superlattice cladding layer 208 is composed of p- [GaN (2.5 [nm]) / AlGaN (2.5 [nm]) X 4] having a layer thickness of 20 [nm]. . N— GaN (OOOl) above
0. 15 0. 85  0. 15 0. 85
基板 101から第 1の超格子クラッド層 208までの極性は、上述した Ga極性 220となる ように構成されている。  The polarity from the substrate 101 to the first superlattice cladding layer 208 is configured to be the Ga polarity 220 described above.
[0099] 極性反転層 209は、 Mg濃度 3 X 102G [cm—3]で高濃度ドーピングされた層厚 2 [n m]の Mg+ : GaN層より構成され、第 2の超格子クラッド層 210は、層厚 0. 6 [ /ζ πι]の リッジ型 p—[GaN (2. 5 [nm]) ZAl Ga N (2. 5 [nm]) X 120]により構成され [0099] The polarity inversion layer 209 is composed of a Mg +: GaN layer having a layer thickness of 2 [nm] that is highly doped with an Mg concentration of 3 X 10 2G [cm- 3 ], and the second superlattice cladding layer 210 Ridge type p— [GaN (2.5 [nm]) ZAl Ga N (2.5 [nm]) X 120] with a layer thickness of 0.6 [/ ζ πι]
0. 15 0. 85  0. 15 0. 85
る。第 2の超格子クラッド層 210からコンタクト層 111までの極性は、 N極性 221となる ように構成されている。  The The polarity from the second superlattice cladding layer 210 to the contact layer 111 is configured to be N polarity 221.
[0100] 上記積層体 250の上面には、電流狭窄マスク 113、 P電極 212が形成されている。  [0100] On the top surface of the laminate 250, a current confinement mask 113 and a P electrode 212 are formed.
また、 n—GaN (0001)基板 101の裏面には、 N電極 114が形成されている。 P電極 212は、 20[nm]の Pdと 20[nm]の Ptにより形成されている。そして、窒素ガス環境 で 400 [°C]、 10 [min]間のァ-—ノレを行って、ォーミック接触を形成した。  An N electrode 114 is formed on the back surface of the n-GaN (0001) substrate 101. The P electrode 212 is formed of 20 [nm] Pd and 20 [nm] Pt. An ohmic contact was formed by performing a keyhole between 400 [° C] and 10 [min] in a nitrogen gas environment.
[0101] 本実施形態 2においては、以下の点において上記実施形態 1と異なる。すなわち、 上記実施形態 1にお ヽては、極性反転界面が p— GaNカゝら構成される SCH層内部（ 第 2の SCH層 107上に形成された極性反転層 108の表面）にあったが、本実施形態 2では、極性反転界面が超格子クラッド層内部（第 1の超格子クラッド層 208上に形成 された極性反転層 209の表面）にある点が異なる。  [0101] The second embodiment differs from the first embodiment in the following points. That is, in Embodiment 1 above, the polarity reversal interface was inside the SCH layer (the surface of the polarity reversal layer 108 formed on the second SCH layer 107) composed of p-GaN. However, the second embodiment is different in that the polarity inversion interface is inside the superlattice cladding layer (the surface of the polarity inversion layer 209 formed on the first superlattice cladding layer 208).
また、上記実施形態 1においては、極性反転層 108として、 Mg単原子層を用いた 力 本実施形態 2においては、極性反転層 209として層厚 2[nm]の Mg+ : GaN層を 用いている点が異なる。  In the first embodiment, a force using an Mg monoatomic layer is used as the polarity inversion layer 108. In the second embodiment, a Mg +: GaN layer having a layer thickness of 2 [nm] is used as the polarity inversion layer 209. The point is different.
また、上記実施形態 1においては、第 2のクラッド層として p—Al Ga Nを用い たが、本実施形態 2では上述の超格子クラッド層を用いた。超格子クラッド層の平均 A1濃度は 0. 07であり、上記実施形態 1と同じである。 In Embodiment 1 above, p-AlGaN is used as the second cladding layer. However, in the second embodiment, the superlattice clad layer described above was used. The average A1 concentration of the superlattice cladding layer is 0.07, which is the same as in the first embodiment.
[0102] 本実施形態 2によれば、極性反転層 209を設けることにより、超格子クラッド層の極 性を、この極性反転層を介して反転できる。具体的には、 Ga極性の第 1の超格子クラ ッド層 208上に極性反転層 209を介することにより、 N極性の第 2の超格子クラッド層 210を積層せしめることができる。第 2の超格子クラッド層 210は、 N極性なのでゥエツ トエッチングにより良好にエッチングされる。一方、第 1の超格子クラッド層 208は、 Ga 極性なのでエッチング停止層として機能する。従って、極性反転層 209を用いて超 格子クラッド層の極性を反転させることにより、第 1の超格子クラッド層をエッチング停 止層とすることができた。  According to the second embodiment, by providing the polarity inversion layer 209, the polarity of the superlattice cladding layer can be inverted through this polarity inversion layer. Specifically, the N-polarity second superlattice cladding layer 210 can be stacked on the Ga-polarity first superlattice cladding layer 208 via the polarity inversion layer 209. Since the second superlattice cladding layer 210 is N-polar, it is etched well by wet etching. On the other hand, the first superlattice cladding layer 208 functions as an etching stop layer because it has Ga polarity. Therefore, by inverting the polarity of the superlattice cladding layer using the polarity inversion layer 209, the first superlattice cladding layer could be used as an etching stop layer.
[0103] また、本実施形態 2によれば、第 1の超格子クラッド層 208がエッチング停止層の役 目を果たしているので、結晶欠陥が発生しな力つた。そのため、再成長時に欠陥が 拡散することもなく活性層 105への損傷がな力つた。また、メサストライプを形成する に際して、メサ脇を高精度に制御された半導体素子を得ることができた。その結果、 設計どおりの構造を得ることができた。  [0103] Further, according to the second embodiment, the first superlattice cladding layer 208 serves as an etching stop layer, so that no crystal defects are generated. As a result, the active layer 105 was not damaged during the regrowth without any defects diffusing. In addition, when forming the mesa stripe, a semiconductor element in which the mesa side was controlled with high precision could be obtained. As a result, the structure as designed was obtained.
また、本実施形態 2によれば、超格子クラッド層の p—Al Ga N (2. 5 [nm])  Further, according to Embodiment 2, the p-AlGaN (2.5 [nm]) of the superlattice cladding layer is used.
0. 15 0. 85  0. 15 0. 85
力 発生したホールキャリアが p— GaN (2. 5 [nm])に溜まる構造により、 pクラッドの 実効的なキャリア濃度を I X 1018[cm_3]程度に高めることができる。このため、素子 抵抗が小さくなる利点がある。 Due to the structure in which force-generated hole carriers accumulate in p-GaN (2.5 [nm]), the effective carrier concentration of the p-clad can be increased to about IX 10 18 [cm _3 ]. For this reason, there is an advantage that the element resistance is reduced.
[0104] また、本実施形態 2によれば、 p電極 212を N面 (N極性表面）に接することができる ため、上記実施形態 1と同様に低いァ-—ル温度で pコンタクトを形成することができ る。とりわけ本実施形態 2においては、層電極 212の構成元素として Pdを含んでいる ため、コンタクト表面が清浄であれば、 N面に 10_3[ Ω «η2]台のコンタクト抵抗を有 する ρ型電極が形成できる。これは、接触界面に PdGaなどの合金が形成されるため である。さらに、 400[°C]以下のァ-—ルによりコンタクト抵抗は、 10_5[ Q cm2]台〜 10_4[ Ω。πι2]台に低減できる。 [0104] Also, according to the second embodiment, the p-electrode 212 can be in contact with the N-plane (N-polar surface), so that a p-contact is formed at a low mark temperature as in the first embodiment. be able to. In particular, in Embodiment 2, since Pd is included as a constituent element of the layer electrode 212, if the contact surface is clean, it has a contact resistance of 10 _3 [Ω «η 2 ] on the N plane. An electrode can be formed. This is because an alloy such as PdGa is formed at the contact interface. Furthermore, the contact resistance is 10 _5 [Q cm 2 ] to 10 _4 [Ω by a cable of 400 [° C] or less. πι 2 ] level.
[0105] [実施形態 3]  [Embodiment 3]
次に、上記実施形態 1及び 2の窒化物半導体レーザとは異なる例について説明す る。図 3は、実施形態 3に係る窒化物半導体レーザ素子 300の断面図である。 Next, an example different from the nitride semiconductor lasers of the first and second embodiments will be described. The FIG. 3 is a cross-sectional view of the nitride semiconductor laser element 300 according to the third embodiment.
[0106] 基板としては、転位密度が l X 106[cm_2]で層厚 110[ /ζ πι]の n— GaN (OOOl) 基板 301を用いた。基板の転位密度は、 5 X 106[cm_2]以下のものを用いることが 好ましい。転位密度を 5 X 106[cm_2]以下のものを用いることにより、平均転位間隔 が 5 [ μ m]以上の転位の影響を強く受けな 、ため、平坦な成長面を得ることができる ためである。 [0106] As the substrate, the dislocation density using n- GaN (OOOl) substrate 301 of thickness 110 [/ ζ πι] in l X 10 6 [cm_ 2] . The dislocation density of the substrate is preferably 5 × 10 6 [cm — 2 ] or less. By using a dislocation density of 5 × 10 6 [cm_ 2 ] or less, the average dislocation interval is not strongly affected by dislocations of 5 [μm] or more, so a flat growth surface can be obtained. It is.
[0107] この n— GaN (0001)基板 301上には、図 3に示すように、以下の層が積層されて いる。すなわち、第 1のノ ッファ層 302、極性反転層 303、第 2のバッファ層 304、第 1 のクラッド層 305、第 1の SCH層 306、活性層 307、 OFP層 308、第 2の SCH層 309 、超格子クラッド層 310、コンタクト層 111が、この順に積層されている（以下、これら の層をまとめて積層体 350という）。なお、本実施形態 3における第 1の半導体層は第 1のバッファ層 302であり、第 2の半導体層は第 2のバッファ層 304である。  On the n-GaN (0001) substrate 301, the following layers are stacked as shown in FIG. That is, the first notch layer 302, the polarity inversion layer 303, the second buffer layer 304, the first cladding layer 305, the first SCH layer 306, the active layer 307, the OFP layer 308, and the second SCH layer 309 The superlattice cladding layer 310 and the contact layer 111 are laminated in this order (hereinafter, these layers are collectively referred to as a laminated body 350). Note that the first semiconductor layer in Embodiment 3 is the first buffer layer 302, and the second semiconductor layer is the second buffer layer 304.
[0108] 本実施形態 3に係る第 1のバッファ層 302は、層厚 0. 2 [ m]の n— GaNにより構 成される。また、極性反転層 303は、 Mg単原子層により構成される。上記 n— GaN ( 0001)基板 301から第 1のバッファ層 302までの極性は、 Ga極性 320となるように構 成されている。  [0108] The first buffer layer 302 according to the third embodiment is made of n-GaN having a layer thickness of 0.2 [m]. The polarity inversion layer 303 is composed of an Mg monoatomic layer. The polarity from the n-GaN (0001) substrate 301 to the first buffer layer 302 is configured to be Ga polarity 320.
[0109] 第 2のバッファ層 304は、層厚 0. 1 [ m]の n— GaNにより構成され、第 1のクラッド 層 305は、層厚 1. 5 [ m]の n— Al Ga Nにより構成されている。そして、第 1  [0109] The second buffer layer 304 is made of n-GaN having a layer thickness of 0.1 [m], and the first cladding layer 305 is made of n-AlGaN having a layer thickness of 1.5 [m]. It is configured. And first
0. 07 0. 93  0. 07 0. 93
の SCH層 306は n— GaN、活性層 307は、 In Ga N (2. 5 [nm]) /GaN (10[n  SCH layer 306 is n-GaN, and active layer 307 is InGaN (2.5 [nm]) / GaN (10 [n
0. 2 0. 8  0. 2 0. 8
m])の 3層の InGaN— 3QW活性層から構成され、 OFP層 308は、 p—Al Ga  m]) three layers of InGaN—3QW active layer, OFP layer 308 is composed of p—Al Ga
0. 14 0. 86 0. 14 0. 86
Nより、第 2の SCH層は層厚 100[nm]の p— GaNより構成される。さらに、超格子ク ラッド層 310は、層厚 0. 6 [ m]の p— Al Ga NZGaNより、コンタクト層 111 From N, the second SCH layer is composed of p-GaN with a layer thickness of 100 [nm]. Furthermore, the superlattice cladding layer 310 is made of p-AlGa NZGaN with a layer thickness of 0.6 [m], and the contact layer 111
0. 14 0. 86  0. 14 0. 86
は、層厚 20[nm]の p— Gaより構成されている。第 2のノ ッファ層 304力も、コンタクト 層 111までの極性は、 N極性 321となるように構成されて！、る。  Is composed of p-Ga with a layer thickness of 20 [nm]. The second noffer layer 304 force is also configured so that the polarity up to the contact layer 111 is N polarity 321! RU
[0110] 上記積層体 350の上面には、埋め込み層 313、及び P電極 212が形成されている[0110] A buried layer 313 and a P-electrode 212 are formed on the upper surface of the laminate 350.
。また、 n— GaN (0001)基板 301の裏面には、 N電極 114が形成されている。 . An N electrode 114 is formed on the back surface of the n-GaN (0001) substrate 301.
[0111] 埋め込み層 313は、以下の方法により形成した。まず、ェピウェハ上に厚さ 300 [n m]のストライプ状の SiOマスクを形成し、上記実施形態 1と同じ方法でウエットエッチ ングを行う。その後、第 1のバッファ層 302上に、アンドープ i—Al Ga In N [0111] The buried layer 313 was formed by the following method. First, a striped SiO mask having a thickness of 300 [nm] is formed on an epoxy wafer, and wet etching is performed in the same manner as in the first embodiment. Perform. Then, on the first buffer layer 302, undoped i-Al Ga In N
0. 15 0. 80 0. 05 埋め込み層 313を選択領域成長させ、リッジメサを埋め込んだ。リッジ幅は 1. 6 [ m ]である。  0. 15 0. 80 0. 05 The buried layer 313 was grown in a selected region, and a ridge mesa was buried. The ridge width is 1.6 [m].
[0112] 埋め込み層 313は、高抵抗なため電流狭窄の働きをする。また、埋め込み層 313 は、屈折率が活性層より小さいため、横方向に光を閉じ込める働きがある。  [0112] The buried layer 313 functions as a current constriction because of its high resistance. Further, since the buried layer 313 has a refractive index smaller than that of the active layer, it functions to confine light in the lateral direction.
本実施形態 3に係る埋め込み層 313は、構成元素として Inを含むため成長温度を 800 [°C]以下に低くできる。本実施形態 3においては、埋め込み層 313の成長温度 を 780[°C]とした。活性層 307の成長温度 800[°C]より低く設定することにより、活性 層 307の劣化を防ぐことができる。  Since the buried layer 313 according to the third embodiment includes In as a constituent element, the growth temperature can be lowered to 800 [° C.] or lower. In the third embodiment, the growth temperature of the buried layer 313 is 780 [° C.]. By setting the growth temperature of the active layer 307 lower than 800 [° C.], the active layer 307 can be prevented from deteriorating.
[0113] 本実施形態 3によれば、極性反転層 303を設けることにより、ノ ッファ層の極性を、 この極性反転層を介して反転できる。具体的には、 Ga極性の第 1のノ ッファ層 302 上に Mg単原子層たる極性反転層 303を介することにより、 N極性の第 2のバッファ層 304を積層せしめることができる。第 2のバッファ層 304及び、この第 2のバッファ層 3 04上に積層される第 1のクラッド層 305からコンタクト層 111までの層は、 N極性なの でウエットエッチングにより良好にエッチングされる。一方、第 1のバッファ層 302は、 Ga極性なのでウエットエッチングによりエッチングされない。従って、極性反転層 303 を用いてバッファ層の極性を反転させることにより、第 1のバッファ層をエッチング停 止層とすることができた。その結果、高精度に制御された半導体素子を得ることがで きた。  [0113] According to the third embodiment, by providing the polarity inversion layer 303, the polarity of the notch layer can be inverted through this polarity inversion layer. Specifically, the N-polar second buffer layer 304 can be laminated on the Ga-polar first notch layer 302 via the polarity inversion layer 303 which is an Mg monoatomic layer. The second buffer layer 304 and the layers from the first clad layer 305 to the contact layer 111 stacked on the second buffer layer 304 are N-polar, so that they are satisfactorily etched by wet etching. On the other hand, since the first buffer layer 302 is Ga-polar, it is not etched by wet etching. Therefore, by inverting the polarity of the buffer layer using the polarity inversion layer 303, the first buffer layer could be used as an etching stop layer. As a result, it has been possible to obtain a semiconductor element controlled with high accuracy.
[0114] 本実施形態 3によれば、埋め込み層 313を活性層の成長温度程度かそれ以下の 成長温度で、低屈折率半導体を用いて埋め込み再成長をすることができた。その結 果、活性層の品質を劣化させることなく埋め込み構造が得ることができた。  [0114] According to the third embodiment, the buried layer 313 can be buried and regrown using a low refractive index semiconductor at a growth temperature approximately equal to or lower than the growth temperature of the active layer. As a result, an embedded structure could be obtained without degrading the quality of the active layer.
また、本実施形態 3に係る埋め込み型の窒化物半導体レーザによれば、屈折率分 布と利得分布が一致した特徴により、低閾値、高出力時の安定横モード、放熱性の 向上により、高信頼性を得ることができた。また、長寿命化が実現できた。  Further, according to the buried nitride semiconductor laser according to the third embodiment, the characteristics of the refractive index distribution and the gain distribution coincide with each other, so that the low threshold, the stable transverse mode at high output, and the heat dissipation are improved. Reliability was obtained. In addition, a long life could be realized.
さらに、基板 301の転位密度が低いので、 N極性の活性層は平坦な界面を有し、そ の発光効率も Ga極性のものと同等レベルのものを得ることができた。  Furthermore, since the dislocation density of the substrate 301 was low, the N-polar active layer had a flat interface, and the light emission efficiency was equivalent to that of the Ga-polar one.
[0115] [実施形態 4] 次に、上記実施形態 1〜3とは異なる窒化物半導体レーザの実施形態について説 明する。 [0115] [Embodiment 4] Next, an embodiment of a nitride semiconductor laser different from those of Embodiments 1 to 3 will be described.
図 4は、本実施形態 4に係る窒化物半導体レーザの断面図である。  FIG. 4 is a cross-sectional view of the nitride semiconductor laser according to the fourth embodiment.
基板としては、層厚 110[ /ζ πι]の n— GaN (OOOl)基板 101を用いた。この n— Ga N (0001)基板 101上には、図 4に示すように、以下の層が積層されている。すなわ ち、バッファ層 102、第 1のクラッド層 103、第 1の SCH層 104、 3層からなる量子井戸 の活性層 105、 OFP層 106、第 2の SCH層 107、極性反転層 108、電流狭窄層 40 9、超格子クラッド層 410、コンタクト層 111が、この順に積層されている（以下、これら の層をまとめて積層体 450という）。なお、本実施形態における第 1の半導体層は第 2 の SCH層 107であり、第 2の半導体層は電流狭窄層 409である。  As the substrate, an n-GaN (OOOl) substrate 101 having a layer thickness of 110 [/ ζ πι] was used. On the n-Ga N (0001) substrate 101, the following layers are stacked as shown in FIG. In other words, buffer layer 102, first cladding layer 103, first SCH layer 104, three-layer quantum well active layer 105, OFP layer 106, second SCH layer 107, polarity inversion layer 108, current A constricting layer 409, a superlattice cladding layer 410, and a contact layer 111 are laminated in this order (hereinafter, these layers are collectively referred to as a laminated body 450). In this embodiment, the first semiconductor layer is the second SCH layer 107, and the second semiconductor layer is the current confinement layer 409.
[0116] 本実施形態 4に係る窒化物半導体レーザは、内部電流狭窄型のものである。電流 狭窄層 409は、層厚 80 [nm]の n— In Al N力も構成される。また、超格子クラ The nitride semiconductor laser according to Embodiment 4 is of an internal current confinement type. The current confinement layer 409 also has an n—In Al N force having a layer thickness of 80 [nm]. Also, superlattice class
0. 18 0. 82  0. 18 0. 82
ッド層 410は、層厚 0. 5 [ m]の p— Al Ga N (2. 5 [nm]) /p-GaN (2. 5 [  The lead layer 410 is composed of p-AlGaN (2.5 [nm]) / p-GaN (2.5 [m] with a layer thickness of 0.5 [m].
0. 14 0. 86  0. 14 0. 86
nm])を 100周期形成したものから構成される。ドーピング条件は、上記実施形態 1と 同じである。本実施形態 4においては、電流狭窄層 409のみが N極性 (結晶の面方 位が（000— 1)面）の結晶であり、他の積層体 450は、 Ga極性の結晶である。電流 狭窄層 409は、 p— Al Ga Nと格子整合しており、 2 X 1018[cm_3]の濃度で Si nm]). The doping conditions are the same as in the first embodiment. In the fourth embodiment, only the current confinement layer 409 is an N-polar crystal (the crystal plane direction is (000-1) plane), and the other stacked body 450 is a Ga-polar crystal. The current confinement layer 409 is lattice-matched with p-AlGaN and has a concentration of 2 X 10 18 [cm_ 3 ].
0. 07 0. 93  0. 07 0. 93
ドープされている。  Doped.
[0117] 次に、本実施形態 4の窒化物半導体レーザの製造方法について述べる。  [0117] Next, a method for manufacturing the nitride semiconductor laser of the fourth embodiment will be described.
電流狭窄層 409まで成長した後、電流狭窄層 409表面に SiOの絶縁膜で覆い、  After growing to the current confinement layer 409, the surface of the current confinement layer 409 is covered with a SiO insulating film,
2  2
バッファードフッ酸（BHF)でストライプ形状の開口幅 1 · 4 [； z m]の SiOストライプマ  Stripe-shaped SiO stripe mask with buffered hydrofluoric acid (BHF) with an opening width of 1 · 4 [; z m]
2  2
スクを形成した。そして、 150[°C]の燐酸硫酸（2 : 1)の混合溶液中に 10秒間浸漬し た。その後、ストライプ形状の開口部表面の下の N極性の電流狭窄層 409がウエット エッチングにより除去された。電流狭窄層 409のエッチングレートは 1. Ot ^ m/min ]であった。エッチング後の表面は平坦であり、第 2の SCH層 107の表面が露出した 。横方向のエッチングにより、電流狭窄層の開口幅は 1. 4 [ /z m]より大きくなつた。バ ッファードフッ酸 (BHF)で絶縁膜 (SiO )を除去し、開口幅 1. 7 [ m]の電流狭窄  A disc was formed. Then, it was immersed in a mixed solution of 150 [° C.] phosphoric acid sulfuric acid (2: 1) for 10 seconds. Thereafter, the N-polarity current confinement layer 409 under the surface of the stripe-shaped opening was removed by wet etching. The etching rate of the current confinement layer 409 was 1. Ot ^ m / min]. The surface after etching was flat, and the surface of the second SCH layer 107 was exposed. Due to the lateral etching, the opening width of the current confinement layer became larger than 1.4 [/ z m]. The insulating film (SiO 2) is removed with buffered hydrofluoric acid (BHF), and the current confinement is 1.7 [m]
2  2
層 409を得た。そして、この電流狭窄層 409をマスクにして、第 2の SCH層上に超格 子クラッド層 410を再成長させた。 Layer 409 was obtained. Then, using this current confinement layer 409 as a mask, the superconductivity is formed on the second SCH layer. The child cladding layer 410 was regrown.
[0118] 電流狭窄層 409を構成する n型 InAIN層に含まれる Siの濃度は、ドーピングレベル であり、 SiOマスクに含まれる Siの濃度より 5桁以上低い濃度である。そのため、高温 [0118] The concentration of Si contained in the n-type InAIN layer constituting the current confinement layer 409 is a doping level, which is 5 or more orders of magnitude lower than the concentration of Si contained in the SiO mask. Therefore, high temperature
2  2
で p—AlGaNクラッド層を成長させても、再成長界面の Si汚染の影響は小さぐ殆ど 動作電圧に影響しない。マスク厚が 100[nm]以下であれば埋め込み後の表面はほ ぼ平坦になる。  Even if the p-AlGaN cladding layer is grown, the influence of Si contamination at the regrowth interface is small, and the operating voltage is hardly affected. If the mask thickness is 100 [nm] or less, the surface after embedding becomes almost flat.
[0119] 本実施形態 4においては、電流狭窄層 409を埋め込んだ後の素子表面は平坦で あった。素子分離のときは、ストライプが見えにくいので、間隔 300 [ m]ピッチであ らカゝじめケガキ装置でストライプに平行にケガキ線を入れてチップを分離した。得られ た素子は P電極側を下にしてヒ トシンクに融着した。  In the fourth embodiment, the element surface after embedding the current confinement layer 409 was flat. When separating the elements, it is difficult to see the stripes, so if the pitch was 300 [m], the chip was separated by placing a marking line parallel to the stripes using a graduation marking device. The resulting device was fused to the heat sink with the P electrode side down.
[0120] このようにして製造された半導体レーザ 400は、共振器長 650 [ m]で、閾値電流 値 40 [mA]、良好なアスペクト比 1. 9を得ることができた。 40[mA]における動作電 圧は 4. 5 [V]であった。これは PdZPtの P電極 212力 ¾コンタクト層 411全面に形成 されて、コンタクト抵抗が低減した効果と、 p型超格子クラッド層（Ga極性) 410により ホ一ル障壁が低減した効果によるものと考えて 、る。  [0120] The semiconductor laser 400 manufactured in this way had a cavity length of 650 [m], a threshold current value of 40 [mA], and a good aspect ratio of 1.9. The operating voltage at 40 [mA] was 4.5 [V]. This is thought to be due to the PdZPt P electrode 212 force ¾ contact layer 411 formed over the entire surface, reducing the contact resistance, and the p-type superlattice cladding layer (Ga polarity) 410 reducing the hole barrier. And
本実施形態 4においては、活性層 105とヒートシンクとの間に SiOなどの熱伝導率  In Embodiment 4, the thermal conductivity of SiO or the like between the active layer 105 and the heat sink
2  2
が低い層がないので、素子の放熱特性が優れる。発振波長の温度変化力 見積もつ た 70 [mW]時の活性層の温度上昇は 15 [K]であり、これまでの 30 [K]の 1/2とな つた o  Since there is no low layer, the heat dissipation characteristics of the device are excellent. The temperature change power of the oscillation wavelength is estimated at 70 [mW], and the temperature rise of the active layer is 15 [K], which is half of the current 30 [K] o
[0121] 活性層の劣化の様子を、 150[°C]で 10[kAZcm2]の高い電流密度で通電し、 L Dを強制劣化させて観察した (力ソードルミネッセンス法)。 A1N電流狭窄層を用いた 場合は、劣化が早ぐ素子に A1Nに起因する水平方向の暗線や多数のクラックの発 生が見られた。一方、本実施形態 4の場合、全体的に暗くなる傾向は見られたものの 、電流狭窄層 409に起因する暗線や多数のクラックの発生は全く見られな力つた。 [0121] The deterioration of the active layer was observed by applying a high current density of 10 [kAZcm 2 ] at 150 [° C] and forcibly degrading the LD (forced sword luminescence method). In the case of using the A1N current confinement layer, horizontal dark lines and numerous cracks due to A1N were observed in the elements that deteriorated quickly. On the other hand, in the case of Embodiment 4, although there was a tendency to darken as a whole, the generation of dark lines and a large number of cracks due to the current confinement layer 409 was not observed at all.
[0122] 本実施形態 4によれば、極性反転層 108を設けることにより、第 2の SCH層 107と 電流狭窄層 409との極性を、この極性反転層を介して反転させることができる。具体 的には、 Ga極性の第 2の SCH層 107上に Mg単原子層たる極性反転層 108を介す ることにより、 N極性の電流狭窄層 409を積層せしめることができる。電流狭窄層 409 は、 N極性なのでウエットエッチングにより良好にエッチングされる。一方、第 2の SC H層 107は、 Ga極性なのでウエットエッチングによりエッチングされない。従って、極 性反転層 108を用いて SCH層の極性を反転させることにより、第 2の SCH層 107を エッチング停止層とすることができた。 According to the fourth embodiment, by providing the polarity inversion layer 108, the polarity of the second SCH layer 107 and the current confinement layer 409 can be inverted via this polarity inversion layer. Specifically, the N-polarity current confinement layer 409 can be stacked on the Ga-polar second SCH layer 107 via the polarity inversion layer 108 as an Mg monoatomic layer. Current confinement layer 409 Since N polarity, it is etched well by wet etching. On the other hand, the second SCH layer 107 is not etched by wet etching because it has Ga polarity. Therefore, by inverting the polarity of the SCH layer using the polarity inversion layer 108, the second SCH layer 107 could be used as an etching stop layer.
[0123] 従来、 n型 InAIN層（電流狭窄層）をドライエッチングで除去すると、少なくとも結晶 欠陥が p— GaN力もなる第 2の SCH層 107に導入されるので、その後の再成長によ り p— GaN力 なる第 2の SCH層の Mgド—パントが欠陥と共に活性層に拡散し、非 発光センタを導入してしまう。その結果、活性層の発光効率が著しく減少してしまう。  [0123] Conventionally, when the n-type InAIN layer (current confinement layer) is removed by dry etching, at least crystal defects are introduced into the second SCH layer 107 with p-GaN force. — The Mg dopant in the second SCH layer, which is the GaN force, diffuses into the active layer along with the defects, and introduces a non-luminescent center. As a result, the luminous efficiency of the active layer is significantly reduced.
[0124] 本実施形態 4によれば、電流狭窄層 409をウエットエッチングで除去したため、その 下の活性層には結晶欠陥などの加工損傷は生じない。従って再成長後も活性層の 高い発光効率が維持される。本実施形態によれば、電流狭窄層 409として、 InAIN 組成を採用し、 In組成比を 0. 2程度としたので、低い屈折率を実現することができる 。その結果、レーザ光を活性層により効果的に閉じ込められる。 InAIN層は n型なの で電流ブロック効果が高い。なお、アンドープ InAIN層は高抵抗となるので、それを 用いてもよい。  According to the fourth embodiment, since the current confinement layer 409 is removed by wet etching, processing damage such as crystal defects does not occur in the active layer therebelow. Therefore, the high luminous efficiency of the active layer is maintained even after regrowth. According to the present embodiment, since the InAIN composition is adopted as the current confinement layer 409 and the In composition ratio is about 0.2, a low refractive index can be realized. As a result, the laser light can be effectively confined by the active layer. The current blocking effect is high because the InAIN layer is n-type. Note that the undoped InAIN layer has a high resistance and may be used.
[0125] 本実施形態 4によれば、第 2の SCH層 107がエッチング停止層の役目を果たして いるので、ウエットエッチングによる活性層への損傷がな力つた。また、電流狭窄層 4 09をパターユングするに際して高精度にパターユングを行うことができた。その結果 、設計どおりの構造を得ることができた。  According to the fourth embodiment, since the second SCH layer 107 serves as an etching stop layer, the active layer was not damaged by wet etching. In addition, the patterning of the current confinement layer 409 was performed with high accuracy. As a result, the structure as designed was obtained.
[0126] また、本実施形態 4によれば、電流狭窄層 409として構成されて ヽる n型 InAIN層 は、従来例の A1N層のような非結晶ではなぐ結晶であり、クラッド層に対して格子不 整合が殆どない特徴を有する。そのため、非結晶に起因するすべての問題が解決す る。本実施形態 4の n型 InAIN層は、平坦であるため電流リークがない。ブロック層に 起因する転位がないので、それによつて寿命が制限されない。開口部のストライプ幅 の制御もしゃすぐストライプが直線であるため、散乱による導波損失が極めて少ない 。高品質の n型 InAIN層を選択成長のマスクに用いると、開口部の p型超格子クラッ ド層が設計通りに得られるため、低い動作電圧を安定して得ることができる。図 13に Al Ga In N系混晶におけるバンドギャップと a軸長の関係を示す。 [0127] 本実施形態 4では電流狭窄層に GaNに格子整合する n— In Al N電流狭窄 [0126] According to the fourth embodiment, the n-type InAIN layer configured as the current confinement layer 409 is not a crystal like the conventional A1N layer, and is not a crystal. It has the characteristic that there is almost no lattice mismatch. Therefore, all problems caused by non-crystals are solved. Since the n-type InAIN layer of Embodiment 4 is flat, there is no current leakage. Since there are no dislocations due to the block layer, it does not limit the lifetime. The control of the stripe width of the opening also makes the waveguide loss very small due to scattering because the straight stripe is straight. When a high-quality n-type InAIN layer is used as a selective growth mask, a p-type superlattice cladding layer in the opening can be obtained as designed, and a low operating voltage can be stably obtained. Figure 13 shows the relationship between the band gap and the a-axis length in Al Ga In N mixed crystals. In Embodiment 4, n—In Al N current confinement that lattice matches with GaN in the current confinement layer
0. 18 0. 82  0. 18 0. 82
層 409を用いた力 それ以外の組成あるいは材料を適用してもよい。好適な例として は、例えば、電流狭窄層が In Ga Al N (ただし、 0≤X≤1、 0≤Y≤1、 0≤X+  Forces using layer 409 Other compositions or materials may be applied. As a suitable example, for example, the current confinement layer is In Ga Al N (where 0≤X≤1, 0≤Y≤1, 0≤X +
X 1 -X-y  X 1 -X-y
Y≤ 1)を挙げることができる。また、電流狭窄層 409が In Al Nであり、その In組  Y≤ 1). In addition, the current confinement layer 409 is InAlN, and the In group
X 1 -X  X 1 -X
成 Xの値が 0. 05≤X≤0. 3としてもよい。 Xの範囲のより好ましい範囲は、 0. 1≤X ≤0. 25であり、さらに好ましい範囲は 0. 15≤X≤0. 2である。また、電流狭窄層 40 9が（In Al ) Ga Nの格子整合層であり、その Ga組成 Zの値が 0. 2≤Z≤ 1 The value of the composition X may be 0.05.X≤X≤0.3. A more preferable range of the range of X is 0.1 ≤ X ≤ 0.25, and a more preferable range is 0.15 ≤ X ≤ 0.2. In addition, the current confinement layer 40 9 is a lattice matching layer of (In Al) Ga N and the value of its Ga composition Z is 0.2≤Z≤ 1
0. 18 0. 82 Z 1 -Z 0. 18 0. 82 Z 1 -Z
としてちよい。  As good as.
[0128] 本実施形態 4によれば、上述した効果にカ卩えて、以下の効果を奏することができた 第 1に、 200 [mW]の高いキンクレベルと 1. 9の低いアスペクト比を実現することが できた。  [0128] According to the fourth embodiment, in addition to the above-mentioned effects, the following effects could be achieved. First, a high kink level of 200 [mW] and a low aspect ratio of 1.9 were realized. We were able to.
第 2に、 pコンタクト面積の増大により、 25 [で]、 30 [mW]動作時の電圧を 4. 5 [V] に低減させることができた。  Second, by increasing the p-contact area, we were able to reduce the operating voltage to 25 [V] and 30 [mW] to 4.5 [V].
第 3に、閾値の低減と放熱の向上により、 70 [°C] , 70 [mW]で 2500時間以上の直 流電流動作を実現し、信頼性を大きく向上させることができた。  Third, by reducing the threshold and improving heat dissipation, DC current operation for more than 2500 hours was achieved at 70 [° C] and 70 [mW], greatly improving reliability.
[0129] [実施形態 5] [Embodiment 5]
図 5は、実施形態 5に係る窒化物半導体レ—ザの断面図である。基板としては、層 厚 l lO^ m]の n— GaN (0001)基板 101を用いた。この n— GaN (0001)基板 10 1上には、図 5に示すように、以下の層が積層されている。すなわち、ノ ッファ層 102 、第 1のクラッド層 103、第 1の SCH層 104、 3層力もなる量子井戸の活性層 105、 O FP層 106、第 2の SCH層 507、極性反転層 508、電流狭窄層 409、第 2の格子クラ ッド層 510、コンタクト層 111が、この順に積層されている。なお、本実施形態 5にお ける第 1の半導体層は第 2の SCH層 507であり、第 2の半導体層は電流狭窄層 409 である。  FIG. 5 is a cross-sectional view of the nitride semiconductor laser according to the fifth embodiment. As the substrate, an n-GaN (0001) substrate 101 having a layer thickness of l lO ^ m] was used. On the n-GaN (0001) substrate 101, the following layers are stacked as shown in FIG. That is, the nofer layer 102, the first cladding layer 103, the first SCH layer 104, the quantum well active layer 105 that also has a three-layer force, the OFP layer 106, the second SCH layer 507, the polarity inversion layer 508, the current A constriction layer 409, a second lattice cladding layer 510, and a contact layer 111 are laminated in this order. In the fifth embodiment, the first semiconductor layer is the second SCH layer 507, and the second semiconductor layer is the current confinement layer 409.
[0130] 本実施形態 5に係る窒化物半導体レーザは、内部電流狭窄型のものである。第 2の SCH層は、層厚 50[nm]の p— GaNにより構成される。また、極性反転層 508は、 0 . 1 [%]の Mgを含んだ Gaの 2原子層により構成される。第 3の SCH層 509は、層厚 50 [nm]の p— GaNにより、電流狭窄層（N極性） 409は、層厚 80[nm]の n— In [0130] The nitride semiconductor laser according to Embodiment 5 is of the internal current confinement type. The second SCH layer is composed of p-GaN having a layer thickness of 50 [nm]. Further, the polarity inversion layer 508 is composed of a Ga atomic layer containing 0.1 [%] Mg. The third SCH layer 509 has a layer thickness P-GaN of 50 [nm] makes the current confinement layer (N polarity) 409 n-In with a layer thickness of 80 [nm]
0. 18 0. 18
Al Nにより、第 2のクラッド層 510は、層厚 0. 5 [ /ζ πι]の p— Al Ga NによりWith Al N, the second cladding layer 510 is made of p—Al Ga N with a layer thickness of 0.5 [/ ζ πι].
0. 82 0. 07 0. 93 構成される。 0. 82 0. 07 0. 93 Consists of.
[0131] 本実施形態 5の電流狭窄層 409は、第 3の SCH層 509よりエッチングレ―トが 1桁 大きいので、電流狭窄層 409だけを選択的にエッチングできる。また、仮に第 3の SC H層 509がエッチングされた場合であっても、再成長時に第 3の SCH層 509をエッチ ングされた厚みだけ成長させれば、元の厚さに回復させることができる。  [0131] Since the current confinement layer 409 of Embodiment 5 has an etching rate that is an order of magnitude higher than that of the third SCH layer 509, only the current confinement layer 409 can be selectively etched. Even if the third SCH layer 509 is etched, if the third SCH layer 509 is grown by the etched thickness during regrowth, the original thickness can be recovered. it can.
[0132] 極性反転層 508は、 0. 1 [%]の Mgを含んだ Gaの 2層力もなる原子層により構成さ れる。積層体 550は、上記変形例 1に記載した製造方法により製造した。すなわち活 性層を含む Ga極性結晶を MOVPE法で、極性反転層とその後の N極性の結晶成長 を MBE法により形成した。  [0132] The polarity inversion layer 508 is composed of an atomic layer having a double layer force of Ga containing 0.1 [%] Mg. Laminate 550 was manufactured by the manufacturing method described in Modification 1 above. In other words, the Ga polar crystal including the active layer was formed by the MOVPE method, and the polarity inversion layer and the subsequent N-polar crystal growth were formed by the MBE method.
MBE法を用いることにより、面内の In糸且成の揺らぎが小さい n— In Al N電流  By using the MBE method, in-plane In yarn and fluctuations are small n—In Al N current
0. 18 0. 82 狭窄層（N極性) 409が得られる。結晶中に In組成の大きい部分があると光を吸収す る損失になり、レーザの閾値が増加する。しかし、本実施形態 5の製造方法では、青 色光の吸収損失のない n— In Al N電流狭窄層（N極性) 409が得られる。  0.18 0. 82 A constriction layer (N polarity) 409 is obtained. If there is a part with a large In composition in the crystal, it will result in a loss of light absorption and the laser threshold will increase. However, in the manufacturing method of the fifth embodiment, an n-In Al N current confinement layer (N polarity) 409 having no blue light absorption loss can be obtained.
0. 18 0. 82  0. 18 0. 82
[0133] 本実施形態 5によれば、極性反転層 508を設けることにより、 SCH層の極性を、こ の極性反転層を介して反転できる。具体的には、 Ga極性の第 2の SCH層 507上に 極性反転層 508を介することにより、 N極性の第 3の SCH層 509を積層せしめること ができる。第 3の SCH層 509は、 N極性なのでウエットエッチングにより良好にエッチ ングされる。一方、第 2の SCH層 507は、 Ga極性なのでウエットエッチングによりエツ チングされない。従って、極性反転層 508を用いて SCH層の極性を反転させること により、第 2の SCH層 507をエッチング停止層とすることができた。  [0133] According to the fifth embodiment, by providing the polarity inversion layer 508, the polarity of the SCH layer can be inverted through this polarity inversion layer. Specifically, the N-polarity third SCH layer 509 can be stacked on the Ga-polarity second SCH layer 507 via the polarity inversion layer 508. Since the third SCH layer 509 is N-polar, it is etched well by wet etching. On the other hand, since the second SCH layer 507 is Ga-polar, it is not etched by wet etching. Therefore, by inverting the polarity of the SCH layer using the polarity inversion layer 508, the second SCH layer 507 could be used as an etching stop layer.
[0134] また、第 2の SCH層 507がエッチング停止層の役目を果たしているので、ウエットェ ツチングによる活性層への損傷がなカゝつた。また、電流狭窄層 409を形成するに際し て、高精度にパターユング形成することができた。その結果、設計どおりの構造を得 ることがでさた。  [0134] Further, since the second SCH layer 507 served as an etching stop layer, the active layer was not damaged by wet etching. In addition, when forming the current confinement layer 409, it was possible to form a pattern with high accuracy. As a result, it was possible to obtain the structure as designed.
[0135] さらに、第 3の SCH層 509と第 2のクラッド層 510とが接しているために、ホ一ルの 注入障壁がな 、特徴と、 N極性の p— GaNコンタクト層 111上に PdZPtの P電極 21 2を形成するために、 pコンタクト電圧が小さ ヽと 、う特徴とを有する。 [0135] Further, since the third SCH layer 509 and the second cladding layer 510 are in contact with each other, there is no hole injection barrier, and there is a feature of PdZPt on the N-polar p-GaN contact layer 111. P electrode 21 In order to form 2, the p-contact voltage has small characteristics and characteristics.
[0136] [実施形態 6]  [Embodiment 6]
図 6は、実施形態 6に係る窒化物半導体発光素子 (LED)の断面図である。基板と しては、厚さ 110 [ /z m]の n型 GaN (0001)基板 101を用いた。この n型 GaN (0001 )基板 101上には、図 6に示すように、以下の層が積層されている。すなわち、ノッフ ァ層 102、第 1のクラッド層 103、第 1の SCH層 104、単一量子井戸の活性層 605、 OFP層 606、第 2の SCH層 607、第 1のコンタクト層 608、極性反転層 609、第 3の S CH層 610、第 2のコンタクト層 611がこの順に積層されている（以下、これらの層をま とめて積層体 650という）。なお、本実施形態 6における第 1の半導体層は第 1のコン タクト層 608であり、第 2の半導体層は第 3の SCH層 610である。  FIG. 6 is a cross-sectional view of the nitride semiconductor light emitting device (LED) according to the sixth embodiment. As the substrate, an n-type GaN (0001) substrate 101 having a thickness of 110 [/ z m] was used. On the n-type GaN (0001) substrate 101, the following layers are stacked as shown in FIG. That is, the nofer layer 102, the first cladding layer 103, the first SCH layer 104, the single quantum well active layer 605, the OFP layer 606, the second SCH layer 607, the first contact layer 608, the polarity inversion A layer 609, a third SCH layer 610, and a second contact layer 611 are stacked in this order (hereinafter, these layers are collectively referred to as a stacked body 650). In the sixth embodiment, the first semiconductor layer is the first contact layer 608, and the second semiconductor layer is the third SCH layer 610.
[0137] 本実施形態 6に係る単一量子井戸の活性層 605は、 In Ga ON (2. 5 [nm])  [0137] The active layer 605 of the single quantum well according to the sixth embodiment is composed of In Ga ON (2.5 [nm]).
0. 20 0. 8  0. 20 0. 8
Zn— GaN (10[nm])により構成される。また、 OFP層 606は、 10[nm]厚の p— A1 o Zn—composed of GaN (10 [nm]). The OFP layer 606 is a 10 nm thick p-A1 o
Ga Nにより、第 2の SCH層 607は、層厚 50[nm]の p— GaNにより構成されるDue to GaN, the second SCH layer 607 is composed of p-GaN with a layer thickness of 50 [nm].
. 12 0. 88 . 12 0. 88
。また、第 1のコンタクト層 608は、層厚 20[nm]の p— GaNにより構成される。上記 n — GaN (0001)基板 101から第 1のコンタクト層 608までの極性は、上述した Ga極性 619となるように構成されて！ヽる。  . The first contact layer 608 is made of p-GaN having a layer thickness of 20 [nm]. The polarity from the n — GaN (0001) substrate 101 to the first contact layer 608 is configured to be the Ga polarity 619 described above! Speak.
[0138] 極性反転層 609は、 Mg単原子層により構成されている。また、第 3の SCH層 610 は層厚 230[nm]の p— GaNにより、第 2のコンタクト層 611は、層厚 20[nm]の p— G aNにより構成されている。第 3の SCH層 610、及び第 2のコンタクト層 611の極性は 、 N極性となるように構成されている。  [0138] The polarity inversion layer 609 is composed of an Mg monoatomic layer. The third SCH layer 610 is composed of p-GaN having a layer thickness of 230 [nm], and the second contact layer 611 is composed of p-GaN having a layer thickness of 20 [nm]. The polarities of the third SCH layer 610 and the second contact layer 611 are configured to be N polarities.
[0139] 上記極性反転層 609及び第 3の SCH層 610と第 2のコンタクト層 611との上には、 図 6に示すように、層厚 70 [nm]の透明電極 612が形成されている。また、この透明 電極 612上の図中左側には、 p電極 613が形成されている。透明電極 612は、 Ni(l 0 [nm] ) /Au ( 10 [nm] )の上に 50 [nm]厚の ITO (屈折率 1. 5)をつけた膜である 。 ρ電極 613には、 TiZPtZAuを用いた。 N電極 114には、反射率の高い TiZAu を用いた。 pド一パントには Mg (マグネシウム）を用いた。  A transparent electrode 612 having a layer thickness of 70 [nm] is formed on the polarity inversion layer 609, the third SCH layer 610, and the second contact layer 611 as shown in FIG. . A p-electrode 613 is formed on the left side of the transparent electrode 612 in the figure. The transparent electrode 612 is a film in which ITO (refractive index 1.5) having a thickness of 50 [nm] is formed on Ni (l 0 [nm]) / Au (10 [nm]). TiZPtZAu was used for the rho electrode 613. For the N electrode 114, TiZAu having high reflectivity was used. Mg (magnesium) was used for the p-type punch.
[0140] nドーパントには Siを用いた。 Mgの原子濃度は第 1のコンタクト層 608と第 2のコン タクト層 611には l X 102G[cm_3]、それ以外には 2 X 1019[cm_3]、 Siの原子濃度は すべて 2 X 1018[cm"d]とした。 [0140] Si was used as the n dopant. The atomic concentration of Mg is l X 10 2G [cm _3 ] for the first contact layer 608 and the second contact layer 611, and 2 X 10 19 [cm _3 ] for the other, and the atomic concentration of Si is All were set to 2 X 10 18 [cm " d ].
[0141] 本実施形態 6に係る半導体素子の上部に形成されたフォトニック結晶 614は、円柱 状に加工された第 3の SCH層 610と第 2のコンタクト層 611が、周期 b617として 1. 6 [ m]の間隔で三角格子位置に 2次元に配列されている。第 3の SCH層 610と第 2 のコンタクト層 611からなる円柱の高さ h615は、 250[nm]であり、円柱の上面の直 径 a618は、 800[nm]である。フォトニック結晶 614は、 N極'性となっている。  [0141] The photonic crystal 614 formed on the top of the semiconductor element according to the sixth embodiment has a third SCH layer 610 and a second contact layer 611 that are processed into a cylindrical shape with a period b617 of 1.6. They are arranged two-dimensionally at triangular lattice positions at intervals of [m]. The height h615 of the cylinder composed of the third SCH layer 610 and the second contact layer 611 is 250 [nm], and the diameter a618 of the upper surface of the cylinder is 800 [nm]. The photonic crystal 614 is N-pole '.
図 7は、本実施形態 6に係るフォトニック結晶付き半導体素子の上面図である。円柱 状のフォト ック結晶が、同図に示すように、 3角格子状配置 650で配置されている。  FIG. 7 is a top view of the semiconductor element with a photonic crystal according to the sixth embodiment. Cylindrical photonic crystals are arranged in a triangular lattice arrangement 650 as shown in the figure.
[0142] 図 11は、本実施形態 6に係る窒化物半導体発光素子の作用を説明する図である。  FIG. 11 is a diagram for explaining the operation of the nitride semiconductor light emitting device according to the sixth embodiment.
本実施形態 6の窒化物半導体発光素子は、 pコンタクト層の上に円柱を三角格子状 に配列させた 2次元のフォトニック結晶を有している。このフォトニック結晶 614が無い 場合は、活性層 1200から出た光は臨界角 23. 6 [° ]のエスケ一プ円錐内 1205に 入る光だけを上面から取り出すことができる。臨界角 1206は、 GaNの屈折率 2. 5と 空気の屈折率 1との比で決まる。この場合の取り出し効率は、 8. 3 [%]と極めて小さ い。  The nitride semiconductor light emitting device of Embodiment 6 has a two-dimensional photonic crystal in which cylinders are arranged in a triangular lattice pattern on a p-contact layer. In the absence of the photonic crystal 614, the light emitted from the active layer 1200 can be extracted from the top surface only from the upper surface of the escape cone 1205 having a critical angle of 23.6 [°]. The critical angle 1206 is determined by the ratio of the refractive index 2.5 of GaN and the refractive index 1 of air. In this case, the extraction efficiency is as low as 8.3 [%].
[0143] 本実施形態 6のようにフォトニック結晶 614がある場合、 2次元回折格子の作用によ り、活性層からの光の波数ベクトル kl 201とフォトニック結晶 614による回折ベクトル d 1202の和力 素子から取り出せる回折光の波数ベクトル hl203 (h=k+d)となる。 回折光の波数ベクトル hl203が平板の時の臨界角 23. 6 [° ]になるように回折べク トノレ dl202 ( = 2 π /h)を与えるフォトニック結晶の周期 bを決めた。  When the photonic crystal 614 is present as in Embodiment 6, the sum of the wave vector kl 201 of light from the active layer and the diffraction vector d 1202 by the photonic crystal 614 due to the action of the two-dimensional diffraction grating. The wave vector of diffracted light that can be extracted from the force element is hl203 (h = k + d). The period b of the photonic crystal that gives the diffraction vector dl202 (= 2 π / h) was determined so that the wave vector hl203 of the diffracted light would be the critical angle 23.6 [°] when flat.
[0144] 本実施形態 6では、円柱の直径 aを 0. 80[ /ζ ηι]、周期 bを 1. 6 [ /z m]に最適化し て、臨界角 42[° ]、効率 25 [%]の値を得た。この効率は 8. 3 [%]の 3倍に相当す る。本実施形態 6の LEDは、従来の LEDの 3倍の効率増加となり、蛍光灯の発光効 率と同程度かそれ以上となる。本実施形態 6の LEDはウエットエッチングで作成する ので、低コストで作成できる。寿命と費用を考えると本実施形態 6の LEDは十分蛍光 灯を代替することができる。  [0144] In the sixth embodiment, the diameter a of the cylinder is optimized to 0.80 [/ ζ ηι] and the period b is optimized to 1.6 [/ zm], and the critical angle is 42 [°] and the efficiency is 25 [%]. Was obtained. This efficiency is equivalent to three times 8.3 [%]. The LED of Embodiment 6 has a three-fold increase in efficiency compared to the conventional LED, which is about the same as or better than the luminous efficiency of fluorescent lamps. Since the LED of Embodiment 6 is manufactured by wet etching, it can be manufactured at low cost. Considering the lifetime and cost, the LED of Embodiment 6 can sufficiently replace the fluorescent lamp.
[0145] 上記のように構成された半導体素子の発光波長ピ―クは、 405 [nm]であった。本 実施形態 6の特徴は、活性層 705から第 1のコンタクト層 608の表面までの距離 dが 9 0[nm]と小さいことである。このときの円柱状のフォトニック結晶の最適周期 bは 1. 6 [ μ m]であり、このとき本実施形態 6に係る半導体素子の光の取り出し効率は最大とな つた。本実施形態 6の半導体素子の光の取り出し効率は、活性層から表面までの距 離が 1 [； z m]ある半導体素子より、約 2倍大き力 た。 [0145] The emission wavelength peak of the semiconductor device configured as described above was 405 [nm]. The feature of Embodiment 6 is that the distance d from the active layer 705 to the surface of the first contact layer 608 is 9 It is as small as 0 [nm]. The optimum period b of the columnar photonic crystal at this time is 1.6 [μm], and at this time, the light extraction efficiency of the semiconductor device according to the sixth embodiment has been maximized. The light extraction efficiency of the semiconductor device of Embodiment 6 was about twice as large as that of the semiconductor device having a distance of 1 [; zm] from the active layer to the surface.
活性層から表面までの距離を 0. 2 [； z m]以下にできるのは、本実施形態 6の製造 方法が加工損傷の少な!/、ウエットエッチングを使用して 、るからである。本実施形態 6の製造方法が完全なエッチング停止層を有するために、層厚 20 [nm]の高 Mg濃 度の pコンタクト層を残して、その上に p電極を作製できる。  The reason why the distance from the active layer to the surface can be 0.2 [; z m] or less is that the manufacturing method of Embodiment 6 uses less etching damage and / or wet etching. Since the manufacturing method of Embodiment 6 has a complete etching stop layer, a p-electrode can be formed on the p-contact layer having a layer thickness of 20 [nm] and a high Mg concentration.
[0146] 本実施形態 6の半導体素子の発光波長ピークは InGaN活性層の In組成を増加さ せ、量子井戸幅を 3 [nm]に大きくすることで 490 [nm]まで、発光効率の顕著な低下 なしに、変化させることができた。本実施形態 6においては、緑青色の発光である 48 0 [nm]帯の LEDも得ることができた。  [0146] The emission wavelength peak of the semiconductor device of this Embodiment 6 shows remarkable emission efficiency up to 490 [nm] by increasing the In composition of the InGaN active layer and increasing the quantum well width to 3 [nm]. It was possible to change without degradation. In the sixth embodiment, a 48 0 [nm] band LED that emits greenish blue light was also obtained.
[0147] [実施形態 7]  [Embodiment 7]
図 8は、実施形態 7に係る窒化物半導体発光素子 (LED)の断面図である。基板と しては、厚さ 110 [ /z m]の n型 GaN (0001)基板 101を用いた。この n型 GaN (0001 )基板 101上には、図 8に示すように、以下の層が積層されている。  FIG. 8 is a cross-sectional view of the nitride semiconductor light emitting device (LED) according to the seventh embodiment. As the substrate, an n-type GaN (0001) substrate 101 having a thickness of 110 [/ z m] was used. On the n-type GaN (0001) substrate 101, the following layers are laminated as shown in FIG.
すなわち、ノ ッファ層 102、第 1の超格子光反射層 703、第 1の SCH層 704、単一量 子井戸の活性層 705、 OFP層 706、第 2の SCH層 707、第 1のコンタクト層 708、極 性反転層 709、第 3の SCH層 710、第 2のコンタクト層 711がこの順に積層されてい る（以下、これらの層をまとめて積層体 750という）。なお、本実施形態 7においては、 第 1の半導体層は第 1のコンタクト層 708であり、第 2の半導体層として第 3の SCH層 710である。  That is, the nofer layer 102, the first superlattice light reflecting layer 703, the first SCH layer 704, the single quantum well active layer 705, the OFP layer 706, the second SCH layer 707, and the first contact layer 708, a polarity inversion layer 709, a third SCH layer 710, and a second contact layer 711 are laminated in this order (hereinafter, these layers are collectively referred to as a laminate 750). In the seventh embodiment, the first semiconductor layer is the first contact layer 708, and the second semiconductor layer is the third SCH layer 710.
[0148] 本実施形態 7に係る超格子光反射層 703は、層厚 830[nm]の n— [GaN (32. 2[ nm])Al Ga N (37 [nm]) ] (12周期）から構成されている。また、第 1の SCH [0148] The superlattice light reflecting layer 703 according to Embodiment 7 includes n- [GaN (32.2 [nm]) AlGaN (37 [nm])] (12 periods) having a layer thickness of 830 [nm]. It is composed of The first SCH
0. 38 0. 62 0. 38 0. 62
層は、層厚 100[nm]の n— Al Ga Nからなり、単一量子井戸の活性層 705は  The layer consists of n-AlGaN with a layer thickness of 100 [nm], and the active layer 705 of a single quantum well is
0. 13 0. 87  0. 13 0. 87
、 GaN (2. 5 [nm]) ZAl Ga N ( 10 [nm])力ら構成されている。さらに、 OFP  GaN (2.5 [nm]) ZAlGaN (10 [nm]) force. In addition, OFP
0. 13 0. 87  0. 13 0. 87
そう 706は、 10[nm]厚の p— Al Ga N、第 2の SCH層は、層厚 50 [nm]の p—  So 706 is p-AlGaN with a thickness of 10 [nm], and the second SCH layer is p- with a thickness of 50 [nm].
0. 18 0. 82  0. 18 0. 82
Al Ga N力も構成されている。さらに、その上に第 1のコンタクト層が、層厚 20[ nm]の p— Al Ga Nにより形成されている。上記 n—GaN (0001)基板 101かAl Ga N force is also constructed. Furthermore, a first contact layer is formed on the layer with a thickness of 20 [ nm] p—AlGaN. N-GaN (0001) substrate 101
0. 13 0. 87 0. 13 0. 87
ら第 1のコンタクト層 708までの極性は、上述した Ga極性 619となるように構成されて いる。  The first contact layer 708 is configured to have the above-mentioned Ga polarity 619.
[0149] 極性反転層 709は、 Mg単原子層により構成されている。また、第 3の SCH層 710 は、層厚 230[nm]の p— Al Ga N層により、第 2のコンタクト層 711は、層厚 20  [0149] The polarity inversion layer 709 is composed of an Mg monoatomic layer. The third SCH layer 710 is a p-AlGaN layer with a layer thickness of 230 [nm], and the second contact layer 711 has a layer thickness of 20
0. 13 0. 87  0. 13 0. 87
[nm]の p—Al Ga Nにより構成されている。第 3の SCH層 710、及び第 2のコ  [nm] p-AlGaN. The third SCH layer 710 and the second
0. 13 0. 87  0. 13 0. 87
ンタクト層 711の極性は、 N極性となるように構成されて！、る。  The contact layer 711 has a polarity of N polarity! RU
[0150] 上記極性反転層 709及び第 3の SCH層 710と第 2のコンタクト層 711との上には、 図 8に示すように、層厚 70 [nm]の透明電極 612が形成されている。また、この透明 電極 612上の図中左側には、 p電極 613が形成されて!、る。 A transparent electrode 612 having a layer thickness of 70 [nm] is formed on the polarity inversion layer 709, the third SCH layer 710, and the second contact layer 711 as shown in FIG. . A p-electrode 613 is formed on the left side of the transparent electrode 612 in the drawing.
[0151] 本実施形態 7に係る半導体素子の上部に形成されたフォトニック結晶 714は、円柱 状に加工された第 3の SCH層 610と第 2のコンタクト層 611が、周期 b617として 1. 6 [ m]の間隔で三角格子位置に 2次元に配列されている。第 3の SCH層 710と第 2 のコンタクト層 711からなる円柱の高さ h615は、 250[nm]であり、円柱の上面の直 径 a618は、 800[nm]である。フォトニック結晶 614は、 N極'性となっている。 [0151] In the photonic crystal 714 formed on the top of the semiconductor device according to the seventh embodiment, the third SCH layer 610 and the second contact layer 611 processed into a cylindrical shape have a period b617 of 1.6. They are arranged two-dimensionally at triangular lattice positions at intervals of [m]. The height h615 of the cylinder composed of the third SCH layer 710 and the second contact layer 711 is 250 [nm], and the diameter a618 of the upper surface of the cylinder is 800 [nm]. The photonic crystal 614 is N-pole '.
[0152] 円柱状のフォトニック結晶は、図 7に示すように、 3角格子状配置 650で配置されて いる。表 1に、本実施形態 7に係る紫外光 LEDの n型超格子光反射層の材料と設計 層厚を示す。 n型超格子光反射層 703は 32. 2[11111]厚の0&?^と37[11111]厚の八1 [0152] The columnar photonic crystals are arranged in a triangular lattice arrangement 650 as shown in FIG. Table 1 shows the material and design layer thickness of the n-type superlattice light reflecting layer of the ultraviolet LED according to Embodiment 7. n-type superlattice light reflection layer 703 is 32.2 [11111] thick 0 &? ^ and 37 [11111] thick 8
0. 3 0. 3
Ga Nが 12周期積層された超格子層である。 It is a superlattice layer in which GaN is laminated 12 periods.
8 0. 62  8 0. 62
波長は 348 [nm]での GaNと Al Ga Nの屈折率はそれぞれ 2. 70、 2. 35で  At 348 [nm], the refractive indices of GaN and AlGaN are 2.70 and 2.35, respectively.
0. 38 0. 62  0. 38 0. 62
ある。それらの結晶内での 1Z4波長は、それぞれ 32. 2[nm]、 37. 0[nm]である。 12周期の超格子で最大反射率は 95 [%]に達し、 90 [%]以上の反射率を与える幅 は 40 [nm]であった。  is there. The 1Z4 wavelength in these crystals is 32.2 [nm] and 37.0 [nm], respectively. The maximum reflectivity reached 95 [%] with a 12-period superlattice, and the width giving a reflectivity of 90 [%] or more was 40 [nm].
[表 1] a軸格子定数 ハ'ンドキ 'ャッフ。 屈折率 層厚（隱） 材料 a (nm) Eg(eV) n (348nm) 348 (nm)/4n[table 1] a-axis lattice constant. Refractive index Layer thickness (隱) Material a (nm) Eg (eV) n (348nm) 348 (nm) / 4n
AIN 0.3112 6.20 2.40 36.3 AIN 0.3112 6.20 2.40 36.3
Alo.38Gao.62N 0.3160 4.46 2.35 37.0 Alo.38Gao.62N 0.3160 4.46 2.35 37.0
GaN 0.3189 3.39 2.70 32.2  GaN 0.3189 3.39 2.70 32.2
[0153] GaNに対する Al Ga Nの格子不整合は 0· 91[%]であり、 0.44 [； zm]厚の [0153] The lattice mismatch of Al Ga N with respect to GaN is 0 · 91 [%], 0.44 [; zm] thick
0.38 0.62  0.38 0.62
Al Ga Nの歪量は 2· 2 [； zm]の Al Ga Nクラッド層の歪量に相当する。  The strain of Al Ga N is equivalent to the strain of the Al Ga N cladding layer of 2.2 [zm].
0.38 0.62 0.07 0.93  0.38 0.62 0.07 0.93
12周期を超える周期数の超格子では結晶性の低下が懸念される。 n型超格子光反 射層を 1Z4波長厚の InGaNと AlGaNで構成すると、結晶全体の歪量を減らしかつ 同じ層数でより高い反射率が得られる。  With a superlattice having a period number exceeding 12 periods, there is a concern that the crystallinity is lowered. When the n-type superlattice light reflecting layer is composed of InGaN and AlGaN with a 1Z4 wavelength thickness, the amount of strain in the entire crystal can be reduced and higher reflectivity can be obtained with the same number of layers.
[0154] 図 12は、本実施形態 7に係る紫外光 LEDの発光スペクトルを示す。 25[°C]で光出 力 5[mW]時の発光のピーク波長は 348[nm]であり、発光量の 98[%]が 35[nm] の波長幅に収まっていた。 FIG. 12 shows an emission spectrum of the ultraviolet LED according to the seventh embodiment. The peak wavelength of light emission at 25 [° C] and light output of 5 [mW] was 348 [nm], and 98 [%] of the light emission amount was within the wavelength width of 35 [nm].
従って本実施形態 7に係る紫外 LEDでは、 GaN基板側に放射された紫外光の 90 Therefore, in the ultraviolet LED according to the seventh embodiment, the ultraviolet light emitted to the GaN substrate side is 90%.
[%]以上が、基板に吸収されずに、 n型超格子光反射層 703で反射され、その多く 力 ¾側のフォトニック結晶 714から取り出されている。紫外光 LEDは小型かつ長寿命 の露光装置に用いることができる。あるいは紫外光 LEDは誘蛾灯や殺菌灯や歯科 用の紫外線硬化樹脂の硬化用光源の用途がある。 [%] Or more is reflected by the n-type superlattice light reflecting layer 703 without being absorbed by the substrate, and most of it is taken out from the photonic crystal 714 on the higher power side. The UV LED can be used in a small and long-life exposure apparatus. Alternatively, UV LED can be used as a light source for hardening kidnapping lamps, germicidal lamps and dental UV-curing resins.
[0155] 窒化物 LEDは青色光や紫外光を受けると電流が流れるので、そのまま青色光や紫 外光の検知器として使用できる。火炎には太陽光より多い紫外光が含まれるので、青 色 LEDと紫外光 LEDを組み合わせて、青色光と紫外光の強度の比の変化を検知す ることにより、火炎の検知器を作ることができる。 [0155] Nitride LEDs can be used as detectors for blue light and ultraviolet light as they flow when they receive blue or ultraviolet light. Since flames contain more ultraviolet light than sunlight, a flame detector can be created by combining blue and ultraviolet LEDs to detect changes in the intensity ratio of blue and ultraviolet light. Can do.
[0156] [実施形態 8] [Embodiment 8]
図 9は、実施形態 8に係る高電子移動度トランジスタの断面図である。本実施形態 8 に係る高電子移動度トランジスタは、リセスゲ—ト型高電子移動度トランジスタ (HEM T)であり、半絶縁性 SiC基板 800上に、以下の半導体層が積層されている。すなわ ち、核形成層 801、チャネル層 802、スぺーサ層 803、電子供給層 804、極性半転 層 805、コンタクト層 806が、この順に積層されている。なお、本実施形態 8における 第 1の半導体層は、電子供給層 804であり、第 2の半導体層はコンタクト層 806であ る。 FIG. 9 is a cross-sectional view of the high electron mobility transistor according to the eighth embodiment. The high electron mobility transistor according to the eighth embodiment is a recess gate type high electron mobility transistor (HEM). T), and the following semiconductor layers are stacked on a semi-insulating SiC substrate 800. That is, a nucleation layer 801, a channel layer 802, a spacer layer 803, an electron supply layer 804, a polar half-rotation layer 805, and a contact layer 806 are laminated in this order. In the eighth embodiment, the first semiconductor layer is the electron supply layer 804, and the second semiconductor layer is the contact layer 806.
[0157] 核形成層 801は、層厚 40 [nm]の GaNにより構成される。また、チャネル層 802は 層厚 2. 6 [ m]の i GaN (Ga極性）〖こより、スぺーサ層 803は層厚 5 [nm]の i A1 Ga Nにより、電子供給層 804は、層厚 15 [nm]の n—Al Ga Nにより構 [0157] The nucleation layer 801 is made of GaN having a layer thickness of 40 nm. The channel layer 802 is made of i GaN (Ga polarity) having a thickness of 2.6 [m], the spacer layer 803 is made of i A1 Ga N with a thickness of 5 [nm], and the electron supply layer 804 is made of a layer It is composed of n-AlGaN with a thickness of 15 nm.
0. 35 0. 65 0. 35 0. 65 成される。 0. 35 0. 65 0. 35 0. 65
上記核形成層 801から電子供給層 804までの極性は、上述した Ga極性となるよう に構成されている。  The polarity from the nucleation layer 801 to the electron supply layer 804 is configured to be the Ga polarity described above.
[0158] 極性反転層 805は、 0. 1 [%]の Siドープ A1の 2層よりなる原子層により構成されて いる。また、コンタクト層 806は、層厚 40[nm]の n— GaNにより構成されている。この コンタクト層 806は、 N極性となるように構成されて！、る。  [0158] The polarity inversion layer 805 is composed of an atomic layer composed of two layers of 0.1% Si-doped A1. The contact layer 806 is composed of n-GaN having a layer thickness of 40 [nm]. This contact layer 806 is configured to be N-polar! RU
また、本実施形態 8に係る半導体素子は、ドレイン電極 807、ソース電極 808、リセ スゲート電極 809、素子分離層 810を備えている。  The semiconductor element according to the eighth embodiment includes a drain electrode 807, a source electrode 808, a recess gate electrode 809, and an element isolation layer 810.
[0159] 電子供給層 804のキャリア濃度は、 1 X 1018[cm_3]であり、コンタクト層 806のキヤ リア濃度は 1 X 1019[cm_3]である。 [0159] The carrier concentration of the electron supply layer 804 is a 1 X 10 18 [cm_ 3] , the wire carrier rear concentration of the contact layer 806 is a 1 X 10 19 [cm _3] .
本実施形態 8においては、半絶縁性 SiC基板 800上に、 MOVPEを用いて上記の 構造を成長させた。核形成層 801は、 500 [°C]の比較的低温環境下で成長させるこ とにより当該層を形成した。チャネル層 802は 1000[°C]、スぺーサ層 803は 1080[ °C]で成長させることにより当該層を形成した。極性反転層 805は、成長温度を 850 [ °C]にしてアンモニア流量を小さくし、ジシランを流しながら、 A1原料を 2分子層厚分 だけ、成長速度から見積もって供給することにより形成した。その後、コンタクト層 806 を成長させながら成長温度を 950 [°C]まで上げて成長させた。  In Embodiment 8, the above structure is grown on a semi-insulating SiC substrate 800 using MOVPE. The nucleation layer 801 was formed by growing it in a relatively low temperature environment of 500 [° C.]. The channel layer 802 was grown at 1000 [° C.] and the spacer layer 803 was grown at 1080 [° C.] to form the layer. The polarity inversion layer 805 was formed by setting the growth temperature to 850 [° C], decreasing the ammonia flow rate, and supplying the A1 raw material by the thickness of the bimolecular layer by estimating the growth rate while flowing disilane. Thereafter, the contact layer 806 was grown while the growth temperature was raised to 950 [° C].
[0160] リセスゲート電極 809のコンタクト面から i— GaN (Ga極性）チャネル層 802とスぺー サ層 803の界面までのチャネル深さ距離 hは 20 [nm]である。素子分離層 810は、そ れ以外の領域をフォトレジストで覆 、、イオンエネルギ 20 [keV]と 100 [keV]の窒素 のイオン注入を 2回行って、形成した。注入量は 10 [cm ]である。ドレイン電極 80 7とソース電極 808は Ti (25 [nm] ) /Al ( 150 [nm] )であり、 600 [°C]で 30秒のァ- —ルを行って、ォ一ミック化した。本実施形態 8によれば、コンタクト層 806上のコンタ タト抵抗は 5 X 10_6[ Q cm2]であり、 n— Al Ga N上に形成するより 1桁以上低 [0160] The channel depth h from the contact surface of the recess gate electrode 809 to the interface between the i-GaN (Ga polarity) channel layer 802 and the spacer layer 803 is 20 [nm]. The element isolation layer 810 is covered with a photoresist in other regions, and nitrogen with ion energy of 20 [keV] and 100 [keV] is applied. The ion implantation was performed twice to form. The injection volume is 10 [cm]. The drain electrode 807 and the source electrode 808 were Ti (25 [nm]) / Al (150 [nm]), and they were made ohmic by carrying out a 30 second roll at 600 [° C]. According to the eighth embodiment, the contact resistance on the contact layer 806 is 5 × 10 _6 [Q cm 2 ], which is one digit lower than that formed on n- AlGaN .
0. 35 0. 65  0. 35 0. 65
い値が得られた。  A good value was obtained.
[0161] SiN膜をエッチングマスクにして、燐酸硫酸のウエットエッチングにより、 n-GaN ( N極性)層 806をエッチングして、電子供給層 804の表面を露出させ、その上にリセ スゲート電極 809を蒸着して形成した。ソ一スとドレイン間の間隔は 3 [ m]であった 。ゲート電極 809は Ni (20[nm]) ZAu(130[nm])で、ゲート長は 0. 2[ /ζ πι]であ る。なお、ウエットエッチング時に極性反転層 805を残すようにしてもよいが、極性反 転層 805を除去して電子供給層 804とゲート電極 809とを直接接触させる方が好ま LV、。ショットキー障壁を高く設定することができるためである。  [0161] Using the SiN film as an etching mask, the n-GaN (N-polarity) layer 806 is etched by wet etching of phosphoric acid sulfuric acid to expose the surface of the electron supply layer 804, and a recess gate electrode 809 is formed thereon. It was formed by vapor deposition. The distance between the source and the drain was 3 [m]. The gate electrode 809 is Ni (20 [nm]) ZAu (130 [nm]), and the gate length is 0.2 [/ ζ πι]. Although the polarity inversion layer 805 may be left during wet etching, it is preferable to remove the polarity inversion layer 805 and directly contact the electron supply layer 804 and the gate electrode 809 LV. This is because the Schottky barrier can be set high.
[0162] 選択ウエットエッチングにより、 2インチウェハ内でのチャネル深さ距離 hの均一性は  [0162] By selective wet etching, the uniformity of the channel depth distance h within the 2-inch wafer is
± l [nm]と極めて均一であった。これは、ェピの均一性によるものである。得られた 素子は、ゲ―ト電圧 4 [V]で 25 [°C]での最大相互コンダクタンスは 550 [mS/mm] 、最大ドレイン電流 IDSは 1. 3 [AZmm]の高い特性を示した。  It was extremely uniform at ± l [nm]. This is due to the uniformity of the epi. The obtained device showed a high characteristic of a maximum transconductance of 550 [mS / mm] and a maximum drain current IDS of 1.3 [AZmm] at a gate voltage of 4 [V] and 25 [° C]. .
[0163] [実施形態 9]  [0163] [Embodiment 9]
図 10は、本実施形態 9に係る高電子移動度トランジスタの断面図である。本実施形 態 9の高電子移動度トランジスタは、リセスゲート型高電子移動度トランジスタ (HEM T)であり、層厚 110 [ μ m]の半絶縁性 GaN基板 900上に以下の層が積層されて ヽ る。すなわち、ノ ッファ層 901、チャネル層 802、スぺ—サ層 803、電子供給層 804、 極性反転層 805、ソース領域、ドレイン領域を形成するコンタクト層 806が、この順に 積層されている。また、この窒化物半導体素子は、ドレイン電極 807、ソース電極 808 、リセスゲート電極 809、素子分離層 810を備えている。なお、本実施形態における 第 1の半導体層は電子供給層 804であり、第 2の半導体層はコンタクト層 806である FIG. 10 is a cross-sectional view of the high electron mobility transistor according to the ninth embodiment. The high electron mobility transistor of Embodiment 9 is a recessed gate type high electron mobility transistor (HEM T), and the following layers are stacked on a semi-insulating GaN substrate 900 having a layer thickness of 110 [μm].ヽ. That is, a nofer layer 901, a channel layer 802, a spacer layer 803, an electron supply layer 804, a polarity inversion layer 805, a source layer, and a contact layer 806 forming a drain region are laminated in this order. The nitride semiconductor element includes a drain electrode 807, a source electrode 808, a recess gate electrode 809, and an element isolation layer 810. In the present embodiment, the first semiconductor layer is the electron supply layer 804, and the second semiconductor layer is the contact layer 806.
[0164] 本実施形態に係るバッファ層 901は、層厚 100[nm]の i GaNにより構成されてい る。上記バッファ層 901から電子供給層 804までの極性は、上述した Ga極性となるよ うに構成されている。 [0164] The buffer layer 901 according to the present embodiment is composed of iGaN having a layer thickness of 100 [nm]. The polarity from the buffer layer 901 to the electron supply layer 804 is the Ga polarity described above. It is configured as follows.
[0165] 半絶縁性 GaN基板 900は、 GaNに Fe、 Ni、又は、白金系の金属を 1 X 1018[cm" 3]程度の濃度でド ビングした基板、ある ヽは酸素や N欠陥を含まな!/、アンド プ高 抵抗の GaN基板である。その他の構造は、上記実施形態 8に記載の構造を備えて いる。半絶縁性 GaN基板 900の GaN結晶は、格子整合しているので、品質の高い 平坦な界面が得られる。その結果、高い電子移動度が得られる。 [0165] Semi-insulating GaN substrate 900 is a substrate in which Fe, Ni, or platinum-based metal is doped on GaN at a concentration of about 1 X 10 18 [cm "3]. Not included! /, High-resistance GaN substrate The other structure has the structure described in Embodiment 8. The GaN crystal of the semi-insulating GaN substrate 900 is lattice-matched. A flat interface with high quality is obtained, resulting in high electron mobility.
産業上の利用可能性  Industrial applicability
[0166] LDに関しては、 400 [nm]帯は光ディスク用、 480 [nm]帯はアルゴン ·ガスレーザ の代替が可能で、研究'医療用の光源の用途がある。 LEDに関しては、 400 [nm] 帯は照明光源用が主な市場である。そのほか、紫外露光用光源、フルカラーデイス プレイ用光源、 480 [nm]帯の集魚灯用光源などへの用途がある。ヘテロ接合型電 界効果トランジスタに関しては、第三世代携帯電話基地局のマイクロ波帯送信電力 増幅器、加入者系ワイヤレス ·アクセスや衛星インタ一ネット ·アクセスにおける高効率 増幅器としての利用可能性が挙げられる。 [0166] Regarding the LD, the 400 [nm] band can be used for optical discs, and the 480 [nm] band can be substituted for an argon / gas laser. As for LEDs, the 400 nm band is mainly used for illumination light sources. Other applications include UV light sources, full-color display light sources, and 480 [nm] band fishlight source. Heterojunction field-effect transistors can be used as microwave power transmitters in third-generation mobile phone base stations and high-efficiency amplifiers in subscriber wireless access and satellite Internet access. .

Claims

請求の範囲 The scope of the claims
[1] 基板と、該基板上に複数の半導体層が形成されている窒化物半導体素子であって 該基板上に形成される第 1の半導体層と、  [1] a substrate, and a nitride semiconductor device in which a plurality of semiconductor layers are formed on the substrate, and a first semiconductor layer formed on the substrate;
該第 1の半導体層の直上に積層される極性反転層と、  A polarity reversal layer laminated directly on the first semiconductor layer;
該極性反転層の直上に積層されて、少なくとも一部がウエットエッチングによりパタ 一ユングされる第 2の半導体層とからなる積層体を少なくとも一つ備え、  Comprising at least one laminate comprising a second semiconductor layer laminated immediately above the polarity inversion layer and at least partially patterned by wet etching;
該第 2の半導体層は、ウエットエッチングによりエッチングされる極性、  The second semiconductor layer has a polarity etched by wet etching,
該第 1の半導体層は、該第 2の半導体層の該ウエットエッチングによるエッチング停 止層となる極性に配設された窒化物半導体素子。  The nitride semiconductor device, wherein the first semiconductor layer is arranged in a polarity to be an etching stop layer by the wet etching of the second semiconductor layer.
[2] 請求項 1の窒化物半導体素子において、 [2] In the nitride semiconductor device of claim 1,
上記極性反転層は、以下の（1)から（5)のいずれかの層であることを特徴とする窒 化物半導体素子。  The nitride semiconductor element, wherein the polarity inversion layer is any one of the following layers (1) to (5).
(1) II族原子が 102°[cm_3]以上、 1023[cm_3]以下の濃度でドーピングされた 2 [n m]以下の層 (1) A layer of 2 [nm] or less doped with a group II atom at a concentration of 10 2 ° [cm_ 3 ] or more and 10 23 [cm_ 3 ] or less
(2) II族原子の単原子層  (2) Group II atom monolayer
(3) II族原子と V族原子とを含む単原子層、又は単分子層  (3) Monoatomic layer or monomolecular layer containing group II and group V atoms
(4) II族原子と ΠΙ族原子とを含む単原子層、又は単分子層  (4) Monoatomic layer or monomolecular layer containing group II atoms and group IV atoms
(5) ΠΙ族原子、又は Ζ及び、 V族原子の 2原子層  (5) V-group atoms or bi-layers of V and V-group atoms
[3] 請求項 1又は 2の窒化物半導体素子において、 [3] The nitride semiconductor device according to claim 1 or 2,
上記極性反転層は下記（1)から（5)の 、ずれかであることを特徴とする窒化物半導 体素子。  The nitride semiconductor device according to any one of the following (1) to (5), wherein the polarity inversion layer is a deviation.
(1) η型不純物原子が 102°[cm_3]以上、 1023 [cm—3]以下の濃度でドーピングされ た 2 [nm]以下の層 (1) A layer of 2 nm or less doped with η-type impurity atoms at a concentration of 10 2 ° [cm_ 3 ] or more and 10 23 [cm- 3 ] or less
(2) n型不純物原子の単原子層  (2) Monolayer of n-type impurity atoms
(3) n型不純物原子と ΠΙ族原子とを含む単原子層、又は単分子層  (3) Monoatomic layer or monomolecular layer containing n-type impurity atoms and ΠΙ group atoms
(4) n型不純物原子と V族原子とを含む単原子層、又は単分子層  (4) Monoatomic layer or monomolecular layer containing n-type impurity atoms and group V atoms
(5) n型不純物原子と III族原子と V族原子とを含む単原子層、又は単分子層 [4] 上記基板上であって、上記第 1の半導体層の下層、又は上記第 2の半導体層の上 層に活性層を備えている請求項 1〜3に記載の窒化物半導体素子。 (5) Monoatomic layer or monomolecular layer containing n-type impurity atoms, group III atoms and group V atoms [4] The nitride semiconductor device according to any one of [1] to [3], wherein an active layer is provided on the substrate and below the first semiconductor layer or above the second semiconductor layer.
[5] 請求項 4の窒化物半導体素子において、 [5] The nitride semiconductor device according to claim 4,
上記第 1の半導体層の下層に上記活性層を備え、上記第 2の半導体層がリッジ形 状にパターニングされることを特徴とするリッジ型の窒化物半導体素子。  A ridge-type nitride semiconductor device comprising the active layer below the first semiconductor layer, wherein the second semiconductor layer is patterned into a ridge shape.
[6] 請求項 4の窒化物半導体素子において、 [6] The nitride semiconductor device according to claim 4,
上記第 2の半導体層が、内部電流狭窄層であり、上記第 1の半導体層の下層に上 記活性層を備えることを特徴とする内部電流狭窄層型の窒化物半導体素子。  An internal current confinement layer type nitride semiconductor device, wherein the second semiconductor layer is an internal current confinement layer, and the active layer is provided below the first semiconductor layer.
[7] 請求項 6の窒化物半導体素子において、 [7] The nitride semiconductor device according to claim 6,
上記内部電流狭窄層は、以下の（1)から（3)のいずれかの条件を満たすことを特 徴とする窒化物半導体素子。  The nitride semiconductor device, wherein the internal current confinement layer satisfies any of the following conditions (1) to (3).
(1) ln Ga Al N (0≤X≤1、 0≤Y≤1、 0≤X+Y≤1)、  (1) ln Ga Al N (0≤X≤1, 0≤Y≤1, 0≤X + Y≤1),
X Υ 1 -Χ-Υ  X Υ 1 -Χ-Υ
(2) In Al Ν (0. 05≤Χ≤0. 3)、  (2) In Al Ν (0. 05≤Χ≤0.3.),
X 1 -Χ  X 1 -Χ
(3) (In Al ) Ga Ν (0. 2≤Ζ≤1)  (3) (In Al) Ga Ν (0. 2≤Ζ≤1)
Ο. 18 0. 82 Ζ 1 -Ζ  0. 18 0. 82 Ζ 1 -Ζ
[8] 請求項 4の窒化物半導体素子お 、て、  [8] The nitride semiconductor device according to claim 4, wherein
上記第 2の半導体層、及び該第 2の半導体層上に積層される半導体層がパター二 ングされ、当該パターユングにより開口した部位に埋め込み層を形成することを特徴 とする埋め込み型の窒化物半導体素子。  A buried nitride characterized in that the second semiconductor layer and a semiconductor layer stacked on the second semiconductor layer are patterned, and a buried layer is formed in a portion opened by the patterning. Semiconductor element.
[9] 請求項 4〜8のいずれかに記載の窒化物半導体素子において、 [9] The nitride semiconductor device according to any one of claims 4 to 8,
上記第 1の半導体層が分離光閉じ込めヘテロ構造層であり、該第 1の半導体層の 下層に上記活性層を備えて 、ることを特徴とする窒化物半導体素子。  The nitride semiconductor device, wherein the first semiconductor layer is a separated light confinement heterostructure layer, and the active layer is provided below the first semiconductor layer.
[10] 請求項 1〜9のいずれかに記載の窒化物半導体素子において、 [10] The nitride semiconductor device according to any one of claims 1 to 9,
上記半導体層は、 GaN系の半導体層により形成されていることを特徴とする窒化 物半導体素子。  The nitride semiconductor device, wherein the semiconductor layer is formed of a GaN-based semiconductor layer.
[11] 請求項 1〜： LOのいずれかに記載の窒化物半導体素子において、  [11] Claim 1 ~: The nitride semiconductor device according to any one of LOs,
上記第 2の半導体層の結晶の面方位が（000—1)、又は V族極性であることを特徴 とする窒化物半導体素子。  A nitride semiconductor device, wherein the crystal plane orientation of the second semiconductor layer is (000-1) or V group polarity.
[12] 請求項 1〜： L 1のいずれかに記載の窒化物半導体素子において、 窒化物フォトニック結晶を備えていることを特徴とする窒化物半導体素子。 [12] Claim 1 ~: The nitride semiconductor device according to any one of L1, A nitride semiconductor device comprising a nitride photonic crystal.
請求項 12の窒化物半導体素子において、  The nitride semiconductor device according to claim 12,
n型超格子光反射層を備えていることを特徴とする窒化物半導体素子。  A nitride semiconductor device comprising an n-type superlattice light reflecting layer.
請求項 1〜13のいずれかに記載の窒化物半導体素子において、  The nitride semiconductor device according to any one of claims 1 to 13,
P電極と、  P electrode,
該 p電極に接続される pコンタクト層とを備え、  A p-contact layer connected to the p-electrode,
該 pコンタクト層は、 N極性であり、その層厚が 10[nm]以上、 50[nm]以下であること を特徴とする窒化物半導体素子。  The p-contact layer is N-polar and has a layer thickness of 10 [nm] or more and 50 [nm] or less.
請求項 1〜14のいずれかに記載の窒化物半導体素子において、  The nitride semiconductor device according to any one of claims 1 to 14,
P電極と、  P electrode,
該 p電極に接続される pコンタクト層とを備え、  A p-contact layer connected to the p-electrode,
該 pコンタクト層は、 N極性であり、該 p電極力 SPdを少なくとも含む材料により構成さ れて 、ることを特徴とする窒化物半導体素子。  The nitride semiconductor device, wherein the p contact layer is N-polar and is made of a material containing at least the p electrode force SPd.
請求項 1、 2、又は 3の窒化物半導体素子において、  The nitride semiconductor device according to claim 1, 2, or 3,
上記第 1の半導体層は、ゲート電極に接続される電子供給層であり、  The first semiconductor layer is an electron supply layer connected to the gate electrode,
上記第 2の半導体層は、ソース電極、及びドレイン電極にォーミックに接するコンタ タト層であることを特徴とする窒化物半導体素子。  The nitride semiconductor device, wherein the second semiconductor layer is a contact layer in ohmic contact with the source electrode and the drain electrode.
請求項 16の窒化物半導体素子において、  The nitride semiconductor device of claim 16,
上記コンタクト層は、当該コンタクト層の成長方向の面方位が（000— 1 )である V族 極性の n型半導体層であり、  The contact layer is a group V polar n-type semiconductor layer whose plane direction in the growth direction of the contact layer is (000-1),
上記電子供給層は、当該電子供給層の成長方向の面方位が（0001)である III族 極性の n型半導体層であることを特徴とする窒化物半導体素子。  The nitride semiconductor element, wherein the electron supply layer is a group III polar n-type semiconductor layer whose plane direction in the growth direction of the electron supply layer is (0001).
請求項 16又は 17の窒化物半導体素子において、  The nitride semiconductor device according to claim 16 or 17,
上記半導体層として、上記第 1の半導体層の下層にチャネル層、スぺーサ層の順 に積層されている半導体層を含み、  The semiconductor layer includes a semiconductor layer laminated in the order of a channel layer and a spacer layer under the first semiconductor layer,
該チャネル層は、 III族極性のアンドープの GaN層、  The channel layer comprises a group III polar undoped GaN layer,
該スぺーサ層は、アンドープの Al Ga N層（ただし、 0<X≤ 1)、  The spacer layer is an undoped Al Ga N layer (where 0 <X≤ 1),
X 1 -X  X 1 -X
上記電子供給層は、 n型の Al Ga N層（ただし、 0<X≤ 1)、 上記コンタクト層は、 V族極性の n型の Al Ga N層（ただし、 0≤Y<X)、又は、 η The electron supply layer is an n-type AlGaN layer (where 0 <X≤ 1), The contact layer is a group V polar n-type Al Ga N layer (where 0≤Y <X) or η
Υ 1— Υ  Υ 1— Υ
型の In Ga N層（ただし、 0≤Z≤0. 2)であることを特徴とする窒化物半導体素子 Nitride semiconductor device characterized by a type of InGaN layer (where 0≤Z≤0.2)
Z 1 -Z Z 1 -Z
[19] 請求項 18の窒化物半導体素子において、 [19] The nitride semiconductor device of claim 18,
上記スぺーサ層は、 III族極性であって、該スぺーサ層と上記電子供給層との層厚 の和は、 10[nm]以上、 25[nm]以下であり、かつ、該電子供給層及び該スぺーサ層 の組成比 Xの値が、 0. 25以上、 0. 45以下であることを特徴とする窒化物半導体素 子。  The spacer layer has group III polarity, and the sum of the layer thicknesses of the spacer layer and the electron supply layer is not less than 10 [nm] and not more than 25 [nm], and the electron A nitride semiconductor device, wherein the composition layer X of the supply layer and the spacer layer has a value of 0.25 or more and 0.45 or less.
[20] 請求項 15〜19のいずれかに記載の窒化物半導体素子において、  [20] In the nitride semiconductor device according to any one of claims 15 to 19,
上記基板が、半導体絶縁性の SiC基板、又は半導体絶縁性の GaN基板であること を特徴とする窒化物半導体素子。  A nitride semiconductor device, wherein the substrate is a semiconductor insulating SiC substrate or a semiconductor insulating GaN substrate.
[21] 基板上に第 1の半導体層と、該第 1の半導体層の直上に形成される極性反転層と、 該極性反転層の直上に形成され、該第 1の半導体層とは極性の異なる第 2の半導体 層とからなる積層体を少なくとも一つ含む複数の半導体層を備える窒化物半導体素 子の製造方法であって、 [21] A first semiconductor layer formed on the substrate, a polarity reversal layer formed immediately above the first semiconductor layer, and formed on the polarity reversal layer, the first semiconductor layer having a polarity A method for manufacturing a nitride semiconductor device comprising a plurality of semiconductor layers including at least one laminate comprising different second semiconductor layers,
該第 2の半導体層のパターユング形成におけるウエットエッチング時にエッチング 停止層となる該第 1の半導体層を形成し、  Forming the first semiconductor layer serving as an etching stop layer during wet etching in patterning of the second semiconductor layer;
該極性反転層を形成し、  Forming the polarity inversion layer;
該第 2の半導体層を形成し、  Forming the second semiconductor layer;
該第 2の半導体層をウエットエッチング法によりエッチングし、  Etching the second semiconductor layer by a wet etching method,
該第 2の半導体層のパターンを形成する窒化物半導体素子の製造方法。  A method for manufacturing a nitride semiconductor device, wherein the pattern of the second semiconductor layer is formed.
[22] 請求項 21の窒化物半導体素子の製造方法において、 [22] In the method of manufacturing a nitride semiconductor device according to claim 21,
上記ウエットエッチングは、燐酸と硫酸の混合液を用い、  The wet etching uses a mixed solution of phosphoric acid and sulfuric acid,
該ウエットエッチングを 80 [°C]以上、 300 [°C]以下の温度で行うことを特徴とする 窒化物半導体素子の製造方法。  The method of manufacturing a nitride semiconductor device, characterized in that the wet etching is performed at a temperature of 80 [° C] or higher and 300 [° C] or lower.
[23] 請求項 21又は 22の窒化物半導体素子の製造方法において、 [23] The method for producing a nitride semiconductor device according to claim 21 or 22,
上記複数の半導体層は、以下の（1)から（3)の方法により製造されることを特徴と する窒化物半導体素子の製造方法。 (1)有機金属気相成長法 The method for manufacturing a nitride semiconductor device, wherein the plurality of semiconductor layers are manufactured by the following methods (1) to (3). (1) Metalorganic vapor phase epitaxy
(2)分子線ヱピタキシ法  (2) Molecular beam pitaxi method
(3) V族極性、又は (000— 1)面の該半導体層を形成は有機金属気相成長法、 ΠΙ 族極性、又は (0001)面の該半導体層を形成は分子線ェピタキシ法  (3) Group V polarity or (000-1) plane semiconductor layer is formed by metalorganic vapor phase epitaxy, Group V polarity or (0001) plane semiconductor layer is formed by molecular beam epitaxy
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