WO2006013177A3 - Planar connection technique for guiding a current in the event of a failure - Google Patents
Planar connection technique for guiding a current in the event of a failure Download PDFInfo
- Publication number
- WO2006013177A3 WO2006013177A3 PCT/EP2005/053644 EP2005053644W WO2006013177A3 WO 2006013177 A3 WO2006013177 A3 WO 2006013177A3 EP 2005053644 W EP2005053644 W EP 2005053644W WO 2006013177 A3 WO2006013177 A3 WO 2006013177A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- components
- event
- failure
- guiding
- current
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
- H01L2224/24051—Conformal with the semiconductor or solid-state device
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H01L2924/01032—Germanium [Ge]
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- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
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- H—ELECTRICITY
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004037078.8 | 2004-07-30 | ||
DE200410037078 DE102004037078A1 (en) | 2004-07-30 | 2004-07-30 | Planar connection technology for power supply in the event of a fault |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2006013177A2 WO2006013177A2 (en) | 2006-02-09 |
WO2006013177A3 true WO2006013177A3 (en) | 2006-07-27 |
Family
ID=34973200
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2005/053644 WO2006013177A2 (en) | 2004-07-30 | 2005-07-26 | Planar connection technique for guiding a current in the event of a failure |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE102004037078A1 (en) |
WO (1) | WO2006013177A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3379710B1 (en) * | 2017-03-24 | 2021-10-27 | Thales | Switching power converter configured to control at least one phase of a polyphase electrical receiver with at least three phases |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10037533C1 (en) * | 2000-08-01 | 2002-01-31 | Semikron Elektronik Gmbh | Low-inductance circuit arrangement |
EP1209742A1 (en) * | 2000-11-22 | 2002-05-29 | ABB Schweiz AG | Power Semiconductor Module and application of such a Power Semiconductor Module |
WO2003030247A2 (en) * | 2001-09-28 | 2003-04-10 | Siemens Aktiengesellschaft | Method for contacting electrical contact surfaces of a substrate and device consisting of a substrate having electrical contact surfaces |
DE10244748A1 (en) * | 2002-09-25 | 2003-09-11 | Siemens Ag | Power semiconductor module has chips contacted by high current capability metal straps to withstand short circuits |
DE10255602A1 (en) * | 2002-11-28 | 2004-06-24 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | Semiconductor circuit arrangement for controlling a high voltage or a current of large amperage |
-
2004
- 2004-07-30 DE DE200410037078 patent/DE102004037078A1/en not_active Ceased
-
2005
- 2005-07-26 WO PCT/EP2005/053644 patent/WO2006013177A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10037533C1 (en) * | 2000-08-01 | 2002-01-31 | Semikron Elektronik Gmbh | Low-inductance circuit arrangement |
EP1209742A1 (en) * | 2000-11-22 | 2002-05-29 | ABB Schweiz AG | Power Semiconductor Module and application of such a Power Semiconductor Module |
WO2003030247A2 (en) * | 2001-09-28 | 2003-04-10 | Siemens Aktiengesellschaft | Method for contacting electrical contact surfaces of a substrate and device consisting of a substrate having electrical contact surfaces |
DE10244748A1 (en) * | 2002-09-25 | 2003-09-11 | Siemens Ag | Power semiconductor module has chips contacted by high current capability metal straps to withstand short circuits |
DE10255602A1 (en) * | 2002-11-28 | 2004-06-24 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | Semiconductor circuit arrangement for controlling a high voltage or a current of large amperage |
Also Published As
Publication number | Publication date |
---|---|
WO2006013177A2 (en) | 2006-02-09 |
DE102004037078A1 (en) | 2006-03-23 |
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