WO2006000138A1 - Tampon et procede associe - Google Patents
Tampon et procede associe Download PDFInfo
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- WO2006000138A1 WO2006000138A1 PCT/CN2005/000199 CN2005000199W WO2006000138A1 WO 2006000138 A1 WO2006000138 A1 WO 2006000138A1 CN 2005000199 W CN2005000199 W CN 2005000199W WO 2006000138 A1 WO2006000138 A1 WO 2006000138A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
- G06F12/125—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being generated by decoding an array or storage
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
Definitions
- the present invention is an invention of an apparatus and method for buffering data. More specifically, the cache apparatus and method of the present invention have higher cache memory usage than the previous method, and are capable of high-speed cache processing for large-capacity cache memories. Furthermore, the present invention is a cache device and method for enabling high speed data reading and writing between a host and a storage device. Background technique
- the read and write speeds of data and external main storage media are slow compared to the processing speed of the CPU or host. Therefore, regardless of the ability of the CPU or the host, the data read/write speed with the external main storage medium becomes a bottleneck that affects the speed of the entire system.
- a local cache memory is provided between the CPU and an external main storage medium.
- the reason for this is that although the cache memory is smaller than the capacity of the external main storage medium, it can be read and written relatively quickly, so that the data that has been read from the external main storage medium is stored therein, thereby improving the overall Processing speed.
- data reading and writing between the CPU and the external main storage medium is performed in units of blocks of multiple bytes, that is, in units of blocks (or lines).
- This block has an address consisting of multiple bits, which is the data address of the data in the external primary storage medium.
- the n-Way Set Associative method is adopted in Japanese Patent Laid-Open No. 2004-38807.
- the cache memory is composed of a plurality of paths, and each of the routes is composed of a plurality of blocks.
- an index indicating its position within the road is given in each block in the road.
- the lower bits of the data address of the data are indexed, and the higher bits a2 are used as the identifier of the data.
- the blocks in the cache memory are associated with the data of the external primary storage medium.
- data having the same lower address a1 that is, data having the same index
- LRU Least Recently Used
- New data will it Replace it.
- the lower bits a1 of the data address of the external primary storage media data are designated as a specific index in the cache memory, thereby being limited to this position. Therefore, in this method, even if there is an empty block as a whole from the cache memory, there is a case where the data in the cache memory has to be deleted in order to store new data, so that the storage space usage rate of the cache memory is lowered.
- all the blocks in the cache memory can be used as a way.
- the data of the external primary storage medium is not limited to a specific location on the cache memory, so that all data can be stored anywhere on the cache memory.
- the capacity and the block capacity of the cache memory are the same, compared with the foregoing method, since the identifier of this method is greatly increased, there is a problem that the processing time at the time of querying the identifier is greatly increased.
- An object of the present invention is to provide an apparatus and method capable of performing cache processing at a high speed even for a large-capacity cache memory, and a cache processing apparatus having a higher storage space utilization rate than a conventional cache memory and method.
- the present invention provides a cache device, including: a module for querying an identifier of data stored in a cache memory; and outputting an address of a hit identifier if the query result is a hit, If there is no hit, the module that outputs the address of the identifier of the LRU prepared in advance; and, for the next query, the module that determines the identifier of the LRU at the current time.
- the cache device of an embodiment comprising: a module having the following features, comprising: in the form of an identifier corresponding to the data to be read and written, increasing the order of reading and writing data each time the data is read or written
- the pointer value is stored in the module, and the identifier of the LRU is determined by the pointer value, and when all the pointer values reach a given value, the module is corrected for all the pointer values.
- the present invention provides a caching method, including: a process of querying an identifier of data stored in a cache memory; and outputting a hit identifier if the query result is a hit The process of outputting the address of the identifier of the LRU prepared in advance if there is no hit; and, the process of determining the identifier of the LRU at the current time for the next inquiry.
- the caching method in an embodiment is characterized in that the process includes the following steps, that is, in the form of an identifier corresponding to the read and written data, each time the data is read or written, the order is increased according to the read and write data.
- Pointer The value is stored; the identifier of the LRU is determined by the pointer value; when the maximum value of all the pointer values reaches a given value, all pointer values are corrected.
- a cache method comprising: setting a global pointer having a global pointer value corresponding to a current time, and assigning the pointer value stored corresponding to the read/write data to the global The process of the pointer value currently possessed by the pointer; the global pointer value possessed by the global pointer is incremented by one; and, when the global pointer value reaches a given value, the value from the global pointer And the process of shifting the given value by all the pointer values stored corresponding to the data for translation processing.
- the translation processing is performed in a sequential manner.
- the caching method is characterized in that: according to the size of the stored pointer value, it is divided into an MRU group with a large pointer value, an LRU group with a small pointer value, and an MRU group and Intermediate grouping between LRU groups.
- the pointer value of the hit identifier is not updated; when the identifier belonging to the intermediate group and the LRU group is hit, the pointer value of the hit identifier is updated, and The smallest pointer value among the pointer values belonging to the MRU group is moved to the intermediate group.
- a cache method comprising: storing the pointer value, using an identifier of each data as an LRU table, and dividing the LRU table into sub-LRU tables of the same size. a process of extracting a minimum pointer value from the sub-LRU tables and generating an intermediate LRU table using the extracted pointer value; a process of dividing the intermediate LRU table into intermediate sub-LRU tables of the same size; and, The process of extracting the smallest pointer value from the respective intermediate sub-LRU tables to generate the next intermediate LRU table is iterated until the process of extracting the identifier of the final LRU.
- the identifier of the final LRU i.e., the identifier of the data which has been used longest in the cache memory
- the hit rate of the cache memory can be improved.
- the present invention can significantly improve the read/write speed of data when the present invention is applied to a medium having an excessive OVERHEAD such as a disk array or a DVD array.
- a lower cost can be used.
- the present invention can further increase the system speed by using a relatively high-speed inquiry method such as CAM (Content Addressed Memory) or the like.
- FIG. 1 is a schematic view of a system in an embodiment of the present invention.
- Fig. 2 is a view showing a more detailed configuration of a cache processing device in the embodiment of the present invention.
- FIG. 3 is a flowchart of a cache process performed by a processing unit in the embodiment of the present invention.
- FIG. 4 is a diagram showing an index 1 table, an index 2 table, an index n table, and an identifier table used when the cache processing in the embodiment of the present invention is implemented.
- Fig. 5 is a diagram showing an LRU table, an intermediate 1LRU table, and an intermediate nLRU table used in the cache processing in the embodiment of the present invention.
- Fig. 6 is a view showing the relationship between an LRU table and a cache memory in the embodiment of the present invention.
- Fig. 7 is a view showing the shifting process of the pointer value and the shifting process in the embodiment of the present invention. detailed description
- FIG. 1 is a schematic illustration of a system in which the present invention is used.
- Symbol 1 is a host, a PC or workstation that issues data read and write commands.
- the symbol 2 is a buffer device, and the cache device 2 is composed of a cache control unit 7a and a cache memory 7b.
- Symbol 3 is a storage device and is an external main storage medium such as a disk array or a DVD array that stores data.
- the function of the cache device 2 is to transfer data between the host 1 and the storage device 3.
- the data transfer with the host 1 is performed via the host interface 7c, and the data transfer with the storage device 3 is performed via the target interface 7d.
- the cache device 2 accepts the data sent from the host 1 and writes the data to the storage device 3, while using this data as the latest data used, both MRU (Most Recently Used ( Most recently used) data is stored in the cache memory 7b in the cache device 2.
- MRU Mobile Recently Used
- the cache device 2 first confirms whether or not the required data is stored in the cache memory 7b. If there is such data, the cache device 2 immediately transmits this data to the host 1. Then, the data is regarded as data used by the MRU update so far, and the current MRU data is replaced with the data, and is continuously stored in the cache memory 7b as new MRU data. If there is no required data in the cache memory 7b, the cache device 2 obtains this data through the storage device 3, and stores this data as new MRU data in the cache memory 7b. This data is then transferred to host 1.
- the cache device 2 stores the data in the cache memory 7b, and speeds up the system by processing the data, i.e., buffer processing.
- This cache processing is realized by using an identifier obtained from several data addresses of the data, and a detailed description of the cache processing using the identifier will be described later.
- Fig. 2 is a diagram showing a more detailed structure of the cache device 2.
- the cache control unit 7a in the cache device 2 is composed of a CPU indicated by reference numeral 4 and a peripheral circuit (hereinafter referred to as CPU 4) and a control circuit indicated by reference numeral 5.
- the control circuit 5 is composed of an interface unit 6a that performs data transfer and a cache processing unit 6b which will be described later in detail.
- the cache device 2 transfers the read/write command from the host 1 to the CPU 4 via the host interface 7c, the interface unit 6a, and the interface 6c. Based on this command, the CPU 4 transmits the cache processing command to the cache processing unit 6b via the CPU interface 6c and the interface unit 6a. The cache processing unit 6b performs a cache process based on this command. Thereafter, the cache processing unit 6b sends the result of the cache processing to the CPU 4. Then, the CPU 4 performs read/write control of the host 1, the storage device 3, or the cache memory 7b via the interface unit 6a.
- the control circuit 5 herein can be realized by, for example, an FPGA (Field Programmable Gate Array) or the like. Further, although the control circuit is employed in the present embodiment, it is not always necessary to adopt a circuit configuration. For example, this feature can also be implemented in software.
- Fig. 3 is a flowchart of the buffer processing performed by the cache processing unit 6b.
- the CPU 4 sends a cache processing command to the cache processing unit 6b.
- the command here is a query request for the specified identifier, represented as symbol 30 in the figure.
- the cache processing of the present invention performed by the cache processing unit 6b is characterized by two stages of processing consisting of the query processing P1 and the subsequent processing P2 surrounded by the broken line in the figure. That is, in the query processing P1, the identifier is queried in the cache memory 7b according to the query request, and the query result shown by the symbols 31, 32 is first sent to the CPU 4. Then, after the query result is sent to the CPU 4, it is prepared for the next cache processing in the subsequent processing P2.
- Fig. 4 shows an index 1 table 8a, an index 2 table 9a, a "*, an index n table 10a, and an identifier table 11a" used in the cache processing.
- the above-described query processing P1 is performed using these tables.
- the table 11a is composed of a plurality of sub-identifier tables 11b, llc, lid, ... having the same size.
- the query is gradually narrowed down.
- each unit 8b, 8c, 8d, ... contains information for grouping the identifiers in the cache memory 7b according to the range in which their values are located.
- the conditions for performing this group division are: the identifier value of the area packet, the identifier value of the identifier of the data in the cache memory; and the number of identifiers in the group is within a given number. Therefore, each unit 8b, 8c, 8d, ... is represented by the front-end identifier value in the index 2 sub-tables 9b, 9c, 9d...
- each unit 8b, 8c, 8d ... is classified in order of the identifier value.
- the query is performed on the target identifier by gradually narrowing down the range by obtaining the sub-table number of the index 2 table in the range.
- Index 2 Table 9a consists of a plurality of sub-tables 9b, 9c, 9 (1 ⁇ of index 2. These sub-tables 9b, 9c, 9d, ... of index 2 are the same as index 1 table 8a,
- the front-end identifier in the sub-table of the index 3 table and the number of the sub-table of the index 3 are composed of a plurality of units. Among these, if the index 2 is selected from the index 1 table 8a When the identifier of the target identifier is included in the given range displayed by each unit of the sub-table of the table, the sub-table number of the index 3 table of the range can be obtained. Thus, the target identifier can be further narrowed down.
- This index n table 10a is composed of a plurality of sub-tables 10b, 10c, 10d, ... of index n.
- the sub-tables 10b, 10c, 10d, ... of these indices n are further represented by: the front-end identifier values of the sub-identifier tables 11b, llc, lid, ..., and the numbers of the sub-identifier tables 11b, llc, lid, ...
- the sub-table number containing the identifier value of the target identifier can be obtained, thereby querying the target identifier.
- Each of the identifiers in the sub-identifier tables llb, llc, lld, ... is sorted in order according to the size of the identifier value, so that it is possible to check whether there is a target identifier here.
- the data address of the identifier in the cache memory 7b can be obtained.
- the table in the identifier table 11a must be sorted.
- the LRU data is replaced with new MRU data by a cache process.
- it is inserted into a certain sub-identifier table llb, llc, lid, ... of the identifier table 11a.
- the identifier of the data replaced by the new MRU data that is, the identifier of the LRU data, is deleted from the sub-identifier table in which the identifier is written.
- the sub-table 11a is sorted as described above. However, by sorting the table, the sub-identifier tables 11b, llc, lld, ... sometimes increase or decrease, and in this case, it is necessary to sort the respective index tables.
- the increase or decrease of these tables is managed by map tables 13, ..., 14, and 15 corresponding to the respective tables.
- Sub-table 1 will occur under the following conditions? The increase or decrease of , llc, lld, ..., that is, when the number of identifiers in the sub-identifier table after the identifier of the MRU data is inserted exceeds a given number.
- the unused sub-identifier table is obtained from the mapping 15 of the sub-table, and half of the identifiers of the sub-table overflowing the identifier are placed in the table, thus adding a sub-identifier table. Further, when the number of identifiers in the sub-identifier table in which the identifier of the LRU data is deleted is a given number, for example, only 1 I 4 of the sub-table, the sub-identifier table is reduced. At this time, the sub-identifier table is merged with the sub-identifier table that is logically adjacent or has the closest value to its front-end identifier, so that one sub-identifier table will become an unused table.
- the number of the merged identifiers is divided into two halves respectively in the two sub-identifier tables, so the identifier The deletion of the character does not affect the increase or decrease of the sub-identifier table.
- the LRU table 16 the intermediate 1LRU table 17, and the intermediate nLRU table 18 used in the cache processing are shown. These tables are used to extract an identifier indicating the data that has been read and written the longest time in the cache memory 7b, that is, the identifier of the final LRU 19.
- the LRU table 16 is composed of identifiers of all data stored in the cache memory 7b, and these identifiers have pointer values required for extracting the LRU.
- the pointer value is a value given to the data to be read or written, and the value is obtained by the global pointer indicated by the symbol 23, corresponding to the current time in the buffer processing.
- the value of this global pointer 23 is always the value of the pointer value of the MRU of the current stage plus one.
- These identifiers having this pointer value are respectively divided into a plurality of sub-LRU tables 20a, 20b, ... of equal size by a given number, and the LRU table 16 is composed of a plurality of sub-LRU tables 20a, 20b, ....
- the identifier having the smallest pointer value is first extracted from each of the sub-LRU tables 20a, 20b, ... of the LRU table 16. Then, they are concentrated to form an intermediate 1LRU table 17.
- the contents of the intermediate 1LRU table 17 are composed of pointer values of identifiers extracted from the LRU table and data addresses corresponding to the identifiers.
- the intermediate 1LRU table 17, is divided into a plurality of equal-sized intermediate 1 sub-LRU tables 21a, 21b, ....
- the smallest pointer value is extracted from each of the intermediate 1 sub-LRU tables 21a, 21b, .... Then concentrate them to form an intermediate 2LRU table.
- the number of identifiers be 1000, set the sub-LRU tables 20a, 20b, ... and each intermediate sub-LRU
- the number of identifiers in the table is ten, and the number of sub-LRU tables 21a, 21b, ... is 100, and the number of intermediate sub-sub-LRU tables 21a, 21b, ... is ten.
- the middle 2 sub-LRU table is one, and the final LRU 19 is extracted through this table.
- the 15th identifier of the LRU table 16 is replaced with the identifier of the new MRU data
- the new final LRU 19 is extracted, only the table in which the change has occurred, that is, the (No.
- the LRU table 20b and the (1st) intermediate 1 sub-LRU table 21a also have a middle 2 sub-LRU table.
- the processing of these three tables is as follows.
- the LRU1 with the smallest pointer value is extracted from the sub-LRU table 20b of (No. 2), and the LRU2 and LRU3 with the smallest pointer value in the middle 1 sub-LRU table 21a of the (1st) and the middle 2 sub-LRU table are respectively extracted. .
- this LRU1 is written to the intermediate 1 sub-LRU table 21a of (No. 1), and LRU1 and LRU2 are compared at the same time.
- the smaller value is then written to the middle 2 sub-LRU table while it is compared to LRU3.
- the smaller value is the smallest LRU, the new final LRU19.
- Figure 6 shows the relationship between the LRU table 16 and the cache memory 7b.
- the sub-LRU table 20 in the LRU table 16 corresponds to the memory chunks in the cache memory 7b, the data represented by one of the sub-LRU tables 20a, 20b, ..., and the cache memory 7b.
- the corresponding memory block corresponds.
- the size of the memory block is 64 KB.
- the size of the sub-LRU table 20 is 10
- the size of the memory chunk is 640 KB. If the entire capacity of the cache memory 7b is 64 GB, the LRU table 16 is composed of 100,000 sub-LRU tables 20.
- Fig. 7 shows the state before the shift processing of the pointer value and after the shift processing.
- the shift processing is a process of reducing the pointer value of all the identifiers in the cache memory 7b by a given value. Namely, by replacing the identifier having the pointer value of the final LRU 19 with the identifier having the MRU pointer value by the cache processing, the pointer value of each identifier in the cache memory 7b is always changed in the direction in which the pointer value is increased. Therefore, in order to prevent the pointer value of the MRU from overflowing after a certain period of time, the processing is performed periodically based on the upper limit value of the pointer value of the MRU.
- This processing is performed for each sub-LRU table 20a, 20b, ... and each of the intermediate 1 sub-LRUs 21a, 21b, ... and ..., the intermediate n sub-LRU table 22, and is expressed in units of tables. For example, after one cache processing, one of the tables is shifted in a predetermined order. For this reason, in the process of extracting the final LRU 19, when the pointer value is moved from the shifted processed table to the unshifted table, it is first returned to the value before the shift processing.
- the number of identifiers in the LRU table 16 is 10,000 and the number of identifiers in each sub-LRU table is 10, the number of shift processing is 111.
- the flow of the cache processing in the cache processing unit 6b will be described using the flowchart of Fig. 3 .
- the entry of the cache processing unit 6b is subjected to the inquiry request waiting process of step S91, and the inquiry request 30 of the CPU 4 is accepted.
- the query request here waits for processing, and iterates through the loop until the query request 30 is accepted before proceeding to the next step.
- the inquiry request 30 is accepted by the step S91 to start the buffer processing.
- the processing is divided into the inquiry processing P1 and the subsequent processing P2 in the present invention.
- each index table 8a, 9a, ..., 10a and the identifier table 11a are used to check whether or not the target identifier exists in the cache memory 7b.
- the data address of the target identifier obtained by the query result 31, that is, the identifier table lia, in the cache memory 7b is transferred to the CPU 4 in step S103. Then, the process proceeds to step S203. If the target identifier is not found, i.e., there is no hit, the previously prepared query result 32, i.e., the data address of the identifier of the final LRU in the cache memory 7b, is transferred to the CPU 4 by step S102.
- the cache processing of the present invention first transmits the query result of the query request 30 to the CPU 4 by the query processing P1 regardless of whether the target identifier exists or not, and then performs the subsequent processing P2 for preparing for the next buffer processing. Speed up the overall processing of the system.
- step S201 the identifier of the new data stored in the cache memory 7b is inserted into the identifier table 11a as described above. Then, from step S202, the identifier of the LRU data replaced with this new data is deleted from the identifier table 11a. Then, after the respective tables are arranged, the process proceeds to step S203.
- step S203 the identifier of the final LRU 19 is prepared for the next buffer processing. Further, even if the target identifier is hit by the query processing P1, this processing is performed via step S103. Here, the identifier of the final LRU 19 is extracted using the LRU table 16. After this processing, it is judged whether or not the pointer value of the MRU reaches the given reference value. If the entry to the cache processing is not reached, that is, step S91, if it is reached, the process proceeds to step S204.
- step S204 shift processing is performed on the pointer value. That is, before the overflow of the increasing pointer value, the pointer value is shifted in the decreasing direction as described above.
- the identifier of the MRU in the LRU table 16 the difference between the pointer value of the MRU in the LRU table 16 and the pointer value of the LRU, and the identifier in the LRU table 16
- the numbers are equal.
- the pointer value of the hit identifier is not the pointer value of the LRU, the identifier becomes the difference between the new MRU, the pointer value of the MRU and the pointer value of the final LRU, and becomes the identifier in the LRU table 16.
- the number of characters is large. An extreme example of this is that if the identifier of the MRU and the identifier of the MRU-1 are alternately hit repeatedly, only the two pointer values increase. If the shift processing is done in this case, the other pointer values will become close to zero, or smaller than zero.
- all the identifiers in the LRU table 16 are grouped, and different pointer values are processed for different groups. That is, first, the pointer value of the MRU is first, and the identifier of the given number of the most recently used identifiers is sequentially added to form an MRU group. Then, when the identifier in the MRU group is hit, the pointer value of the identifier is not overwritten with the value of the global pointer value 23. In addition, for example, when the pointer value is shifted to zero or less due to being unable to be hit all the time, the value is set to the zero pointer value. An identifier that makes the pointer value zero constitutes an LRU group.
- the identifiers in the LRU group are not prioritized, and the final LRU can be selected in a given order (e.g., physical order) in the LRU table. Identifies identifiers other than the LRU group and the MRU group into the middle group. If the identifier of the LRU group and the intermediate group is hit, the pointer value of the identifier is overwritten with the value of the global pointer value 23 to become the new MRU pointer value.
- a given order e.g., physical order
- the pointer value of the identifier will not be updated to the pointer value of the new MRU.
- the pointer values of all the identifiers in the LRU table 16 do not change.
- the identifier of the 500th number in the MRU group will automatically become a member of the intermediate group.
- the data of the LRU is replaced with the data. Since the identifier of the data is an identifier with an MRU pointer value, it is added to the MRU group. Then, in preparation for the next cache processing, the final LRU is extracted by a given order (such as physical order) in the LRU group.
- a cache storage device and method in a PC or the like as a host, an external main storage device as a storage device, and the like have been described.
- the invention is not limited to these.
- the method of the present invention can also be used in a CPU and a cache memory generally composed of SRAM (Static RAM) located near the CPU.
- the method of the present invention can also be used in various software cache processes implemented by the OS on the main memory, such as a so-called map cache.
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US11/597,494 US7627719B2 (en) | 2004-06-29 | 2005-02-18 | Cache device and method for determining LRU identifier by pointer values |
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US8782143B2 (en) * | 2008-12-17 | 2014-07-15 | Adobe Systems Incorporated | Disk management |
JP4734432B2 (ja) * | 2009-02-18 | 2011-07-27 | 株式会社東芝 | データ記憶システム |
US8700646B2 (en) * | 2009-08-12 | 2014-04-15 | Apple Inc. | Reference file for formatted views |
CN105740352A (zh) * | 2016-01-26 | 2016-07-06 | 华中电网有限公司 | 用于智能电网调度控制***的历史数据服务*** |
CN109032969A (zh) * | 2018-06-16 | 2018-12-18 | 温州职业技术学院 | 一种基于k值动态监测的lru-k算法的缓存方法 |
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US4322795A (en) * | 1980-01-24 | 1982-03-30 | Honeywell Information Systems Inc. | Cache memory utilizing selective clearing and least recently used updating |
US5701426A (en) * | 1995-03-31 | 1997-12-23 | Bull Information Systems Inc. | Data processing system and method using cache miss address prediction and forced LRU status in a cache memory to improve cache hit ratio |
US6138213A (en) * | 1997-06-27 | 2000-10-24 | Advanced Micro Devices, Inc. | Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line |
JP3989312B2 (ja) * | 2002-07-05 | 2007-10-10 | 富士通株式会社 | キャッシュメモリ装置およびメモリ割付方法 |
US20050071564A1 (en) * | 2003-09-25 | 2005-03-31 | International Business Machines Corporation | Reduction of cache miss rates using shared private caches |
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2004
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2005
- 2005-02-18 CN CNB200580017597XA patent/CN100476756C/zh not_active Expired - Fee Related
- 2005-02-18 WO PCT/CN2005/000199 patent/WO2006000138A1/zh active Application Filing
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US5490259A (en) * | 1992-07-22 | 1996-02-06 | Hitachi, Ltd. | Logical-to-real address translation based on selective use of first and second TLBs |
US6754776B2 (en) * | 2001-05-17 | 2004-06-22 | Fujitsu Limited | Method and system for logical partitioning of cache memory structures in a partitoned computer system |
CN1499382A (zh) * | 2002-11-05 | 2004-05-26 | 华为技术有限公司 | 廉价冗余磁盘阵列***中高效高速缓存的实现方法 |
CN1607510A (zh) * | 2003-10-14 | 2005-04-20 | 国际商业机器公司 | 改善高速缓存性能的方法和*** |
Also Published As
Publication number | Publication date |
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US7627719B2 (en) | 2009-12-01 |
CN100476756C (zh) | 2009-04-08 |
JP4327669B2 (ja) | 2009-09-09 |
JP2006012006A (ja) | 2006-01-12 |
CN1961296A (zh) | 2007-05-09 |
US20070233958A1 (en) | 2007-10-04 |
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