WO2005062383A1 - Magnetic memory device - Google Patents

Magnetic memory device Download PDF

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Publication number
WO2005062383A1
WO2005062383A1 PCT/JP2003/016286 JP0316286W WO2005062383A1 WO 2005062383 A1 WO2005062383 A1 WO 2005062383A1 JP 0316286 W JP0316286 W JP 0316286W WO 2005062383 A1 WO2005062383 A1 WO 2005062383A1
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WO
WIPO (PCT)
Prior art keywords
write
line
lines
current
layer
Prior art date
Application number
PCT/JP2003/016286
Other languages
French (fr)
Japanese (ja)
Inventor
Joichiro Ezaki
Yuji Kakinuma
Keiji Koga
Shigekazu Sumita
Original Assignee
Tdk Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Tdk Corporation filed Critical Tdk Corporation
Priority to PCT/JP2003/016286 priority Critical patent/WO2005062383A1/en
Priority to AU2003289435A priority patent/AU2003289435A1/en
Publication of WO2005062383A1 publication Critical patent/WO2005062383A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices

Definitions

  • the present invention relates to a magnetic memory device including a storage cell including a magnetoresistive element and capable of recording and reading information.
  • Magnetic random access memory (hereinafter referred to as "
  • MR AM Magnetic Random Access Memory
  • This MRAM is configured by arranging memory cells composed of magnetoresistive elements having two ferromagnetic layers in a matrix. In each of these storage cells, the magnetization of each ferromagnetic layer of the magnetoresistive effect generator is set to be parallel or anti-parallel along the axis of easy magnetization in accordance with the binary information of “0” and “1”. The information is stored. In this case, in the magnetoresistance effect-generating body, the resistance value in a specific direction differs depending on whether the magnetization direction of each ferromagnetic layer is parallel or antiparallel. Therefore, information is read from the memory cell by detecting a difference in resistance value corresponding to information as a change in current or voltage. Because it operates on such a principle, it is important for MRAM that the rate of change in resistance be as large as possible in order to perform stable writing / reading.
  • GMR Giant Magneto-Resistive
  • GMR- MR AM is a coercive force difference type (pseudo spin valve type; Pseudo Spin) Valve type) and exchange bias type (spin valve; Spin Valve type).
  • a coercive force difference type MR AM is composed of a GMR element that is formed by laminating two ferromagnetic layers and a nonmagnetic layer sandwiched between them, and utilizes the difference in coercive force between the two ferromagnetic layers. Reading and writing of information is performed.
  • the exchange bias type MRAM includes two ferromagnetic layers each including a fixed layer having a fixed magnetization direction and a free layer having a magnetization direction changed by an external magnetic field.
  • the magnetization of the fixed layer is stably fixed by antiferromagnetic coupling with the antiferromagnetic layer with the nonmagnetic layer interposed therebetween.
  • the resistance change rate of each type of GMR element is about 6 to 8% for the coercive force difference type element with a laminated structure of (NiFe / Cu / Co), and (PtMn / CoF It is about 10% even in the exchange bias type device having the laminated structure of e / Cu / CoFe). For this reason, a read output in which a resistance difference is a difference between a current and a voltage has not yet been sufficiently obtained, and it is said that it is difficult to improve storage capacity and access speed.
  • TMR-MRAM Tunneling Magneto-Resistive
  • MR Tunneling Magneto-Resistive
  • TMR-MRAM tunneling Magneto-Resistive
  • TMR-MRAM is easier to achieve higher output than GMR-MRAM, and is expected to improve storage capacity and access speed.
  • a semiconductor device such as a MOS field effect transistor (MSFET).
  • TMR-MRAM information is written by changing the magnetization direction of a ferromagnetic layer using a current magnetic field induced by a current flowing through a conductor. Therefore, the binary information is stored corresponding to the relative magnetization direction (parallel or antiparallel) between the ferromagnetic layers.
  • a method is adopted in which a current is passed through the insulating layer in a direction perpendicular to the layer surface to detect a tunnel current value or a tunnel resistance. In this case, a difference in the relative magnetization direction (parallel or antiparallel) between the ferromagnetic layers appears as a difference in the output current value or the cell resistance value.
  • TMR elements in parallel on the data line and arrange semiconductor elements for selection corresponding to each TMR element, or to arrange for each data line.
  • semiconductor element a MOSFET configured by short-circuiting between the gate and the drain of the MOSFET, a pn junction diode, a Schottky diode, and the like are used.
  • TMR elements are arranged in a matrix using row data lines and column data lines, and a selection semiconductor element is arranged for each data line.
  • the structure having the best characteristic in terms of power consumption efficiency at the time of reading is a structure in which a semiconductor element for selection is arranged for each TMR element.
  • a semiconductor element for selection is arranged for each TMR element.
  • noise caused by the variation cannot be ignored.
  • the SZN ratio of the output voltage of the memory cell is only a few dB. May not be possible.
  • a commonly used method is to compare the output voltage V of one selected memory cell with a reference voltage Vref and differentially amplify the difference voltage Vsig.
  • the purpose of differential amplification is The first is to remove noise generated in the data line pair to which the storage cell is connected.
  • the second is to remove the output voltage offset due to the characteristic variation of the semiconductor element for driving the sense well or selecting the cell. That is.
  • the circuit for generating the reference voltage Vref is realized by a circuit using a dummy cell or a semiconductor element, and the characteristics of the semiconductor element exist between this circuit and the storage cell. Is impossible in principle.
  • a method has been adopted in which a memory cell is constituted by a pair of TMR elements and the output from the pair of TMR elements is differentially amplified.
  • writing is performed so that the magnetization directions of the magneto-sensitive layers of the paired TMR elements are always antiparallel to each other. That is, in one TMR element, writing is performed complementarily so that the magnetization of the free layer and the magnetization of the free layer are parallel to each other, and the magnetization of both layers is antiparallel to each other in the other TMR element.
  • differentially amplifying the output and reading it out common-mode noise is removed and the S / N ratio is improved.
  • Such a differential amplification type circuit configuration is disclosed in, for example, JP-A-2001-236781, JP-A-2001-266567, and a document (ISSCC 2000 Digest paper TA7.2).
  • the first TMR element and the second TMR element that constitute a storage cell are: One end of each is separately connected to a pair of first and second data lines, and the other end is connected to a bit line via the same cell selecting semiconductor element.
  • the word line is connected to a semiconductor element for cell selection.
  • the first data line and the second data line are kept at the same potential, and a potential difference is applied between the bit line and the first and second data lines to obtain the first data line. This is performed by outputting a difference value of the amount of current flowing through the second data line.
  • Japanese Patent Application Laid-Open No. 2000-2737759 discloses that the effect of a demagnetizing field at the end of a free layer is reduced by introducing a closed magnetic circuit structure into a storage cell, thereby stabilizing the magnetization.
  • a technique for causing this to occur is disclosed.
  • the memory cell disclosed in the publication includes a stacked fixed layer, insulating layer, and free layer, and a closed magnetic circuit layer.
  • the closed magnetic path layer promotes the magnetization reversal of the free layer and also contributes to the stabilization of the magnetization against the external leakage magnetic field. Therefore, miniaturization is possible in this memory cell.
  • the publication also proposes that the write line be bent to reduce the minimum period of the write line for high integration. Note that a similar wiring structure is also disclosed in Japanese Patent Application Laid-Open No. 2002-289708.
  • the inventor of the present application has a problem that in this magnetic memory device, further miniaturization is difficult due to a configuration that requires a pair of write lines and a pair of read lines for one TMR element. I noticed the existence of a point.
  • the present invention has been made in view of a serious problem, and it is an object of the present invention to provide a magnetic memory device that can reduce the common mode noise, improve the SZN ratio, improve the write efficiency, and reduce the size of a memory cell. Aim.
  • the magnetic memory device includes a plurality of first lines each having a pair of lines connected in parallel with one end connected to each other via a switch element that shifts between a conductive state and a non-conductive state.
  • a plurality of write lines each intersecting with each of the first write lines
  • a second write line, and each of the first write lines is disposed at each intersection of each line of the first write lines and the second write line, and each of the first write lines is
  • An annular magnetic layer configured to be penetrated by the line and the second write line; a magnetic sensing layer in each of the annular magnetic layers; and a surface disposed on the surface of the magnetic sensing layer.
  • a stacked body including a magnetoresistive effect-generating body and configured to allow a current to flow in a direction perpendicular to the stacked surface; and the second writing lines arranged in parallel with and corresponding to the plurality of second writing lines, respectively.
  • a plurality of read lines electrically connected to the annular magnetic layer, the first write line and the second write line being parallel to each other at the intersection. And penetrates the annular magnetic layer at the parallel portion, and is connected to one of the first write lines.
  • the two magnetic magnetic layers and the two magnetoresistive effect members provided at the respective intersections between the pair of lines and the one second write line.
  • Each of the lines of the first write line is electrically connected to a back side of a surface of the laminate provided in the annular magnetic layer, through which the respective line passes, in contact with the annular magnetic layer. It is connected to the.
  • the term “parallel to each other” in the present invention includes a manufacturing error range of ⁇ 10 °.
  • each of the storage cells includes, when the switch element is in the conductive state, a write current flowing through each line of the first write line and the second write line via the switch element.
  • Information is stored by changing the magnetization direction of the magneto-sensitive layer according to a magnetic field generated by a write current flowing through the first write line when the switch element is in the non-conductive state. The stored information is read based on the magnitude of each read current flowing through each of the lines, the laminate, the annular magnetic layer, and the read line.
  • each of the first write lines is connected to a first current drive circuit that supplies the write current and a sense amplifier circuit that supplies a write current flowing through each line of the first write line.
  • each of the second write lines is connected to a second current drive circuit that supplies the write current flowing through the second write line.
  • each line of the first write line is connected to a read line (read bit line).
  • the number of lines (current supply lines) to be formed inside can be reduced. Therefore, the structure can be simplified, and as a result, the magnetic memory device can be miniaturized, and the manufacturing can be facilitated, and the productivity can be sufficiently improved.
  • the first write line is constituted by a pair of lines, information stored in the storage cell can be read by the differential amplifier circuit based on a difference between the amounts of current flowing through each line. Therefore, even if the resistance value of the magnetoresistive element or the resistance value of each line varies, it is possible to keep the fluctuation of the read current in each line within a certain range in accordance with the total current value. it can.
  • each line and the second write line are surrounded by the annular magnetic layer, so that each line and the second write line are surrounded. Due to the write current flowing through both write lines, the magnetic flux generated around each line and the second write line can be confined in the closed magnetic path composed of each annular magnetic layer, so that the leakage flux As a result, it is possible to significantly reduce the adverse effect on adjacent storage cells. Therefore, the magnetic memory device can be further miniaturized. '' Brief description of the drawings
  • FIG. 1 is a block diagram showing an overall configuration of a magnetic memory device according to the present invention.
  • FIG. 2 is a block diagram mainly showing a configuration of a storage cell group of the magnetic memory device shown in FIG.
  • FIG. 3 is a cross-sectional view showing a specific configuration of the memory cell shown in FIG.
  • FIG. 4 is a main part showing the configuration of a storage cell in the magnetic memory device shown in FIG. It is a perspective view.
  • FIG. 5 is a circuit diagram of the sense amplifier circuit, Y-direction current drive circuit, constant current circuit, and switch circuit shown in FIG.
  • FIG. 6 is a voltage-current characteristic diagram for explaining the operation of the switch circuit.
  • FIG. 7 is a circuit diagram showing paths of respective write currents when information “0” and “1” are recorded in the memory cells respectively in the circuit diagram shown in FIG.
  • FIG. 8 is a cross-sectional view of the memory cell shown in FIG. 3 for explaining the operation when writing “0” to the memory cell.
  • FIG. 9 is a cross-sectional view of the memory cell shown in FIG. 3 for explaining the operation when writing “1” to the memory cell.
  • FIG. 10 is a circuit diagram of another switch S1 included in the switch circuit 59.
  • FIG. 11 is a circuit diagram of another switch S2 included in the switch circuit 59.
  • FIG. 12 is a circuit diagram of another switch S3 included in the switch circuit 59.
  • FIG. 13 is a block diagram showing a configuration of another magnetic memory device including another storage cell group, and a configuration of a storage cell forming another storage cell group.
  • FIG. 14 is a circuit diagram of a sense amplifier circuit of another magnetic memory device shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • the magnetic memory device M includes an address buffer 51, a data buffer 52, a control logic unit 53, a storage cell group 54, and a Y-direction drive control circuit unit 5. 6, an X-direction drive control circuit section 58 and a switch circuit 59 are provided.
  • the address buffer 51 has external address input terminals AO to A20, and drives the address signals taken in from the external address input terminals AO to A20 via the Y-direction address line 57 in the Y-direction.
  • the signal is output to the circuit section 56 and to the X-direction drive control circuit section 58 via the X-direction address line 55.
  • the data buffer 52 has external data terminals D0 to D7, an input buffer 52A, and an output buffer 52B.
  • the data buffer 52 is connected to the control logic section 53 via a control signal and a line 53A.
  • the input buffer 52A is connected to the X-direction drive control circuit 58 through the X-direction write data bus 60, and is connected to the Y-direction write data bus 61 through the Y-direction write data bus 61. It is connected to the direction drive control circuit section 56.
  • the input buffer 52A generates a data signal XDin and a reference signal XRef based on the data signals input via the external data terminals DO to D7, and sends them to the X-direction drive control circuit 58.
  • each of the reference signals XRef and YRef is an inverted signal of each data signal XDin and YDin.
  • the output buffer 52 B is connected to the Y-direction drive control circuit 56 via the Y-direction read data bus 62.
  • the input buffer 52A and the output buffer 52B operate according to a control signal input from the control logic unit 53 via a control signal line 53A.
  • the control logic unit 53 includes an input terminal CS and an input terminal WE, and controls the operations of the data buffer 52, the Y-direction drive control circuit unit 56, and the X-direction drive control circuit unit 58. More specifically, the control logic unit 53 includes an input buffer 52 A and an output buffer based on a chip select signal input via the input terminal CS and a write enable signal input via the input terminal WE. In addition to deciding which of 5 2 B is to be activated, a control signal for operating the input buffer 52 A and the output buffer 52 B is generated according to this decision, and the control signal line 53 A is connected. Via And outputs it to the data buffer 52. Further, the control logic section 53 generates a read selection signal Sr and a write selection signal Sw based on the chip select signal and the write enable signal, and outputs them to the respective drive control circuit sections 56 and 58.
  • the memory cell group 54 includes a plurality of first lines 5a and 5b arranged side by side and arranged in the X direction (the left and right direction in the figure).
  • the write bit line 5 hereinafter, also referred to as “write bit line”
  • the respective lines 5 a, 5 b of the write bit line 5 which are arranged side by side in the Y direction (vertical direction in FIG.
  • a matrix is formed by disposing at a plurality of (orthogonal) second write lines (hereinafter, also referred to as “write word lines”) 6 and write bit lines 5 and write word lines 6 at respective intersections.
  • a plurality of storage cells (magnetic storage cells) 1 arranged in a matrix and a plurality of read lines (hereinafter, also referred to as “read word lines”) 1 2 arranged in parallel with each write word line 6 are provided. It is configured.
  • the storage cell 1 is a minimum unit for storing data in the magnetic memory device M, and includes a pair of storage elements (tunnel magnetoresistive elements) la and lb. The storage cell 1 will be described later in detail.
  • the write bit line 5 (lines 5a and 5b) and the write mode line 6 are connected to each other at each intersection (each intersecting region) at a parallel portion 1 formed so as to extend in parallel with each other. It is configured to have 0.
  • the parallel part 10 is formed by being bent each time it intersects with the writing lines f and the power lines 5a and 5b to form a rectangular wave shape. Therefore, two parallel portions 10 are formed at the intersection of one write bit line 5 and one write read line 6, and the storage elements la and 1b forming the storage cell 1 are connected to the parallel portions 1 0 is arranged for each. As shown in the figure, a pair of lines 5a and 5b of each write bit line 5 are connected to a corresponding switch S ( ⁇ ⁇ ⁇ , Sn, Sn + 1, ⁇ ) in the switch circuit 59.
  • each switch S when not particularly distinguished, it is also called “switch S”, and corresponds to “switch element” in the present invention), and one end side (lower end side in the figure) is connected to each end.
  • each switch S has one anode connected to the other power source and one power source connected to the other anode. It is composed of a pair of diodes Dl and D2 connected in parallel (parallel with opposite polarities). Based on the voltage applied to both ends, the internal state is automatically set to one of conduction state and non-conduction state. It is configured to be able to shift to.
  • the Y-direction drive control circuit 56 includes a Y-direction address decoder circuit 56 A, a sense amplifier circuit 56 B for reading, and a Y-direction current drive circuit (for writing). (A first current drive circuit according to the present invention).
  • the X-direction drive control circuit 58 includes an X-direction address decoder circuit 58 A, a constant current circuit 58 B for reading, and an X-direction current drive circuit for writing (the second The current drive circuit) has 58 C.
  • the Y-direction address decoder circuit 56A based on the address signal input via the Y-direction address line 57, as shown in FIG. Selects the bit-decoded line Y (-,-, Yn, ⁇ + 1, 1 ⁇ 2 ⁇ ) for the circuit 56C, and outputs the bit line selection signal S bi to the selected bit decode line ⁇ .
  • the X-direction address decoder circuit 58 A receives a word decode line X ( ⁇ X, X) for the X-direction current drive circuit 58 C based on the address signal input via the X-direction address line 55. m, Xm + 1, ⁇ ⁇ ⁇ ).
  • the X-direction address decoder circuit 58 Select the word decode line XR (--, XRm, XRm + 1,---). That is, the word decode line XRm is selected when the first decode line Xm is selected and the read select signal Sr is input.
  • the Y-direction current drive circuit 56C and the X-direction current drive circuit 58C perform a write operation to the storage cell group 54 (when the write selection signal Sw is input). To work. More specifically, each Y-direction current drive circuit 56C is provided for each write bit line 5, as shown in FIG.
  • each X-direction current drive circuit 58 C is connected to each write word line 6 and supplies a write current during a write operation.
  • each of the Y-direction current drive circuits 56 C and each of the X-direction current drive circuits 58 C determine the state of the input data signals XD in, YD in and the reference signals XR ef, YR ef, ie
  • a write current in a direction corresponding to the content of the information to be written to the line (“1” force, “0”) is supplied to the lines 5 a and 5 b and the write lead line 6 respectively.
  • the sense amplifier circuit 56 B and the constant current circuit 58 B operate during a read operation on the memory cell group 54.
  • the sense amplifier circuit 56 B is connected to the other end of each of the lines 5 a and 5 b (connected in parallel to the Y-directional force rent drive circuit 56 C),
  • the information stored in each storage cell 1 is read by detecting each read current (or a voltage generated based on the read current) flowing through each of the lines 5a and 5b.
  • Each constant current circuit 58B is connected to one end of the read word line 12 and connected to the storage cell group 54 via the read word line 12, and is connected to the storage cell 1 via the storage cell 1.
  • the total current value of the read current flowing through each of the lines 5a and 5b connected to the read word line 12 (read current flowing through the storage elements 1a and lb) is controlled to a constant value.
  • each memory cell 1 has an intersection (parallel portion 10) between a pair of lines 5 a and 5 b and one write gate line 6 in one write bit line 5.
  • ) are provided with two annular magnetic layers 4 a and 4 b (hereinafter, also referred to as “annular magnetic layer 4 J” when not distinguished) and a pair of magnetoresistive effect generators 20 a and 2 Ob.
  • the line 5a is configured as a storage element la
  • the line 5b is configured as a storage element 1b, as shown in FIG.
  • GMR or TMR can be used as the magnetoresistance effect generators 20a and 20b of the memory cell 1, but the memory cell 1 is configured using the TMR as an example. I have.
  • the annular magnetic layer 4a has a direction along the lamination surface of the magnetoresistive body 20a (a direction orthogonal to the laminating direction of the magnetoresistive body 20a. It is formed in an annular shape (for example, a rectangular tube shape) whose axial direction is the Y direction), and is penetrated by the parallel portion 10 of the line 5 a and the write line 6.
  • the entire upper wall of the annular magnetic layer 4a in the figure constitutes a first magnetosensitive layer 14a (a magnetosensitive layer in the present invention: a cross hatched portion).
  • the annular magnetic layer 4 is electrically insulated by the insulating film 7a disposed therein.
  • the direction of the annular magnetic layer 4b along the laminating surface of the magnetoresistive body 20b (the direction orthogonal to the laminating direction of the magnetoresistive body 2 ⁇ b; Y direction in the figure) Is formed in an annular shape (for example, a rectangular tube shape) having the axis as the axial direction, and is penetrated by the parallel portion 10 of the line 5 b and the write word line 6.
  • the entire upper wall of the annular magnetic layer 4b in the figure constitutes the first magneto-sensitive layer 14b (the magneto-sensitive layer in the present invention: a cross hatched portion).
  • the line 5b and the write lead 6 also have the insulating film 7b disposed in the annular magnetic layer 4b. As a result, they are electrically insulated from each other and from the annular magnetic layer 4b. As shown in FIG. 3, the annular magnetic layers 4a and 4b are provided on conductive layers 24a and 24b, respectively, which will be described later.
  • the magnetoresistive body 20a has a second magnetic layer (second magnetically sensitive layer) 8a, a tunnel barrier layer (nonmagnetic layer) 3a, and a first magnetic layer. 2a are laminated on the surface of the first magnetosensitive layer 14a in this order.
  • the magnetoresistive effect generator 20a together with the first magneto-sensitive layer 14a, has the TMR film S20a (this "Laminate" in the invention).
  • a current flows in a direction perpendicular to the lamination surface of the magnetoresistive body 20a (the Z direction in the figure).
  • the magnetoresistive effect-generating body 20a has a conductive stack 13a on the back side (the first magnetic layer 2a side) of the surface in contact with the annular magnetic layer 4a. It is electrically connected to a line 5a (a line 5a penetrating the annular magnetic layer 4a on which the magnetoresistance effect generator 20a is laminated).
  • the conductive deposit 13a is formed along the surface of the annular magnetic layer 4a and the write word line 6, as shown in FIG.
  • the non-conductive state is maintained.
  • the magnetoresistive body 20 b ′ has a second magnetic layer (second magnetically sensitive layer) 8 b, a tunnel barrier layer (nonmagnetic layer) 3 b,
  • the first magnetic layer 2b is laminated on the surface of the first magneto-sensitive layer 14b in this order.
  • the magnetoresistive effect generator 20b, together with the first magneto-sensitive layer 14b, is provided with a TMR film.
  • the magnetoresistive effect-generating body 20b has a conductive stack 13b on the back side (the first magnetic layer 2b side) of the surface in contact with the annular magnetic layer 4b. Is electrically connected to a line 5b (a line 5b penetrating the annular magnetic layer 4b on which the magnetoresistive body 20b is laminated).
  • the conductive stack 13b also maintains a non-conductive state with the annular magnetic layer 4b and the write lead line 6, similarly to the conductive stack 13a.
  • first free layer 14a and the second free layer 8a are magnetically exchange-coupled to each other.
  • first magnetic layer 14b and the second magnetic layer 8b are magnetically exchange-coupled with each other.
  • the magnetization directions of the first magnetic layers 2a and 2b are fixed in advance in the same direction.
  • the TMR film S20a 2 magneto-sensitive layer 8 a Is configured such that a tunnel current flows when one of the electrons passes through the tunnel barrier layer 3a and moves to the other of the two layers 2a, 8a.
  • the tunnel current changes depending on the relative angle between the spin of the first magnetic layer 2a and the spin of the second magnetosensitive layer 8a at the interface with the tunnel barrier layer 3a.
  • the resistance value is minimum, and when the spin is antiparallel, the resistance value is maximum. Become. The same applies to the TMR film S20b.
  • each of the tunnel barrier layers 3 a and 3 b is set to, for example, 0.3 nm or more and 2 nm or less. Therefore, the magnetic memory device has been increased in density and operation speed, and the MR ratio has been prevented from lowering. Further, since the TMR films S 20 a and S 20 b have a coercive force difference type structure, the coercive force of the first magnetic layers 2 a and 2 b is equal to that of the second magnetically sensitive layers 8 a and 8 b It is set to be larger than the coercive force.
  • the first magnetic 1 "green layers 2a and 2b are made of, for example, a 5 nm thick cobalt iron alloy (CoFe).
  • the first magnetic layers 2a and 2b may be made of an alloy (CoPt), a nickel-iron-cobalt alloy (NiFeCo), etc.
  • the second magnetically sensitive layers 8a and 8b For example, simple cobalt (Co), cobalt iron alloy (CoFe), cobalt platinum alloy (CoPt), nickel iron alloy (NiFe) or nickel iron covanolate alloy (N i F e C o)
  • the easy axes of the first magnetic layers 2 a and 2 b and the second magnetically sensitive layers 8 a and 8 b correspond to the first magnetic layer 2 a , 2b and the second magnetosensitive layers 8a, 8b are desirably parallel to each other in order to stabilize the magnetization directions in parallel or antiparallel with each other.
  • each of the annular magnetic layers 4 a and 4 b due to the above-described configuration, a return magnetic field is generated inside each of the lines 5 a and 5 b and the write current flowing through the parallel portion 10 in the write lead line 6. appear. This return magnetic field is reversed according to the direction of the current flowing through each of the lines 5 a and 5 b and the write guide line 6.
  • the annular magnetic layer 4 is made of, for example, nickel-iron It is composed of gold (NiFe).
  • the lines 5a and 5b and the write word line 6 are, for example, 10 nm thick titanium (T i), 10 nm thick titanium nitride (T i N), and 500 nm thick aluminum. (A 1) are sequentially laminated. Further, as shown in FIG.
  • each of the annular magnetic layers 4 a and 4 b in each memory cell 1 has a pair of Schottky diodes 76 a and 76 b (hereinafter simply referred to as “diodes 76 a and 76 b”). Is laminated on the substrate 11 on which is formed. As shown in FIG. 2, the lower surface of each storage element 1a, lb (the lower surface of each annular magnetic layer 4a, 4b) is connected to a read-out lead line through the diodes 76a, 76b. 1 2 (read word lines 1 2 arranged in parallel with the write word lines 6 penetrating the respective annular magnetic layers 4 a and 4 b).
  • each diode 76a, 76b has its anode side electrically connected to each of the annular magnetic layers 4a, 4b, and its cathode side electrically connected to the read word line 12, respectively.
  • the diode 76a is composed of a substrate 26, an epitaxy layer 25 laminated on the substrate 26, and a conductive layer 24a laminated on the epitaxy layer 25.
  • a Schottky barrier is formed between the conductive layer 24 a and the epitaxial layer 25.
  • the diode 76 b also includes a substrate 26, an epitaxy layer 25 laminated on the substrate 26, and a conductive layer 24 b laminated on the epitaxy layer 25.
  • a Schottky barrier is formed between 4 b and the epitaxial layer 25.
  • each part indicated by reference numeral 11A is formed of an insulating layer.
  • the write circuit system includes a Y-direction current drive circuit 56 C and a switch circuit 59, and uses the lines 5 a and 5 b and the write word line 6 to store data in each storage cell 1. Information can be written to the two magnetoresistive effectors 20a and 20b.
  • the Y-direction current drive circuit 56 C functions as a switch for controlling the direction of the current flowing through each of the lines 5 a and 5 b constituting the write bit and line 5, and a function of fixing the amount of the current to a constant value. It is configured to supply a stable constant current by eliminating the influence of the variation in the resistance value of each line 5a, 5b.
  • the current direction control unit 74 includes three differential switch pairs of first and second differential switch pairs 71 and 72 and a differential control circuit 73 (third differential switch pair).
  • the first differential switch pair 71 is configured to include switches Ql and Q2.
  • the switches Ql and Q2 are provided between the power supply Vcc and the end A of the line 5a and between the power supply Vcc and the end B of the line 5b, and one of them is in an on state. When the other is turned off, a current flows from one of the ends A and B from the power supply Vcc.
  • the second differential switch pair 72 is configured to include switches Q 3 and Q 4.
  • the switches Q 3 and Q 4 are provided between the end A of the line 5 a and the current control unit 75 described later, and between the end B of the line 5 b and the current control unit 75, respectively. When one of them is turned on and the other is turned off, current flows from one of the ends A,, ⁇ to the ground via the current control unit 75. Thus, when the switches Q1 and Q4 are off and the switches Q2 and Q3 are on, the potential at the end ⁇ on the line 5b side becomes a voltage close to the power supply Vcc, and the line 5 The potential at the end A on the a side becomes a voltage close to the ground potential.
  • switch Q 1 and switch Q 4 are on
  • switch Q When the switch 2 and the switch Q3 are off, the potential of the end A on the line 5a side is a voltage close to the power supply Vcc, and the potential of the end B on the line 5b side is a voltage close to the ground potential.
  • the diode D1 of the switch S shifts to the switch-on state (conduction state), and a current flows in a direction indicated by a solid line in each of the lines 5a and 5b.
  • the complementary operation of the first and second differential switch pairs 71 and 72 is controlled by the differential control circuit 73.
  • the differential control circuit 73 includes, for example, a switch Q5 whose collector is connected to a power supply Vcc via a resistor R1, and a collector which is connected to a power supply Vcc via a resistor R2 and an emitter. Is provided with a switch Q6 commonly connected to the emitter of the switch Q5, differentially senses the on / off state of the switches Q3 and Q4, and turns on the switches Q1 and Q2 based on the sensing result. Off Activates two differential switch pairs 71, 72 by controlling.
  • the switches Q1 to Q6 correspond to the transistors Q1 to Q6 in the specific circuit example of FIG.
  • a data signal line for inputting a data signal YD in is connected to a base terminal of the transistor Q3, and a reference signal line for inputting a reference signal YR ef is connected to a base terminal of the transistor Q4.
  • the current amount control unit 75 includes a switch (transistor) Q7 connected between each emitter terminal of the switches Q5 and Q6 and the grounding resistor R3, and an emitter of each of the switches Q3 and Q4.
  • the switch (transistor) Q8 connected between the terminal and the grounding resistor R4 and the bit line selection signal Sbi and the write selection signal Sw are input, the switches Q7 and Q8 are simultaneously turned on.
  • a switch (an example of an AND element) Q9 for shifting to a state is provided.
  • the current amount control unit 75 is provided on the ground side (lower potential side) with respect to each of the lines 5a and 5b, and keeps the amount of write current flowing out of each of the lines 5a and 5b at a constant value. maintain. In other words, the current control unit 75 sets a constant current for the write current flowing out of each of the lines 5a and 5b. Perform flow control.
  • the Y-direction power rent drive circuit 56 C responds to the states of the input data signal YD in and the reference signal YR ef.
  • a write current in the direction is supplied to each of the lines 5a and 5b.
  • the data signal YD in is “High” and the reference signal YR ef power S is “Low”
  • the write current in the direction indicated by the broken line in FIG. Is supplied to each line 5a, 5b
  • the data signal YD in force S “Low” and the reference signal YR e ⁇ is“ High ” writing in the direction shown by the solid line in FIG.
  • a current is supplied to each line 5a, 5b.
  • the read circuit system includes a sense amplifier circuit 56B and a constant current circuit 58B, and uses each of the lines 5a and 5b as a read line (read bit line).
  • Read current flowing through the two magnetoresistive effect generators 20a and 20b flows from the lines 5a and 5b to the magnetoresistive effect generators 20a and 20b, respectively, and flows out to the common read lead line 12) By outputting the difference value of the current, the information can be read from the storage cell 1.
  • the collector terminal is connected to the power supply Vcc via the current-voltage conversion resistors R11 and R12, respectively, and the emitter terminal is connected to each line 5a. , 5b, a pair of switches Q 11, connected to the ends A, B respectively. 1 2 and each voltage generated at both ends of each resistor R 11, R 12 based on each read current flowing through each line 5 &, 5 b (the end A, B of each line 5 a, 5 b
  • a differential amplifier circuit 70 that amplifies the potential difference between the ends A and B and outputs the amplified signal to the output buffer 52B, and a bit / ⁇ selection signal Sbi and a read selection signal Sr.
  • the switches Q13 and Q13 (an AND element as an example) for simultaneously switching the differential amplifier circuit 70 to the ON state.
  • the switches Q 11 and Q 12 correspond to the transistors Q ll and Q 12, respectively.
  • the constant current circuit 58B has a transistor whose emitter terminal is grounded via a resistor, a transistor whose collector terminal is connected to the read word line 12, and a transistor of the transistor. It consists of a pair of diodes connected in series with each other between the base terminal and the ground.
  • the constant current circuit 58B has a function of flowing the read current flowing through the read word line 12 to the ground while maintaining the read current at a constant value. Further, the constant current circuit 58B operates when the word decode line XR is selected by the X-direction address decoder circuit 58A.
  • the sense amplifier circuit 56 B configured as described above, when the pair of switches Q 11 and Q 12 and the differential amplifier circuit 70 are in operation, the pair of switches Q 11 and Q 1 Since a signal of the same potential is applied to each base terminal of 2, the respective emitter terminals have substantially the same potential.
  • the voltage applied to each of the diodes D1, D2 of the switch S connected to one end of each of the lines 5a, 5b is equal to the voltage of the diode. Lower than V f (forward voltage). Therefore, both diodes Dl and D2 are maintained in the switch-off state (non-conduction state). As a result, the switch S prevents the read current from flowing between the lines 5a and 5b.
  • the first magnetic layers 2a and 2b of the pair of magnetoresistive effectors 20a and 2Ob have the magnetic field in a fixed direction (both in FIGS. 8 and 9). (Rightward), but the second magnetosensitive layers 8a and 8b are magnetized in directions antiparallel to each other. Therefore, in the magnetoresistive effect manifesters 20a and 2Ob, each combination of the magnetization directions of the first magnetic layers 2a and 2b and the second magnetosensitive layers 8a and 8b is Inevitably (parallel, antiparallel) force ⁇ (antiparallel, parallel).
  • the address buffer 51 inputs and amplifies the voltage of the address signal input to the external address input terminals AO to A20, and transmits the signal via the X-direction address line 55 and the Y-direction address line 57.
  • the Y-direction address decoder circuit 56A selects one of the bit-decode # springs ( ⁇ , ⁇ , ⁇ , ⁇ + 1, ⁇ , ⁇ ) based on the input address signal.
  • the X-direction address decoder circuit 58 ⁇ selects one of the word decode lines X ( ⁇ ⁇ ⁇ , Xm, Xm + 1, ⁇ ⁇ ⁇ ) based on the input address signal. Further, the control logic unit 53 generates a write selection signal Sw based on the chip select signal and the write enable signal, and outputs it to the drive control circuit units 56, 58. As a result, one of the X-direction current drive circuits 58 C and one of the Y-direction current drive circuits 56 are selected as driving targets. In the selected Y-direction current drive circuit 56C, the bit decode line Y is selected and becomes the high level, and the write selection signal Sw also becomes the high level, and the switch Q9 shown in FIG. As a result, a High level voltage is applied to the base terminals of the switches Q7 and Q8 via the switches Q7 and Q8, so that the switches Q7 and Q8 are turned on.
  • the input buffer 52A of the data buffer 52 generates a data signal XDin and a reference signal XRef based on the data signal input through the external data terminals D0 to D7, and outputs a current in the X direction.
  • the data signal YDin and the reference signal YRef are generated and output to the Y-direction current drive circuit 56C.
  • the Y-direction current drive circuit 56C and the X-direction current drive circuit 58C which are selected as the drive targets, are oriented in accordance with the information to be written, with the respective lines 5a and 5b and the write word line. Supply write current to 6.
  • the Y-direction current drive circuit selected as the drive target Information is stored in the memory cell 1 provided at the intersection (parallel portion 10) of the write bit line 5 and the write word line 6 connected to the 56 C and X direction current drive circuits 58 C, respectively. It is memorized.
  • a write current in a direction shown by a broken line is supplied to the write bit line 5 (lines 5 a and 5 b) and the write gate line 6 so that As an example, binary information “0” is stored.
  • the portion (parallel portion 10) of the write word line 6 that passes through the storage element 1a is directed from the near side to the far side (in the + Y direction) of the drawing.
  • a write current flows, and a write current also flows in the same direction in line 5a.
  • a write current flows in a portion (parallel portion 10) of the write word line 6 passing through the storage element 1 b from the back side of the paper to the front (in the Y direction), and the line 5 b
  • the write current also flows in the same direction.
  • a return magnetic field in the clockwise direction is generated inside the annular magnetic layer 4a as shown in FIG.
  • a return magnetic field in the counterclockwise direction is generated inside the annular magnetic layer 4b.
  • the magnetization directions of the first magneto-sensitive layer 14 a and the second magneto-sensitive layer 8 a become the + X direction
  • the magnetization direction of the second magnetosensitive layer 8b becomes the 1X direction. Therefore, as shown in the figure, in the storage element 1a, the magnetization direction of the second magneto-sensitive layer 8a and the magnetization direction of the first magnetic layer 2a are matched (become parallel).
  • the magnetization direction of the second magnetically sensitive layer 8b and the magnetization direction of the first magnetic layer 2b are opposite (antiparallel). As a result, information “0” is stored in the storage cell 1.
  • the write current in the direction shown by the solid line is supplied to the write bit lines 5 (lines 5 a and 5 b) and the write Binary information “1” is stored.
  • the write current is applied to the portion of the write word line 6 passing through the storage element 1a so that the write current is directed from the back side of the paper to the front side (in the Y direction).
  • the write current also flows in the same direction on the line 5a.
  • the portion of the write word line 6 that passes through the storage element 1 b extends from the near side to the far side of the page (+ Y
  • the write current flows in the same direction, and the write current also flows in the same direction on the line 5b.
  • the magnetization direction of the second magnetically sensitive layer 8a and the magnetization direction of the first magnetic layer 2a are opposite (antiparallel).
  • the magnetization direction of the second magneto-sensitive layer 8b and the magnetization direction of the first magnetic layer 2b are parallel (become parallel).
  • information for example, “1” is stored in the storage cell 1.
  • a Y-direction address decoder circuit 56 A which has input an address signal via an address buffer 51, selects one of a plurality of bit-decoded lines Y based on the address signal, and The bit line selection signal S bi is output to the sense amplifier circuit 56B. Further, the control logic section 53 outputs the read selection signal Sr to the sense amplifier circuit 56.B and the X-direction address decoder circuit 58A. Next, the sense amplifier to which the bit line selection signal Sbi and the read selection signal Sr are input In the circuit 56B, the switches Q11 and Q12 are turned on, and the differential amplifier circuit 70 operates.
  • the sense amplifier circuit 56B applies the power supply Vcc to the connected lines 5a and 5b via the resistors Rll and R12.
  • the lines 5a and 5b and the first magnetic layers 2a and 2b are electrically connected to each other through the conductive stacks 13a and 13b, respectively.
  • the first magnetic layers 2a and 2b have substantially the same positive potential via the conductive stacks 13a and 13b.
  • the X-direction address decoder circuit 58A to which the read selection signal Sr and the address signal are input via the address buffer 51, receives one of the plurality of code decode lines XR based on the address signal.
  • the write bit line 5 (each line 5 a, 5 b), each TMR film S 20 a, S 20 b, each annular magnetic layer 4 a, 4 b, and read A read current flows through the lead lines 1 and 2.
  • each of the storage elements 1 a and lb in the storage cell 1 one is maintained in a low resistance state and the other is maintained in a high resistance state in accordance with the value of stored information, and the read current flowing through the storage cell 1 is maintained. Is maintained at a constant value by the constant current circuit 58B. Therefore, the read current flowing through one of the storage elements la and 'lb is large, and the read current flowing through the other is small. For example, in the state of the storage cell 1 shown in FIG.
  • the respective magnetization directions of the first magnetic layer 2a and the second magnetosensitive layer 8a are parallel, and the first direction in the storage element 1b is The magnetization directions of the magnetic layer 2b and the second magnetosensitive layer 8b are antiparallel. Therefore, as a result of the storage element 1a being in the low resistance state and the storage element 1b being in the high resistance state, the read current flowing through the storage element 1a is large, and the read current flowing through the storage element 1b is reduced.
  • the respective magnetization directions of the first magnetic layer 2a and the second magnetosensitive layer 8a in each of the storage elements 1a and 1b are as shown in FIG.
  • the differential amplifier circuit ⁇ 0 generates a voltage difference between the voltages generated at both ends of the resistors R11 and R12 in accordance with the read current flowing through the lines 5a and 5b. (Which is also the difference between the amounts of read currents flowing through the lines 5a and 5b), the information (binary information) stored in the storage cell 1 is obtained.
  • the output buffer 52B outputs information input via the sense amplifier circuit 56B to the external data terminals DO to D7.
  • each of the lines 5 a and 5 b of the write bit line 5 is configured to be usable as a read line (read bit line).
  • the number of lines (current supply lines) to be formed can be reduced. Therefore, the structure can be simplified, and as a result, the magnetic memory device M can be miniaturized, and the manufacturing can be facilitated, and the productivity can be sufficiently improved.
  • the write bit line 5 is composed of a pair of lines 5a and 5b, and the information stored in the storage cell 1 is differentially amplified based on the difference between the currents flowing through the lines 5a and 5b.
  • each line 5a , 5b can always be kept within a certain range according to the total current value.
  • a stable differential output can be output from the sense amplifier circuit 56B, so that the information stored in the storage cell 1 can be stably read.
  • the lines 5 a and 5 b forming the write bit line 5 are provided.
  • the second write line 6 is surrounded by the annular magnetic layers 4 a and 4 b, so that the write current flowing through both the lines 5 a and 5 b and the second write line 6 causes Since the magnetic flux generated around each of the lines 5a and 5b and the write word line 6 can be confined in the closed magnetic path composed of the annular magnetic layers 4a and 4b, the generation of leakage magnetic flux is sufficiently reduced. Can As a result, the adverse effect on adjacent storage cells can be significantly reduced. Therefore, the magnetic memory device M can be further miniaturized.
  • each switch S of the switch circuit 59 is configured by connecting a pair of diodes D 1 and D 2 in parallel with opposite polarities has been described, as in switch S 1 shown in FIG. , Multiple
  • each transistor is driven by the data signal YDin and the reference signal YRef to turn on / off at the same timing as the switches Q3 and Q4 in the Y-direction current drive circuit 56C. Turn off.
  • both transistors are turned on during the write operation by driving each transistor with the write selection signal Sw.
  • a switch can be configured by using an FET (field effect transistor) in place of each transistor of the switch S2, and a switch can be configured by using one equalizer MO SFET in place of each transistor of the switch S3. Can also be configured.
  • the sense amplifier circuit 56 shown in FIG. 14 is configured by omitting the switches Ql1 and Q12 from the sense amplifier circuit 56B of the magnetic memory device M.
  • a configuration using the storage cell group 54A having the configuration shown in FIG. 13 can be adopted. Note that the same components as those of the memory cell group 54 and the sense amplifier circuit 56 B are denoted by the same reference numerals, and a duplicate explanation is given. The description is omitted. In this case, the other ends of the lines 5a and 5b are connected to the respective resistors R11 and R12 of the sense amplifier circuit 86B (the differential amplifier circuit 70) as shown in FIG. (Base of each transistor). Also, as shown in FIG.
  • the constant current circuit 58B is configured to be selected by the same bit decode line Y as the corresponding Y-direction current drive circuit 56C.
  • the magnetic memory device Ml includes, in the same manner as the magnetic memory device M, each write mode line 6 and the X-directional force drive circuit 58C connected to each write mode line 6. Have. In this magnetic memory device Ml, information is written to each storage cell 1 by the same write operation as that of the magnetic memory device M.
  • the Y-direction address decoder circuit 56A selects one bit decode line Y based on the address signal.
  • the X-direction address decoder circuit 58A selects one word decode line X (the read word line 12 in the figure).
  • the transistors 85a and 85b connected to the selected word decode line X (read word line 12) shift to the ON state, and at the same time, the sense amplifier selected by the bit decode line ⁇ .
  • a current is supplied from the circuit 86B to the write bit line 5 (lines 5a and 5b) connected to the sense amplifier circuit 86B, and the corresponding constant current circuit 58B operates.
  • a read current flows through storage cell 1 arranged at the intersection of write bit line 5 and word decode line X (read word line 12).
  • the binary information stored in the storage cell 1 is read.
  • each of the second magnetically sensitive layers 8a and 8b is provided together with the first magnetically sensitive layers 14a and 14b of the annular magnetic layer 4.
  • the second magnetic sensing layer 8a, 8b is omitted, and the first magnetic sensing layer 14a, 14a of the annular magnetic layer 4 is used as the magnetic sensing layer.
  • a storage cell configured with only 14 b Can also be adopted.
  • each first magneto-sensitive layer 14 a, 14 b of the annular magnetic layer 4 and each second magneto-sensitive layer 8 ′ a, 8 b It is also possible to configure a storage cell in which each first magnetically sensitive layer 14a, 14b and each second magnetically sensitive layer 8a, 8b are antiferromagnetically coupled. Also, an example in which the present invention is applied to a storage cell in which the TMR films S 20 a and S 20 b have a coercive force difference structure has been described. It goes without saying that the present invention can be applied. Industrial applicability
  • each of the lines constituting the first write line is used as another read line (read bit line), and the stacked body, the annular magnetic layer, and the read line (read line) are used.
  • read bit line By reading the information stored in the recording cell based on the magnitude of each read current flowing through each line of the first write line via the word line), an independent read line (read word line) becomes unnecessary. can do. Therefore, the configuration of the magnetic memory device can be simplified, and a magnetic memory device that can be miniaturized and easily manufactured is realized.

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Abstract

A magnetic memory device comprising an annular magnetic layer arranged at the intersections of lines (5a, 5b) and a write word line (6) connected through a switch (S), wherein the write lines (5, 6) penetrate the annular magnetic layer at a parallel part (10), and a memory cell (1) comprises two annular magnetic layers arranged at the intersections of the lines (5a, 5b) and the write word line (6) and two magnetoresistive effect exhibiting bodies (20a, 20b). According to the arrangement, number of current supply lines can be decreased and scaling-down of a magnetic memory device can be realized.

Description

糸田: »  Itoda: »
磁気メモリデバイス  Magnetic memory device
技術分野 Technical field
この発明は、 磁気抵抗効果発現体を含む記憶セルを備えて情報の記録および読 出が可能に構成された磁気メモリデバイスに関するものである。 背景技術  The present invention relates to a magnetic memory device including a storage cell including a magnetoresistive element and capable of recording and reading information. Background art
この種の磁気メモリデバイスとして、 磁気ランダムアクセスメモリ （以下、 「 Magnetic random access memory (hereinafter referred to as "
MR AM： Magnetic Random Access Memory」 ともいう） が知られている。 この MR AMは、 2つの強磁性層を備えた磁気抵抗効果発現体で構成された記憶セル をマトリクス状に配列して構成されている。 この各記憶セルでは、 「0」 および 「 1」 の 2値情報に対応させて磁気抵抗効果発現体の各強磁性層の磁化を磁化容 易軸に沿って平行または反平行な状態とすることで情報が記憶される。 この場合 、 磁気抵抗効果発現体では、 各強磁性層の磁化方向が平行か反平行かによつて特 定方向の抵抗値が異なる。 したがって、 情報に対応させた抵抗値の違いを電流ま たは電圧の変化として検出することにより、 記憶セルから情報が読み出される。 このような原理で動作することから、 MR AMでは、 安定した書き込み/読み出 しを行うために抵抗変化率ができるだけ大きいことが重要である。 MR AM: Magnetic Random Access Memory). This MRAM is configured by arranging memory cells composed of magnetoresistive elements having two ferromagnetic layers in a matrix. In each of these storage cells, the magnetization of each ferromagnetic layer of the magnetoresistive effect generator is set to be parallel or anti-parallel along the axis of easy magnetization in accordance with the binary information of “0” and “1”. The information is stored. In this case, in the magnetoresistance effect-generating body, the resistance value in a specific direction differs depending on whether the magnetization direction of each ferromagnetic layer is parallel or antiparallel. Therefore, information is read from the memory cell by detecting a difference in resistance value corresponding to information as a change in current or voltage. Because it operates on such a principle, it is important for MRAM that the rate of change in resistance be as large as possible in order to perform stable writing / reading.
現在実用化されている MR AMは、 巨大磁気抵抗効果 （GMR： Giant Magnet o-Resistive ) を利用したものである。 GM Rとは、 2つの磁性層を磁化容易軸 が平行であるように配設したときに、 これらの各層の磁化方向が、 磁化容易軸に 沿って平行となる場合に抵抗ィ直が最小となり、 反平行の場合に最大となる現象で ある。 この GMR素子を用いた MR AM (以下、 「GMR— MR AM」 ともいう ) としては、 例えば米国特許第 5 3 4 3 4 2 2号公報に開示された技術が知られ ている。  The MRAM currently in practical use utilizes the Giant Magneto-Resistive (GMR). GMR means that when two magnetic layers are arranged so that their easy axes of magnetization are parallel to each other, when the magnetization directions of these layers are parallel to each other along the easy axis of magnetization, the resistance is minimized. This is the maximum phenomenon in the case of antiparallel. As an MR AM using the GMR element (hereinafter, also referred to as “GMR—MR AM”), for example, a technique disclosed in US Pat. No. 5,344,422 is known.
GMR— MR AMとしては、 保磁力差型 （擬似スピンバルブ型； Pseudo Spin Valve型） と、 交換バイアス型 （スピンバルブ； Spin Valve型） とが存在する。 保磁力差型の MR AMは、 GMR素子が 2つの強磁性層とそれらの間に挟まれた 非磁性層とを積層して構成され、 2つの強磁性層の保磁力の差を利用して情報の 書き込みノ読み出しが行われる。 また、 交換バイアス型の MR AMは、 2つの強 磁性層が、 磁化方向が固定されている固定層、 および外部磁界によって磁化方向 が変化する自由層を備えて構成されている。 この場合、 固定層は、 非磁性層を挟 んで反強磁性層と反強磁性結合させることにより、 磁化が安定して固定される。 それぞれの型の GMR素子の抵抗変化率は、 （N i F e/C u/C o) の積層構 造をとる保磁力差型の素子では約 6〜8%、 (P tMn/C o F e/C u/C o F e) の積層構造をとる交換バイアス型の素子でも 10%程度である。 そのため 、 抵抗差を電流または電圧の差とする読み出し出力は、 未だ十分に得られておら ず、 記憶容量やアクセス速度を改善するのは難しいとされている。 GMR- MR AM is a coercive force difference type (pseudo spin valve type; Pseudo Spin) Valve type) and exchange bias type (spin valve; Spin Valve type). A coercive force difference type MR AM is composed of a GMR element that is formed by laminating two ferromagnetic layers and a nonmagnetic layer sandwiched between them, and utilizes the difference in coercive force between the two ferromagnetic layers. Reading and writing of information is performed. In addition, the exchange bias type MRAM includes two ferromagnetic layers each including a fixed layer having a fixed magnetization direction and a free layer having a magnetization direction changed by an external magnetic field. In this case, the magnetization of the fixed layer is stably fixed by antiferromagnetic coupling with the antiferromagnetic layer with the nonmagnetic layer interposed therebetween. The resistance change rate of each type of GMR element is about 6 to 8% for the coercive force difference type element with a laminated structure of (NiFe / Cu / Co), and (PtMn / CoF It is about 10% even in the exchange bias type device having the laminated structure of e / Cu / CoFe). For this reason, a read output in which a resistance difference is a difference between a current and a voltage has not yet been sufficiently obtained, and it is said that it is difficult to improve storage capacity and access speed.
その点、 強磁性トンネル効果 (丁 MR： Tunneling Magneto-Resistive ) を利 用した MRAM (以下、 「TMR— MRAM」 ともいう） では、 抵抗変化率を格 段に大きくすることができる。 ここで、 TMRとは、 極薄の絶縁層を挟んで積層 された 2つの強磁性層 （磁化方向が固定された固定層と、 磁化方向が変化可能な 感磁層 （すなわち自由層） ) において、 互いの磁化方向の相対角度により絶縁層 を流れるトンネル電流が変化する現象である。 すなわち、 磁化方向が平行のとき にトンネル電流が最大 （セルの抵抗値が最小） となり、 反平行のときにトンネル 電流が最小 （セルの抵抗 が最大） となる。 この原理により、 TMR素子には、 抵抗変化率が 40%以上にも及ぶものがある。  In that regard, the MRAM utilizing the ferromagnetic tunneling effect (MR: Tunneling Magneto-Resistive) (hereinafter also referred to as “TMR-MRAM”) can greatly increase the resistance change rate. Here, TMR refers to two ferromagnetic layers (a fixed layer with a fixed magnetization direction and a magneto-sensitive layer (that is, a free layer) with a variable magnetization direction) stacked with an extremely thin insulating layer interposed therebetween. This is a phenomenon in which the tunnel current flowing through the insulating layer changes depending on the relative angle between the magnetization directions. That is, when the magnetization directions are parallel, the tunnel current is maximum (cell resistance is minimum), and when antiparallel, the tunnel current is minimum (cell resistance is maximum). Due to this principle, some TMR elements have a resistance change rate of over 40%.
また、 TMR素子の抵抗が高いために、 MOS型電界効果トランジスタ （M〇 S FET) などの半導体デバイスと組み合わせた場合のマッチングが取り易いと されている。 以上の利点から、 TMR—MRAMは、 GMR— MRAMと比較し て、 高出力化が容易であり、 記憶容量やアクセス速度の向上が期待されている。 このような TMR— MRAMとしては、 米国特許第 5629922号公報、 特開 平 9一 9 1 9 4 9号公報に開示された技術などが知られている。 In addition, the high resistance of the TMR element makes it easy to match when combined with a semiconductor device such as a MOS field effect transistor (MSFET). Because of the above advantages, TMR-MRAM is easier to achieve higher output than GMR-MRAM, and is expected to improve storage capacity and access speed. As such a TMR-MRAM, US Pat. No. 5,629,922, A technique disclosed in Japanese Patent Application Laid-Open No. 9-191949 is known.
このような T MR—MR AMでは、 情報の書き込みについては、 導線に流す電 流によって誘導する電流磁界を利用して強磁性層の磁化方向を変化させる方式が 採用されている。 したがって、 2値情報は、 強磁性層間の相対的な磁化方向 （平 行または反平行） に対応して記憶される。 また、 記憶情報の読み出しについては 、 絶縁層に対して、 層面に垂直方向に電流を流し、 トンネル電流値若しくはトン ネル抵抗を検出する方法が採用されている。 この場合、 強磁性層間の相対的な磁 化方向 （平行または反平行） の違いが、 出力電流値またはセル抵抗値の差として 現れる。  In such TMR-MRAM, information is written by changing the magnetization direction of a ferromagnetic layer using a current magnetic field induced by a current flowing through a conductor. Therefore, the binary information is stored corresponding to the relative magnetization direction (parallel or antiparallel) between the ferromagnetic layers. For reading stored information, a method is adopted in which a current is passed through the insulating layer in a direction perpendicular to the layer surface to detect a tunnel current value or a tunnel resistance. In this case, a difference in the relative magnetization direction (parallel or antiparallel) between the ferromagnetic layers appears as a difference in the output current value or the cell resistance value.
また、 セルアレイ構造としては、 データ線上に複数の TMR素子を並列接続し たうえで、 選択用の半導体素子を、 各々の TMR素子に対応させて配置するもの やデータ線毎に配置するものが提案されている。 また、 半導体素子には、 MO S F E T、 F E Tのゲート ' ドレイン間を短絡して構成されるダイオード、 p n接 合ダイオード、 およびショットキーダイオード等が用いられている。 また、 行デ ータ線および列データ線を用いて TMR素子をマトリクス状に配置し、 データ線 毎に選択用の半導体素子を配設したものも提案されている。  In addition, as cell array structure, it is proposed to connect multiple TMR elements in parallel on the data line and arrange semiconductor elements for selection corresponding to each TMR element, or to arrange for each data line. Have been. Further, as the semiconductor element, a MOSFET configured by short-circuiting between the gate and the drain of the MOSFET, a pn junction diode, a Schottky diode, and the like are used. In addition, a proposal has been made in which TMR elements are arranged in a matrix using row data lines and column data lines, and a selection semiconductor element is arranged for each data line.
このうち、 読み出し時の消費電力効率の面で最も優れた特性を有しているのは 、 各々の TMR素子に対して選択用の半導体素子を配置する構造である。 ただし 、 各半導体素子の特性にばらつきが生じている場合、 それに起因する雑音が無視 できない。 加えて、 各データ線に結合した雑音、 センスアンプの特性のばらつき による雑音、 電源回路から回り込む周辺回路の雑音も考慮した場合、 記憶セルの 出力電圧の S ZN比は、 数 d B程度にしかならない可能性がある。  Among them, the structure having the best characteristic in terms of power consumption efficiency at the time of reading is a structure in which a semiconductor element for selection is arranged for each TMR element. However, when the characteristics of each semiconductor element vary, noise caused by the variation cannot be ignored. In addition, considering the noise coupled to each data line, the noise due to the variation in the characteristics of the sense amplifier, and the noise of peripheral circuits wrapping around from the power supply circuit, the SZN ratio of the output voltage of the memory cell is only a few dB. May not be possible.
そのため、 読み出し出力の S /N比を向上すべく、 TMR—MR AMのセルァ レイには、 以下のような改良がなされてきた。  Therefore, the following improvements have been made to the TMR-MRAM cell array in order to improve the S / N ratio of the read output.
よく用いられるのは、 選択した一つの記憶セルの出力電圧 Vを参照電圧 Vref と比較し、 その差分電圧 Vsig を差動増幅する方法である。 差動増幅の目的は、 第 1に、 記憶セルが接続されるデータ線対に生じる雑音を除去することであり、 第 2に、 センス泉駆動用またはセル選択用の半導体素子の特性ばらつきによる出 力電圧のオフセットを除去することである。 しかしながら、 参照電圧 Vref の発 生回路はダミーセルや半導体素子を用いた回路によって実現され、 この回路と記 憶セルとの間でも半導体素子の特性ばらつきが存在するため、 出力電圧のオフセ ットを完全に除去することは原理的に不可能である。 A commonly used method is to compare the output voltage V of one selected memory cell with a reference voltage Vref and differentially amplify the difference voltage Vsig. The purpose of differential amplification is The first is to remove noise generated in the data line pair to which the storage cell is connected. The second is to remove the output voltage offset due to the characteristic variation of the semiconductor element for driving the sense well or selecting the cell. That is. However, the circuit for generating the reference voltage Vref is realized by a circuit using a dummy cell or a semiconductor element, and the characteristics of the semiconductor element exist between this circuit and the storage cell. Is impossible in principle.
このため、 1対の TMR素子によって記憶セルを構成して、 これらの対をなす TMR素子からの出力を差動増幅する方法も採用されている。 この方法において は、 対をなす TMR素子それぞれの感磁層の磁化方向が、 常に互いに反平行とな るように書き込みされる。 すなわち、 一方の TMR素子では感磁層の磁化と固定 層の磁化が平行で、 他方の TMR素子では両層の磁化が互いに反平行となるよう に相補的に書き込みを行い、 2つの TMR素子の出力を差動増幅して読み出すこ とによって同相雑音を除去して、 S/N比を向上させるというものである。 その ような差動増幅型の回路構成は、 特開 2001— 236781号公報、 特開 20 01-266567号公報および文献 （ISSCC 2000 Digest paper TA7.2 ) など に開示されている。  For this reason, a method has been adopted in which a memory cell is constituted by a pair of TMR elements and the output from the pair of TMR elements is differentially amplified. In this method, writing is performed so that the magnetization directions of the magneto-sensitive layers of the paired TMR elements are always antiparallel to each other. That is, in one TMR element, writing is performed complementarily so that the magnetization of the free layer and the magnetization of the free layer are parallel to each other, and the magnetization of both layers is antiparallel to each other in the other TMR element. By differentially amplifying the output and reading it out, common-mode noise is removed and the S / N ratio is improved. Such a differential amplification type circuit configuration is disclosed in, for example, JP-A-2001-236781, JP-A-2001-266567, and a document (ISSCC 2000 Digest paper TA7.2).
具体的には、 特開 200 1— 236781号公報ゃ特開 2001— 26656 7号公報に記載されている技術では、 記憶セルを構成する第 1の TMR素子およ び第 2の TMR素子は、 それぞれの一端が一対の第 1、 第 2のデータ線に別々に 接続され、 他端が共に同一のセル選択用の半導体素子を介してビット線に接続さ れるようになっている。 また、 ワード線はセル選択用の半導体素子に接続されて いる。 この場合、 情報の読み出しについては、 第 1のデータ線と第 2のデータ線 とを等電位に保ちつつ、 ビット線と第 1および第 2のデータ線との間に電位差を 与えて、 第 1および第 2のデータ線を流れる電流量の差分値を出力とすることで 行われている。  Specifically, in the technology described in Japanese Patent Application Laid-Open No. 2001-236781 and Japanese Patent Application Laid-Open No. 2001-266657, the first TMR element and the second TMR element that constitute a storage cell are: One end of each is separately connected to a pair of first and second data lines, and the other end is connected to a bit line via the same cell selecting semiconductor element. The word line is connected to a semiconductor element for cell selection. In this case, when reading information, the first data line and the second data line are kept at the same potential, and a potential difference is applied between the bit line and the first and second data lines to obtain the first data line. This is performed by outputting a difference value of the amount of current flowing through the second data line.
一方、 MR AMにおいては、 近年、 書き込み効率の向上を目的としたセル構造 も提案されてきている。 例えば、 特開 2 0 0 1— 2 7 3 7 5 9号公報には、 記憶 セルに閉磁路構造を導入することにより、 自由層の末端における反磁界の影響を 低減させて、 その磁化を安定させる技術が開示されている。 同公報に開示されて いる記憶セルは、 積層された固定層、 絶縁層および自由層と、 閉磁路層とを備え ている。 この場合、 閉磁路層は、 自由層の磁化反転を促進すると共に、 外部漏洩 磁界に対する磁化の安定化にも寄与する。 したがって、 この記憶セルでは微細化 が可能となる。 また、 同公報では、 書込線を曲折して書込線の最小周期を低減す ることによって高集積化させることも提案されている。 なお、 同様の配線構造は 、 特開 2 0 0 2 - 2 8 9 8 0 7号公報においても提示されている。 On the other hand, in recent years, the cell structure of MRAM has been Have also been proposed. For example, Japanese Patent Application Laid-Open No. 2000-2737759 discloses that the effect of a demagnetizing field at the end of a free layer is reduced by introducing a closed magnetic circuit structure into a storage cell, thereby stabilizing the magnetization. A technique for causing this to occur is disclosed. The memory cell disclosed in the publication includes a stacked fixed layer, insulating layer, and free layer, and a closed magnetic circuit layer. In this case, the closed magnetic path layer promotes the magnetization reversal of the free layer and also contributes to the stabilization of the magnetization against the external leakage magnetic field. Therefore, miniaturization is possible in this memory cell. The publication also proposes that the write line be bent to reduce the minimum period of the write line for high integration. Note that a similar wiring structure is also disclosed in Japanese Patent Application Laid-Open No. 2002-289708.
したがって、 特開 2 0 0 1— 2 3 6 7 8 1号公報等に開示された構成、 つまり 1対の TMR素子によって記憶セルを形成すると共に、 これらの対をなす TMR 素子からの出力を差動増幅する構成と、 特開 2 0 0 1— 2 7 3 7 5 9号公報等に 開示された閉磁路層を備える構成とを組み合わせることにより、 同相雑音を除去 して S /N比を向上させると共に、 書き込み効率を向上させつつ記憶セルを微細 化可能な磁気メモリデバイスを実現し得ると考えられる。 発明の開示  Therefore, the configuration disclosed in Japanese Patent Application Laid-Open No. 2000-236781, or the like, that is, a memory cell is formed by a pair of TMR elements, and the outputs from these pairs of TMR elements are compared. Combining the dynamic amplification configuration with the configuration having a closed magnetic circuit layer disclosed in Japanese Patent Application Laid-Open No. 2001-2737559 removes common-mode noise and improves the S / N ratio. In addition, it is considered that a magnetic memory device capable of miniaturizing a memory cell while improving write efficiency can be realized. Disclosure of the invention
しかしながら、 本願の発明者は、 この磁気メモリデバイスでは、 1つの TMR 素子に対して一対の書込線および一対の読出線が必要となる構成に起因してさら なる微細化が困難であるという問題点の存在に気付いた。  However, the inventor of the present application has a problem that in this magnetic memory device, further miniaturization is difficult due to a configuration that requires a pair of write lines and a pair of read lines for one TMR element. I noticed the existence of a point.
本発明は、 力かる問題点に鑑みてなされたもので、 同相雑音を除去して S ZN 比を向上させると共に書き込み効率を向上させつつ記憶セルを微細化し得る磁気 メモリデバイスを提供することを主目的とする。  SUMMARY OF THE INVENTION The present invention has been made in view of a serious problem, and it is an object of the present invention to provide a magnetic memory device that can reduce the common mode noise, improve the SZN ratio, improve the write efficiency, and reduce the size of a memory cell. Aim.
この発明に係る磁気メモリデバイスは、 導通状態および非導通状態のレ、ずれか に移行するスィツチ素子を介して互いの一端側が接続されて並設された一対の線 路を有する複数の第 1の書込線と、 前記各第 1の書込線とそれぞれ交差する複数 の第 2の書込線と、 前記各第 1の書込線の各線路と前記第 2の書込線との各交差 部分にそれぞれ配設されると共に当該各第 1の書込線の各線路と当該第 2の書込 線とによつて貫かれるように構成された環状磁性層と、 前記各環状磁性層におけ る感磁層およぴ当該感磁層の表面に配設された磁気抵抗効果発現体を含んで積層 面に垂直な方向に電流が流れるように構成された積層体と、 前記複数の第 2の書 込線にそれぞれ並設されると共に対応する当該第 2の書込線によつて貫かれる前 記環状磁性層に電気的に接続された複数の読出線とを備え、 前記第 1の書込線お よび前記第 2の書込線は前記交差部分において互いに平行になるように形成され ると共に当該平行に形成された部位において前記環状磁性層を貫通し、 1つの前 記第 1の書込線における前記一対の線路と 1つの前記第 2の書込線との前記各交 差部分に配設された 2つの前記環状磁性層および 2つの前記磁気抵抗効果発現体 を備えて 1つの記憶セルが構成され、 前記各第 1の書込線の各線路は、 当該各線 路が貫通する前記環状磁性層に配設された前記積層体における当該環状磁性層に 接触する面の背面側にそれぞれ電気的に接続されている。 なお、 本発明にいう 「 互いに平行」 とは、 製造上の誤差範囲 ± 1 0 ° を含んでいる。 The magnetic memory device according to the present invention includes a plurality of first lines each having a pair of lines connected in parallel with one end connected to each other via a switch element that shifts between a conductive state and a non-conductive state. A plurality of write lines each intersecting with each of the first write lines A second write line, and each of the first write lines is disposed at each intersection of each line of the first write lines and the second write line, and each of the first write lines is An annular magnetic layer configured to be penetrated by the line and the second write line; a magnetic sensing layer in each of the annular magnetic layers; and a surface disposed on the surface of the magnetic sensing layer. A stacked body including a magnetoresistive effect-generating body and configured to allow a current to flow in a direction perpendicular to the stacked surface; and the second writing lines arranged in parallel with and corresponding to the plurality of second writing lines, respectively. A plurality of read lines electrically connected to the annular magnetic layer, the first write line and the second write line being parallel to each other at the intersection. And penetrates the annular magnetic layer at the parallel portion, and is connected to one of the first write lines. The two magnetic magnetic layers and the two magnetoresistive effect members provided at the respective intersections between the pair of lines and the one second write line. Each of the lines of the first write line is electrically connected to a back side of a surface of the laminate provided in the annular magnetic layer, through which the respective line passes, in contact with the annular magnetic layer. It is connected to the. The term “parallel to each other” in the present invention includes a manufacturing error range of ± 10 °.
この場合、 前記各記憶セルは、 前記スィッチ素子が前記導通状態のときに、 当 該スィツチ素子を介して前記第 1の書込線の各線路を流れる書込電流および前記 第 2の書込線を流れる書込電流によって生ずる磁界に応じて前記感磁層の磁化方 向が変化することで情報を記憶し、 かつ、 前記スィッチ素子が前記非導通状態の ときに、 前記第 1の書込線の各線路、 前記積層体、 前記環状磁性層および前記読 出線を流れる各読出電流の大小に基づいて前記記憶している情報が読み出される ように 成されている。  In this case, each of the storage cells includes, when the switch element is in the conductive state, a write current flowing through each line of the first write line and the second write line via the switch element. Information is stored by changing the magnetization direction of the magneto-sensitive layer according to a magnetic field generated by a write current flowing through the first write line when the switch element is in the non-conductive state. The stored information is read based on the magnitude of each read current flowing through each of the lines, the laminate, the annular magnetic layer, and the read line.
また、 前記各第 1の書込線は、 前記書込電流を供給する第 1のカレントドライ ブ回路および前記各第 1の書込線の各線路を流れる書込電流を供給するセンスァ ンプ回路に接続され、 前記各第 2の書込線は、 当該第 2の書込線を流れる前記書 込電流を供給する第 2のカレントドライブ回路に接続されて構成されている。 この磁気メモリデバイスでは、 第 1の書込線の各線路を読出線 （読出ビット線Further, each of the first write lines is connected to a first current drive circuit that supplies the write current and a sense amplifier circuit that supplies a write current flowing through each line of the first write line. And each of the second write lines is connected to a second current drive circuit that supplies the write current flowing through the second write line. In this magnetic memory device, each line of the first write line is connected to a read line (read bit line).
) としても使用可能に構成したことにより、 内部に形成すべき線路 （電流供給線 路） の本数を低減することができる。 したがって、 構造を簡略化できる結果、 磁 気メモリデバイスを微細化できると共に、 製造が容易となって生産性を十分に向 上させることができる。 また、 第 1の書込線を一対の線路で構成したことにより 、 各線路を流れる電流量の差分に基づいて記憶セルに記憶された情報を差動増幅 回路で読み出す構成にすることができる。 したがって、 磁気抵抗効果発現体の抵 抗値や、 各線路の抵抗値がばらついていたとしても、 各線路の各々における読出 電流のぶれを総電流値に応じて常に一定の範囲内に抑え込むことができる。 この ため、 差動増幅回路から安定した差動出力を出力できる結果、 記憶セルに記憶さ れた情報を安定して読み出すことができる。 さらに、 記憶セルが配設される各線 路および第 2の書込線の交差部分において、 各線路および第 2の書込線を環状磁 性層で取り囲むようにしたことにより、 各線路および第 2の書込線の双方を流れ る書込電流によつ 1：各線路および第 2の書込線の周囲に生じる磁束を各環状磁性 層からなる閉磁路内に閉じ込めることができるため、 漏れ磁束の発生を十分に低 減することができる結果、 隣接する記憶セルへの悪影響を大幅に低減することが できる。 したがって、 磁気メモリデバイスのさらなる微細化を可能とすることが できる。 ' 図面の簡単な説明 ), The number of lines (current supply lines) to be formed inside can be reduced. Therefore, the structure can be simplified, and as a result, the magnetic memory device can be miniaturized, and the manufacturing can be facilitated, and the productivity can be sufficiently improved. In addition, since the first write line is constituted by a pair of lines, information stored in the storage cell can be read by the differential amplifier circuit based on a difference between the amounts of current flowing through each line. Therefore, even if the resistance value of the magnetoresistive element or the resistance value of each line varies, it is possible to keep the fluctuation of the read current in each line within a certain range in accordance with the total current value. it can. As a result, a stable differential output can be output from the differential amplifier circuit, so that the information stored in the storage cell can be read stably. Furthermore, at the intersection of each line on which the memory cell is provided and the second write line, each line and the second write line are surrounded by the annular magnetic layer, so that each line and the second write line are surrounded. Due to the write current flowing through both write lines, the magnetic flux generated around each line and the second write line can be confined in the closed magnetic path composed of each annular magnetic layer, so that the leakage flux As a result, it is possible to significantly reduce the adverse effect on adjacent storage cells. Therefore, the magnetic memory device can be further miniaturized. '' Brief description of the drawings
図 1は、 本発明に係る磁気メモリデバイスの全体構成を示すプロック図である 図 2は、 図 1に示した磁気メモリデバイスの記憶セル群の構成を主として表す ブロック図である。  FIG. 1 is a block diagram showing an overall configuration of a magnetic memory device according to the present invention. FIG. 2 is a block diagram mainly showing a configuration of a storage cell group of the magnetic memory device shown in FIG.
図 3は、 図 4に示した記憶セルの具体的構成を示す断面図である。  FIG. 3 is a cross-sectional view showing a specific configuration of the memory cell shown in FIG.
図 4は、 図 1に示した磁気メモリデバイスにおける記憶セルの構成を示す要部 斜視図である。 FIG. 4 is a main part showing the configuration of a storage cell in the magnetic memory device shown in FIG. It is a perspective view.
図 5は、 図 1に示したセンスアンプ回路、 Y方向カレントドライブ回路、 定電 流回路、 およびスィッチ回路の回路図である。  FIG. 5 is a circuit diagram of the sense amplifier circuit, Y-direction current drive circuit, constant current circuit, and switch circuit shown in FIG.
図 6は、 スィツチ回路の動作を説明するための電圧一電流特性図である。 図 7は、 図 5に示した回路図において情報 「0」 および 「1」 を記憶セルにそ れぞれ記録する際の各書込電流の経路を表す回路図である。  FIG. 6 is a voltage-current characteristic diagram for explaining the operation of the switch circuit. FIG. 7 is a circuit diagram showing paths of respective write currents when information “0” and “1” are recorded in the memory cells respectively in the circuit diagram shown in FIG.
図 8は、 図 3に示した記憶セルにおいて、 記憶セルに 「0」 を書き込む際の動 作を説明するための記憶セルの断面図である。  FIG. 8 is a cross-sectional view of the memory cell shown in FIG. 3 for explaining the operation when writing “0” to the memory cell.
図 9は、 図 3に示した記憶セルにおいて、 記憶セルに 「1」 を書き込む際の動 作を説明するための記憶セルの断面図である。  FIG. 9 is a cross-sectional view of the memory cell shown in FIG. 3 for explaining the operation when writing “1” to the memory cell.
図 1 0は、 スィッチ回路 5 9を構成する他のスィッチ S 1の回路図である。 図 1 1は、 スィツチ回路 5 9を構成する他のスィツチ S 2の回路図である。 図 1 2は、 スィツチ回路 5 9を構成する他のスィツチ S 3の回路図である。 図 1 3は、 他の記憶セル群を備えた他の磁気メモリデバイスの構成、 および他 の記憶セル群を構成する記憶セルの構成を示すプロック図である。  FIG. 10 is a circuit diagram of another switch S1 included in the switch circuit 59. FIG. 11 is a circuit diagram of another switch S2 included in the switch circuit 59. FIG. 12 is a circuit diagram of another switch S3 included in the switch circuit 59. FIG. 13 is a block diagram showing a configuration of another magnetic memory device including another storage cell group, and a configuration of a storage cell forming another storage cell group.
図 1 4は、 図 1 3に示した他の磁気メモリデバイスのセンスアンプ回路の回路 図である。 発明を実施するための最良の形態  FIG. 14 is a circuit diagram of a sense amplifier circuit of another magnetic memory device shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明に係る磁気メモリデバイスについて、 図面を参照して詳細に説明 する。  Hereinafter, a magnetic memory device according to the present invention will be described in detail with reference to the drawings.
(磁気メモリデバイスの構成の説明）  (Description of configuration of magnetic memory device)
まず、 図 1〜図 6を参照して、 本発明に係る磁気メモリデバイス Mの構成につ いて説明する。  First, the configuration of a magnetic memory device M according to the present invention will be described with reference to FIGS.
図 1に示すように、 磁気メモリデバイス Mは、 アドレスバッファ 5 1、 データ バッファ 5 2、 制御ロジック部 5 3、 記憶セル群 5 4、 Y方向駆動制御回路部 5 6、 X方向駆動制御回路部 5 8およびスィツチ回路 5 9を備えている。 As shown in FIG. 1, the magnetic memory device M includes an address buffer 51, a data buffer 52, a control logic unit 53, a storage cell group 54, and a Y-direction drive control circuit unit 5. 6, an X-direction drive control circuit section 58 and a switch circuit 59 are provided.
アドレスバッファ 5 1は、 外部アドレス入力端子 A O〜A 2 0を備え、 この外 部ァドレス入力端子 A O〜A 2 0から取り込んだァドレス信号を、 Y方向ァドレ ス線 5 7を介して Y方向駆動制御回路部 5 6に出力すると共に、 X方向アドレス 線 5 5を介して X方向駆動制御回路部 5 8に出力する。  The address buffer 51 has external address input terminals AO to A20, and drives the address signals taken in from the external address input terminals AO to A20 via the Y-direction address line 57 in the Y-direction. The signal is output to the circuit section 56 and to the X-direction drive control circuit section 58 via the X-direction address line 55.
データバッファ 5 2は、 外部データ端子 D 0〜D 7、 入力バッファ 5 2 Aおよ び出力バッファ 5 2 Bを備えている。 また、 データバッファ 5 2は、 制御信号,線 5 3 Aを介して制御ロジック部 5 3に接続されている。 この場合、 入力バッファ 5 2 Aは、 X方向書込用データバス 6 0を介して X方向駆動制御回路部 5 8に接 続されると共に、 Y方向書込用データバス 6 1を介して Y方向駆動制御回路部 5 6に接続されている。 また、 入力バッファ 5 2 Aは、 外部データ端子 D O〜D 7 を介して入力したデータ信号に基づいて、 データ信号 X D i nおよびリファレン ス信号 X R e f を生成して X方向駆動制御回路部 5 8に出力すると共に、 データ 信号 Y D i nおよびリファレンス信号 Y R e f を生成して Y方向駆動制御回路部 5 6に出力する。 この場合、 各リファレンス信号 X R e f , Y R e f は、 各デー タ信号 X D i n , Y D i nの反転信号である。 一方、 出力バッファ 5 2 Bは、 Y 方向読出用データバス 6 2を介して Y方向駆動制御回路部 5 6に接続されている 。 また、 入力バッファ 5 2 Aおよび出力バッファ 5 2 Bは、 制御ロジック部 5 3 から制御信号線 5 3 Aを介して入力した制御信号に従って作動する。  The data buffer 52 has external data terminals D0 to D7, an input buffer 52A, and an output buffer 52B. The data buffer 52 is connected to the control logic section 53 via a control signal and a line 53A. In this case, the input buffer 52A is connected to the X-direction drive control circuit 58 through the X-direction write data bus 60, and is connected to the Y-direction write data bus 61 through the Y-direction write data bus 61. It is connected to the direction drive control circuit section 56. Also, the input buffer 52A generates a data signal XDin and a reference signal XRef based on the data signals input via the external data terminals DO to D7, and sends them to the X-direction drive control circuit 58. At the same time, it generates a data signal YD in and a reference signal YR ef and outputs them to the Y-direction drive control circuit 56. In this case, each of the reference signals XRef and YRef is an inverted signal of each data signal XDin and YDin. On the other hand, the output buffer 52 B is connected to the Y-direction drive control circuit 56 via the Y-direction read data bus 62. The input buffer 52A and the output buffer 52B operate according to a control signal input from the control logic unit 53 via a control signal line 53A.
制御ロジック部 5 3は、 入力端子 C Sおよび入力端子 W Eを備え、 データバッ ファ 5 2、 Y方向駆動制御回路部 5 6および X方向駆動制御回路部 5 8の動作を 制御する。 具体的には、 この制御ロジック部 5 3は、 入力端子 C Sを介して入力 したチップセレクト信号、 および入力端子 WEを介して入力した書込許可信号に 基づいて、 入力バッファ 5 2 Aおよび出力バッファ 5 2 Bのいずれをアクティブ にするか否かを決定すると共に、 この決定に従って入力バッファ 5 2 Aおよび出 力バッファ 5 2 Bを作動させるための制御信号を生成して制御信号線 5 3 Aを介 してデータバッファ 5 2に出力する。 また、 制御ロジック部 5 3は、 チップセレ クト信号および書込許可信号に基づいてリード選択信号 S rおよびライト選択信 号 S wを生成して各駆動制御回路部 5 6， 5 8に出力する。 The control logic unit 53 includes an input terminal CS and an input terminal WE, and controls the operations of the data buffer 52, the Y-direction drive control circuit unit 56, and the X-direction drive control circuit unit 58. More specifically, the control logic unit 53 includes an input buffer 52 A and an output buffer based on a chip select signal input via the input terminal CS and a write enable signal input via the input terminal WE. In addition to deciding which of 5 2 B is to be activated, a control signal for operating the input buffer 52 A and the output buffer 52 B is generated according to this decision, and the control signal line 53 A is connected. Via And outputs it to the data buffer 52. Further, the control logic section 53 generates a read selection signal Sr and a write selection signal Sw based on the chip select signal and the write enable signal, and outputs them to the respective drive control circuit sections 56 and 58.
記憶セル群 5 4は、 図 2に示すように、 互いに並設された一対の線路 5 a， 5 bを有して X方向 （同図中の左右方向） に並設された複数の第 1の書込線 （以下 、 「書込ビット線」 ともいう） 5と、 Y向 （同図中の上下方向） に並設されて書 込ビット線 5の各線路 5 a , 5 bとそれぞれ交差 （直交） する複数の第 2の書込 線 （以下、 「書込ワード線」 ともいう） 6と、 書込ビット線 5および書込ワード 線 6の各交差部分に配設されることによってマトリクス状に配列された複数の記 憶セル （磁気記憶セル） 1と、 各書込ワード線 6に並設された複数の読出線 （以 下、 「読出ワード線」 ともいう） 1 2とを備えて構成されている。 記憶セル 1は 、 磁気メモリデバイス Mにおいてデータを記憶する最小単位であって、 一対の記 憶素子 （トンネル磁気抵抗効果素子） l a， l bを備えている。 なお、 記憶セル 1については後に詳述する。 書込ビット線 5 (線路 5 a , 5 b ) および書込ヮー ド線 6は、 互いの各交差部分 （交差する各領域） において、 互いに平行に延在す るように形成された平行部分 1 0を有して構成されている。 具体的には、 書込ヮ ード f泉 6力 線路 5 a， 5 bと交差する度に曲折され、 矩形波状となることで、 平行部分 1 0が形成されている。 したがって、 1つの書込ビット線 5と 1つの書 込ヮード線 6との交差部分には、 2つの平行部分 1 0が形成され、 記憶セル 1を 構成する記憶素子 l a , 1 bが平行部分 1 0のそれぞれに配置されている。 また 、 各書込ビット線 5の一対の線路 5 a， 5 bは、 同図に示すように、 スィツチ回 路 5 9内の対応するスィッチ S (■ · ■， S n， S n + 1 , · ' ·。 以下、 特に 区別しないときには 「スィッチ S」 ともいい、 本発明における 「スィッチ素子」 に対応する) の両端に互いの一端側 （同図中の下端側） がそれぞれ接続されてい る。 各スィッチ Sは、 一例として、 図 5に示すように、 一方のアノードが他方の 力ソードに、 また一方の力ソードが他方のアノードにそれぞれ接続されて互いに 並列 （逆極性で並列） に接続された一対のダイオード D l， D 2で構成されて、 両端に印加される電圧に基づいて、 導通状態と非導通状態のいずれか一方に内部 状態を自動的に移行し得るように構成されている。 As shown in FIG. 2, the memory cell group 54 includes a plurality of first lines 5a and 5b arranged side by side and arranged in the X direction (the left and right direction in the figure). Of the write bit line 5 (hereinafter, also referred to as “write bit line”) and the respective lines 5 a, 5 b of the write bit line 5 which are arranged side by side in the Y direction (vertical direction in FIG. A matrix is formed by disposing at a plurality of (orthogonal) second write lines (hereinafter, also referred to as “write word lines”) 6 and write bit lines 5 and write word lines 6 at respective intersections. A plurality of storage cells (magnetic storage cells) 1 arranged in a matrix and a plurality of read lines (hereinafter, also referred to as “read word lines”) 1 2 arranged in parallel with each write word line 6 are provided. It is configured. The storage cell 1 is a minimum unit for storing data in the magnetic memory device M, and includes a pair of storage elements (tunnel magnetoresistive elements) la and lb. The storage cell 1 will be described later in detail. The write bit line 5 (lines 5a and 5b) and the write mode line 6 are connected to each other at each intersection (each intersecting region) at a parallel portion 1 formed so as to extend in parallel with each other. It is configured to have 0. More specifically, the parallel part 10 is formed by being bent each time it intersects with the writing lines f and the power lines 5a and 5b to form a rectangular wave shape. Therefore, two parallel portions 10 are formed at the intersection of one write bit line 5 and one write read line 6, and the storage elements la and 1b forming the storage cell 1 are connected to the parallel portions 1 0 is arranged for each. As shown in the figure, a pair of lines 5a and 5b of each write bit line 5 are connected to a corresponding switch S (■ · ■, Sn, Sn + 1, 内) in the switch circuit 59. In the following, when not particularly distinguished, it is also called “switch S”, and corresponds to “switch element” in the present invention), and one end side (lower end side in the figure) is connected to each end. As an example, as shown in FIG. 5, each switch S has one anode connected to the other power source and one power source connected to the other anode. It is composed of a pair of diodes Dl and D2 connected in parallel (parallel with opposite polarities). Based on the voltage applied to both ends, the internal state is automatically set to one of conduction state and non-conduction state. It is configured to be able to shift to.
Y方向,駆動制御回路部 5 6は、 図 1に示すように、 Y方向アドレスデコーダ回 路 5 6 A、 読み出しのためのセンスアンプ回路 5 6 B、 および書き込みのための Y方向カレントドライブ回路 （本発明における第 1のカレントドライブ回路） 5 6 Cを有している。 一方、 X方向駆動制御回路部 5 8は、 X方向アドレスデコー ダ回路 5 8 A、 読み出しのための定電流回路 5 8 B、 および書き込みのための X 方向カレントドライブ回路 （本発明における第 2のカレントドライブ回路） 5 8 Cを有している。  As shown in FIG. 1, the Y-direction drive control circuit 56 includes a Y-direction address decoder circuit 56 A, a sense amplifier circuit 56 B for reading, and a Y-direction current drive circuit (for writing). (A first current drive circuit according to the present invention). On the other hand, the X-direction drive control circuit 58 includes an X-direction address decoder circuit 58 A, a constant current circuit 58 B for reading, and an X-direction current drive circuit for writing (the second The current drive circuit) has 58 C.
この場合、 Y方向アドレスデコーダ回路 5 6 Aは、 Y方向アドレス線 5 7を介 して入力したアドレス信号に基づいて、 図 2に示すように、 センスアンプ回路 5 6 Bおよび Y方向力レントドライブ回路 5 6 Cのためのビットデコ一ド線 Y ( - , -， Y n， Υ η + 1 , ■ ■ ■ ) を選択し、 選択したビットデコード線 Υにビッ ト線選択信号 S b iを出力する。 一方、 X方向ァドレスデコーダ回路 5 8 Aは、 X方向ァドレス ,線5 5を介して入力したァドレス信号に基づいて X方向カレント ドライブ回路 5 8 Cのためのワードデコード線 X (■ ■ ·， X m, Xm + 1 , ■ ■ ■ ) を選択する。 また、 X方向アドレスデコーダ回路 5 8 Αは、 アドレス信号 に基づいてヮードデコ一ド線 Xを選択した際に、 リード選択信号 S rを入力して いるときは、 定電流回路 5 8 Bのためのワードデコード線 X R ( · - ■ , X Rm ， X R m+ 1 , ■ ■ · ) を選択する。 すなわち、 ワードデコード線 X R mは、 ヮ 一ドデコ一ド線 Xmが選択されて、 かつリード選択信号 S rを入力しているとき. に選択される。 Y方向カレントドライブ回路 5 6 Cおよび X方向カレントドライ ブ回路 5 8 Cは、 同図に示すように、 記憶セノレ群 5 4に対する書込動作の際 （ラ イト選択信号 S wを入力した際） に作動する。 具体的には、 各 Y方向カレントド ライプ回路 5 6 Cは、 同図に示すように、 各書込ビット線 5毎に配設されて、 各  In this case, the Y-direction address decoder circuit 56A, based on the address signal input via the Y-direction address line 57, as shown in FIG. Selects the bit-decoded line Y (-,-, Yn, Υη + 1, 1 ■ 2 ■) for the circuit 56C, and outputs the bit line selection signal S bi to the selected bit decode line Υ. . On the other hand, the X-direction address decoder circuit 58 A receives a word decode line X (■ X, X) for the X-direction current drive circuit 58 C based on the address signal input via the X-direction address line 55. m, Xm + 1, ■ ■ ■). When the read direction signal Sr is input when the code line X is selected based on the address signal, the X-direction address decoder circuit 58 Select the word decode line XR (--, XRm, XRm + 1,---). That is, the word decode line XRm is selected when the first decode line Xm is selected and the read select signal Sr is input. As shown in the figure, the Y-direction current drive circuit 56C and the X-direction current drive circuit 58C perform a write operation to the storage cell group 54 (when the write selection signal Sw is input). To work. More specifically, each Y-direction current drive circuit 56C is provided for each write bit line 5, as shown in FIG.
L 1 線路 5 a， 5 bの各他端側に接続されると共に、 書込動作の際にスィツチ Sを介 してループ状に接続された線路 5 a， 5 bに書込電流を供給する。 これにより、 各線路 5 a , 5 bには、 書込動作の際に、 互いに逆向きの書込電流が流れること になる。 同様にして、 各 X方向カレントドライブ回路 5 8 Cは、 各書込ワード線 6に接続されて、 書込動作の際に書込電流を供給する。 この場合、 各 Y方向カレ ントドライブ回路 5 6 Cおよび各 X方向カレントドライブ回路 5 8 Cは、 入力す るデータ信号 X D i n , Y D i nおよびリファレンス信号 X R e f , Y R e f の 状態、 すなわち記憶セル 1に書き込む情報の内容 （ 「1」 力、 「0」 ） に応じた方 向の書込電流を線路 5 a， 5 bおよぴ書込ヮ一ド線 6にそれぞれ供給する。 L 1 A write current is supplied to the other ends of the lines 5a and 5b and to the lines 5a and 5b connected in a loop via the switch S during a write operation. As a result, write currents in opposite directions flow through the lines 5a and 5b during the write operation. Similarly, each X-direction current drive circuit 58 C is connected to each write word line 6 and supplies a write current during a write operation. In this case, each of the Y-direction current drive circuits 56 C and each of the X-direction current drive circuits 58 C determine the state of the input data signals XD in, YD in and the reference signals XR ef, YR ef, ie A write current in a direction corresponding to the content of the information to be written to the line (“1” force, “0”) is supplied to the lines 5 a and 5 b and the write lead line 6 respectively.
一方、 センスァンプ回路 5 6 Bおよぴ定電流回路 5 8 Bは、 記憶セル群 5 4に 対する読出動作の際に作動する。 この場合、 センスアンプ回路 5 6 Bは、 図 2に 示すように、 各線路 5 a， 5 bの他端側に接続されて （Y方向力レントドライブ 回路 5 6 Cに並列接続されて） 、 読出動作の際に各線路 5 a， 5 bを流れる各読 出電流 （または読出電流に基づいて発生する電圧） を検出することによって各記 憶セル 1に記憶されている情報を読み出す。 各定電流回路 5 8 Bは、 読出ワード' 線 1 2の一端側にそれぞれ接続されると共に、 読出ワード線 1 2を介して記憶セ ル群 5 4に接続されて、 記憶セル 1を介して読出ワード線 1 2に接続された各線 路 5 a， 5 bを流れる読出電流 （記憶素子 1 a， l bをそれぞれ流れる読出電流 ) の総電流値を一定値に制御する。  On the other hand, the sense amplifier circuit 56 B and the constant current circuit 58 B operate during a read operation on the memory cell group 54. In this case, as shown in FIG. 2, the sense amplifier circuit 56 B is connected to the other end of each of the lines 5 a and 5 b (connected in parallel to the Y-directional force rent drive circuit 56 C), At the time of the read operation, the information stored in each storage cell 1 is read by detecting each read current (or a voltage generated based on the read current) flowing through each of the lines 5a and 5b. Each constant current circuit 58B is connected to one end of the read word line 12 and connected to the storage cell group 54 via the read word line 12, and is connected to the storage cell 1 via the storage cell 1. The total current value of the read current flowing through each of the lines 5a and 5b connected to the read word line 12 (read current flowing through the storage elements 1a and lb) is controlled to a constant value.
次に、 記憶セル 1について説明する。  Next, the memory cell 1 will be described.
記憶セル 1は、 図 3， 4に示すように、 1つの書込ビット線 5における一対の 線路 5 a， 5 bと 1つの書込ヮ一ド線 6との各交差部分 （平行部分 1 0 ) に配設 された 2つの環状磁性層 4 a， 4 b (以下、 区別しないときには、 「環状磁性層 4 J ともいう） および一対の磁気抵抗効果発現体 2 0 a， 2 O bを備えて構成さ れている。 また、 記憶セル 1は、 同図に示すように、 線路 5 a側が記憶素子 l a として構成されると共に、 線路 5 b側が記憶素子 1 bとして構成されている。 こ の場合、 記憶セル 1の磁気抵抗効果発現体 2 0 a , 2 0 bとしては、 GMRまた は TMRを利用することができるが、 記憶セル 1は、 一例として、 TMRを利用 して構成されている。 As shown in FIGS. 3 and 4, each memory cell 1 has an intersection (parallel portion 10) between a pair of lines 5 a and 5 b and one write gate line 6 in one write bit line 5. ) Are provided with two annular magnetic layers 4 a and 4 b (hereinafter, also referred to as “annular magnetic layer 4 J” when not distinguished) and a pair of magnetoresistive effect generators 20 a and 2 Ob. In the storage cell 1, the line 5a is configured as a storage element la, and the line 5b is configured as a storage element 1b, as shown in FIG. In the case of, GMR or TMR can be used as the magnetoresistance effect generators 20a and 20b of the memory cell 1, but the memory cell 1 is configured using the TMR as an example. I have.
環状磁性層 4 aは、 図 3に示すように、 磁気抵抗効果発現体 2 0 aの積層面に 沿った方向 （磁気抵抗効果発現体 2 0 aの積層方向と直交する方向。 同図中の Y 方向） を軸方向とする環状 （一例として四角筒状） に形成されると共に線路 5 a および書込ヮ一ド線 6における平行部分 1 0によつて貫かれて構成されている。 この場合、 環状磁性層 4 aは、 同図中における上壁全体が第 1の感磁層 1 4 a ( 本発明における感磁層：クロスハッチを施した部分） を構成する。 また、 線路 5 aと書込ヮード線 6との間、 線路 5 aと環状磁性層 4 aとの間、 および書込ヮー ド線 6と環状磁性層 4 aとの間は、 環状磁性層 4 a内に配設された絶縁膜 7 aに よってそれぞれ電気的に絶縁されている。  As shown in FIG. 3, the annular magnetic layer 4a has a direction along the lamination surface of the magnetoresistive body 20a (a direction orthogonal to the laminating direction of the magnetoresistive body 20a. It is formed in an annular shape (for example, a rectangular tube shape) whose axial direction is the Y direction), and is penetrated by the parallel portion 10 of the line 5 a and the write line 6. In this case, the entire upper wall of the annular magnetic layer 4a in the figure constitutes a first magnetosensitive layer 14a (a magnetosensitive layer in the present invention: a cross hatched portion). In addition, between the line 5a and the write mode line 6, between the line 5a and the annular magnetic layer 4a, and between the write mode line 6 and the annular magnetic layer 4a, the annular magnetic layer 4 Each of them is electrically insulated by the insulating film 7a disposed therein.
同様にして、 環状磁性層 4 bも、 磁気抵抗効果発現体 2 0 bの積層面に沿った 方向 （磁気抵抗効果発現体 2◦ bの積層方向と直交する方向。 同図中の Y方向） を軸方向とする環状 （一例として四角筒状） に形成されると共に線路 5 bおよび 書込ワード線 6における平行部分 1 0によって貫かれて構成されている。 この場 合、 環状磁性層 4 bは、 同図中における上壁全体が第 1の感磁層 1 4 b (本発明 における感磁層：クロスハッチを施した部分） を構成する。 また、 線路 5 bおよ び書込ヮ一ド線 6も、 線路 5 aおよぴ書込ヮ一ド線 6と同様にして、 環状磁性層 4 b内に配設された絶縁膜 7 bによって、 相互間および環状磁性層 4 bとの間が それぞれ電気的に絶縁されている。 また、 環状磁性層 4 a， 4 bは、 図 3に示す ように、 後述する導電層 2 4 a， 2 4 b上にそれぞれ配設されている。  Similarly, the direction of the annular magnetic layer 4b along the laminating surface of the magnetoresistive body 20b (the direction orthogonal to the laminating direction of the magnetoresistive body 2◦b; Y direction in the figure) Is formed in an annular shape (for example, a rectangular tube shape) having the axis as the axial direction, and is penetrated by the parallel portion 10 of the line 5 b and the write word line 6. In this case, the entire upper wall of the annular magnetic layer 4b in the figure constitutes the first magneto-sensitive layer 14b (the magneto-sensitive layer in the present invention: a cross hatched portion). Similarly to the line 5a and the write lead 6, the line 5b and the write lead 6 also have the insulating film 7b disposed in the annular magnetic layer 4b. As a result, they are electrically insulated from each other and from the annular magnetic layer 4b. As shown in FIG. 3, the annular magnetic layers 4a and 4b are provided on conductive layers 24a and 24b, respectively, which will be described later.
磁気抵抗効果発現体 2 0 aは、 図 3に示すように、 第 2の磁性層 （第 2の感磁 層） 8 a、 トンネルバリァ層 （非磁性層） 3 aおよび第 1の磁性層 2 aがこの順 に第 1の感磁層 1 4 aの表面に積層されて構成されている。 この構成により、 磁 気抵抗効果発現体 2 0 aは、 第 1の感磁層 1 4 aと共に、 TMR膜 S 2 0 a (本 発明における 「積層体」 ） を構成する。 この TMR膜 S 2 0 aでは、 磁気抵抗効 果発現体 2 0 aの積層面に垂直な方向 （同図中の Z方向） に電流が流れる。 また 、 磁気抵抗効果発現体 2 0 aは、 図 4に示すように、 環状磁性層 4 aに接触する 面の背面側 （第 1の磁性層 2 a側） が導通用堆積体 1 3 aを介して線路 5 a (磁 気抵抗効果発現体 2 0 aが積層されている環状磁性層 4 aを貫通する線路 5 a ) に電気的に接続されている。 なお、 導通用堆積体 1 3 aは、 同図に示すように、 環状磁性層 4 aおよび書込ワード線 6の表面に沿って形成されるが、 環状磁性層As shown in FIG. 3, the magnetoresistive body 20a has a second magnetic layer (second magnetically sensitive layer) 8a, a tunnel barrier layer (nonmagnetic layer) 3a, and a first magnetic layer. 2a are laminated on the surface of the first magnetosensitive layer 14a in this order. With this configuration, the magnetoresistive effect generator 20a, together with the first magneto-sensitive layer 14a, has the TMR film S20a (this "Laminate" in the invention). In the TMR film S20a, a current flows in a direction perpendicular to the lamination surface of the magnetoresistive body 20a (the Z direction in the figure). As shown in FIG. 4, the magnetoresistive effect-generating body 20a has a conductive stack 13a on the back side (the first magnetic layer 2a side) of the surface in contact with the annular magnetic layer 4a. It is electrically connected to a line 5a (a line 5a penetrating the annular magnetic layer 4a on which the magnetoresistance effect generator 20a is laminated). The conductive deposit 13a is formed along the surface of the annular magnetic layer 4a and the write word line 6, as shown in FIG.
4 aおよび書込ワード線 6との間に配設された不図示の絶縁層によって、 環状磁 性層 4 aおよび書込ヮ一ド線 6とは非導通状態を維持する。 By the insulating layer (not shown) disposed between the ring magnetic layer 4a and the write word line 6, the non-conductive state is maintained.
同様にして、 磁気抵抗効果発現体 2 0 b'は、 図 3に示すように、 第 2の磁性層 (第 2の感磁層） 8 b、 トンネルバリァ層 （非磁性層） 3 bおよび第 1の磁性層 2 bがこの順に第 1の感磁層 1 4 bの表面に積層されて構成されている。 この構 成により、 磁気抵抗効果発現体 2 0 bは、 第 1の感磁層 1 4 bと共に、 TMR膜 Similarly, as shown in FIG. 3, the magnetoresistive body 20 b ′ has a second magnetic layer (second magnetically sensitive layer) 8 b, a tunnel barrier layer (nonmagnetic layer) 3 b, The first magnetic layer 2b is laminated on the surface of the first magneto-sensitive layer 14b in this order. With this configuration, the magnetoresistive effect generator 20b, together with the first magneto-sensitive layer 14b, is provided with a TMR film.
5 2 0 b (本発明における 「積層体」 ） を構成する。 この TMR膜 S 2 0 bでも 、 磁気抵抗効果発現体 2 0 bの積層面に垂直な方向に電流が流れる。 また、 磁気 抵抗効果発現体 2 0 bも、 図 4に示すように、 環状磁性層 4 bに接触する面の背 面側 （第 1の磁性層 2 b側） が導通用堆積体 1 3 bを介して線路 5 b (磁気抵抗 効果発現体 2 0 bが積層されている環状磁性層 4 bを貫通する線路 5 b ) に電気 的に接続されている。 なお、 導通用堆積体 1 3 bも導通用堆積体 1 3 aと同様に して、 環状磁性層 4 bおよび書込ヮード線 6とは非導通状態を維持する。 5 20 b (the “laminate” in the present invention). Even in the TMR film S20b, a current flows in a direction perpendicular to the laminated surface of the magnetoresistance effect generating body 20b. Also, as shown in FIG. 4, the magnetoresistive effect-generating body 20b has a conductive stack 13b on the back side (the first magnetic layer 2b side) of the surface in contact with the annular magnetic layer 4b. Is electrically connected to a line 5b (a line 5b penetrating the annular magnetic layer 4b on which the magnetoresistive body 20b is laminated). The conductive stack 13b also maintains a non-conductive state with the annular magnetic layer 4b and the write lead line 6, similarly to the conductive stack 13a.
この場合、 第 1の感磁層 1 4 aおよび第 2の感磁層 8 aは、 互いに磁気的に交 換結合している。 同様にして、 第 1の感磁層 1 4 bおよび第 2の感磁層 8 bも互 いに磁気的に交換結合している。 なお、 各第 1の磁性層 2 a， 2 bは、 磁化方向 が同一方向に予め固定されている。  In this case, the first free layer 14a and the second free layer 8a are magnetically exchange-coupled to each other. Similarly, the first magnetic layer 14b and the second magnetic layer 8b are magnetically exchange-coupled with each other. The magnetization directions of the first magnetic layers 2a and 2b are fixed in advance in the same direction.
TMR膜 S 2 0 aは、 積層面に垂直方向の電圧を第 1の磁性層 2 aと第 2の感 磁層 8 aとの間に印加したときに、 第 1の磁性層 2 aおよび第 2の感磁層 8 aの 内の一方の電子がトンネルバリア層 3 aを突き抜けて両層 2 a, 8 aの内の他方 に移動することによってトンネル電流が流れるように構成されている。 この場合 、 トンネル電流は、 トンネルバリア層 3 aとの界面部分における第 1の磁性層 2 aのスピンと第 2の感磁層 8 aのスピンとの相対的な角度によって変化する。 具 体的には、 第 1の磁性層 2 aのスピンと第 2の感磁層 8 aのスピンとが互いに平 行なときに抵抗値が最小となり、 反平行のときに抵抗値が最大となる。 なお、 T MR膜 S 20 bについても同様である。 When a voltage in the direction perpendicular to the laminated surface is applied between the first magnetic layer 2a and the second magnetosensitive layer 8a, the TMR film S20a 2 magneto-sensitive layer 8 a Is configured such that a tunnel current flows when one of the electrons passes through the tunnel barrier layer 3a and moves to the other of the two layers 2a, 8a. In this case, the tunnel current changes depending on the relative angle between the spin of the first magnetic layer 2a and the spin of the second magnetosensitive layer 8a at the interface with the tunnel barrier layer 3a. Specifically, when the spin of the first magnetic layer 2a and the spin of the second magnetically sensitive layer 8a are parallel to each other, the resistance value is minimum, and when the spin is antiparallel, the resistance value is maximum. Become. The same applies to the TMR film S20b.
また、 トンネルバリア層 3 a , 3 bは、 一例としてその厚みが 0. 3 nm以上 2 nm以下に設定されている。 したがって、 磁気メモリデバイスにおける高密度 化および動作の高速度化が図られると共に、 MR比の低下防止が図られている。 また、 TMR膜 S 20 a, S 20 bは、 保磁力差型構造に構成されているため 、 第 1の磁性層 2 a， 2 bの保磁力は第 2の感磁層 8 a， 8 bの保磁力よりも大 きくなるように設定されている。 第 1の磁 1"生層 2 a, 2 bは、 例えば、 5 nmの 厚みのコバルト鉄合金 （C o F e) で構成されている。 なお、 単体のコバルト （ C o) や、 コバルト白金合金 （C o P t) 、 ニッケル鉄コバルト合金 （N i F e C o ) 等で第 1の磁性層 2 a， 2 bを構成することもできる。 第 2の感磁層 8 a , 8 bは、 例えば、 単体のコバルト （C o) 、 コバルト鉄合金 （C o F e) 、 コ バルト白金合金 （C o P t) 、 ニッケル鉄合金 （N i F e) またはニッケル鉄コ バノレト合金 （N i F e C o) で構成することができる。 また、 第 1の磁性層 2 a ， 2 bおよび第 2の感磁層 8 a , 8 bの磁化容易軸は、 第 1の磁性層 2 a， 2 b と第 2の感磁層 8 a, 8 bとの各磁化方向を互いに平行または反平行となる状態 で安定化させるためには、 互いに平行であることが望ましい。  The thickness of each of the tunnel barrier layers 3 a and 3 b is set to, for example, 0.3 nm or more and 2 nm or less. Therefore, the magnetic memory device has been increased in density and operation speed, and the MR ratio has been prevented from lowering. Further, since the TMR films S 20 a and S 20 b have a coercive force difference type structure, the coercive force of the first magnetic layers 2 a and 2 b is equal to that of the second magnetically sensitive layers 8 a and 8 b It is set to be larger than the coercive force. The first magnetic 1 "green layers 2a and 2b are made of, for example, a 5 nm thick cobalt iron alloy (CoFe). In addition, simple cobalt (Co) or cobalt platinum is used. The first magnetic layers 2a and 2b may be made of an alloy (CoPt), a nickel-iron-cobalt alloy (NiFeCo), etc. The second magnetically sensitive layers 8a and 8b For example, simple cobalt (Co), cobalt iron alloy (CoFe), cobalt platinum alloy (CoPt), nickel iron alloy (NiFe) or nickel iron covanolate alloy (N i F e C o) The easy axes of the first magnetic layers 2 a and 2 b and the second magnetically sensitive layers 8 a and 8 b correspond to the first magnetic layer 2 a , 2b and the second magnetosensitive layers 8a, 8b are desirably parallel to each other in order to stabilize the magnetization directions in parallel or antiparallel with each other.
各環状磁性層 4 a， 4 bでは、 上述した構成により、 各線路 5 a， 5 bおよび 書込ヮード線 6における平行部分 1 0を流れる睿込電流に起因して、 その内部に 還流磁界が発生する。 この還流磁界は、 各線路 5 a , 5 bおよび書込ヮ一ド線 6 を流れる電流の向きに応じて反転する。 環状磁性層 4は、 例えば、 ニッケル鉄合 金 （N i F e ) で構成されている。 各線路 5 a， 5 bおよび書込ワード線 6は、 一例として 1 0 n m厚のチタン （T i ) と、 1 0 n m厚の窒化チタン （T i N) と、 5 0 0 n m厚のアルミニウム （A 1 ) とが順に積層されて構成されている。 また、 各記憶セル 1における各環状磁性層 4 a , 4 bは、 図 3に示すように、 一対のショットキ一ダイォード 7 6 a， 7 6 b (以下、 単に 「ダイォード 7 6 a ， 7 6 b」 ともいう。 ） が形成された基体 1 1の上に積層されている。 また、 各 記憶素子 1 a， l bの下面 （各環状磁性層 4 a， 4 bの下面） は、 図 2に示すよ うに、 このダイオード 7 6 a , 7 6 bを介して読出ヮ一ド線 1 2 (各環状磁性層 4 a , 4 bを貫通する書込ワード線 6に並設された読出ワード線 1 2 ) にそれぞ れ電気的に接続されている。 また、 各ダイオード 7 6 a， 7 6 bは、 それぞれ、 そのアノード側が各環状磁性層 4 a , 4 bに電気的に接続されると共にそのカソ ード側が読出ワード線 1 2に電気的に接続されている。 この場合、 ダイオード 7 6 aは、 図 3に示すように、 基板 2 6、 基板 2 6上に積層されたェピタキシャル 層 2 5、 およびェピタキシャル層 2 5上に積層された導電層 2 4 aを備え、 導電 層 2 4 aとェピタキシャル層 2 5との間にショットキ一障壁が形成されて構成さ れている。 同様にして、 ダイオード 7 6 bも、 基板 2 6、 基板 2 6上に積層され たェピタキシャル層 2 5、 およびェピタキシャル層 2 5上に積層された導電層 2 4 bを備え、 導電層 2 4 bとェピタキシャル層 2 5との間にショットキ一障壁が 形成されて構成されている。 なお、 同図中において、 符号 1 1 Aで示す各部位は 、 絶縁層で構成されている。 In each of the annular magnetic layers 4 a and 4 b, due to the above-described configuration, a return magnetic field is generated inside each of the lines 5 a and 5 b and the write current flowing through the parallel portion 10 in the write lead line 6. appear. This return magnetic field is reversed according to the direction of the current flowing through each of the lines 5 a and 5 b and the write guide line 6. The annular magnetic layer 4 is made of, for example, nickel-iron It is composed of gold (NiFe). The lines 5a and 5b and the write word line 6 are, for example, 10 nm thick titanium (T i), 10 nm thick titanium nitride (T i N), and 500 nm thick aluminum. (A 1) are sequentially laminated. Further, as shown in FIG. 3, each of the annular magnetic layers 4 a and 4 b in each memory cell 1 has a pair of Schottky diodes 76 a and 76 b (hereinafter simply referred to as “diodes 76 a and 76 b”). Is laminated on the substrate 11 on which is formed. As shown in FIG. 2, the lower surface of each storage element 1a, lb (the lower surface of each annular magnetic layer 4a, 4b) is connected to a read-out lead line through the diodes 76a, 76b. 1 2 (read word lines 1 2 arranged in parallel with the write word lines 6 penetrating the respective annular magnetic layers 4 a and 4 b). Each diode 76a, 76b has its anode side electrically connected to each of the annular magnetic layers 4a, 4b, and its cathode side electrically connected to the read word line 12, respectively. Have been. In this case, as shown in FIG. 3, the diode 76a is composed of a substrate 26, an epitaxy layer 25 laminated on the substrate 26, and a conductive layer 24a laminated on the epitaxy layer 25. And a Schottky barrier is formed between the conductive layer 24 a and the epitaxial layer 25. Similarly, the diode 76 b also includes a substrate 26, an epitaxy layer 25 laminated on the substrate 26, and a conductive layer 24 b laminated on the epitaxy layer 25. A Schottky barrier is formed between 4 b and the epitaxial layer 25. Note that, in the figure, each part indicated by reference numeral 11A is formed of an insulating layer.
一方、 書込回路系は、 Y方向カレントドライブ回路 5 6 Cとスィッチ回路 5 9 とを備え、 各線路 5 a， 5 bと書込ワード線 6とを使用して、 各記憶セル 1内の 2つの磁気抵抗効果発現体 2 0 a， 2 0 bに情報を書き込み可能に構成されてい る。  On the other hand, the write circuit system includes a Y-direction current drive circuit 56 C and a switch circuit 59, and uses the lines 5 a and 5 b and the write word line 6 to store data in each storage cell 1. Information can be written to the two magnetoresistive effectors 20a and 20b.
スィッチ回路 5 9の構成については、 上述したため、 Y方向カレントドライブ 回路 5 6 Cの構成とその作用について説明する。 なお、 スィッチ回路 5 9による 作用についても併せて説明する。 Since the configuration of the switch circuit 59 has been described above, the configuration and operation of the Y-direction current drive circuit 56C will be described. Note that the switch circuit 59 The operation will also be described.
Y方向カレントドライブ回路 5 6 Cは、 書込ビット,線 5を構成する各線路 5 a ， 5 bに流す電流の向きを制御するスィッチとしての機能と、 その電流量を一定 値に固定する機能とを兼ね備え、 各線路 5 a， 5 bにおける抵抗値のばらつきの 影響を排除して安定した定電流を供給するように構成されている。  The Y-direction current drive circuit 56 C functions as a switch for controlling the direction of the current flowing through each of the lines 5 a and 5 b constituting the write bit and line 5, and a function of fixing the amount of the current to a constant value. It is configured to supply a stable constant current by eliminating the influence of the variation in the resistance value of each line 5a, 5b.
これらの機能のうち、 電流方向に対する制御機能については、 図 5に示す電流 方向制御部 7 4によって実現される。 この電流方向制御部 7 4は、 第 1および第 2の差動スィツチ対 7 1， 7 2および差動制御回路 7 3 (第 3の差動スィッチ対 ) の 3つの差動スィッチ対を備えている。 ここで、 第 1の差動スィッチ対 7 1は 、 スィッチ Q l， Q 2を備えて構成されている。 スィッチ Q l， Q 2は、 電源 V c cと線路 5 aの端部 Aとの間、 電源 V c cと線路 5 bの端部 Bとの間にそれぞ れ設けられ、 いずれか一方がオン状態で、 他方がオフ状態となることで、 端部 A ， Bの一方に電源 V c cから電流を流入させる。 第 2の差動スィッチ対 7 2は、 スィッチ Q 3 , Q 4を備えて構成されている。 スィッチ Q 3， Q 4は、 線路 5 a の端部 Aと後述する電流量制御部 7 5との間、 線路 5 bの端部 Bと電流量制御部 7 5との間にそれぞれ設けられ、 いずれか一方がオン状態で、 他方がオフ状態と なることで、 端部 A, ,Βの一方から電流量制御部 7 5を介して接地に電流を流出 させる。 これにより、 スィッチ Q 1とスィッチ Q 4がオフ状態で、 スィッチ Q 2 とスィツチ Q 3がオン状態のときは、 線路 5 b側の端部 Βの電位が電源 V c cに 近い電圧となり、 線路 5 a側の端部 Aの電位が接地電位に近い電圧となる。 この 結果、 各線路 5 a , 5 bの一端側に接続されたスィッチ S (各ダイォード D 1 , D 2 ) の両端に印加される電圧がダイオードの V i (順方向電圧） を超えるため に、 各ダイォ一ド D 1， D 2が逆極性で並列に接続されることによって全体とし て図 6に示すような電圧一電流特性を有するスィッチ Sのダイォード D 2がスィ ツチオン状態 （導通状態） に移行して、 各線路 5 a， 5 bに破線で示す向きの書 込電流が流れる。 また、 スィッチ Q 1とスィッチ Q 4がオン状態で、 スィッチ Q 2とスィッチ Q 3がオフ状態のときは、 線路 5 a側の端部 Aの電位が電源 V c c に近い電圧となり、 線路 5 b側の端部 Bの電位が接地電位に近い電圧となる。 こ の結果、 逆に、 スィッチ Sのダイオード D 1がスィッチオン状態 （導通状態） に 移行して、 各線路 5 a， 5 bには実線で示す向きの電流が流れる。 このような第 1および第 2の差動スィッチ対 7 1 , 7 2の相補的な動作は、 差動制御回路 7 3 によって制御される。 この場合、 差動制御回路 7 3は、 例えば、 抵抗 R 1を介し てコレクタが電源 V c cに接続されたスィッチ Q 5と、 抵抗 R 2を介してコレク タが電源 V c cに接続されてエミッタがスィツチ Q 5のェミッタと共通接続され たスィッチ Q 6を備えて構成され、 スィッチ Q 3 , Q 4のオンノオフ状態を差動 センシングし、 そのセンシング結果に基づいてスィッチ Q 1， Q 2をオン Zオフ 制御することによって 2つの差動スィッチ対 7 1， 7 2を作動させる。 なお、 ス イッチ Q 1〜Q 6は、 図 5の具体的な回路例では、 それぞれトランジスタ Q 1〜 Q 6に対応している。 また、 トランジスタ Q 3のベース端子には、 データ信号 Y D i nが入力されるデータ信号線が接続され、 トランジスタ Q 4のベース端子に は、 リファレンス信号 Y R e f が入力されるリファレンス信号線が接続されてい る。 Among these functions, the control function for the current direction is realized by the current direction control unit 74 shown in FIG. The current direction control unit 74 includes three differential switch pairs of first and second differential switch pairs 71 and 72 and a differential control circuit 73 (third differential switch pair). I have. Here, the first differential switch pair 71 is configured to include switches Ql and Q2. The switches Ql and Q2 are provided between the power supply Vcc and the end A of the line 5a and between the power supply Vcc and the end B of the line 5b, and one of them is in an on state. When the other is turned off, a current flows from one of the ends A and B from the power supply Vcc. The second differential switch pair 72 is configured to include switches Q 3 and Q 4. The switches Q 3 and Q 4 are provided between the end A of the line 5 a and the current control unit 75 described later, and between the end B of the line 5 b and the current control unit 75, respectively. When one of them is turned on and the other is turned off, current flows from one of the ends A,, Β to the ground via the current control unit 75. Thus, when the switches Q1 and Q4 are off and the switches Q2 and Q3 are on, the potential at the end の on the line 5b side becomes a voltage close to the power supply Vcc, and the line 5 The potential at the end A on the a side becomes a voltage close to the ground potential. As a result, since the voltage applied across the switch S (each diode D 1, D 2) connected to one end of each line 5 a, 5 b exceeds the diode V i (forward voltage), Since the diodes D 1 and D 2 are connected in parallel with opposite polarities, the diode D 2 of the switch S having the voltage-current characteristic as a whole as shown in FIG. 6 is in the switch-on state (conductive state). Then, the write current flows in the direction indicated by the broken line in each of the lines 5a and 5b. Also, when switch Q 1 and switch Q 4 are on, switch Q When the switch 2 and the switch Q3 are off, the potential of the end A on the line 5a side is a voltage close to the power supply Vcc, and the potential of the end B on the line 5b side is a voltage close to the ground potential. As a result, conversely, the diode D1 of the switch S shifts to the switch-on state (conduction state), and a current flows in a direction indicated by a solid line in each of the lines 5a and 5b. The complementary operation of the first and second differential switch pairs 71 and 72 is controlled by the differential control circuit 73. In this case, the differential control circuit 73 includes, for example, a switch Q5 whose collector is connected to a power supply Vcc via a resistor R1, and a collector which is connected to a power supply Vcc via a resistor R2 and an emitter. Is provided with a switch Q6 commonly connected to the emitter of the switch Q5, differentially senses the on / off state of the switches Q3 and Q4, and turns on the switches Q1 and Q2 based on the sensing result. Off Activates two differential switch pairs 71, 72 by controlling. The switches Q1 to Q6 correspond to the transistors Q1 to Q6 in the specific circuit example of FIG. A data signal line for inputting a data signal YD in is connected to a base terminal of the transistor Q3, and a reference signal line for inputting a reference signal YR ef is connected to a base terminal of the transistor Q4. You.
一方、 各線路 5 a， 5 bを流れる書込電流に対する定電流制御機能については 、 図 5に示す電流量制御部 7 5によって実現される。 この電流量制御部 7 5は、 スィツチ Q 5， Q 6の各エミッタ端子と接地用抵抗 R 3との間に接続されたスィ ツチ （トランジスタ） Q 7と、 スィッチ Q 3 , Q 4の各ェミッタ端子と接地用抵 抗 R 4との間に接続されたスィッチ （トランジスタ） Q 8と、 ビット線選択信号 S b iおよびライ ト選択信号 S wを入力したときにスィッチ Q 7， Q 8を同時に オン状態に移行させるスィッチ （一例として AN D素子） Q 9とを備えている。 また、 電流量制御部 7 5は、 各線路 5 a , 5 bよりも接地側 （低電位側） に設け られて、 各線路 5 a , 5 bから流出する書込電流の量を一定値に維持する。 つま り、 電流量制御部 7 5は、 各線路 5 a， 5 bから流出する書込電流に対して定電 流制御を行う。 On the other hand, the constant current control function for the write current flowing through each of the lines 5a and 5b is realized by the current amount control unit 75 shown in FIG. The current amount control unit 75 includes a switch (transistor) Q7 connected between each emitter terminal of the switches Q5 and Q6 and the grounding resistor R3, and an emitter of each of the switches Q3 and Q4. When the switch (transistor) Q8 connected between the terminal and the grounding resistor R4 and the bit line selection signal Sbi and the write selection signal Sw are input, the switches Q7 and Q8 are simultaneously turned on. A switch (an example of an AND element) Q9 for shifting to a state is provided. Further, the current amount control unit 75 is provided on the ground side (lower potential side) with respect to each of the lines 5a and 5b, and keeps the amount of write current flowing out of each of the lines 5a and 5b at a constant value. maintain. In other words, the current control unit 75 sets a constant current for the write current flowing out of each of the lines 5a and 5b. Perform flow control.
以上の構成により、 Y方向力レントドライブ回路 56 Cは、 ビット線選択信号 S b iおよびライト選択信号 Swを入力したときに、 入力しているデータ信号 Y D i nとリファレンス信号 YR e f の状態に応じた向きの書込電流を各線路 5 a , 5 bに供給する。 具体的には、 Y方向カレントドライブ回路 56 Cは、 データ 信号 YD i nが 「H i g h」 で、 リファレンス信号 YR e f 力 S 「L o w」 のとき に、 図 5において破線で示す向きの書込電流を各線路 5 a， 5 bに供給し、 デー タ信号 YD i n力 S 「L o w」 で、 リファレンス信号 YR e ίが 「H i g h」 のと きに、 図 5において実線で示す向きの書込電流を各線路 5 a， 5 bに供給する。 また、 読出回路系は、 センスアンプ回路 5 6 Bと定電流回路 58 Bとを備え、 各線路 5 a, 5 bを読出線 （読出ビット線） として使用して、 各記憶セル 1内の 2つの磁気抵抗効果発現体 20 a, 20 bを流れる読出電流 （線路 5 a， 5 bか ら磁気抵抗効舉発現体 20 a， 20 bにそれぞれ流入して、 共通の読出ヮード線 1 2に流出する電流） の差分値を出力することにより、 記憶セル 1から情報を読 み出し可能に構成されている。  With the above configuration, when the bit line selection signal S bi and the write selection signal Sw are input, the Y-direction power rent drive circuit 56 C responds to the states of the input data signal YD in and the reference signal YR ef. A write current in the direction is supplied to each of the lines 5a and 5b. Specifically, when the data signal YD in is “High” and the reference signal YR ef power S is “Low”, the write current in the direction indicated by the broken line in FIG. Is supplied to each line 5a, 5b, and when the data signal YD in force S “Low” and the reference signal YR e 「is“ High ”, writing in the direction shown by the solid line in FIG. A current is supplied to each line 5a, 5b. The read circuit system includes a sense amplifier circuit 56B and a constant current circuit 58B, and uses each of the lines 5a and 5b as a read line (read bit line). Read current flowing through the two magnetoresistive effect generators 20a and 20b (flows from the lines 5a and 5b to the magnetoresistive effect generators 20a and 20b, respectively, and flows out to the common read lead line 12) By outputting the difference value of the current, the information can be read from the storage cell 1.
具体的には、 センスアンプ回路 56 Bは、 コレクタ端子がそれぞれ電流電圧変 換用の抵抗 R 1 1， R 1 2を介して電源 Vc cに接続されると共に、 ェミッタ端 子が各線路 5 a， 5 bの端部 A， Bにそれぞれ接続された一対のスィツチ Q 1 1 ， 。 1 2と、 各線路5 &， 5 bを流れる各読出電流に基づいて各抵抗 R 1 1， R 1 2の両端に発生する各電圧 （各線路 5 a， 5 bの端部 A， Bの電位） を取り込 むと共に、 端部 A， Bの電位差を増幅して出力バッファ 5 2 Bに出力する差動增 幅回路 70と、 ビット,锒選択信号 S b iおよびリード選択信号 S rを入力してい るときにスィッチ Q l l， Q 1 2、 および差動増幅回路 70を同時にオン状態に 移行させるスィッチ Q 1 3 (—例として AND素子） とを備えて構成されている 。 各スィッチ Q 1 1， Q 1 2は、 図 5の具体的な回路例では、 それぞれトランジ スタ Q l l, Q 1 2に対応している。 一方、 定電流回路 5 8 Bは、 図 2， 5に示すように、 抵抗を介してェミッタ端 子が接地されると共に、 コレクタ端子が読出ワード線 1 2に接続されたトランジ スタと、 トランジスタのベース端子と接地との間に互いに直列となるように接続 された一対のダイオードとで構成されている。 この場合、 定電流回路 5 8 Bは、 読出ワード線 1 2を流れる読出電流を一定値に維持しつつ、 接地に流出させる機 能を備えている。 また、 定電流回路 5 8 Bは、 X方向アドレスデコーダ回路 5 8 Aによってワードデコード線 X Rが選択されたときに作動する。 Specifically, in the sense amplifier circuit 56B, the collector terminal is connected to the power supply Vcc via the current-voltage conversion resistors R11 and R12, respectively, and the emitter terminal is connected to each line 5a. , 5b, a pair of switches Q 11, connected to the ends A, B respectively. 1 2 and each voltage generated at both ends of each resistor R 11, R 12 based on each read current flowing through each line 5 &, 5 b (the end A, B of each line 5 a, 5 b And a differential amplifier circuit 70 that amplifies the potential difference between the ends A and B and outputs the amplified signal to the output buffer 52B, and a bit / 锒 selection signal Sbi and a read selection signal Sr. And the switches Q13 and Q13 (an AND element as an example) for simultaneously switching the differential amplifier circuit 70 to the ON state. In the specific circuit example of FIG. 5, the switches Q 11 and Q 12 correspond to the transistors Q ll and Q 12, respectively. On the other hand, as shown in FIGS. 2 and 5, the constant current circuit 58B has a transistor whose emitter terminal is grounded via a resistor, a transistor whose collector terminal is connected to the read word line 12, and a transistor of the transistor. It consists of a pair of diodes connected in series with each other between the base terminal and the ground. In this case, the constant current circuit 58B has a function of flowing the read current flowing through the read word line 12 to the ground while maintaining the read current at a constant value. Further, the constant current circuit 58B operates when the word decode line XR is selected by the X-direction address decoder circuit 58A.
また、 このように構成されたセンスアンプ回路 5 6 Bでは、 一対のスィッチ Q 1 1， Q 1 2と差動増幅回路 7 0とが作動状態のときに、 一対のスィツチ Q 1 1 ， Q 1 2の各ベース端子に同電位の信号が印加されるため、 その各ェミッタ端子 はほぼ同電位になる。 その結果、 センスアンプ回路 5 6 Bが作動しているときに は、 各線路 5 a， 5 bの一端側に接続されたスィツチ Sの各ダイォード D 1 , D 2に印加される電圧がダイオードの V f (順方向電圧） よりも低下する。 このた め、 両ダイオード D l , D 2ともにスィッチオフ状態 （非導通状態） に維持され る。 この結果、 スィッチ Sは、 各線路 5 a， 5 b相互間においての読出電流の流 出を阻止する。  Further, in the sense amplifier circuit 56 B configured as described above, when the pair of switches Q 11 and Q 12 and the differential amplifier circuit 70 are in operation, the pair of switches Q 11 and Q 1 Since a signal of the same potential is applied to each base terminal of 2, the respective emitter terminals have substantially the same potential. As a result, when the sense amplifier circuit 56B is operating, the voltage applied to each of the diodes D1, D2 of the switch S connected to one end of each of the lines 5a, 5b is equal to the voltage of the diode. Lower than V f (forward voltage). Therefore, both diodes Dl and D2 are maintained in the switch-off state (non-conduction state). As a result, the switch S prevents the read current from flowing between the lines 5a and 5b.
(磁気メモリデバイスにおける情報の書込動作の説明）  (Explanation of information writing operation in magnetic memory device)
次に、 記憶セル 1における情報の書込動作について説明する。  Next, an operation of writing information in storage cell 1 will be described.
前提として、 記憶セル 1では、 1対の磁気抵抗効果発現体 2 0 a , 2 O bの第 1の磁性層 2 a， 2 bは、 共に磁ィヒが一定方向 （図 8， 9では共に右向き） に固 定されているが、 第 2の感磁層 8 a， 8 bは互いに反平行となる向きに磁化され る。 このため、 磁気抵抗効果発現体 2 0 a， 2 O bにおいては、 それぞれの第 1 の磁性層 2 a， 2 bと第 2の感磁層 8 a , 8 bの磁化方向の各組み合わせは、 必 ず （平行、 反平行） 力 \ (反平行、 平行） となる。 したがって、 この磁化方向の 組み合わせに 2値情報 「 0」 および 「 1」 をそれぞれ対応させて、 記憶セル 1を レ、ずれかの磁化状態にすることで、 1つの記憶セル 1に 1ビットの情報を記憶す ることができる。 なお、 各磁気抵抗効果発現体 20 a , 20 bは、 必ず一方が低 抵抗状態、 他方が高抵抗状態となって情報を記憶する。 As a premise, in the memory cell 1, the first magnetic layers 2a and 2b of the pair of magnetoresistive effectors 20a and 2Ob have the magnetic field in a fixed direction (both in FIGS. 8 and 9). (Rightward), but the second magnetosensitive layers 8a and 8b are magnetized in directions antiparallel to each other. Therefore, in the magnetoresistive effect manifesters 20a and 2Ob, each combination of the magnetization directions of the first magnetic layers 2a and 2b and the second magnetosensitive layers 8a and 8b is Inevitably (parallel, antiparallel) force \ (antiparallel, parallel). Therefore, by associating the binary information “0” and “1” with the combination of the magnetization directions, and by setting the storage cell 1 to the demagnetized state or the shifted magnetization state, one bit of information is stored in one storage cell 1. Memorize Can. It is to be noted that one of the magnetoresistive effect manifesters 20a and 20b always stores information in a low resistance state and the other in a high resistance state.
書き込み時には、 まず、 アドレスバッファ 5 1力 外部アドレス入力端子 AO 〜A 2 0に入力されるァドレス信号の電圧を取り込んで増幅し、 X方向ァドレス 線 5 5および Y方向ァドレス線 5 7を介して X方向ァドレスデコーダ回路 5 8 A および Y方向アドレスデコーダ回路 5 6 Aに出力する。 この際に、 Y方向アドレ スデコーダ回路 5 6 Aは、 入力したァドレス信号に基づいて、 ビットデコ一ド #泉 Υ ( · · · , Υη， Υη+ 1， ■ ■ · ) の一つを選択する。 同様にして、 X方向 ァドレスデコーダ回路 5 8 Αは、 入力したァドレス信号に基づいてワードデコー ド線 X (■ · ■， Xm, Xm+ 1 , · ■ ■ ) の一つを選択する。 また、 制御ロジ ック部 5 3は、 チップセレクト信号および書込許可信号に基づいてライト選択信 号 Swを生成して各駆動制御回路部 5 6， 5 8に出力する。 これにより、 X方向 カレントドライブ回路 5 8 Cの 1つおよび Y方向カレントドライブ回路 5 6じの 1つが駆動対象に選択される。 選択された Y方向カレントドライブ回路 5 6 Cで は、 そのビットデコ一ド線 Yが選択されて H i g hレベルになると共に、 ライト 選択信号 Swも H i g hレベルになり、 図 5に示すスィッチ Q 9を介して各スィ ツチ Q 7， Q 8のベース端子に H i g tレベルの電圧が印加される結果、 各スィ ツチ Q 7, Q 8が導通状態になる。  At the time of writing, first, the address buffer 51 inputs and amplifies the voltage of the address signal input to the external address input terminals AO to A20, and transmits the signal via the X-direction address line 55 and the Y-direction address line 57. Output to the direction address decoder circuit 58 A and the Y direction address decoder circuit 56 A. At this time, the Y-direction address decoder circuit 56A selects one of the bit-decode # springs (Υ, ·, Υη, Υη + 1, ■, ·) based on the input address signal. Similarly, the X-direction address decoder circuit 58Α selects one of the word decode lines X (■ · ■, Xm, Xm + 1, · ■ ■) based on the input address signal. Further, the control logic unit 53 generates a write selection signal Sw based on the chip select signal and the write enable signal, and outputs it to the drive control circuit units 56, 58. As a result, one of the X-direction current drive circuits 58 C and one of the Y-direction current drive circuits 56 are selected as driving targets. In the selected Y-direction current drive circuit 56C, the bit decode line Y is selected and becomes the high level, and the write selection signal Sw also becomes the high level, and the switch Q9 shown in FIG. As a result, a High level voltage is applied to the base terminals of the switches Q7 and Q8 via the switches Q7 and Q8, so that the switches Q7 and Q8 are turned on.
また、 データバッファ 5 2の入力バッファ 5 2 Aは、 外部データ端子 D 0〜D 7を介して入力したデータ信号に基づいて、 データ信号 XD i nおよびリファレ ンス信号 X R e f を生成して X方向カレントドライブ回路 5 8 Cに出力すると共 に、 データ信号 YD i nおよびリファレンス信号 YR e f を生成して Y方向カレ ントドライブ回路 5 6 Cに出力する。 これにより、 駆動対象に選択された Y方向 カレントドライブ回路 5 6 Cおよび X方向カレントドライブ回路 5 8 Cは、 書き 込むべき情報に応じた向きで、 各線路 5 a , 5 bおよび書込ワード線 6に書込電 流を供給する。 これにより、 駆動対象に選択された Y方向カレントドライブ回路 5 6 Cおよび X方向カレントドライプ回路 5 8 Cにそれぞれ接続されている書込 ビット線 5および書込ワード線 6の交差部分 （平行部分 1 0 ) に配設されている 記憶セル 1に情報が記憶される。 The input buffer 52A of the data buffer 52 generates a data signal XDin and a reference signal XRef based on the data signal input through the external data terminals D0 to D7, and outputs a current in the X direction. In addition to outputting to the drive circuit 58C, the data signal YDin and the reference signal YRef are generated and output to the Y-direction current drive circuit 56C. As a result, the Y-direction current drive circuit 56C and the X-direction current drive circuit 58C, which are selected as the drive targets, are oriented in accordance with the information to be written, with the respective lines 5a and 5b and the write word line. Supply write current to 6. As a result, the Y-direction current drive circuit selected as the drive target Information is stored in the memory cell 1 provided at the intersection (parallel portion 10) of the write bit line 5 and the write word line 6 connected to the 56 C and X direction current drive circuits 58 C, respectively. It is memorized.
具体的には、 図 7において、 破線で示す向きの書込電流を書込ビット線 5 (線 路 5 a， 5 b ) および書込ヮ一ド線 6に供給することにより、 記憶セル 1に一例 として 2値情報 「0」 が記憶される。 この場合、 図 8に示すように、 書込ワード 線 6の記憶素子 1 aを通過する部位 （平行部分 1 0 ) には、 紙面の手前側から奥 側に （+ Y方向へ） 向かうように書込電流が流れ、 線路 5 aにも同方向に書込電 流が流れる。 また、 書込ワード線 6の記憶素子 1 bを通過する部位 （平行部分 1 0 ) には、 紙面の奥側から手前に （一 Y方向へ） 向かうように書込電流が流れ、 線路 5 bにも同方向に書込電流が流れる。 この場合、 記憶素子 l aでは、 同図に 示すように、 環状磁性層 4 aの内部に時計回り方向の還流磁界が発生する。 一方 、 記憶素子 l bでは、 環状磁性層 4 bの内部に反時計回り方向の還流磁界が発生 する。 これにより、 記憶素子 l aでは、 第 1の感磁層 1 4 aおよび第 2の感磁層 8 aの磁化方向が + X方向となり、 記憶素子 1 bでは、 第 1の感磁層 1 4 bおよ び第 2の感磁層 8 bの磁化方向が一 X方向となる。 したがって、 同図に示すよう に、 記憶素子 1 aでは、 第 2の感磁層 8 aの磁化方向と第 1の磁性層 2 aの磁化 方向とがー致する （平行になる） 。 一方、 記憶素子 l bでは、 第 2の感磁層 8 b の磁化方向と第 1の磁性層 2 bの磁化方向とが逆になる （反平行になる） 。 この 結果、 この記憶セル 1に情報 「0」 が記憶される。  Specifically, in FIG. 7, a write current in a direction shown by a broken line is supplied to the write bit line 5 (lines 5 a and 5 b) and the write gate line 6 so that As an example, binary information “0” is stored. In this case, as shown in FIG. 8, the portion (parallel portion 10) of the write word line 6 that passes through the storage element 1a is directed from the near side to the far side (in the + Y direction) of the drawing. A write current flows, and a write current also flows in the same direction in line 5a. In addition, a write current flows in a portion (parallel portion 10) of the write word line 6 passing through the storage element 1 b from the back side of the paper to the front (in the Y direction), and the line 5 b The write current also flows in the same direction. In this case, in the storage element la, a return magnetic field in the clockwise direction is generated inside the annular magnetic layer 4a as shown in FIG. On the other hand, in the storage element lb, a return magnetic field in the counterclockwise direction is generated inside the annular magnetic layer 4b. Thereby, in the memory element la, the magnetization directions of the first magneto-sensitive layer 14 a and the second magneto-sensitive layer 8 a become the + X direction, and in the memory element 1 b, the first magneto-sensitive layer 14 b And the magnetization direction of the second magnetosensitive layer 8b becomes the 1X direction. Therefore, as shown in the figure, in the storage element 1a, the magnetization direction of the second magneto-sensitive layer 8a and the magnetization direction of the first magnetic layer 2a are matched (become parallel). On the other hand, in the memory element lb, the magnetization direction of the second magnetically sensitive layer 8b and the magnetization direction of the first magnetic layer 2b are opposite (antiparallel). As a result, information “0” is stored in the storage cell 1.
一方、 図 7において、 実線で示す向きの書込電流を書込ビット線 5 (線路 5 a ， 5 b ) およぴ書込ヮ一ド線 6に供給することにより、 記憶セル 1に一例として 2値情報 「1」 が記憶される。 この場合、 図 9に示すように、 書込ワード線 6の 記憶素子 1 aを通過する部位には、 紙面の奥側から手前側に （一 Y方向へ） 向か うように書込電流が流れ、 線路 5 aにも同方向に書込電流が流れる。 また、 書込 ワード線 6の記憶素子 1 bを通過する部位には、 紙面の手前側から奥側に （+ Y 方向へ） 向かうように書込電流が流れ、 線路 5 bにも同方向に書込電流が流れる 。 この場合、 記憶素子 l aでは、 同図に示すように、 環状磁性層 4 aの内部に反 時計回り方向の還流磁界が発生する。 一方、 記憶素子 l bでは、 環状磁性層 4 b の内部に時計回り方向の還流磁界が発生する。 これにより、 記憶素子 l aでは、 第 1の感磁層 1 4 aおよび第 2の感磁層 8 aの磁化方向が一 X方向となり、 記憶 素子 1 bでは、 第 1の感磁層 1 4 bおよび第 2の感磁層 8 bの磁化方向が + X方 向となる。 したがって、 同図に示すように、 記憶素子 l aでは、 第 2の感磁層 8 aの磁化方向と第 1の磁性層 2 aの磁化方向とが逆になる （反平行になる） 。 一 方、 記憶素子 1 bでは、 第 2の感磁層 8 bの磁化方向と第 1の磁性層 2 bの磁化 方向とがー致する （平行になる） 。 この結果、 この記憶セル 1に情報 （一例とし て 「1」 ） が記憶される。 On the other hand, in FIG. 7, the write current in the direction shown by the solid line is supplied to the write bit lines 5 (lines 5 a and 5 b) and the write Binary information “1” is stored. In this case, as shown in FIG. 9, the write current is applied to the portion of the write word line 6 passing through the storage element 1a so that the write current is directed from the back side of the paper to the front side (in the Y direction). The write current also flows in the same direction on the line 5a. In addition, the portion of the write word line 6 that passes through the storage element 1 b extends from the near side to the far side of the page (+ Y The write current flows in the same direction, and the write current also flows in the same direction on the line 5b. In this case, in the storage element la, as shown in the figure, a return magnetic field in the counterclockwise direction is generated inside the annular magnetic layer 4a. On the other hand, in the storage element lb, a return magnetic field in the clockwise direction is generated inside the annular magnetic layer 4b. Thus, in the memory element la, the magnetization directions of the first magneto-sensitive layer 14a and the second magneto-sensitive layer 8a are in the X direction, and in the memory element 1b, the first magneto-sensitive layer 14b The magnetization direction of the second magnetosensitive layer 8b is in the + X direction. Therefore, as shown in the figure, in the storage element la, the magnetization direction of the second magnetically sensitive layer 8a and the magnetization direction of the first magnetic layer 2a are opposite (antiparallel). On the other hand, in the storage element 1b, the magnetization direction of the second magneto-sensitive layer 8b and the magnetization direction of the first magnetic layer 2b are parallel (become parallel). As a result, information (for example, “1”) is stored in the storage cell 1.
この場合、 記憶素子 1 a， l bでは、 第 1の磁性層 2 a， 2 bと第 2の感磁層 8 a , 8 bとの磁化方向が平行であれば大きなトンネル電流が流れる低抵抗状態 となり、 反平行であれば小さなトンネル電流しか流れない高抵抗状態となって、 情報を記憶する。 なお、 書込ビット線 5と書込ワード線 6とで互いに逆方向に書 込電流が流れたとき、 あるいは、 どちらか一方のみに書込電流が流れたときには 、 各第 2の感磁層 8 a , 8 bの磁化方向が反転せずに、 データの書き換えは行わ れない。  In this case, in the storage element 1 a, lb, if the magnetization directions of the first magnetic layer 2 a, 2 b and the second magneto-sensitive layer 8 a, 8 b are parallel, a large tunnel current flows and a low resistance state If it is antiparallel, it will be in a high resistance state in which only a small tunnel current flows, and information will be stored. Note that when a write current flows in the opposite direction to the write bit line 5 and the write word line 6, or when a write current flows to only one of them, each second magnetosensitive layer 8 The data is not rewritten because the magnetization directions of a and 8b are not reversed.
(磁気メモリデバイスにおける情報の読出動作の説明）  (Explanation of information reading operation in magnetic memory device)
次に、 磁気メモリデバイス Mの読出動作について説明する。  Next, the read operation of the magnetic memory device M will be described.
まず、 ァドレスバッファ 5 1を介してァドレス信号を入力した Y方向ァドレス デコーダ回路 5 6 Aが、 このァドレス信号に基づいて複数のビットデコ一ド線 Y のうちの 1つを選択して、 駆動対象のセンスァンプ回路 5 6 Bにビット線選択信 号 S b iを出力する。 また、 制御ロジック部 5 3が、 リード選択信号 S rをセン スアンプ回路 5 6. Bおよび X方向ァドレスデコーダ回路 5 8 Aに出力する。 次い で、 ビット線選択信号 S b iおよびリード選択信号 S rを入力したセンスアンプ 回路 5 6 Bでは、 スィッチ Q 1 1 , Q 1 2がオン状態になると共に、 差動増幅回 路 7 0が作動する。 これにより、 センスアンプ回路 5 6 Bは、 接続されている線 路 5 a , 5 bに対して、 抵抗 R l l， R 1 2を介して電源 V c cを印加する。 こ の際に、 各記憶素子 l a , l bでは、 各導通用堆積体 1 3 a , 1 3 bを介して線 路 5 a , 5 bと第 1の磁性層 2 a， 2 bとがそれぞれ電気的に接続されているた め、 各導通用堆積体 1 3 a， 1 3 bを介して、 各第 1の磁性層 2 a， 2 bに正の ほぼ同電位が与えられる。 一方、 リード選択信号 S rとアドレスバッファ 5 1を 介してァドレス信号とを入力した X方向ァドレスデコーダ回路 5 8 Aは、 このァ ドレス信号に基づいて複数のヮードデコ一ド線 X Rのうちの 1つを選択して、 駆 動対象の定電流回路 5 8 Bに制御信号を出力して作動させる。 これにより、 駆動 対象に選択されたセンスアンプ回路 5 6 Bおよび定電流回路 5 8 Bにそれぞれ接 続されている書込ビット線 5および読出ワード線 1 2の交差部分 （平行部分 1 0 ) に配設されている記憶セル 1に、 書込ビット線 5 (各線路 5 a , 5 b ) 、 各 T MR膜 S 2 0 a , S 2 0 b、 各環状磁性層 4 a , 4 bおよび読出ヮード線 1 2を 介して読出電流が流れる。 この場合、 記憶セル 1における各記憶素子 1 a， l b では、 記憶されている情報の値に応じて一方が低抵抗状態で他方が高抵抗状態に 維持されると共に、 記憶セル 1を流れる読出電流の総和が定電流回路 5 8 Bによ つて一定値に維持されている。 このため、 各記憶素子 l a，' l bの一方を流れる 読出電流が多く、 かつ他方を流れる読出電流が少なくなる。 例えば、 図 8に示す 記憶セル 1の状態では、 記憶素子 1 aにおいて第 1の磁性層 2 aと第 2の感磁層 8 aの各磁化方向が平行となり、 記憶素子 1 bにおいて第 1の磁性層 2 bと第 2 の感磁層 8 bの各磁化方向が反平行となっている。 このため、 記憶素子 1 aが低 抵抗状態、 記憶素子 1 bが高抵抗状態になる結果、 記憶素子 1 aを流れる読出電 流が多く、 記憶素子 1 bを流れる読出電流が少なくなる。 これに対して、 図 9に 示す記憶セル 1の状態では、 各記憶素子 1 a， 1 bにおける第 1の磁性層 2 aお よび第 2の感磁層 8 aの各磁化方向が図 8のときとは逆となるため、 記憶素子 1 aが高抵抗状態、 記憶素子 1 bが低抵抗状態になる結果、 記憶素子 1 aを流れる 読出電流が少なく、 記憶素子 1 bを流れる読出電流が多くなる。 センスアンプ回 路 5 6 Bでは、 差動増幅回路 Ί 0が各線路 5 a， 5 bを流れる読出電流に応じて 、 各抵抗 R 1 1， R 1 2の両端に発生する各電圧の電圧差 （線路 5 a， 5 bを流 れる読出電流の電流量の差分でもある） を検出することにより、 記憶セル 1に記 憶されている情報 （2値情報） を取得する。 また、 出力バッファ 5 2 Bは、 セン スアンプ回路 5 6 Bを介して入力した情報を外部データ端子 D O〜D 7に出力す る。 これにより、 記憶セル 1に記憶されている 2値情報の読み取りが完了する。 このように、 この磁気メモリデバイス Mによれば、 書込ビット線 5の各線路 5 a , 5 bを読出線 （読出ビット線） としても使用可能に構成したことにより、 記 憶セル群 5 4に形成すべき線路 （電流供給線路） の本数を低減することができる 。 したがって、 構造を簡略化できる結果、 磁気メモリデバイス Mを微細化できる と共に、 製造が容易となって生産性を十分に向上させることができる。 また、 書 込ビット線 5を一対の線路 5 a , 5 bで構成して、 各線路 5 a , 5 bを流れる電 流量の差分に基づいて記憶セル 1に記憶された情報を差動増幅回路 7 0で読み出 す構成としたことにより、 磁気抵抗効果発現体 2 0 a， 2 0 bの抵抗値や、 各線 路 5 a， 5 bの抵抗値がばらついていたとしても、 各線路 5 a， 5 bの各々にお ける読出電流のぶれを総電流値に応じて常に一定の範囲内に抑え込むことができ る。 このため、 センスアンプ回路 5 6 Bから安定した差動出力を出力できる結果 、 記憶セル 1に記憶された情報を安定して読み出すことができる。 さらに、 記憶 セル 1が配設される書込ビット線 5および書込ヮ一ド線 6 6の交差部分 （平行部 分 1 0 ) において、 書込ビット線 5を構成する線路 5 a， 5 bおよび第 2の書込 線 6を環状磁性層 4 a， 4 bで取り囲むようにしたことにより、 各線路 5 a， 5 bおよび第 2の書込線 6の双方を流れる書込電流によつて各線路 5 a , 5 bおよ び書込ワード線 6の周囲に生じる磁束を各環状磁性層 4 a， 4 bからなる閉磁路 内に閉じ込めることができるため、 漏れ磁束の発生を十分に低減することができ る結果、 隣接する記憶セルへの悪影響を大幅に低減することができる。 したがつ て、 磁気メモリデバイス Mのさらなる微細化を可能とすることができる。 First, a Y-direction address decoder circuit 56 A, which has input an address signal via an address buffer 51, selects one of a plurality of bit-decoded lines Y based on the address signal, and The bit line selection signal S bi is output to the sense amplifier circuit 56B. Further, the control logic section 53 outputs the read selection signal Sr to the sense amplifier circuit 56.B and the X-direction address decoder circuit 58A. Next, the sense amplifier to which the bit line selection signal Sbi and the read selection signal Sr are input In the circuit 56B, the switches Q11 and Q12 are turned on, and the differential amplifier circuit 70 operates. Thus, the sense amplifier circuit 56B applies the power supply Vcc to the connected lines 5a and 5b via the resistors Rll and R12. At this time, in each of the storage elements la and lb, the lines 5a and 5b and the first magnetic layers 2a and 2b are electrically connected to each other through the conductive stacks 13a and 13b, respectively. The first magnetic layers 2a and 2b have substantially the same positive potential via the conductive stacks 13a and 13b. On the other hand, the X-direction address decoder circuit 58A, to which the read selection signal Sr and the address signal are input via the address buffer 51, receives one of the plurality of code decode lines XR based on the address signal. Is selected and a control signal is output to the constant current circuit 58B to be driven to operate. As a result, at the intersection (parallel portion 10) of the write bit line 5 and the read word line 12 connected to the sense amplifier circuit 56 B and the constant current circuit 58 B selected as the drive target, respectively. In the memory cell 1 provided, the write bit line 5 (each line 5 a, 5 b), each TMR film S 20 a, S 20 b, each annular magnetic layer 4 a, 4 b, and read A read current flows through the lead lines 1 and 2. In this case, in each of the storage elements 1 a and lb in the storage cell 1, one is maintained in a low resistance state and the other is maintained in a high resistance state in accordance with the value of stored information, and the read current flowing through the storage cell 1 is maintained. Is maintained at a constant value by the constant current circuit 58B. Therefore, the read current flowing through one of the storage elements la and 'lb is large, and the read current flowing through the other is small. For example, in the state of the storage cell 1 shown in FIG. 8, in the storage element 1a, the respective magnetization directions of the first magnetic layer 2a and the second magnetosensitive layer 8a are parallel, and the first direction in the storage element 1b is The magnetization directions of the magnetic layer 2b and the second magnetosensitive layer 8b are antiparallel. Therefore, as a result of the storage element 1a being in the low resistance state and the storage element 1b being in the high resistance state, the read current flowing through the storage element 1a is large, and the read current flowing through the storage element 1b is reduced. On the other hand, in the state of the storage cell 1 shown in FIG. 9, the respective magnetization directions of the first magnetic layer 2a and the second magnetosensitive layer 8a in each of the storage elements 1a and 1b are as shown in FIG. Storage element 1 As a result, a becomes a high resistance state and the storage element 1b becomes a low resistance state. As a result, the read current flowing through the storage element 1a is small, and the read current flowing through the storage element 1b is large. In the sense amplifier circuit 56B, the differential amplifier circuit Ί0 generates a voltage difference between the voltages generated at both ends of the resistors R11 and R12 in accordance with the read current flowing through the lines 5a and 5b. (Which is also the difference between the amounts of read currents flowing through the lines 5a and 5b), the information (binary information) stored in the storage cell 1 is obtained. The output buffer 52B outputs information input via the sense amplifier circuit 56B to the external data terminals DO to D7. Thus, the reading of the binary information stored in the storage cell 1 is completed. As described above, according to the magnetic memory device M, each of the lines 5 a and 5 b of the write bit line 5 is configured to be usable as a read line (read bit line). Thus, the number of lines (current supply lines) to be formed can be reduced. Therefore, the structure can be simplified, and as a result, the magnetic memory device M can be miniaturized, and the manufacturing can be facilitated, and the productivity can be sufficiently improved. The write bit line 5 is composed of a pair of lines 5a and 5b, and the information stored in the storage cell 1 is differentially amplified based on the difference between the currents flowing through the lines 5a and 5b. With the configuration of reading out at 70, even if the resistance values of the magnetoresistive effectors 20a and 20b and the resistance values of the lines 5a and 5b vary, each line 5a , 5b can always be kept within a certain range according to the total current value. As a result, a stable differential output can be output from the sense amplifier circuit 56B, so that the information stored in the storage cell 1 can be stably read. Further, at the intersection (parallel portion 10) of the write bit line 5 and the write pad line 66 where the storage cell 1 is provided, the lines 5 a and 5 b forming the write bit line 5 are provided. And the second write line 6 is surrounded by the annular magnetic layers 4 a and 4 b, so that the write current flowing through both the lines 5 a and 5 b and the second write line 6 causes Since the magnetic flux generated around each of the lines 5a and 5b and the write word line 6 can be confined in the closed magnetic path composed of the annular magnetic layers 4a and 4b, the generation of leakage magnetic flux is sufficiently reduced. Can As a result, the adverse effect on adjacent storage cells can be significantly reduced. Therefore, the magnetic memory device M can be further miniaturized.
なお、 本発明は、 上記した構成に限定されない。 例えば、 スィッチ回路 5 9の 各スィツチ Sは、 一対のダイォード D 1， D 2を逆極性で並列接続することによ つて構成した例について説明したが、 図 1 0に示すスィッチ S 1のように、 複数 Note that the present invention is not limited to the configuration described above. For example, although an example in which each switch S of the switch circuit 59 is configured by connecting a pair of diodes D 1 and D 2 in parallel with opposite polarities has been described, as in switch S 1 shown in FIG. , Multiple
(同図では一例として 2つ） のダイォードを順極性で直列接続したダイォード群 同士を、 互いに逆極性となるように並列接続した構成を採用して、 図 6に示す V f を 2 X V ίとすることにより、 スィッチオフの領域を拡げることもできる。 こ の構成によれば、 非導通状態を維持すべきスィッチ回路 5 9がノイズ等に起因し て誤って導通状態に移行するのを一層確実に防止することができる。 また、 図 1 1， 1 2に示すスィッチ S 2， S 3のように、 一方のェミッタが他方のコレクタ に接続されると共に、 一方のコレクタが他方のエミッタに接続された一対のトラ ンジスタを備えた構成を採用することもできる。 この場合、 このスィッチ S 2で は、 各トランジスタをデータ信号 Y D i nおよびリファレンス信号 Y R e f で駆 動することにより、 Y方向カレントドライブ回路 5 6 Cにおけるスィッチ Q 3， Q 4と同タイミングでオン/オフさせる。 一方、 スィッチ S 3では、 ライト選択 信号 S wで各トランジスタを駆動することにより、 書込動作中において、 両トラ ンジスタをオン状態にする。 また、 スィッチ S 2の各トランジスタに代えて F E T (電界効果型トランジスタ） を使用してスィッチを構成することもできるし、 スィツチ S 3の各トランジスタに代えて 1つのイコライザー MO S F E Tを使用 してスィッチを構成することもできる。 In this figure, two diodes are connected in series with forward polarity (two as an example), and the diode groups are connected in parallel so that they have opposite polarities, and V f shown in Fig. 6 is changed to 2 XV ί. By doing so, the area of the switch-off can be expanded. According to this configuration, it is possible to more reliably prevent the switch circuit 59 that should maintain the non-conductive state from erroneously shifting to the conductive state due to noise or the like. In addition, as shown in switches S2 and S3 shown in FIGS. 11 and 12, one emitter is connected to the other collector and one collector is connected to the other emitter. It is also possible to adopt a configuration that is different from that described above. In this case, in the switch S2, each transistor is driven by the data signal YDin and the reference signal YRef to turn on / off at the same timing as the switches Q3 and Q4 in the Y-direction current drive circuit 56C. Turn off. On the other hand, in the switch S3, both transistors are turned on during the write operation by driving each transistor with the write selection signal Sw. In addition, a switch can be configured by using an FET (field effect transistor) in place of each transistor of the switch S2, and a switch can be configured by using one equalizer MO SFET in place of each transistor of the switch S3. Can also be configured.
また、 図 1 3に示す磁気メモリデバイス M lのように、 磁気メモリデバイス M のセンスアンプ回路 5 6 Bからスィッチ Q l 1 , Q 1 2を省いて構成した図 1 4 に示すセンスアンプ回路 8 6 Bを用いると共に、 図 1 3に示す構成の記憶セル群 5 4 Aを用いた構成を採用することもできる。 なお、 記憶セル群 5 4およびセン スアンプ回路 5 6 Bと同一の構成要素については同一の符号を付して重複する説 明を省略する。 この場合、 各線路 5 a， 5 bの他端側は、 図 1 4に示すように、 センスアンプ回路 8 6 Bの各抵抗 R 1 1， R 1 2 (差動増幅回路 7 0を構成する 各トランジスタのベース） に接続されている。 また、 図 1 3に示すように、 同一 の書込ビット線 5上に配設された複数の記憶セル 1における記憶素子 1 a , 1 b の各環状磁性層 4 a， 4 b (図 3も参照） は、 対応する定電流回路 5 8 Bに接続 されている。 また、 この定電流回路 5 8 Bは、 対応する Y方向カレントドライブ 回路 5 6 Cと同一のビットデコード線 Yによつて選択されるように構成されてい る。 なお、 図示はしないが、 磁気メモリデバイス M lは、 磁気メモリデバイス M と同様にして、 各書込ヮード線 6および各書込ヮード線 6に接続された X方向力 レントドライブ回路 5 8 Cを備えている。 この磁気メモリデバイス M lでは、 磁 気メモリデバイス Mと同様の書込動作で各記憶セル 1に情報が書き込まれる。 一 方、 記憶セル 1から情報を読み出す際には、 アドレス信号に基づいて Y方向アド レスデコーダ回路 5 6 Aが 1つのビッ トデコード線 Yを選択する。 また、 X方向 ァドレスデコーダ回路 5 8 Aが 1つのワードデコード線 X (同図では読出ワード 線 1 2 ) を選択する。 この場合、 選択されたワードデコード線 X (読出ワード線 1 2 ) に接続された各トランジスタ 8 5 a， 8 5 bがオン状態に移行し、 併せて ビットデコード線 γによつて選択されたセンスァンプ回路 8 6 Bからこのセンス アンプ回路 8 6 Bに接続されている書込ビット線 5 (線路 5 a， 5 b ) に電流が 供給されると共に、 対応する定電流回路 5 8 Bが作動する。 この結果、 この書込 ビット線 5とワードデコード線 X (読出ワード線 1 2 ) との交差部分に配設され た記憶セル 1に読出電流が流れる。 これにより、 磁気メモリデバイス Mと同様に して、 記憶セル 1に記憶されている 2値情報の読み取りが行われる。 Also, as in the magnetic memory device Ml shown in FIG. 13, the sense amplifier circuit 56 shown in FIG. 14 is configured by omitting the switches Ql1 and Q12 from the sense amplifier circuit 56B of the magnetic memory device M. In addition to using 6B, a configuration using the storage cell group 54A having the configuration shown in FIG. 13 can be adopted. Note that the same components as those of the memory cell group 54 and the sense amplifier circuit 56 B are denoted by the same reference numerals, and a duplicate explanation is given. The description is omitted. In this case, the other ends of the lines 5a and 5b are connected to the respective resistors R11 and R12 of the sense amplifier circuit 86B (the differential amplifier circuit 70) as shown in FIG. (Base of each transistor). Also, as shown in FIG. 13, each of the annular magnetic layers 4a and 4b of the storage elements 1a and 1b in the plurality of storage cells 1 arranged on the same write bit line 5 (FIG. Is connected to the corresponding constant current circuit 58B. The constant current circuit 58B is configured to be selected by the same bit decode line Y as the corresponding Y-direction current drive circuit 56C. Although not shown, the magnetic memory device Ml includes, in the same manner as the magnetic memory device M, each write mode line 6 and the X-directional force drive circuit 58C connected to each write mode line 6. Have. In this magnetic memory device Ml, information is written to each storage cell 1 by the same write operation as that of the magnetic memory device M. On the other hand, when reading information from the memory cell 1, the Y-direction address decoder circuit 56A selects one bit decode line Y based on the address signal. The X-direction address decoder circuit 58A selects one word decode line X (the read word line 12 in the figure). In this case, the transistors 85a and 85b connected to the selected word decode line X (read word line 12) shift to the ON state, and at the same time, the sense amplifier selected by the bit decode line γ. A current is supplied from the circuit 86B to the write bit line 5 (lines 5a and 5b) connected to the sense amplifier circuit 86B, and the corresponding constant current circuit 58B operates. As a result, a read current flows through storage cell 1 arranged at the intersection of write bit line 5 and word decode line X (read word line 12). Thereby, similarly to the magnetic memory device M, the binary information stored in the storage cell 1 is read.
また、 上記した磁気メモリデバイス M， M lでは、 環状磁性層 4の各第 1の感 磁層 1 4 a , 1 4 bと共に、 各第 2の感磁層 8 a， 8 bを備えた構成の記憶セル 1を例に挙げて説明したが、 各第 2の感磁層 8 a， 8 bを省いて、 感磁層として 、 環状磁性層 4の各第 1の感磁層 1 4 a , 1 4 bのみを備えた構成の記憶セルを 採用することもできる。 また、 環状磁性層 4の各第 1の感磁層 1 4 a， 1 4 bと 各第 2の感磁層 8' a , 8 bとの間に非磁性導電層を配設することにより、 各第 1 の感磁層 1 4 a， 1 4 bと各第 2の感磁層 8 a， 8 bとを反強磁性結合させる記 憶セルを構成することもできる。 また、 TMR膜 S 2 0 a， S 2 0 bを保磁力差 型構造に構成した記憶セルに本発明を適用した例について説明したが、 各 TMR 膜を交換バイアス型に構成した記憶セルに対しても本発明を適用できるのは勿論 である。 産業上の利用可能性 Further, in the magnetic memory devices M and Ml described above, each of the second magnetically sensitive layers 8a and 8b is provided together with the first magnetically sensitive layers 14a and 14b of the annular magnetic layer 4. In the above description, the second magnetic sensing layer 8a, 8b is omitted, and the first magnetic sensing layer 14a, 14a of the annular magnetic layer 4 is used as the magnetic sensing layer. A storage cell configured with only 14 b Can also be adopted. Further, by disposing a non-magnetic conductive layer between each first magneto-sensitive layer 14 a, 14 b of the annular magnetic layer 4 and each second magneto-sensitive layer 8 ′ a, 8 b, It is also possible to configure a storage cell in which each first magnetically sensitive layer 14a, 14b and each second magnetically sensitive layer 8a, 8b are antiferromagnetically coupled. Also, an example in which the present invention is applied to a storage cell in which the TMR films S 20 a and S 20 b have a coercive force difference structure has been described. It goes without saying that the present invention can be applied. Industrial applicability
以上のように、 この磁気メモリデバイスによれば、 第 1の書込線を構成する各 線路を他の読出線 （読出ビット線） として使用して、 積層体、 環状磁性層および 読出線 （読出ワード線） を介して第 1の書込線の各線路を流れる各読出電流の大 小に基づいて記録セルに記憶された情報を読み出すことにより、 独立した読出線 (読出ワード線） を不要にすることができる。 したがって、 磁気メモリデバイス の構成を簡略化することができ、 微細化および製造の容易化が可能な磁気メモリ デバイスが実現される。  As described above, according to this magnetic memory device, each of the lines constituting the first write line is used as another read line (read bit line), and the stacked body, the annular magnetic layer, and the read line (read line) are used. By reading the information stored in the recording cell based on the magnitude of each read current flowing through each line of the first write line via the word line), an independent read line (read word line) becomes unnecessary. can do. Therefore, the configuration of the magnetic memory device can be simplified, and a magnetic memory device that can be miniaturized and easily manufactured is realized.

Claims

請求の範囲 The scope of the claims
1 . 導通状態および非導通状態のいずれかに移行するスィツチ素子を介して 互いの一端側が接続されて並設された一対の線路を有する複数の第 1の書込線と 前記各第 1の書込線とそれぞれ交差する複数の第 2の書込線と、  1. A plurality of first write lines having a pair of lines connected in parallel with one end connected to each other via a switch element that shifts to a conductive state or a non-conductive state, and the first write lines A plurality of second write lines each intersecting the feed line;
前記各第 1の書込線の各線路と前記第 2の書込線との各交差部分にそれぞれ配 設されると共に当該各第 1の書込線の各線路と当該第 2の書込線とによって貫か れるように構成された環状磁性層と、  Each line of the first write line and each line of the first write line and the second write line are provided at respective intersections of the first write line and the second write line. An annular magnetic layer configured to be penetrated by
前記各環状磁性層における感磁層および当該感磁層の表面に配設された磁気抵 抗効果発現体を含んで積層面に垂直な方向に電流が流れるように構成された積層 体と、  A laminated body including a magneto-sensitive layer in each of the annular magnetic layers and a magnetic resistance effect generator disposed on the surface of the magneto-sensitive layer and configured to allow a current to flow in a direction perpendicular to the lamination plane;
前記複数の第 2の書込線にそれぞれ並設されると共に対応する当該第 2の書込 線によつて貫かれる前記環状磁性層に電気的に接続された複数の読出線とを備え 前記第 1の書込線および前記第 2の書込 #泉は前記交差部分において互いに平行 になるように形成されると共に当該平行に形成された部位において前記環状磁性 層を貫通し、  A plurality of read lines electrically connected to the annular magnetic layer, which are provided in parallel with the plurality of second write lines, respectively, and are penetrated by the corresponding second write lines. The first writing line and the second writing spring are formed so as to be parallel to each other at the intersection, and penetrate the annular magnetic layer at a portion formed in parallel with the writing line.
1つの前記第 1の書込線における前記一対の線路と 1つの前記第 2の書込線と の前記各交差部分に配設された 2つの前記環状磁性層および 2つの前記磁気抵抗 効果発現体を備えて 1つの記憶セルが構成され、  Two annular magnetic layers and two magnetoresistance effect generators disposed at the respective intersections of the pair of lines and one second write line in one first write line One storage cell is configured with
前記各第 1の書込線の各線路は、 当該各線路が貫通する前記環状磁性層に配設 された前記積層体における当該環状磁性層に接触する面の背面側にそれぞれ電気 的に接続されている磁気メモリデバイス。  Each line of each of the first write lines is electrically connected to a back side of a surface of the laminated body provided on the annular magnetic layer through which each line penetrates, the surface being in contact with the annular magnetic layer. Magnetic memory device.
2 . 前記各記憶セルは、 前記スィッチ素子が前記導通状態のときに、 当該ス ィツチ素子を介して前記第 1の書込線の各茅泉路を流れる書込電流および前記第 2 の書込線を流れる書込電流によって生ずる磁界に応じて前記感磁層の磁化方向が 変化することで情報を記憶し、 かつ、 前記スィッチ素子が前記非導通状態のとき に、 前記第 1の書込線の各線路、 前記積層体、 前記環状磁性層および前記読出線 を流れる各読出電流の大小に基づいて前記記憶している情報が読み出される請求 項 1記載の磁気メモリデバイス。 2. Each of the storage cells includes, when the switch element is in the conductive state, a write current and a second write current flowing through each of the first and second write lines via the switch element. The magnetization direction of the magneto-sensitive layer changes according to the magnetic field generated by the write current flowing through the wire. When the switch element is in the non-conducting state, the information is stored by the change, and when the switch element is in the non-conductive state, each read flowing through each line of the first write line, the laminate, the annular magnetic layer, and the read line The magnetic memory device according to claim 1, wherein the stored information is read based on a magnitude of a current.
3 . 前記各第 1の書込線は、 前記書込電流を供給する第 1のカレントドライ ブ回路および前記各第 1の書込線の各線路を流れる書込電流を供給するセンスァ ンプ回路に接続され、  3. Each of the first write lines is connected to a first current drive circuit that supplies the write current and a sense amplifier circuit that supplies a write current flowing through each line of the first write line. Connected
前記各第 2の書込線は、 当該第 2の書込線を流れる前記書込電流を供給する第 2のカレントドライブ回路に接続されている請求項 1記載の磁気メモリデバイス  2. The magnetic memory device according to claim 1, wherein each of the second write lines is connected to a second current drive circuit that supplies the write current flowing through the second write line.
PCT/JP2003/016286 2003-12-18 2003-12-18 Magnetic memory device WO2005062383A1 (en)

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JP2002353415A (en) * 2001-05-23 2002-12-06 Internatl Business Mach Corp <Ibm> Storage cell, memory cell and storage circuit block
JP2003318368A (en) * 2002-04-23 2003-11-07 Canon Inc Magnetic memory device and method of driving the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002353415A (en) * 2001-05-23 2002-12-06 Internatl Business Mach Corp <Ibm> Storage cell, memory cell and storage circuit block
JP2003318368A (en) * 2002-04-23 2003-11-07 Canon Inc Magnetic memory device and method of driving the same

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