WO2005004345A1 - A frequency-domain filter and method for realizing frequency-domain filtering - Google Patents

Abstract

The present invention discloses a frequency-domain filter, the frequency-domain filter includes control module, storage unit array, filter coefficient memory, data switch module, twiddle factor lookup module, output data combination module and at least a high-speed general operation unit; Said high-speed general operation unit may be time-division multiplexed by said storage unit array and data switch module, and providing the resources for completing data operation processing such as fast Fourier transform (FFT) , IFFT and frequency-domain filtering operation, etc. At the same time, the present invention also discloses a method for realizing frequency-domain filtering. The present invention overcomes some defects of traditional frequency-domain filtering configuration, and provides a realization scheme that the high-efficiency filter may change dynamicly based on FFT, IFFT and the filtering characteristic of said filter.

Description

一种频域滤波器及实现频域滤波的方法 技术领域  Frequency domain filter and method for realizing frequency domain filter

本发明涉及数字信号处理技术， 特别是指一种频域滤波器及实现频 或滤波的方法。 发明背景  The present invention relates to digital signal processing technology, and particularly to a frequency domain filter and a method for implementing frequency or filtering. Background of the invention

在目前的数字信号处理***中， 滤波器被广泛应用于干扰的滤除、 有用信号的提取、 信号的整形等各方面。 对于一般的、 线性时不变*** 的离散数字信号， 目前主要使用时域卷积型和频域相乘型两种滤波器对 其进行处理。 对于滤波特性不变的滤波器而言, 时域卷积型的滤波器由 于有高效的查表方式的电路实现形式， 非常节省计算资源， 所以在芯片 设计中得到了广泛的应用。 但是在有些场合中， 滤波器的单位脉冲响应 的形状需要进行动态的变化， 从而使得时域卷积形式的滤波器难于设 计， 而且需要的资源也过多。 在这种情况下， 可以用快速傅立叶变换 In current digital signal processing systems, filters are widely used in filtering interference, extracting useful signals, and shaping signals. Discrete digital signals for general, linear time-invariant systems are currently processed using two filters, the time-domain convolution type and the frequency-domain multiplication type. For filters with constant filtering characteristics, time-domain convolution filters are widely used in chip design because of the highly efficient circuit implementation of a look-up table, which saves computing resources. However, in some cases, the shape of the unit pulse response of the filter needs to be dynamically changed, which makes it difficult to design a filter in the form of time-domain convolution, and it also requires too many resources. In this case, a fast Fourier transform can be used

( FFT )将时域信号转换为频域信号， 再与滤波器频域系数简单的相乘 后即可完成滤波， 然后通过快速傅立叶反变换（IFFT )将滤波后的频域 信号转换为时域信号输出。 (FFT) converts the time-domain signal into a frequency-domain signal, and then simply multiplies the filter's frequency-domain coefficients to complete the filtering. Then, the inverse fast Fourier transform (IFFT) is used to convert the filtered frequency-domain signal into the time domain. Signal output.

在一项名称为 "同时宽带和窄带无线通信的方法和装置"、公开号为 CN 1141104A的中国发明专利申请中， 公开了一个基于傅立叶正反变换 的频域滤波方案。 如图 1所示， 模块的输入信号是一个宽带的码分多址 In a Chinese invention patent application entitled "Method and Apparatus for Simultaneous Broadband and Narrowband Wireless Communications" and Publication No. CN 1141104A, a frequency domain filtering scheme based on Fourier forward and inverse transform is disclosed. As shown in Figure 1, the input signal of the module is a wideband code division multiple access

( CDMA )载波信号和几个窄带的调频（FM )信号， 该方案是将上述两 个信号混合后输入 FFT器件 41直接进行快速傅立叶变换， 然后由 BIN 阔值检测器及高电平载波检测器 42在频域进行调频信号功率的检测， 并用频率域陷波滤波器 43 滤除检测到的调频信号， 再将未被滤除的信 号送入反 FFT器件 44进行快速傅立叶反变换还原为不包含调频信号的 码分多址载波时域信号。 (CDMA) carrier signal and several narrow-band frequency-modulated (FM) signals. The solution is to mix the above two signals and input them to the FFT device 41 to directly perform a fast Fourier transform, and then use a BIN threshold detector and a high-level carrier detector. 42 detects the power of the FM signal in the frequency domain, and uses a frequency domain notch filter 43 to filter out the detected FM signal, and then The number is sent to the inverse FFT device 44 for inverse fast Fourier transform to be reduced to a code division multiple access carrier time domain signal that does not include an FM signal.

由于该方案中直接将信号进行快速傅立叶正反变换处理， 这将导致 经过傅立叶变换后的数据段首尾附近的数据经过滤波处理后发生相位 的跳变， 从而严重地影响了滤波效果， 并将使滤波后的信号的相位产生 非线性， 因而对 CDMA ***的解调性能影响很大； 另外， 由于正反傅 立叶变换的运算延时非常大， 从而导致整个滤波器的群延时也非常大， 而在码分多址的蜂窝无线通讯***中， 信号处理的延时过大会严重影响 无线通信***的小区半径和功率控制等指标， 所以需要采取必要的措施 来有效地控制处理延时； 同时， 该方案无法从外部对滤波器频域系数进 行动态的修改。 ，  Because the signal is directly subjected to fast Fourier transform in this solution, this will cause phase jumps in the data near the beginning and end of the data segment after the Fourier transform after filtering, which will seriously affect the filtering effect and will make the The phase of the filtered signal is non-linear, so it has a great impact on the demodulation performance of the CDMA system. In addition, the operation delay of the forward and inverse Fourier transform is very large, which causes the group delay of the entire filter to be very large. In a code division multiple access cellular wireless communication system, the excessive delay of signal processing seriously affects the cell radius and power control of the wireless communication system, so it is necessary to take necessary measures to effectively control the processing delay; at the same time, the The scheme cannot dynamically modify the filter's frequency domain coefficients from the outside. ,

在另一项名称为 "优化移动无线电***发射机的性能的方法"、公开 号为 CN 1354609A的中国发明专利申请中，也公开了一个基于傅立叶正 反变换的频域滤波方案， 如图 2所示。 该专利申请所描述的方案是一种 利用包括离散傅里叶变换（DFT )运算、 频域滤波、 离散傅里叶反变换 ( IDFT )运算、 交叠处理样点块和过采样的一些处理操作优化移动无线 电***多载波发射机的性能的方法。 其中， 对于给定的输入采样频率、 给定的输出釆样频率的数量级和给定的所要求的频率分辨率的数量级， 将 DFT的长度 LDFT和 IDFT的长度 LIDFT选择成能尽可能精细地选择 交叠百分比和过釆样因子。  In another Chinese application titled "Method for Optimizing the Performance of Mobile Radio System Transmitter" and publication number CN 1354609A, a frequency domain filtering scheme based on Fourier inverse transform is also disclosed, as shown in Figure 2. Show. The solution described in this patent application is a kind of processing operation using discrete Fourier transform (DFT) operation, frequency domain filtering, inverse discrete Fourier transform (IDFT) operation, overlapping processing of sample block, and oversampling. Method for optimizing the performance of multi-carrier transmitters in mobile radio systems. Among them, for a given input sampling frequency, a given output sample frequency, and a given required frequency resolution, the length of the DFT LDFT and the length of the IDFT LIDFT are selected as finely as possible. Overlap percentage and over-like factor.

该方案首先根据频域分辨率要求、 DFT 的输入信号带宽以及 IDFT 的输出信号带宽等信息， 来确定离散傅立叶正反变换的长度、 交叠的百 分比和过采样因子； 根据相应交叠百分比进行交叠提取之后的各个载波 信号经过变频器 7、 8 进行频偏处理， 将各信道中心频率调整正确； 接 着将特定交叠百分比的样点块加载到 DET上的装置 1进行补零移位处 理， 将数据长度进行归一化调整； 再由 DFT器件 2进行 DFT运算， 然 后通过频域滤波装置 3 在频域对载波信号进行宽带信号的成型滤波运 算， 之后， 由合并数据及补零装置 4将各个载波的频域数据合并同时补 零以调整数据长度， 然后由 IDFT器件 5进行 IDFT运算， 最后由合并 IDFT的输出装置 6对恢复出来的时域数据进行交叠数据相加合并的处 理， 从而得到最终的滤波后的时域数据。 This solution first determines the length, the percentage of overlap, and the oversampling factor of the discrete Fourier transform, based on the frequency domain resolution requirements, the input signal bandwidth of the DFT, and the output signal bandwidth of the IDFT. Each carrier signal after the overlap extraction is subjected to frequency offset processing by the inverters 7 and 8 to correctly adjust the center frequency of each channel; then a sample block of a specific overlap percentage is loaded to the device 1 on the DET for zero-padded shift. The data length is normalized and adjusted; then the DFT operation is performed by the DFT device 2, and then the carrier signal is subjected to a wideband signal shaping and filtering operation in the frequency domain by the frequency domain filtering device 3, and thereafter, the combined data and zero-padded device 4 Combine the frequency-domain data of each carrier while zero-padded to adjust the data length, then IDFT operation is performed by the IDFT device 5, and finally the output device 6 of the merged IDFT performs overlapping data addition and merge processing on the recovered time-domain data. To obtain the final filtered time domain data.

由于此方案是针对多载波的信号合并成型的应用， 所以在频域滤波 实现方面存在一些缺点。 首先， 由于交叠处理是选用交叠相加方式， 并 且有信号带宽的限制， 所以对滤波群延时指标的优化有限； 并且由于没 有完全改善相位跳变的问题， 所以需要引入额外的相位跳变抑制电路； 其次， 不同信号的离散傅里叶正反变换运算的长度、 速率有很大差异， 无法进行运算模块的复用设计， 导致资源使用过多、 实现难度增加、 成 本大幅上升； 最后， 该方案也无法实现从外部对滤波器频域系数进行动 态的修改。  Since this solution is for the application of multi-carrier signal combining and shaping, there are some disadvantages in the implementation of frequency domain filtering. First of all, because the overlap processing method is an overlap-add method, and the signal bandwidth is limited, the optimization of the filter group delay index is limited; and because the problem of phase transition is not completely improved, additional phase jumps need to be introduced Variable suppression circuit; Secondly, the length and rate of the discrete Fourier inverse transform operation of different signals are very different, and the multiplexing design of the operation module cannot be performed, resulting in excessive use of resources, increased difficulty in implementation, and greatly increased costs; finally This solution also cannot implement dynamic modification of the filter frequency domain coefficients from the outside.

一般情况下频域滤波处理过程的延时都较大， 并且经过分段式傅立 叶变换后的数据段将出现首尾处的信号滤波效果差、 相位的非线性等问 题， 从而使得频域滤波的设计和应用受到了一定的限制， 但是， 如果在 频域滤波处理过程中增加对时域数据的交叠和反交叠处理后， 以上问题 就可以得到明显的改善。 交叠和反交叠处理技术的原理， 如图 3所示： 如果输入的时域信号 S1要进行运算长度为 N的快速傅立叶变换， 并且 要求在交叠处理过程中的交叠长度为 L,那么可从 S1的第一个数据点开 始， 在 S1上每隔（N - L )个数据取一段长度为 N个数据的数据段， 其 中每个数据段中从末端算起的 L个数据与下一个数据段的前 L个数据是 相同的， 即交叠长度为 L。 这样， 可按一定的顺序将 S1分割成若干个长 度为 N、 交叠长度为 L的数据段， 从而完成了对时域信号 S1的交叠处 理。 由于 SI的长度在理论上并没有限制， 所以可以考虑取前 F1个数据 段的交叠处理过程， 更多个数据段的交叠处理过程可依此类推。 In general, the delay of the frequency domain filtering process is large, and the data segment after the piecewise Fourier transform will have problems such as poor signal filtering effect at the beginning and end, and non-linearity of the phase, thus making the design of the frequency domain filtering And applications are subject to certain restrictions, but if the overlap and anti-overlap processing of time-domain data is added during the frequency-domain filtering process, the above problems can be significantly improved. The principle of the overlap and anti-overlap processing technology is shown in Figure 3: If the input time-domain signal S1 is to perform a fast Fourier transform with a length of N, and the overlap length during the overlap processing is required to be L, Then, starting from the first data point of S1, take a data segment of length N data every (N-L) data on S1, where the L data from the end of each data segment and the The first L data of the next data segment are the same, that is, the overlap length is L. In this way, S1 can be divided into several data segments of length N and overlap length L in a certain order, thereby completing the overlap of the time domain signal S1. Management. Since the length of the SI is not theoretically limited, the overlap processing process of the first F1 data segments can be considered, and the overlap processing process of more data segments can be deduced by analogy.

上述进行交叠处理后的 F1个数据段分别进行快速傅立叶变换、频域 滤波、 傅立叶反变换， 经过上述处理后而得到的相应的 F1 个时域输出 数据段再进行如下所述的反交叠处理。  The F1 data segments after the above-mentioned overlap processing are respectively subjected to fast Fourier transform, frequency domain filtering, and inverse Fourier transform, and the corresponding F1 time-domain output data segments obtained after the above processing are then subjected to anti-overlap as described below. deal with.

现有技术中有多种反交叠处理的方法， 其中一种就是将需进行反交 叠处理的各个数据段按照交叠处理过程中的顺序直接进行叠加组合， 组 成希望得到的经过频域滤波之后的数据， 这种方法称为交叠相加方法， 上述现有技术二中就是使用了该种方法； 除上述的交叠相加方法外， 目 前还有一种更有效的交叠处理技术， 如图 3所示， 就是将各个需进行反 交叠处理的 F1个数据段前、后端的各 L/2个数据剔除，将各个数据段中 剩下的（N - L )个数据提出， 按照交叠处理过程中的顺序进行组合， 组 成希望得到的经过频域滤波处理之后的数据。 从图 3可以看出， 经过这 种交叠、 反交叠处理后， 输出的滤波数据比没有进行交叠处理前的输入 数据， 提前了 L/2个数据样点， 也就是使频域滤波的群延时减少了相应 的时间； 同时， 由于在反交叠处理过程中剔除了各个数据段的前、 后端 各 L/2个数据， 从而避免了数据段边缘的数据输出， 使得滤波效果有很 大的改善。 随着交叠长度 L的增大， 滤波的性能就越好， 但是同时也使 实现的资源大大增加， 成本升高。 所以， 在提高滤波性能的同时还必须 有效地解决实现的资源问题。 发明内容  There are various methods of anti-overlap processing in the prior art, and one of them is to directly superimpose and combine each data segment to be subjected to anti-overlap processing in the order of the overlap processing process to form the desired frequency-domain filtering. The following data, this method is called the overlapping addition method, which is used in the above-mentioned prior art 2. In addition to the above-mentioned overlapping addition method, there is currently a more effective overlapping processing technology. As shown in FIG. 3, the L / 2 data before and after each F1 data segment that needs to be anti-overlap processing is eliminated, and the remaining (N-L) data in each data segment are proposed, and The order in the overlapping process is combined to form the desired data after filtering in the frequency domain. It can be seen from FIG. 3 that after this overlap and anti-overlap processing, the output filtered data is L / 2 data samples earlier than the input data before the overlap processing, that is, the frequency domain filtering is performed. The group delay reduces the corresponding time. At the same time, because the front and back L / 2 data of each data segment are eliminated during the anti-overlap processing, the data output at the edge of the data segment is avoided, making the filtering effect There has been a great improvement. As the overlap length L increases, the filtering performance is better, but at the same time, the resources for implementation are greatly increased, and the cost is increased. Therefore, while improving the filtering performance, it is also necessary to effectively solve the implementation resource problem. Summary of the invention

有鉴于此， 本发明的主要目的在于提供一种频域滤波器及实现频域 滤波的方法， 在有效改善滤波性能和降低滤波器延时的同时， 还可大大 降低实现成本。 本发明进一步目的在于可以方便、 快捷、 动态地修改频 域滤波器的滤波特性。 In view of this, the main object of the present invention is to provide a frequency domain filter and a method for implementing frequency domain filtering, which can effectively improve the filtering performance and reduce the filter delay, and can also greatly reduce the implementation cost. A further object of the present invention is to make it possible to modify the frequency conveniently, quickly and dynamically. Filtering characteristics of the domain filter.

为达到上述目的， 本发明的技术方案是这样实现的：  To achieve the above object, the technical solution of the present invention is implemented as follows:

一种频域滤波器， 包括控制模块、 存储单元阵列、 滤波器系数存储 器、 数据切换模块、 旋转因子查表模块、 输出数据合并模块及至少一个 高速通用运算单元； 其中，  A frequency domain filter includes a control module, a storage unit array, a filter coefficient memory, a data switching module, a rotation factor look-up table module, an output data combining module, and at least one high-speed general-purpose arithmetic unit; wherein,

需要进行频域滤波的时域数据通过数据总线连接到所述的存储单元 阵列 , 该存储单元阵列通过数据总线将经过频域滤波处理的时域数据输 出至所述的输出数据合并模块 , 经增益调整后输出最终的时域数据； 所述的控制模块与存储单元阵列之间通过读 /写、 地址信号线相连 接；  The time-domain data that needs to be filtered in the frequency domain is connected to the storage unit array through a data bus, and the storage unit array outputs the time-domain data that has undergone the frequency-domain filtering process to the output data combining module through the data bus, and gains Output the final time-domain data after adjustment; the control module and the storage unit array are connected via read / write and address signal lines;

所述的控制模块连接外部输入的时域数据同步信号；  The control module is connected to an externally input time domain data synchronization signal;

所述的控制模块输出数据合并控制信号至所述的输出数据合并模 块， 控制滤波后的时域输出数据的选通及合并；  The control module outputs a data combination control signal to the output data combination module, and controls the gating and combination of the filtered time-domain output data;

所述的控制模块输出旋转因子查表控制信号至所述的旋转因子查表 模块，控制其在傅立叶正 /反变换时同步查表以及输出相应的旋转因子至 高速通用运算单元；  The control module outputs a rotation factor lookup table control signal to the rotation factor lookup module to control it to look up the table synchronously during Fourier forward / inverse transformation and output the corresponding rotation factor to a high-speed general-purpose arithmetic unit;

所述的控制模块输出数据切换控制信号至所述的数据切换模块， 控 制其对存储单元阵列输入 /输出数据的选通及对高速通用运算单元傅立 叶运算和频域滤波运算数据的切换， 存储单元阵列与数据切换模块及数 据切换模块与高速通用运算单元之间均通过双向数据总线相连；  The control module outputs a data switching control signal to the data switching module to control the gating of the input / output data of the memory cell array and the switching of the high-speed general-purpose arithmetic unit Fourier arithmetic and frequency domain filtering arithmetic data. The array and data switching module and the data switching module and the high-speed general-purpose computing unit are connected through a bidirectional data bus;

所述的控制模块输出状态控制信号至所述的高速通用运算单元， 控 制其傅立叶运算和频域滤波运算状态的切换；  The control module outputs a state control signal to the high-speed general-purpose arithmetic unit to control the switching of the Fourier arithmetic and frequency domain filtering arithmetic states;

所述的滤波器系数存储器接收来自主控制模块的同步控制信号， 将 计算系数送入高速通用运算单元； 或者， 接收外部的系数调整信号， 调 整自身存储的系数。 较佳地， 所述的存储单元阵列由至少两个存储单元构成。 The filter coefficient memory receives a synchronous control signal from the main control module, and sends the calculation coefficient to a high-speed general-purpose arithmetic unit; or receives an external coefficient adjustment signal and adjusts a coefficient stored by itself. Preferably, the memory cell array is composed of at least two memory cells.

较佳地， 所述的存储单元阵列是 RAM阵列。  Preferably, the memory cell array is a RAM array.

较佳地， 所述的存储单元是由至少 2个 RAM构成的 RAM组。 较佳地， 所述的滤波器系数存储器由至少一个 RAM构成。  Preferably, the storage unit is a RAM group composed of at least 2 RAMs. Preferably, the filter coefficient memory is composed of at least one RAM.

较佳地， 所述高速通用运算单元为蝶形运算单元。  Preferably, the high-speed general-purpose operation unit is a butterfly operation unit.

较佳地， 所述数据切换模块至少由输入选择器、 输出选择器、 输入 分路器、 输出分路器和至少两个输入输出切换单元构成； 所述的输入输 出切换单元与存储单元阵列中的存储单元在数目上相等， 并一一对应， 且各输入输出切换单元分别通过双向数据总线与其对应的存储单元连 接， 各输入输出切换单元的一路数据输出端均连接至所述的输入选择 器， 各输入输出切换单元的一路数据输入端均连接至所述的输出分路 器； 输入选择器的数据输出端连接所述的输入分路器； 输入分路器的两 路数据输出端连接所述的高速通用运算单元； 输出选择器的两路数据输 入端连接所述的高速通用运算单元， 输出选择器的数据输出端连接所述 的输出分路器。  Preferably, the data switching module is composed of at least an input selector, an output selector, an input splitter, an output splitter, and at least two input-output switching units; the input-output switching unit and the storage unit array The storage units are equal in number and correspond one-to-one, and each input-output switching unit is connected to its corresponding storage unit through a bidirectional data bus, and a data output terminal of each input-output switching unit is connected to the input selector. A data input end of each input-output switching unit is connected to the output splitter; a data output end of the input selector is connected to the input splitter; two data output ends of the input splitter are connected to The two-way data input terminals of the output selector are connected to the high-speed general-purpose operation unit, and the data output terminal of the output selector is connected to the output splitter.

较佳地， 所述的控制模块进一步输出同步控制信号至所述的滤波器 系数存储器， 控制其在使用期间处于写保护， 在空闲期间取消写保护， 可以进行滤波器系数的更新。  Preferably, the control module further outputs a synchronization control signal to the filter coefficient memory, controls it to be write protected during use, and cancels write protection during idle periods, so that filter coefficients can be updated.

一种实现频域滤波的方法， 包括以下步骤：  A method for implementing frequency domain filtering includes the following steps:

分别将需要进行频域滤波的各段时域数据交叠存储在一存储单元阵 列的各个存储单元中；  The time-domain data that needs to be filtered in the frequency domain is stored separately in each memory cell of a memory cell array;

将上述存储单元阵列存储的各段交叠的时域数据于不同时间段分别 在同一个高速通用运算单元中进行傅立叶变换运算、 频域滤波运算、 傅 立叶反变换运算， 并将经过上述滤波处理后的时域数据再存储在存储单 元阵列的各存储单元中； 依次选择读^ The overlapping time-domain data stored in the storage unit array is subjected to Fourier transform operation, frequency-domain filter operation, and inverse Fourier transform operation in the same high-speed general-purpose operation unit at different time periods, and after the filtering process is performed, Time-domain data is then stored in each storage unit of the storage unit array; Select Read ^

后的时域数据， 同时进行反交叠处理， 合并输出得到最终的时域数据； 并且， The subsequent time domain data, and simultaneously perform anti-overlap processing, and merge and output to obtain the final time domain data; and

对一段时域数据在存储单元阵列一存储单元的存储完成之前， 高速 通用运算单元对存储单元阵列前一存储单元存储的交叠的前一段时域 数据的傅立叶反变换运算已经完成。  Before a period of time-domain data is stored in a memory cell array, a high-speed general-purpose arithmetic unit has completed the inverse Fourier transform operation of the overlapped previous time-domain data stored in the previous memory cell of the memory cell array.

较佳地， 对反交叠处理后的时域数据进一步进行增益调整处理。 较佳地， 所述频域滤波运算中包含滤波系数， 该方法进一步包括对 所述频域滤波运算的滤波系数进行动态更新。  Preferably, the time-domain data after the anti-overlap processing is further subjected to a gain adjustment process. Preferably, the frequency domain filter operation includes a filter coefficient, and the method further includes dynamically updating a filter coefficient of the frequency domain filter operation.

较佳地， 对存储单元阵列中一存储单元存储的一段交叠时域数据在 高速通用运算单元中进行傅立叶变换运算、 频域滤波运算和傅立叶反变 换运算时， 其运算数据的读出和运算结果的写入是交替在存储单元的两 个存储器中同时进行。  Preferably, when performing a Fourier transform operation, a frequency domain filter operation, and an inverse Fourier transform operation on a section of overlapping time domain data stored in a memory cell in a memory cell array, the operation data is read and calculated. The result is written alternately in two memories of the memory cell simultaneously.

本发明针对普通频域滤波方案中数据段首尾附近滤波效果差和滤波 器延时较大的问题， 增加了数据的交叠、 反交叠处理， 通过适当地增加 交叠点数， 有效地的改善了滤波的效果和降低滤波器的延时； 本发明通 过时分复用， 用一个高速通用运算单元， 如蝶形运算单元， 就可完成多 个经过交叠处理的数据段的快速傅立叶变换、 快速傅立叶反变换、 频域 滤波运算等数据运算处理，节省了大量的运算单元,从而大大降低了资源 使用需求， 使实现更加方便， 实现成本大大降低。 同时， 本发明还提供 了一个滤波器系数存储器， 可以方便、快捷、动态的修改滤波器的系数， 在一些需要自适应滤波特性的***中可以得到很好的应用。  The present invention addresses the problems of poor filtering effect and large filter delay near the beginning and end of a data segment in a common frequency domain filtering solution, and adds data overlap and anti-overlap processing. By appropriately increasing the number of overlapping points, the problem is effectively improved. The filtering effect is reduced and the delay of the filter is reduced. The present invention uses time division multiplexing, and uses a high-speed general-purpose operation unit, such as a butterfly operation unit, to complete multiple fast-Fourier transforms of data segments that have undergone overlapping processing. Data operation processing such as inverse Fourier transform and frequency-domain filtering operation saves a large number of arithmetic units, thereby greatly reducing resource usage requirements, making implementation more convenient, and greatly reducing implementation costs. At the same time, the present invention also provides a filter coefficient memory, which can conveniently, quickly and dynamically modify the coefficients of the filter, and can be well applied in some systems that require adaptive filtering characteristics.

图 1为现有技术一的技术方案示意图; 图 2为现有技术二的技术方案示意图； Figure 1 is a schematic diagram of a technical solution of the prior art; FIG. 2 is a schematic diagram of a technical solution of the second prior art;

图 3为交叠、 反交叠处理技术原理示意图；  Figure 3 is a schematic diagram of the overlap and anti-overlap processing technology;

图 4为本发明的动态频域滤波处理原理示意图；  FIG. 4 is a schematic diagram of a dynamic frequency domain filtering processing principle of the present invention;

图 5为本发明的动态频域滤波器实现结构示意图；  5 is a schematic structural diagram of a dynamic frequency domain filter implementation according to the present invention;

图 6为本发明中一实施例中一个 RAM组的数据处理流程图 图 7为本发明的动态频域滤波器中的数据切换模块结构示意图； 图 8为本发明一实施例的数据处理总体时序图。 实施本发明的方式  6 is a data processing flowchart of a RAM group according to an embodiment of the present invention; FIG. 7 is a schematic structural diagram of a data switching module in a dynamic frequency domain filter of the present invention; FIG. 8 is an overall timing of data processing according to an embodiment of the present invention Illustration. Mode of Carrying Out the Invention

下面结合附图对本发明进行详细描述。  The present invention is described in detail below with reference to the drawings.

本发明中对信号进行动态频域滤波处理的原理如图 4所示， 包括以 下步骤：  The principle of performing dynamic frequency domain filtering on a signal in the present invention is shown in FIG. 4 and includes the following steps:

步骤 401 : 将输入的时域信号， 即输入数据流， 进行交叠处理， 使 其被分割成根据一定的交叠百分比进行重叠取值的多个数据段。  Step 401: Perform an overlap processing on the input time domain signal, that is, the input data stream, so that it is divided into a plurality of data segments that are overlapped and valued according to a certain overlap percentage.

步驟 402: 将经过交叠处理后的各数据段分别进行快速傅立叶变换。 步骤 403: 将经过快速傅立叶变换后得到的各段频域数据与滤波器 系数存储器中提供的频域滤波器系数相乘， 完成频域滤波运算。 其中， 频域滤波器的系数放置在一个滤波器系数存储器中， 该存储器可以由软 件或其他计算电路进行实时更新， 实现频域滤波器特性的动态修改。  Step 402: Perform fast Fourier transform on each data segment after the overlap processing. Step 403: Multiply each segment of the frequency domain data obtained after the fast Fourier transform with the frequency domain filter coefficients provided in the filter coefficient memory to complete the frequency domain filtering operation. The coefficients of the frequency domain filter are placed in a filter coefficient memory, which can be updated in real time by software or other calculation circuits to achieve dynamic modification of the characteristics of the frequency domain filter.

步骤 404: 将完成频域滤波的各个数据段分别进行快速傅立叶反变 换， 恢复成时域数据段。  Step 404: Perform fast Fourier inverse transform on each data segment that has been filtered in the frequency domain to restore the time domain data segment.

步驟 405: 将各时域数据段进行反交叠处理， 得到时域输出数据流。 在上述交叠及反交叠处理过程中， 随着交叠长度 L的增大， 所需的 运算资源等也大大增加， 从而导致成本升高。 为解决该问题， 必须提高 运算的效率， 并且有效的将运算和控制单元进行高度的复用。 由于在进 行傅立叶变换运算之前需进行时域数据的存储， 所以可在进行时域数据 的存储时将快速傅立叶运算的速率提高， 使得在等待时域数据存储期间 尽可能多地进行傅立叶变换运算。 一般的宽带通信***中， 基带时域数 据的传输速率往往在几兆赫兹以上， 所以， 可将数据传输速率倍频数十 倍后作为傅立叶变换的运算速率， 从而使运算单元等各种资源得到充分 的利用。 Step 405: Perform anti-overlap processing on each time domain data segment to obtain a time domain output data stream. During the above-mentioned overlap and anti-overlap processing, as the overlap length L increases, the required computing resources and the like also increase greatly, resulting in an increase in cost. In order to solve this problem, it is necessary to improve the efficiency of the operation and effectively perform a high degree of reuse of the operation and control units. Since in Before performing the Fourier transform operation, the time domain data needs to be stored. Therefore, the speed of the fast Fourier operation can be increased when the time domain data is stored, so that the Fourier transform operation can be performed as much as possible while waiting for the time domain data storage. In a general broadband communication system, the transmission rate of baseband time-domain data is often more than a few megahertz. Therefore, the data transmission rate can be multiplied by dozens of times as the operation rate of the Fourier transform, so that various resources such as the operation unit can be obtained. designation.

基于较低速率的时域数据输入和高速的傅立叶变换的运算模块， 可 设计一种性能优良、 低成本的动态频域滤波方案， 其实现结构如图 5所 示。  Based on the lower-rate time-domain data input and the high-speed Fourier transform operation module, a dynamic frequency-domain filtering scheme with excellent performance and low cost can be designed. The implementation structure is shown in Figure 5.

本发明的主要特点之一是使用了一个存储单元阵列， 该阵列由至少 2个独立的存储单元构成， 为经过交叠处理后的数据段和傅立叶运算、 滤波运算的中间数据提供存储空间， 该存储单元阵列可以是随机存取存 贮器（RAM ) 阵列。 以 RAM阵列为例， RAM阵列中的每一个存储单 元称为一个 RAM组，每一个 RAM组由至少 2个 RAM构成， 其功能是 完成数据运算的原位存储。 在同一时间， 两个 RAM中只能是一个处于 读状态， 另一个处于写状态， 处于读状态的那个 RAM负责将需要进行 计算的数据以数据流的方式读出， 送给计算单元； 计算结果则可存储到 同组的另一个处于写状态的 RAM。  One of the main features of the present invention is the use of an array of memory cells, which is composed of at least two independent memory cells, and provides storage space for the data segments after the overlap processing and the intermediate data of Fourier operations and filtering operations. The memory cell array may be a random access memory (RAM) array. Taking the RAM array as an example, each storage unit in the RAM array is called a RAM group, and each RAM group is composed of at least 2 RAMs, and its function is to complete the in-situ storage of data operations. At the same time, only one of the two RAMs is in the read state and the other is in the write state. The RAM in the read state is responsible for reading the data that needs to be calculated in a data stream manner and sending it to the calculation unit; the calculation result Can be stored in another write RAM in the same group.

另外， 本发明利用高速集成电路芯片的特点， 使用了一个高速的通 用运算单元， 如蝶形运算单元， 该单元可通过上述存储单元阵列及本发 明提供的一种数据切换模块进行时分复用， 为其他运算提供资源。  In addition, the present invention utilizes the characteristics of a high-speed integrated circuit chip, and uses a high-speed general-purpose arithmetic unit, such as a butterfly arithmetic unit, which can be time-division multiplexed through the above-mentioned storage unit array and a data switching module provided by the present invention. Provide resources for other operations.

同时， 本发明还提供了一个可由外部控制的滤波器系数存储器， 其 功能是可动态地修改频域滤波器的滤波特性， 并使得外部对滤波器系数 的更新与滤波运算过程实现同步。  At the same time, the invention also provides an externally controllable filter coefficient memory, whose function is to dynamically modify the filtering characteristics of the frequency domain filter, and to synchronize the external update of the filter coefficients with the filtering operation process.

以存储单元阵列为 RAM阵列为例， 如图 5所示： 本发明提供的一 种动态频域滤波器包括控制模块 501、 存储单元阵列 502、 滤波器系数 存储器 503、 数据切换模块 504、 输出数据合并模块 506、 旋转因子查表 模块 507以及至少一个高速通用运算单元 505; 控制模块 501有 6路控 制信号输出端， 分别连接所述的存储单元阵列 502、 滤波器系数存储器 503、数据切换模块 504、高速通用运算单元 505、输出数据合并模块 506 和旋转因子查表模块 507, 控制模块 501还有一路外部控制信号输入端 口。 Taking the memory cell array as a RAM array as an example, as shown in FIG. 5: A dynamic frequency domain filter includes a control module 501, a storage unit array 502, a filter coefficient memory 503, a data switching module 504, an output data combining module 506, a rotation factor lookup table module 507, and at least one high-speed general-purpose arithmetic unit 505; a control module 501 has six control signal output terminals, which are respectively connected to the storage unit array 502, the filter coefficient memory 503, the data switching module 504, the high-speed general-purpose arithmetic unit 505, the output data combining module 506, and the rotation factor look-up table module 507. The module 501 also has an external control signal input port.

其中， 控制信号 10 是提供存储单元阵列的读写控制和选通控制信 号， 控制数据的输入、 输出、 交叠、 反交叠、 蝶形运算、 频域滤波等处 理的读写； 控制信号 11 是输出数据合并控制信号， 控制不同存储单元 的最终时域输出数据的选通、 合并； 控制信号 12是滤波器系数存储器 的同步控制信号 , 控制滤波器系数存储器将计算系数送入高速通用运算 单元， 同时， 在存储器系数使用期间进行存储器的写保护， 在空闲状态 中取消写保护， 可以进行系数的更新； 控制信号 13 是旋转因子查表控 制信号， 使旋转因子的查表与傅立叶运算同步， 并在傅立叶正、 反变换 时控制输出相应的旋转因子； 控制信号 14是高速通用运算单元的状态 控制信号， 实现对该单元的蝶形运算状态和频域滤波运算状态之间的切 换控制； 控制信号 15 是数据切换控制信号， 通过对存储单元和高速通 用运算单元的输入输出数据的选通控制， 实现了高速通用运算单元对多 个存储单元数据运算的时分复用， 并实现对蝶形运算、 频域滤波运算数 据的输入切换控制； 外部控制信号 16是外部的时域数据输入的同步信 号， 使控制模块与外部输入数据的时序同步。  Among them, the control signal 10 is a read-write control and a strobe control signal that provides a memory cell array, and controls the read and write of data input, output, overlap, anti-overlap, butterfly operation, and frequency-domain filtering. Control signal 11 It is an output data combination control signal to control the gating and combination of the final time-domain output data of different storage units. The control signal 12 is a synchronous control signal of the filter coefficient memory, which controls the filter coefficient memory to send the calculation coefficients to the high-speed general-purpose arithmetic unit. At the same time, write protection of the memory is performed during the use of the memory coefficients, and write protection is canceled in the idle state to update the coefficients; the control signal 13 is a rotation factor lookup table control signal, so that the lookup table of the rotation factor is synchronized with the Fourier operation, And control the corresponding rotation factor during Fourier forward and inverse transformation; the control signal 14 is a state control signal of the high-speed general-purpose arithmetic unit, and realizes switching control between the butterfly operation state and the frequency domain filtering operation state of the unit; control Signal 15 is the data switching control signal Through the gating control of the input and output data of the storage unit and the high-speed general-purpose arithmetic unit, the high-speed general-purpose arithmetic unit realizes time-division multiplexing of multiple memory unit data operations, and realizes the input of butterfly operation and frequency-domain filtering operation data. Switching control; The external control signal 16 is a synchronization signal for external time-domain data input, which synchronizes the control module with the timing of the external input data.

首先， 控制模块 501向 RAM阵列 502发出控制信号 10, 通过该控 制信号对各存储单元写地址操作的控制， 在时域数据 1经过输入数据总 线输入到 RAM阵列 502的输入过程 2中完成图 3所示的交叠处理， 并 将交叠处理过程中产生的各个时域数据段逐个分配到 RAM阵列 502中 的各个存储单元， 即 RAM组中； 各个数据段的所有处理过程中所需的 存储空间， 由该数据段所在的 RAM组提供。 First, the control module 501 sends a control signal 10 to the RAM array 502. The control signal is used to control the write operation of each memory cell. The time domain data 1 is input to the RAM array 502 via the input data bus. As shown in the overlapped processing, and All the time-domain data segments generated during the overlap processing are allocated to each storage unit in the RAM array 502, that is, in the RAM group; the storage space required during all processing of each data segment is determined by the location of the data segment. RAM group provided.

然后，根据控制模块 501向 RAM阵列 502、旋转因子查表模块 507、 高速通用运算单元 505、数据切换模块 504分别发出的控制信号 10、 13、 14、 15 , 各个 RAM组中的存储数据与高速通用运算单元 505 , 以下高 速通用运算单元 505以蝶形运算单元为例， 该单元中可以有 4个并行的 乘法器和 6个加法器， 通过数据切换模块 504进行高速的交换， 即将数 据从 RAM组中读出并通过双向数据总线 5上送入数据切换模块 504, 在数据切换模块 504中经数据切换后， 将需要进行蝶形运算的数据经双 向数据总线 6输入蝶形运算单元 505与旋转因子查表模块 507同步输出 的相应的旋转因子 7进行蝶形运算。 经过蝶形运算处理后的数据经双向 数据总线 6传输给数据切换模块 504进行分配， 再经双向数据总线 5写 入到 RAM阵列 502中相应的 RAM组。 根据快速傅立叶运算的原理， 多次重复以上过程， 即可将原输入的时域数据全部转换为与其相对应的 频域数据， 即完成了快速傅立叶变换。  Then, according to the control signals 10, 13, 14, and 15 sent from the control module 501 to the RAM array 502, the rotation factor look-up table module 507, the high-speed general-purpose arithmetic unit 505, and the data switching module 504, the stored data in each RAM group and the high-speed A general-purpose arithmetic unit 505. The following high-speed general-purpose arithmetic unit 505 uses a butterfly arithmetic unit as an example. This unit can have 4 parallel multipliers and 6 adders. High-speed exchange is performed through the data switching module 504. That is, data is transferred from RAM. The data in the group is read out and sent to the data switching module 504 through the bidirectional data bus 5. After the data is switched in the data switching module 504, the data to be subjected to the butterfly operation is input to the butterfly operation unit 505 and the rotation through the bidirectional data bus 6. The corresponding rotation factor 7 synchronously output by the factor look-up table module 507 performs a butterfly operation. The data processed by the butterfly operation is transmitted to the data switching module 504 via the bidirectional data bus 6 for distribution, and then written to the corresponding RAM group in the RAM array 502 via the bidirectional data bus 5. According to the principle of fast Fourier operation, repeating the above process multiple times, all the original input time-domain data can be converted into the corresponding frequency-domain data, and the fast Fourier transform is completed.

接着，根据控制模块 501向 RAM阵列 502、滤波器系数存储器 503、 高速通用运算单元 505、数据切换模块 504分别发出的控制信号 10、 12、 14、 15 , 相应 RAM组中的频域数据和滤波器系数存储器 503中相应的 滤波器系数 9被同步地送入蝶形运算单元 505， 在该单元中进行相乘运 算，完成滤波运算。滤波运算后的结果经数据切换模块 504被送入 RAM 阵列 502中相应的 RAM组进行存储，准备进行快速傅立叶反变换处理。  Then, according to the control signals 10, 12, 14, 15 respectively sent from the control module 501 to the RAM array 502, the filter coefficient memory 503, the high-speed general-purpose arithmetic unit 505, and the data switching module 504, the frequency-domain data and filtering in the corresponding RAM group The corresponding filter coefficient 9 in the filter coefficient memory 503 is synchronously sent to the butterfly operation unit 505, and a multiplication operation is performed in this unit to complete the filtering operation. The result of the filtering operation is sent to the corresponding RAM group in the RAM array 502 via the data switching module 504 for storage, and is ready for inverse fast Fourier transform processing.

接着，根据控制模块 501向 RAM阵列 502、旋转因子查表模块 507、 高速通用运算单元 505、数据切换模块 504分别发出的控制信号 10、 13、 14、 15 , 各个 RAM组中的存储数据通过数据切换模块 504与蝶形运算 单元 505进行高速的交换， 即将数据从 RAM组中读到双向数据总线 5 上送入数据切换模块 504， 在数据切换模块 504中经数据切换后， 将需 要进行蝶形运算的数据经双向数据总线 6输入蝶形运算单元 505与旋转 行蝶形运算。 经过蝶形运算处理后的数据经双向数据总线 6传输给数据 切换模块 504进行分配， 再经双向数据总线 5写入到 RAM阵列 502中 相应的 RAM组。 多次重复以上过程， 即可将需转换的频域数据全部转 换为与其相对应的时域数据， 即完成了快速傅立叶反变换。 Then, according to the control signals 10, 13, 14, and 15 sent from the control module 501 to the RAM array 502, the rotation factor look-up table module 507, the high-speed general-purpose arithmetic unit 505, and the data switching module 504, the stored data in each RAM group passes the data. Switching module 504 and butterfly operation The unit 505 performs high-speed exchange, that is, reads data from the RAM group to the bidirectional data bus 5 and sends the data to the data switching module 504. After the data is switched in the data switching module 504, the data that needs to perform butterfly operations is passed through the bidirectional data bus. The 6-input butterfly operation unit 505 and the rotation row butterfly operation. The data processed by the butterfly operation is transmitted to the data switching module 504 for distribution via the bidirectional data bus 6 and then written to the corresponding RAM group in the RAM array 502 via the bidirectional data bus 5. By repeating the above process multiple times, all the frequency-domain data to be converted can be converted into the corresponding time-domain data, that is, the inverse fast Fourier transform is completed.

根据控制模块 501向 RAM阵列 502、输出数据合并模块 506分别发 出的控制信号 10、 11 , 从相应的 RAM組中输出反交叠处理所需的输出 数据 3; 各存储单元读出的不同的数据段在输出数据合并模块 506中经 过如图 3所示的反交叠处理， 并且进行相应的快速傅立叶反变换结果的 增益调整后， 即可得到最终的时域输出数据 4, 从而达到了频域滤波的 目的。  According to the control signals 10 and 11 issued by the control module 501 to the RAM array 502 and the output data merging module 506, the output data required for anti-overlap processing is output from the corresponding RAM group 3; different data read by each storage unit After the segment is subjected to the anti-overlap processing shown in FIG. 3 in the output data merge module 506 and the gain of the corresponding inverse fast Fourier transform result is adjusted, the final time-domain output data 4 can be obtained, thereby achieving the frequency domain. The purpose of filtering.

图 5中所示的滤波器系数存储器 503由至少一个 RAM构成， 可以 从外部对滤波器系数存储器中的滤波器系数进行动态的调整， 从而实现 频域滤波器特性的动态更新， 该动态更新可由软件或计算电路完成。 外 部输入的对滤波器系数存储器中相应数据 8的更新， 可以在不进行滤波 运算时写入滤波器系数存储器， 为进行下一次频域滤波做好准备。  The filter coefficient memory 503 shown in FIG. 5 is composed of at least one RAM, and the filter coefficients in the filter coefficient memory can be dynamically adjusted from the outside, so as to achieve dynamic update of the frequency domain filter characteristics. The dynamic update can be performed by Software or calculation circuit is done. The update of the corresponding data 8 in the filter coefficient memory input from the outside can be written into the filter coefficient memory when no filtering operation is performed, so as to prepare for the next frequency domain filtering.

图 6所示为一个 RAM组中的两个 RAM的数据处理流程图。 如果 需进行的傅立叶变换的计算长度是 2N个数据点， 则傅立叶正、 反变换 都需进行 N级的蝶形运算处理。 通过如图 6所示的流程图， .以 N=8即 需进行的傅立叶变换的计算长度是 256个数据点为例 , 在一个 RAM组 中， 通过对两个 RAM轮换读写的操作， 可以高速地完成所需的运算处 理。 最后， 在该流程结束时的数据输出时， 只是对 RAM2进行读操作， 而此时的 RAMI就已经可以进行下一段数据的输入处理了。通过反复进 行上述流程， 可以实现对数据流的高速处理， 并可有效提高交叠处理的 交叠比例。 FIG. 6 shows a data processing flowchart of two RAMs in a RAM group. If the calculation length of the Fourier transform to be performed is 2N data points, both the Fourier forward and inverse transforms need to perform N-level butterfly operation processing. According to the flowchart shown in FIG. 6, taking the calculation length of the Fourier transform required for N = 8 as an example, 256 data points, in a RAM group, by rotating read and write operations on two RAMs, it is possible to Complete the required arithmetic processing at high speed. Finally, when the data is output at the end of the process, only the RAM2 is read. At this time, the RAMI can already perform the input processing of the next segment of data. By repeating the above process, high-speed processing of the data stream can be achieved, and the overlap ratio of the overlap processing can be effectively increased.

在图 5中所示的动态频域滤波器实现结构示意图中， 关于数据切换 模块 504的详细描述， 以与其连接的 RAM阵列 502由 3个独立的存储 单元， 即 3个 RAM組构成为例， 如图 7所示。  In the schematic diagram of the implementation structure of the dynamic frequency domain filter shown in FIG. 5, for a detailed description of the data switching module 504, a RAM array 502 connected to the data switching module 504 is composed of 3 independent storage units, that is, 3 RAM groups. As shown in Figure 7.

图 7中的 RAM阵列 502包括 3个 RAM组，每个 RAM组中包含两 个 RAM。 在同一时间， 两个 RAM中只能是一个处于读状态， 另一个处 于写状态。 处于读状态的那个 RAM负责将需要进行计算的数据以数据 流的方式读出， 送给计算单元； 计算结果则可存储到同组的另一个处于 写状态的 RAM。 这样， 同组的两个 ΚλΜ按图 6所示的流程进行 N次 读写操作， 即可完成 2N个数据的傅立叶变换。  The RAM array 502 in FIG. 7 includes three RAM groups, and each RAM group includes two RAMs. At the same time, only one of the two RAMs is in the read state and the other is in the write state. The RAM in the read state is responsible for reading the data to be calculated in a data stream manner and sending it to the computing unit; the calculation result can be stored in another write RAM in the same group. In this way, two KλMs in the same group perform N read and write operations according to the flow shown in FIG. 6 to complete the Fourier transform of 2N data.

如图 7所示， 数据切换模块 504至少由输入选择器 702、 输出分路 器 703、 输入分路器 704、 输出选择器 705和至少两个输入输出切换单 元 701构成。 数据切换模块 504中输入输出切换单元 701的数目与存储 单元阵列存储单元的个数相等， 并与存储单元阵列中的存储单元一一对 应。 在本实施例中， 所述存储单元阵列为 RAM阵列 502, 数据切换模 块 504中有 3个输入输出切换单元 701， 且每个输入输出切换单元 701 分别与 RAM阵列 502中的 RAM组——对应， 其作用是使与其所连接 的 RAM組与选择器之间进行数据交换， 并确保其所连接的 RAM组中 的两个 RAM处在正确的读或写的状态中。 输入选择器 702是一个多选 一模块， 当数据切换模块 504中有 3个输入输出切换单元 701时， 输入 选择器 702可以是一个三选一模块， 并可依此类推， 以下以输入选择器 702是一个三选一模块为例进行说明。 该输入选择器 702的作用是根据 通用运算单元所处的时分复用的状态， 通过控制信号 15从由 3个输入 输出切换单元 701传输的 3个 RAM组的输出数据中选择其中一个 RAM 组的输出数据， 传输给输入分路器 704, 输入分路器 704根据控制信号 15判断该数据需进行蝶形运算还是需进行频域滤波运算后，再将该数据 送给高速通用运算单元 505中相应的运算单元。 输出选择器 705是一个 二选一模块，其作用是根据控制信号 15判断当前高速通用运算单元 505 所处的运算状态， 再对其输出的频域滤波输出数据和蝶形运算输出数据 进行二选一的选择， 得到所需的输出数据， 然后将该数据传输给输出分 路器 703。 输出分路器 703根据控制信号 15判断高速通用运算单元 505 当前所处的时分复用的状态， 再将该数据分配给相应的正在进行数据读 写的 RAM组所连接的输入输出切换单元 701。 该数据再经过输入输出 切换单元 701的输入输出切换， 将数据送给当前 RAM组中负责数据存 储的 RAM, 完成数据的存储。 上述数据切换模块 504对时分复用的数 据控制和运算状态的切换时序分别由上述控制信号 15进行控制。 As shown in FIG. 7, the data switching module 504 includes at least an input selector 702, an output splitter 703, an input splitter 704, an output selector 705, and at least two input-output switching units 701. The number of input-output switching units 701 in the data switching module 504 is equal to the number of storage units in the storage unit array, and corresponds one-to-one to the storage units in the storage unit array. In this embodiment, the storage unit array is a RAM array 502, and there are three input-output switching units 701 in the data switching module 504, and each input-output switching unit 701 corresponds to a RAM group in the RAM array 502, respectively-corresponding to Its role is to enable data exchange between the RAM group and the selector connected to it, and to ensure that the two RAMs in the connected RAM group are in the correct read or write state. The input selector 702 is a multi-select one module. When there are three input-output switching units 701 in the data switching module 504, the input selector 702 may be a three-select one module, and so on. The input selector is hereinafter 702 is a three-choice one module as an example for illustration. The function of the input selector 702 is based on the time division multiplexing state of the general-purpose arithmetic unit, and the control signal 15 is used to select from three inputs. The output data of one of the three RAM groups selected from the output data of the three RAM groups transmitted by the output switching unit 701 is transmitted to the input splitter 704, and the input splitter 704 judges whether the data needs to perform a butterfly operation or needs to be controlled according to the control signal 15. After performing a frequency domain filtering operation, the data is then sent to a corresponding operation unit in the high-speed general-purpose operation unit 505. The output selector 705 is a two-choice one-module, and its role is to determine the current computing state of the high-speed general-purpose arithmetic unit 505 according to the control signal 15, and then perform two selections on its output frequency-domain filtered output data and butterfly operation output data. Select one to obtain the required output data, and then transmit the data to the output splitter 703. The output splitter 703 determines the state of the time division multiplexing of the high-speed general-purpose arithmetic unit 505 according to the control signal 15, and then allocates the data to the input / output switching unit 701 connected to the corresponding RAM group that is performing data reading and writing. This data is then input-output switched by the input-output switching unit 701, and the data is sent to the RAM in charge of data storage in the current RAM group to complete the data storage. The data switching module 504 controls the time division multiplexed data control and the switching timing of the operation state by the control signal 15 respectively.

上述的对数据切换模块的描述均是以存储单元阵列为 RAM阵列， 且 RAM阵列由 3个 RAM组构成为例而进行的说明， 当存储单元阵列 的不是 RAM阵列而是由其他类型的存储单元构成， 或 RAM阵列中的 RAM組的数目为 2或大于 3时， 上述数据切换的方法也同样适用， 只 是数据切换模块的构造将做相应地进行变化， 以适合数据切换的需要。 另外， 由于上述数据切换模块内的各个子模块均较筒单， 因而所谓数据 切换模块内构造的变化， 只是整体的电路结构需适应 RAM阵列和时分 复用的通用运算单元的接口要求。  The above descriptions of the data switching module are all described by taking the memory cell array as a RAM array and the RAM array consisting of three RAM groups as an example. When the memory cell array is not a RAM array, it is composed of other types of memory cells. When the composition or the number of RAM groups in the RAM array is 2 or more, the above data switching method is also applicable, except that the structure of the data switching module will be changed accordingly to meet the needs of data switching. In addition, since each of the sub-modules in the above-mentioned data switching module is relatively simple, the structure change in the so-called data switching module is just that the overall circuit structure needs to adapt to the interface requirements of the RAM array and the general-purpose operation unit of time division multiplexing.

基于图 5所示的动态频域滤波器实现结构示意图， 本发明一具体实 施例中数据处理的总体时序如图 8所示。 图 8中的点状图形表示时域输 入数据， 纵线图形表示傅立叶正反变换和频域滤波运算， 横线图形表示 滤波后的时域输出数据。 在该具体实施例中， 输入的时域数据传输速率 为 2.4576兆赫兹，需要进行计算长度为 256个数据点的快速傅立叶变换 实现频域滤波， 数据的交叠长度要求为 140个数据点。 将时域数据传输 速率进行倍频 25倍后作为蝶形运算的速率， 即 61.44兆赫兹。 Based on the schematic diagram of the implementation structure of the dynamic frequency domain filter shown in FIG. 5, the overall timing of data processing in a specific embodiment of the present invention is shown in FIG. The dotted graphs in FIG. 8 represent time-domain input data, the vertical graphs represent Fourier transform and frequency-domain filtering operations, and the horizontal graphs represent filtered time-domain output data. In this specific embodiment, the input time-domain data transmission rate For 2.4576 MHz, a fast Fourier transform with a calculation length of 256 data points is required to implement frequency domain filtering. The overlapping length of the data is required to be 140 data points. The time-domain data transmission rate is multiplied by 25 times as the butterfly operation rate, that is, 61.44 MHz.

如图 8所示：在频域滤波处理开始时， RAM组 1开始对输入时域数 据流的包括第 1个数据点在内的前 256个数据点的第一个数据段进行处 理， 即将该段时域数据存入 RAM组 1中， 即 801中的点状图形； 当该 段输入时域数据的存储完成后， 通过数据切换模块 504将 RAM组 1中 的存储数据传输到高速通用运算单元 505 中进行傅立叶变换的蝶形运 算，此时旋转因子模块 507同步地进行查表，提供运算所需的旋转因子， 运算结果存回 RAM组 1中； 蝶形运算处理完毕后， 高速通用运算单元 505切换到频域滤波的运算状态， 此时滤波器系数存储器 503也同步的 输出滤波器系数，与通过数据切换模块 504传输到高速通用运算单元 505 中的 RAM组 1中的暂存的蝶形运算之后的频域数据进行频域滤波的运 算， 运算结果存回 RAM组 1中； 滤波运算处理完毕后， 高速通用运算 单元 505再切换回蝶形运算状态， 对 RAM组 1中暂存的滤波之后的频 域数据进行傅立叶反变换， 得到时域数据，运算结果存回 RAM组 1中， 以上的傅立叶正反变换和频域滤波的运算均由 801中的纵线图形表示； 完成上述处理后的数据立即通过输出数据合并模块 506, 对 RAM组 1 中的输出数据进行选择、 输出， 完成反交叠后的数据输出， 输出数据由 801中的横线图形表示。 同理， 数据段 802、 803、 804、 805、 …的处理 方式与上述处理方式相同， 各数据段输出的数椐即所有数据段的横线部 分就能合成完整的经过滤波后的输出时域数据。  As shown in FIG. 8: At the start of the frequency domain filtering process, the RAM group 1 starts processing the first data segment of the first 256 data points including the first data point of the input time domain data stream. Segment time-domain data is stored in RAM group 1, that is, a dot pattern in 801. After the storage of the input time-domain data in this segment is completed, the data stored in RAM group 1 is transferred to the high-speed general-purpose arithmetic unit through the data switching module 504. The butterfly operation of Fourier transform is performed in 505. At this time, the rotation factor module 507 performs a table lookup synchronously, and provides the rotation factor required for the operation. The operation result is stored in the RAM group 1. After the butterfly operation is processed, the high-speed general-purpose operation unit 505 switches to the frequency-domain filtering operation state. At this time, the filter coefficient memory 503 also outputs the filter coefficients in synchronization with the temporarily stored butterfly in the RAM group 1 in the high-speed general-purpose arithmetic unit 505 through the data switching module 504. The frequency-domain data after the operation is subjected to a frequency-domain filtering operation, and the operation result is stored in the RAM group 1. After the filtering operation is completed, the high-speed general-purpose operation unit 505 Switch back to the butterfly operation state, perform inverse Fourier transform on the frequency-domain data temporarily stored in RAM group 1 to obtain time-domain data, and store the operation result in RAM group 1. The above Fourier inverse transform and frequency-domain filtering The operations are represented by the vertical line graphics in 801; the data after the above processing is immediately passed to the output data merge module 506 to select and output the output data in the RAM group 1, and complete the output of the anti-overlap data to output the data It is represented by the horizontal line graph in 801. In the same way, the processing modes of the data segments 802, 803, 804, 805, ... are the same as the above processing methods, and the data output by each data segment, that is, the horizontal line portion of all data segments, can be synthesized into a complete filtered output time domain. data.

因为要进行交叠处理并且实现对高速通用单元的时分复用， 所以可 在输入时域数据流的第 117个数据点输入 RAM组 1的同时将该数据点 后， 包括该数据点在内的 256个数据点的第 2段数据存储到 RAM组 2 中即 802 中的点状图形； 并在输入时域数据流的第 233 个数据点输入 RAM组 1、 RAM组 2的同时将该数据点后， 包括该数据点在内的 256 个数据点的第 3段数据存储到 RAM组 3中即 803中的点状图形；在 RAM 组 2的时域数据输入完毕之前， 高速通用运算模块对 RAM组 1中存储 数据的处理已经完毕，可立即开始对 RAM组 2中的存储数据进行处理； 同时， 由于 RAM组 1中的数据已经处理完毕， 已可接收新的数据进行 存储， 所以在输入时域数据流的第 349个数据点输入 RAM组 2 、 RAM 组 3的同时将该数据点后， 包括该数据点在内的 256个数据点的第 4段 数据重新存储到 RAM组 1中即 804中的点状图形； 同理， RAM组 3的 时域数据输入完毕之前， 高速通用运算模块 505对 RAM组 2中存储数 据的处理已经完毕， 可立即开始对 RAM组 3中的存储数据进行处理； 同时， 由于 RAM组 2中的数据已经处理完毕， 已可接收新的数据进行 存储， 所以在输入时域数据流的第 465个数据点输入 RAM组 3、 RAM 组 1的同时将该数据点后， 包括该数据点在内的 465个数据点的第 5段 数据重新存储到 RAM组 2中即 805中的点状图形； 依次类推， 反复进 行 RAM阵列中 3个 RAM组的轮换， 便可以实现交叠长度为 140个数 据点的交叠处理， 并且， 由于按照这种数据处理方式， 3个 RAM组和 一个高速通用运算单元可进行反复轮换的滤波处理， 完成正常的滤波运 算， 从而也实现了高速通用运算单元的时分复用。 Because overlapping processing is required and time division multiplexing of high-speed general-purpose units is implemented, the 117th data point of the time-domain data stream can be input to RAM group 1 and the data points can be 2nd data of 256 data points are stored in RAM group 2 That is, the dot pattern in 802; and after inputting the 233th data point of the time-domain data stream into RAM group 1 and RAM group 2, after the data point, the 256 data points including the data point The third segment of data is stored in the RAM group 3, that is, the dot pattern in 803; before the time domain data of the RAM group 2 is input, the processing of the data stored in the RAM group 1 by the high-speed general-purpose arithmetic module is completed, and the data can be immediately started. The data stored in the RAM group 2 is processed. At the same time, since the data in the RAM group 1 has been processed, new data can be received for storage, so the 349th data point of the input time domain data stream is input into the RAM group 2, After RAM group 3 simultaneously stores the data point, the fourth segment of data of 256 data points including the data point is re-stored into the dot pattern in RAM group 1, that is, 804; Similarly, the time of RAM group 3 Before the input of the domain data is completed, the high-speed general-purpose arithmetic module 505 has finished processing the data stored in the RAM group 2 and can immediately start processing the data stored in the RAM group 3. At the same time, since the data in the RAM group 2 has been processed, Ready to receive new The data is stored, so after inputting the 465th data point of the time domain data stream into the RAM group 3 and the RAM group 1, the data point is restored, and the fifth segment of the 465 data points including the data point is re-used. Dot pattern stored in RAM group 2 or 805; and so on, and repeating the rotation of the 3 RAM groups in the RAM array repeatedly, the overlap processing with an overlap length of 140 data points can be realized. This kind of data processing method, 3 RAM groups and a high-speed general-purpose arithmetic unit can perform repeated rotation filtering processing to complete normal filtering operations, thereby realizing time division multiplexing of the high-speed general-purpose arithmetic unit.

在本实施例中， 所有数据段进行交叠处理后的快速傅立叶正反变换 以及频域滤波运算都可以通过时分复用的方法用同一个蝶形运算单元 来完成， 从而大大地节约了电路实现资源; 并且， 仅通过 3个独立存储 单元就实现了交叠百分比为 55 %的交叠及反交叠处理，可以完全满足单 位脉冲响应为 140阶的滤波器的性能要求； 同时， 此实施例还将频域滤 波器的群延时降低了 70个数据点釆样时间， 即 28.5微秒。 本发明的电路实现方案和应用应包括、 但不限于上述具体实施例。 本发明中所述的傅立叶变换是应用基 2算法的快速傅立叶变换， 在实际 应用中， 也可以使用其他的快速傅立叶变换算法， 如基 4算法等， 与之 相应的蝶形运算单元的内部结构也会有相应调整； 同时， 所述的高速通 用运算单元可以是蝶形运算单元， 也可以是其他的运算单元； 本发明中 所使用的交叠、 反交叠处理技术可以是图 3所示的处理方法， 也可以是 交叠相加方式或其他的交叠、 反交叠处理方法； 另外， 可以根据时域数 据传输速率的不同、 频域分辨率要求的不同、 交叠百分比的不同以及蝶 形运算速率的不同， 改变快速傅立叶变换的长度和交叠长度， 或增加或 减少存储单元阵列中存储器组的数量， 也可以增加高速通用运算单元的 数量， 以便在实现成本和滤波效果之间得到更加满足需求的平衡点。 本 发明的电路实现方案可以通过专用集成电路芯片实现， 也可以使用可编 程逻辑器件实现； 可以应用在包括通信***信号的接收、 发射在内的多 种数字信号处理场合中。 In this embodiment, the fast Fourier transform and inverse transform and frequency-domain filter operations after all data segments are overlapped can be completed by the same butterfly operation unit through time division multiplexing, thereby greatly saving circuit implementation. Moreover, the overlap and anti-overlap processing with an overlap percentage of 55% is realized by only 3 independent storage units, which can fully meet the performance requirements of a filter with a unit impulse response of order 140; at the same time, this embodiment The group delay of the frequency-domain filter is also reduced by 70 data points, which is 28.5 microseconds. The circuit implementation scheme and application of the present invention should include, but not limited to, the specific embodiments described above. The Fourier transform described in the present invention is a fast Fourier transform using a base-2 algorithm. In practical applications, other fast Fourier transform algorithms such as the base-4 algorithm can also be used, and the internal structure of the corresponding butterfly operation unit. There will also be corresponding adjustments; at the same time, the high-speed general-purpose operation unit may be a butterfly operation unit or other operation units; the overlap and anti-overlap processing technology used in the present invention may be as shown in FIG. 3 The processing method may also be an overlapping addition method or other overlapping and anti-overlap processing methods. In addition, it may be based on different time domain data transmission rates, different frequency domain resolution requirements, different overlap percentages, and The difference in butterfly operation speed changes the length and overlap length of the fast Fourier transform, or increases or decreases the number of memory banks in the memory cell array, and also increases the number of high-speed general-purpose arithmetic units, so as to achieve a cost between filtering and filtering effects. Get a balance that better meets your needs. The circuit implementation scheme of the present invention can be implemented by an application-specific integrated circuit chip or a programmable logic device; it can be applied to a variety of digital signal processing occasions including reception and transmission of communication system signals.

综上所述， 本发明以高速的集成电路芯片器件（如 ASIC或 FPGA ) 为电路实现的基础， 在尽量节省芯片资源、 降低实现成本的前提下， 解 决了传统频率滤波结构的不足之处， 提供了一个完善的基于快速傅立叶 正反变换（FFT / IFFT )、 滤波器的滤波特性可动态变化的高效滤波器的 实现方案。  In summary, the present invention uses a high-speed integrated circuit chip device (such as ASIC or FPGA) as the basis for circuit implementation, and solves the shortcomings of the traditional frequency filtering structure on the premise of saving chip resources and reducing implementation costs as much as possible. Provides a complete high-efficiency filter implementation scheme based on Fast Fourier Transform (FFT / IFFT) and the filter characteristics of which can be dynamically changed.

以上所述， 仅为本发明的较佳实施例而已， 并非用于限定本发明的 保护范围。 凡在本发明的精神和原则之内， 所作的任何修改、等同替换、 改进等， 均应包含在本发明的保护范围之内。  The above description is only the preferred embodiments of the present invention, and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

权利要求书 Claim

1、 一种频域滤波器， 其特征在于： 包括控制模块、 存储单元阵列、 滤波器系数存储器、 数据切换模块、 旋转因子查表模块、 输出数据合并 模块及至少一个高速通用运算单元； 其中，  1. A frequency domain filter, comprising: a control module, a storage unit array, a filter coefficient memory, a data switching module, a rotation factor look-up table module, an output data combining module, and at least one high-speed general-purpose arithmetic unit; wherein,

需要进行频域滤波的时域数据通过数据总线连接到所述的存储单元 阵列， 该存储单元阵列通过数据总线将经过频域滤波处理的时域数据输 出至所述的输出数据合并模块， 经增益调整后输出最终的时域数据； 所述的控制模块与存储单元阵列之间通过读 /写、 地址信号线相连 接；  The time-domain data that needs to be filtered in the frequency domain is connected to the storage unit array through a data bus. The storage unit array outputs the time-domain data that has undergone the frequency-domain filtering process to the output data combining module through the data bus, and gains Output the final time-domain data after adjustment; the control module and the storage unit array are connected via read / write and address signal lines;

所述的控制模块连接外部输入的时域数据同步信号；  The control module is connected to an externally input time domain data synchronization signal;

所述的控制模块输出数据合并控制信号至所述的输出数据合并模 块， 控制滤波后的时域输出数据的选通及合并；  The control module outputs a data combination control signal to the output data combination module, and controls the gating and combination of the filtered time-domain output data;

所述的控制模块输出旋转因子查表控制信号至所述的旋转因子查表 模块，控制其在傅立叶正 /反变换时同步查表以及输出相应的旋转因子至 高速通用运算单元；  The control module outputs a rotation factor lookup table control signal to the rotation factor lookup module to control it to look up the table synchronously during Fourier forward / inverse transformation and output the corresponding rotation factor to a high-speed general-purpose arithmetic unit;

所述的控制模块输出数据切换控制信号至所述的数据切换模块， 控 制其对存储单元阵列输入 /输出数据的选通及对高速通用运算单元傅立 叶运算和频域滤波运算数据的切换， 存储单元阵列与数据切换模块及数 据切换模块与高速通用运算单元之间均通过双向数据总线相连；  The control module outputs a data switching control signal to the data switching module to control the gating of the input / output data of the memory cell array and the switching of the high-speed general-purpose arithmetic unit Fourier arithmetic and frequency domain filtering arithmetic data. The array and data switching module, and the data switching module and the high-speed general-purpose computing unit are connected through a bidirectional data bus;

所述的控制模块输出状态控制信号至所述的高速通用运算单元， 控 制其傅立叶运算和频域滤波运算状态的切换；  The control module outputs a state control signal to the high-speed general-purpose arithmetic unit to control the switching of the Fourier arithmetic and frequency domain filtering arithmetic states;

所述的滤波器系数存储器接收来自主控制模块的同步控制信号， 将 计算系数送入高速通用运算单元； 或者， 接收外部的系数调整信号， 调 整自身存储的系数。 ²、根据权利要求 1所述的频域滤波器， 其特征在于： 所述的存储单 元阵列由至少两个存储单元构成。 The filter coefficient memory receives a synchronous control signal from the main control module, and sends the calculation coefficient to a high-speed general-purpose arithmetic unit; or receives an external coefficient adjustment signal and adjusts a coefficient stored by itself. ^2. The frequency domain filter according to claim 1, wherein the memory cell array is composed of at least two memory cells.

3、根据权利要求 1所述的频域滤波器， 其特征在于： 所述的存储单 元阵列是 RAM阵列。  3. The frequency domain filter according to claim 1, wherein: the memory cell array is a RAM array.

4、根据权利要求 2所述的频域滤波器， 其特征在于： 所述的存储单 元是由至少 2个 RAM构成的 RAM组。  The frequency domain filter according to claim 2, characterized in that: said storage unit is a RAM group composed of at least two RAMs.

5、根据权利要求 1所述的频域滤波器， 其特征在于： 所述的滤波器 系数存储器由至少一个 RAM构成。  5. The frequency domain filter according to claim 1, wherein: said filter coefficient memory is composed of at least one RAM.

6、根据权利要求 1所述的频域滤波器， 其特征在于： 所述高速通用 运算单元为蝶形运算单元。  6. The frequency domain filter according to claim 1, wherein the high-speed general-purpose arithmetic unit is a butterfly arithmetic unit.

7、根据权利要求 2所述的频域滤波器， 其特征在于： 所述数据切换 模块至少由输入选择器、 输出选择器、 输入分路器、 输出分路器和至少 两个输入输出切换单元构成； 所述的输入输出切换单元与存储单元阵列 中的存储单元在数目上相等， 并——对应， 且各输入输出切换单元分别 通过双向数据总线与其对应的存储单元连接， 各输入输出切换单元的一 路数据输出端均连接至所述的输入选择器， 各输入输出切换单元的一路 数据输入端均连接至所述的输出分路器； 输入选择器的数据输出端连接 所述的输入分路器； 输入分路器的两路数据输出端连接所述的高速通用 运算单元； 输出选择器的两路数据输入端连接所述的高速通用运算单 元， 输出选择器的数据输出端连接所述的输出分路器。  7. The frequency domain filter according to claim 2, characterized in that: said data switching module comprises at least an input selector, an output selector, an input splitter, an output splitter and at least two input-output switching units. The input / output switching unit is equal in number to the storage units in the storage unit array and corresponds to each other, and each input / output switching unit is connected to its corresponding storage unit through a bidirectional data bus, and each input / output switching unit One data output terminal of is connected to the input selector, and one data input terminal of each input-output switching unit is connected to the output branch; the data output terminal of the input selector is connected to the input branch; Two data output ends of the input splitter are connected to the high-speed general-purpose arithmetic unit; two data input ends of the output selector are connected to the high-speed general-purpose arithmetic unit, and the data output ends of the output selector are connected to the Output splitter.

8、根据权利要求 1所述的频域滤波器， 其特征在于： 所述的控制模 块进一步输出同步控制信号至所述的滤波器系数存储器， 控制其在使用 期间处于写保护，在空闲期间取消写保护，可以进行滤波器系数的更新。  8. The frequency domain filter according to claim 1, wherein: said control module further outputs a synchronization control signal to said filter coefficient memory, and controls it to be write-protected during use and cancelled during idle periods. Write protection, can update the filter coefficients.

9、 一种实现频域滤波的方法， 其特征在于包括以下步驟： 分别将需要进行频域滤波的各段时域数据交叠存储在一存储单元阵 列的各个存储单元中； 9. A method for implementing frequency-domain filtering, which is characterized by including the following steps: Each time-domain data in which frequency-domain filtering is required is overlapped and stored in a memory cell array In each storage unit of the column;

将上述存储单元阵列存储的各段交叠的时域数据于不同时间段分别 在同一个高速通用运算单元中进行傅立叶变换运算、 频域滤波运算、 傅 立叶反变换运算， 并将经过上述滤波处理后的时域数据再存储在存储单 元阵列的各存储单元中； 后的时域数据， 同时进行反交叠处理， 合并输出得到最终的时域数据； 并且，  The overlapping time-domain data stored in the storage unit array is subjected to Fourier transform operation, frequency-domain filter operation, and inverse Fourier transform operation in the same high-speed general-purpose operation unit at different time periods, and after the filtering process is performed, The time-domain data is then stored in each storage unit of the storage unit array; the subsequent time-domain data is simultaneously anti-overlaid and combined and output to obtain the final time-domain data; and,

对一段时域数据在存储单元阵列一存储单元的存储完成之前， 高速 通用运算单元对存储单元阵列前一存储单元存储的交叠的前一段时域 数据的傅立叶反变换运算已经完成。  Before a period of time-domain data is stored in a memory cell array, a high-speed general-purpose arithmetic unit has completed the inverse Fourier transform operation of the overlapped previous time-domain data stored in the previous memory cell of the memory cell array.

10、 根据权利要求 9所述的频域滤波方法， 其特征在于： 对反交叠 处理后的时域数据进一步进行增益调整处理。  10. The frequency domain filtering method according to claim 9, further comprising: performing gain adjustment processing on the time domain data after the anti-overlap processing.

11、 根据权利要求 9所述的频域滤波方法， 其特征在于： 所述频域 滤波运算中包含滤波系数， 该方法进一步包括对所述频域滤波运算的滤 波系数进行动态更新。  11. The frequency domain filtering method according to claim 9, wherein: the frequency domain filtering operation includes a filtering coefficient, and the method further comprises dynamically updating the filtering coefficient of the frequency domain filtering operation.

12、 根据权利要求 9所述的频域滤波方法， 其特征在于： 对存储单 元阵列中一存储单元存储的一段交叠时域数据在高速通用运算单元中 进行傅立叶变换运算、 频域滤波运算和傅立叶反变换运算时， 其运算数 据的读出和运算结果的写入是交替在存储单元的两个存储器中同时进 行。  12. The frequency domain filtering method according to claim 9, characterized in that: a section of overlapping time domain data stored in a memory unit in the memory unit array is subjected to a Fourier transform operation, a frequency domain filtering operation and During the inverse Fourier transform operation, the reading of the operation data and the writing of the operation result are performed simultaneously in two memories of the storage unit alternately.