WO2004102665A1

WO2004102665A1 - High-density circuits that include inductors

Info

Publication number: WO2004102665A1
Application number: PCT/EP2004/004970
Authority: WO
Inventors: Paulus Van Zeijl; Jacobus Haartsen
Original assignee: Ericsson Technology Licensing Ab
Priority date: 2003-05-14
Filing date: 2004-05-10
Publication date: 2004-11-25

Abstract

A semiconductor integrated circuit has one or more metal layers having fabricated therein an inductor; and a plurality of other layers having fabricated therein other circuitry. The other circuitry is within a region that is directly underneath an area defined by an outer periphery of the inductor; and the other layers are adapted to allow the other circuitry to be fully functional. In some embodiments, the other layers comprise a metal layer having a shield fabricated thereon; and the shield is disposed between the inductor and the other circuitry. The inductor and the other circuitry may be interconnected to form a tuned circuit.

Description

HIGH-DENSITY CIRCUITS THAT INCLUDE INDUCTORS

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 60/470, 194, filed May 14, 2004, which is hereby incorporated herein by reference.

BACKGROUND

The present invention relates to integrated circuits in general, more particularly to high-density integrated circuits, and even more particularly to high- density integrated circuits that include one or more inductors.

Analog circuit designs, such as analog radio designs, require inductors for implementing such things as voltage-controlled oscillators and tuned receiver and/or transmitter circuits. Inductors are characterized by a quality factor, Q, that represents the ratio of the stored energy to the loss energy. The amount of energy stored in an inductor is directly proportional to the value of inductance of the inductor. The amount of power dissipated in an inductor depends on the resistive elements associated with the inductor. Thus, for an inductor formed as part of a semiconductor integrated circuit (IC), the quality factor, Q, is defined as

u- _R . where/is the operating frequency, L is the inductance and R is the resistive loss of the metal, not taking any parasitic losses from an underlying substrate into account.

The quality of the inductor can have a substantial impact on the resulting circuit in which it is used. For example, the quality of inductors used in voltage- controlled-oscillators (NCOs) determines the compromise to be made between dissipated power and carrier-to-phase-noise ratio and consequently determines the quality of the oscillator. For radio communication standards like GSM, WB- CDMA, DECT and Bluetooth™ high-quality inductors are essential for achieving type-approval. The tuned circuits (e.g., bandpass filters, low-pass filters or high-pass filters) as used in receiver and transmitter circuits determine the filtering of out-of-

COΝFIRMATIOΝ COPY band components; these inductors can be avoided only at the expense of performance or power consumption.

Inductors for such circuits are physically quite large and can account for up to 10% or more of the total silicon area of a radio application-specific integrated circuit (ASIC). To give some perspective on this, it is noted that such inductors are the only components that can be seen on an ASIC-die with the naked eye.

The quality of an inductor is normally on the order of 5-10 for normal deep- submicron CMOS processes. Using an extra thick metal layer can result in quality factors of 10-20. The losses in such inductors are attributable to losses in the metal tracks and losses in the silicon substrate. The losses due to the silicon substrate can be lowered by adding a shield below the inductor. See, for example, C. P. Yue and S.S. Wong, "On-Chip Inductors with Patterned Ground Shields for Si-Based RF ICY', IEEE Journal of Solid State Circuits, Vol. 33, No. 5, May 1998; and U.S. Patent No. 5,760,456, issued on February 6, 1998 to A.Z. Grzegorek et al, ("Integrated Circuit Compatible Planar Inductors With Increased Q") for more background information about this technique. Such a shield improves the Q from 10 to 50 %. The shields described in these documents are either metal 1 or poly- shields. That is, both documents show a shield consisting of several segments. US 5,760,456 also shows a shield just consisting of a solid metal plane. As explained in US 5,760,456, a solid shield needs to be placed far enough away from the inductor itself to avoid generating eddy currents in the shield that become so large that they oppose and cancel the magnetic fields generated by the inductor, thereby degrading the inductance value. By contrast, segmented shields do not have this restriction because the pattern that defines the segments in a segmented shield is typically designed to prevent significant eddy currents from flowing in the segmented conductive plane.

The above-mentioned documents deal with the problem of providing a high quality inductor in an IC, but do not address the problem of how to provide such inductors in conjunction with active circuitry (analog and/or digital) in an IC without using up a large amount of silicon area. There are a number of solutions to the problem presented by the large amount of silicon area taken up by these inductors:

1) Use off-chip inductors and/or filters. This is very clumsy because more ASIC pins are needed, which complicates the application of the ASIC. 2) Implement a design without inductors and accept a lower level of performance (like higher current consumption and/or circuitry that is more sensitive to out-of-band spurious components).

3) Implement the high-quality inductors in the package of the ASIC. This requires extra pins on the ASIC-die, but no extra pins on the ASIC package. This solution does not affect the application. The package, however, has to be special.

4) Two (or more) dies can be mounted in one package. The first die then contains all active components built up in a high-density (CMOS) process. The second die should then contain all high-quality inductors (and maybe capacitors, and/or resistors). The two dies are connected to each other and to the package by normal bonding wires.

5) An alternative approach to possibility "4)" is to use a second (relatively) inexpensive silicon process to define the high quality inductors. The die with active components is then flip-chip mounted on the cheap die. The combined assembly is packaged in a standard way. This is described by

Royal Philips Electronics of the Netherlands at the following internet web site: http://www.semiconductors.philips.com/news/backgrounders/bg0034/

6) Place high-quality inductors (and other passive components) on the backside of the silicon wafer. See, for example, Henk Klomp, "Groovy chips, of het storingsnionster goedkoop bedwongen" , DELFT INTEGRAAL, pages 15-19,

April 2002 for a description of research performed by Nga Pham at DIMES (Delft University). Although this method is quite elegant, it requires extra process steps, and it is still unclear how long it will take to get this technique accepted by the manufacturers of low-cost CMOS processes. A number of other configurations and methods for providing an inductor on an integrated circuit are shown in U.S. Patent Application Publication No. 2003/0234437; U.S. Patent No. 6,218,729; U.S. Patent No. 5,747,870; and WO 97/45873.

It has still remained a problem, however, to find a configuration that permits circuitry (analog and/or digital) to be fabricated along with an inductor on an IC in a compact fashion.

It is therefore desirable to provide a high-density IC, including one or more inductor elements, that does not suffer from drawbacks of the known techniques.

SUMMARY It should be emphasized that the terms "comprises" and "comprising", when used in this specification, are taken to specify the presence of stated features, integers, steps or components; but the use of these terms does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof. In accordance with one aspect of the present invention, the foregoing and other objects are achieved in a semiconductor integrated circuit comprising one or more metal layers having fabricated therein an inductor; and a plurality of other layers having fabricated therein other circuitry. The other circuitry is within a region that is directly underneath an area defined by an outer periphery of the inductor; and the other layers are adapted to allow the other circuitry to be fully functional.

In one alternative, the other layers comprise a metal layer having a shield fabricated thereon, wherein the shield is disposed between the inductor and the other circuitry.

In another aspect, the inductor and the other circuitry may be interconnected to form a tuned circuit. In such embodiments, the other circuitry may comprise one or more capacitive elements that in combination with capacitance resulting from interaction between the inductor and the shield cause the tuned circuit to operate at an intended tuned frequency.

In another alternative, the one or more other layers include metal layers having fabricated therein interconnects for interconnecting the other circuitry; and the interconnects are routed perpendicular to a nearest portion of the inductor such that minimal induced current is induced in the other circuitry.

In yet another alternative, the one or more other layers include metal layers having fabricated therein interconnects for interconnecting the other circuitry; and the interconnects are routed such that interfering fields cancel one another, thereby resulting in minimal induced current being induced in the other circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects and advantages of the invention will be understood by reading the following detailed description in conjunction with the drawings in which:

FIG. 1 A illustrates a 1 nH inductor together with a large amount of circuitry as implemented in a conventional layout.

FIG. IB illustrates the inductor portion of the conventional IC of FIG. 1A. FIG. IC illustrates the shield portion of the conventional IC of FIG. 1 A. FIG. 2 A illustrates an area defined by an outer periphery of an inductor.

FIG. 2B illustrates a region that is directly underneath an area defined by an outer periphery of an inductor.

FIG. 2C illustrates an integrated circuit structure in accordance with an aspect of the invention, in which an inductor and inductor shield are fabricated in layers directly above other circuitry.

FIG. 3 depicts a cross-section view of the IC layout in FIG. 2. FIG. 4 is a schematic diagram of a low-noise amplifier that uses a tuned circuit that can be fabricated in accordance with the invention.

DETAILED DESCRIPTION

The various features of the invention will now be described with reference to the figures, in which like parts are identified with the same reference characters.

As mentioned in the Background section, it is desirable to provide a high- density IC that includes not only active circuitry, but also one or more inductor elements. This has proved to be problematic using conventional techniques because of electromagnetic interactions between the inductor and the active circuitry. Consider, for example, the conventional IC design illustrated in FIG. 1 A. In this example, a conventional layout is used to fabricate an IC 100 having a 1 nH inductor 101 together with a large amount of other circuitry 103. The other circuitry 103 comprises analog and/or digital circuitry (e.g., a digital memory). The inductor pattern that forms the inductor 101 can be seen more clearly in FIG. IB. As shown in FIG. IB, some segments of the inductor pattern (depicted with cross-hatching), such as the segment 105, are fabricated on one metal layer, whereas other segments of the inductor pattern (depicted in black), such as the segment 107, are fabricated on a different metal layer. Returning now to FIG. 1 A, a segmented shield 109 is fabricated in a layer below the inductor 101. The segmented shield 109 is more clearly illustrated in FIG. IC. The segmented shield 109 substantially reduces the generation of eddy currents in the IC substrate (not shown), which in turn raises the quality, Q, of the inductor 101. As is conventionally known, the IC 100 comprises a number of layers formed one on top of another in what is referred to herein as a "vertical" direction. In order to avoid having electromagnetic fields from the inductor 101 generate unwanted currents in the other circuitry 103, the other circuitry 103 is displaced relative to the electromagnetic field, so that the other circuitry 103 is not vertically aligned with the inductor 101. In this example, the area of the inductor is 375 μm by 375 μm (= 0.14 mm²). The area of the other circuitry is also 375 μm by 375 μm. Since the inductor 101 and other circuitry 103 are laid out side-by-side, the total area of inductor 101 and the other circuitry 103 is 2*375 μm * 375 μm or 0.28 mm². (In practice, this area will often be larger because other components are not allowed to be placed close to the inductor in order not to influence the electromagnetic field and degrade the quality of the inductor.)

In accordance with the invention, much higher-density circuits that include inductors are provided on an integrated circuit by fabricating one or more inductors on, for example, the top-most metal layers of the integrated circuit. These inductors can be fabricated in any standard way, and can, for example, look like the inductor 101 depicted in FIG. IB. Each of these inductors has an outer periphery that defines a surface area that can be considered to be occupied, covered, or affected by the inductor; this area might also be considered to be the "footprint" of the inductor. For example, the inductor 101 (FIG. IB) has an outer periphery that defines the area 203 illustrated in FIG. 2A. To provide context for this figure, the area 203 is shown within the boundary 203 of the silicon chip in which it has been constructed.

Other layers of the integrated circuit, which are below these top-most metal layers (i.e., the other layers are closer to the substrate of the integrated circuit), include other circuitry (analog and/or digital) that is fabricated on a portion of the integrated circuit that is within a region that is directly underneath the area defined by the outer peripheries of the one or more inductors. FIG. 2B illustrates just such a region. In FIG. 2B, an area 203 defined by an outer periphery of an inductor is shown. This area 203 defines the top of the region. Directly beneath this area 203 are other layers in the integrated circuit. At the bottom-most layer (i.e., the substrate) of the integrated circuit is a similar area 205 that defines the bottom of the region 207 that is directly underneath the area 203. The areas 203 and 205 therefore bound the top and bottom of the region 207 that will contain the other circuitry. These other layers are adapted to allow the other circuitry to occupy the region directly underneath the area defined by the outer periphery of an inductor, and yet be fully functional, h some embodiments, the inductor and at least some portions of the remaining other circuitry are electrically connected so that they operate together as a single circuit, for example, as a tuned circuit. It should be noted that the integrated circuit may also include additional circuits that are not within the region that is directly underneath the area defined by the outer periphery of the inductor. Since such additional circuits would not normally be detrimentally affected by the presence and operation of the inductor, these additional circuits are not considered in this disclosure.

The adaptation of the other layers can take a number of forms. In one set of embodiments, the adaptation is a shield fabricated in a metal layer between the one or more inductors and the other circuitry. The shield substantially blocks the electromagnetic effects of the inductor such that the active and passive components can be laid-out and operated in the layers present below the shield, and disposed within the region that is directly underneath an area defined by an outer periphery of the inductor.

As an exemplary embodiment, consider a design using a 0.18 μm CMOS process, in which six metal layers are available. In this discussion, metal layers are numbered in ascending order beginning with the metal layer closest to the substrate. In accordance with the invention, an inductor can then be built in metal 6 (and maybe also in metal 5 if more than one metal layer is needed to complete the inductor pattern). This leaves a number of other layers below the metal 5 layer. The shield can be fabricated in an intermediate layer within these other layers, such as metal 3. The layers below the shield, which include all ACTINE/POLY layers and the metal 1 and metal 2 layers, are used for placing other circuitry (e.g., active and passive components for forming analog and/or digital circuitry); the components of this other circuitry are connected in the metal 1 and 2 layers. Because of the presence of the shield in metal 3, the other circuitry in the lower layers can be disposed within the region that is directly underneath the area defined by the outer periphery of the inductor, thereby creating a more compact design compared to, for example, the conventional layout illustrated in FIG. 1 A, where it can be seen that the other circuitry 103 is all arranged side-by-side with the inductor 101 (ignoring any vertical displacement that may exist between the inductor 101 and the other circuitry 103), and therefore not directly underneath the inductor 101.

To illustrate this embodiment, FIG. 2C shows an integrated circuit 100' having the same inductor 101 ' as in FIG. 1 A but, in accordance with an aspect of the invention, the other circuitry 103' is placed directly underneath the inductor shield 109' (and therefore also within the region that is directly underneath an area defined by an outer periphery of the inductor 101 '). The total silicon area has been reduced to the size of the inductor 101' (i.e., 375 μm * 375 μm = 0.14 mm²).

FIG. 3 shows a cross-section of the IC layout in FIG. 2. In this exemplary portion of the IC 300, it can be seen that an inductor 301 has been fabricated in the metal 5 (m5) and metal 6 (m.6) layers. Nias 303 electrically connect the metal 5 (m5) and metal 6 (m6) inductor portions. The metal 4 (m.4) layer in this example includes interconnects that are disposed outside of the inductor area, and which are therefore not depicted in this cross-sectional view.

A shield 305 is fabricated in the metal 3 layer (m3) within a region that is directly underneath an area defined by an outer periphery of the inductor 301. The purpose of the shield 305 is to prevent the electromagnetic fields generated by the inductor 301 from interfering with the operation of other (active and/or passive) circuitry (analog and/or digital) disposed directly underneath the shield 305. By way of example, this other circuitry can include a MOS device comprising a source 307, gate 309, and drain 311 fabricated in a low layer 313 of the IC 300. Also by way of example, fabricated in this low layer 313 is a resistor made from a poly-R material 315. Contacts 317 connect these various active and passive components to a metal 1 layer (ml) of interconnects 319. Nias 321 further connect the interconnects 319 to a metal 2 layer (m2) of interconnects 323.

It will be readily apparent from the above description that by adapting the other layers to include a shield between the inductor and the other circuitry, it is possible for the other circuitry to be placed within a region that is directly underneath an area defined by an outer periphery of the inductor. This represents a very large space savings compared to the side-by-side arrangement of the conventional solution illustrated in FIG. 1 A. The drawback of placing the shield on metal 3 instead of metal 1 or 2 is the increase in capacitance to this shield, which lowers the self-resonance frequency of the inductor. In another aspect of the invention, however, it is recognized that this does not have to be a drawback because in tuned circuits (e.g., resonant circuits used for filtering), it is necessary to design in some amount of capacitance. Thus, this added capacitance is taken into account in the overall design of the IC.

A simple layout was built to estimate the increase in capacitance attributable to the shield. A metal 5 plate of 150 μm * 150 μm fabricated above a metal 3 plate of 150 μm * 150 μm resulted in an extracted capacitance of 477 fF. To provide a basis for comparison, a metal 5 plate of 150 μm * 150 μm was fabricated above a metal 1 plate of 150 μm * 150 μm; this resulted in an extracted capacitance of 218 fF. Comparing the two, it can be seen that the capacitance has been approximately doubled by locating the shield at metal 3.

Now suppose that a 5 nH inductor is to be used and that the tuned circuit is to resonate at 2.5 GHz. In this case, a capacitance of

C = , \- =811 fF

{2πf)²L will be needed in the circuit design. The extra capacitance of 259 fF introduced by moving the metal 1 shield to metal 3 is less than this (as is the total capacitance of 477 fF associated with the shield at metal 3), so there is enough margin to design in extra capacitance in the IC to appropriately tune the overall circuit. Note that this is a very rough estimation: In unbalanced circuitry, one side of the inductor is grounded (or connected to the local power supply) so approximately only one half of the capacitance is seen by the tuned circuit. As a consequence, the effective increase in capacitance associated with locating the shield in metal 3 is only 130 fF. FIG. 4 is a schematic diagram of a low-noise amplifier that uses such a tuned circuit. An NMOS transistor 401 (Mlna) functions as common-gate and has close to 50 ohms input impedance when correctly biased. The Nbias voltage source 403 and Ibias current source 405 bias the ΝMOS transistor 401. The output current of the ΝMOS-drain is converted into a voltage by the tuned circuit comprising an inductor 407 (Ltune) and a capacitor 409 (Ctune).

Considering other embodiments, in the event that the shielding between the inductor and the analog and/or digital other (active and/or passive) circuitry directly underneath the shield is not perfect (or in some embodiments, where there is no shield at all), then an alternative adaptation of the other layers is the placement of test circuitry and/or other circuitry that does not operate at the same time as the inductor. For example, U.S. Patent No. 5,842,037 to J. Haartsen ("Interference reduction in TDM-communication/computing devices") describes techniques for suppressing interference in an integrated communication/computing device. An aspect of the technique involves time multiplexing the operations of digital circuitry with analog receiver circuitry. Such an arrangement can be advantageously implemented by fabricating an inductor (used for the analog receiver circuitry) in the top-most layers of an integrated circuit as described above, and by further fabricating the digital circuitry (e.g., a processor, or Random Access Memory) within a region that is directly underneath an area defined by an outer periphery of the inductor. Another alternative adaptation of the other layers is the placement of circuitry that is insensitive to the leakage from the inductor within the region that is directly underneath an area defined by an outer periphery of the inductor, thus still reducing silicon area. For example, balanced or differential circuits can be employed in the other circuitry to provide sufficient common mode rejection to ensure that the other circuitry will be substantially insensitive to electromagnetic radiation generated by the inductor. That is, the electromagnetic radiation from the inductor acts as a common mode signal that is then suppressed by the balanced or differential circuitry.

Or alternatively, the adaptation of the other layers can constitute laying out the other circuits in the other layers such that minimum interference is generated in these circuits. For example, where the shield is disposed at metal level n, the interconnects variously disposed between metal 1 and metal n-\ may be routed perpendicular to a nearest portion of the inductor pattern so that induced current in the active and passive components of the other layers is minimal.

In still other alternatives, the adaptation of the other layers can be laying out the other circuits in the other layers such that interfering influences cancel one another. For example, where the shield is disposed at metal level n, the interconnects variously disposed between metal 1 and metal n-\ may be routed so that interfering fields cancel one another, thereby inducing only minimal currents in the active and passive components. The invention has been described with reference to a particular embodiment.

However, it will be readily apparent to those skilled in the art that it is possible to embody the invention in specific forms other than those of the preferred embodiment described above. This may be done without departing from the spirit of the invention. For example, a number of alternative embodiments have been described. To facilitate the description, each embodiment has been described as having a single adaptation of the other layers. However, in still other embodiments, the various adaptations described above can be combined in various ways in a single embodiment. Furthermore, whether the other circuitry is configured to operate in an analog mode, a digital mode, or a mixture of both, is not essential to the invention, which is capable of operating in any of these configurations.

Also, to facilitate illustrating the invention, the area defined by the outer periphery of an inductor has been shown as being coincident with the outer periphery of the inductor. However, those skilled in the art will recognize that the electromagnetic fields emitted by the inductor may extend somewhat beyond the outer periphery of the inductor pattern, and may therefore define a larger area, or footprint. Nonetheless, since the electromagnetic fields are themselves a function of the physical geometry of the inductor, even this larger area is defined by the outer periphery of the inductor. Thus, the phrase "defined by the outer periphery of an inductor" is intended to encompass any such area. The preferred embodiment is therefore merely illustrative and should not be considered restrictive in any way. The scope of the invention is given by the appended claims, rather than the preceding description, and all variations and equivalents which fall within the range of the claims are intended to be embraced therein.

Claims

WHAT IS CLAIMED IS:

1. A semiconductor integrated circuit comprising: one or more metal layers having fabricated therein an inductor; and a plurality of other layers having fabricated therein other circuitry, wherein: the other circuitry is within a region that is directly underneath an area defined by an outer periphery of the inductor; and the other layers are adapted to allow the other circuitry to be fully functional.

2. The semiconductor integrated circuit of claim 1, wherein: the other layers comprise a metal layer having a shield fabricated thereon; and the shield is disposed between the inductor and the other circuitry.

3. The semiconductor integrated circuit of claim 2, wherein the inductor and the other circuitry are interconnected to form a tuned circuit.

4. The semiconductor integrated circuit of claim 3, wherein the other circuitry comprises one or more capacitive elements that in combination with capacitance resulting from interaction between the inductor and the shield cause the tuned circuit to operate at an intended tuned frequency.

5. The semiconductor integrated circuit of claim 2, wherein: the shield does not eliminate all of the effects of inductor-generated electromagnetic fields in the other circuitry; and the other circuitry is test circuitry whose operation is not detrimentally affected by remaining leakage of the inductor-generated electromagnetic fields.

6. The semiconductor integrated circuit of claim 2, wherein: the shield does not eliminate all of the effects of inductor-generated electromagnetic fields in the other circuitry; and the other circuitry constitutes one or more circuits that are insensitive to remaining leakage of the inductor-generated electromagnetic fields.

7. The semiconductor integrated circuit of claim 1, wherein: the one or more metal layers having fabricated therein the inductor comprise at least two metal layers having fabricated therein the inductor; and the semiconductor integrated circuit further comprises one or more layers of vias for interconnecting the at least two metal layers having fabricated therein the inductor.

8. The semiconductor integrated circuit of claim 1, wherein the other circuitry comprises one or more passive circuit elements.

9. The semiconductor integrated circuit of claim 1, wherein the other circuitry comprises one or more active circuit elements.

10. The semiconductor integrated circuit of claim 1 , wherein the one or more metal layers having fabricated therein the inductor are top-most metal layers.

11. The semiconductor integrated circuit of claim 1 , wherein: the inductor has a shape defined by an inductor pattern; the plurality of other layers include metal layers having fabricated therein interconnects for interconnecting the other circuitry; and the interconnects are routed perpendicular to respective nearest portions of the inductor pattern such that minimal induced current is induced in the other circuitry.

12. The semiconductor integrated circuit of claim 1, wherein: the plurality of other layers include metal layers having fabricated therein interconnects for interconnecting the other circuitry; and the interconnects are routed such that interfering fields cancel one another, thereby resulting in minimal induced current being induced in the other circuitry.

13. The semiconductor integrated circuit of claim 1, wherein the other circuitry is designed to exhibit sufficient common mode rejection so as to make the other circuitry insensitive to electromagnetic radiation generated by the inductor.

14. The semiconductor integrated circuit of claim 1, wherein: the other circuitry is test circuitry that operates only at times when the inductor is not operational.

15. The semiconductor integrated circuit of claim 1 , wherein: the other circuitry constitutes one or more circuits that are insensitive to leakage of inductor-generated electromagnetic fields.

16. The semiconductor integrated circuit of claim 1 , wherein the other circuitry comprises analog circuitry.

17. The semiconductor integrated circuit of claim 1 , wherein the other circuitry comprises digital circuitry.

18. The semiconductor integrated circuit of claim 17, wherein the digital circuitry is configured to operate only at times when the inductor is not operational.

19. The semiconductor integrated circuit of claim 17, wherein the digital circuitry is a digital memory.

20. The semiconductor integrated circuit of claim 17, wherein the digital circuitry is a processor.

21. A method of providing an inductor and other circuitry in a semiconductor integrated circuit, comprising: providing one or more metal layers having fabricated therein an inductor; and providing a plurality of other layers having fabricated therein other circuitry, wherein: the other circuitry is within a region that is directly underneath an area defined by an outer periphery of the inductor; and the other layers are adapted to allow the other circuitry to be fully functional.

22. The method of claim 21 , wherein: the other layers comprise a metal layer having a shield fabricated thereon; and the shield is disposed between the inductor and the other circuitry.