WO2004102216A3 - Test systems and methods - Google Patents

Test systems and methods Download PDF

Info

Publication number
WO2004102216A3
WO2004102216A3 PCT/US2004/014266 US2004014266W WO2004102216A3 WO 2004102216 A3 WO2004102216 A3 WO 2004102216A3 US 2004014266 W US2004014266 W US 2004014266W WO 2004102216 A3 WO2004102216 A3 WO 2004102216A3
Authority
WO
WIPO (PCT)
Prior art keywords
formatter
timing generation
circuit
independent
generation circuit
Prior art date
Application number
PCT/US2004/014266
Other languages
French (fr)
Other versions
WO2004102216A2 (en
Inventor
Ahmed R Syed
Original Assignee
Credence Systems Corp
Ahmed R Syed
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Credence Systems Corp, Ahmed R Syed filed Critical Credence Systems Corp
Publication of WO2004102216A2 publication Critical patent/WO2004102216A2/en
Publication of WO2004102216A3 publication Critical patent/WO2004102216A3/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31928—Formatter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5606—Error catch memory

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The present invention relates to test systems for testing integrated circuit devices. One embodiment of the invention provides a portion of a test system including: on a single CMOS IC, a timing generation circuit; and a formatter coupled to the timing generation circuit. The timing generation circuit generates software words, the formatter receives the software words and provides a specified number of transitions per second and a specified edge placement resolution and accuracy. The formatter includes: a drive circuit and a response circuit. The drive circuit includes a plurality of slices. Each slice receives an independent data stream and produces an independent formatted level. The response circuit includes a plurality of slices. Each slice receives an independent data stream and produces an independent strobe marker.
PCT/US2004/014266 2003-05-07 2004-05-07 Test systems and methods WO2004102216A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US46843803P 2003-05-07 2003-05-07
US60/468,438 2003-05-07
US50591203P 2003-09-25 2003-09-25
US60/505,912 2003-09-25
US50698603P 2003-09-29 2003-09-29
US60/506,986 2003-09-29

Publications (2)

Publication Number Publication Date
WO2004102216A2 WO2004102216A2 (en) 2004-11-25
WO2004102216A3 true WO2004102216A3 (en) 2005-04-07

Family

ID=33458749

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/014266 WO2004102216A2 (en) 2003-05-07 2004-05-07 Test systems and methods

Country Status (2)

Country Link
US (2) US7266739B2 (en)
WO (1) WO2004102216A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7617064B2 (en) * 2005-04-12 2009-11-10 Analog Devices, Inc. Self-test circuit for high-definition multimedia interface integrated circuits
JP4925630B2 (en) * 2005-09-06 2012-05-09 株式会社アドバンテスト Test apparatus and test method
US7502974B2 (en) * 2006-02-22 2009-03-10 Verigy (Singapore) Pte. Ltd. Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets
TWM320674U (en) * 2007-03-29 2007-10-11 Princeton Technology Corp Circuit testing apparatus
US8390352B2 (en) * 2009-04-06 2013-03-05 Honeywell International Inc. Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line
KR101062670B1 (en) * 2009-06-01 2011-09-06 (주)아모레퍼시픽 Composition for the prevention or treatment of obesity-related diseases mediated by the activation of AMPK containing 2,5-bis-aryl-3,4-dimethyltetrahydrofuran lignan as an active ingredient
US10481246B2 (en) * 2017-05-22 2019-11-19 Analog Devices Global Unlimited Company Photo-diode emulator circuit for transimpedance amplifier testing
KR102677512B1 (en) * 2018-08-07 2024-06-24 삼성전자주식회사 Device including safety logic
CN114325348A (en) * 2022-01-13 2022-04-12 苏州博创集成电路设计有限公司 Inter-channel matching test circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5321700A (en) * 1989-10-11 1994-06-14 Teradyne, Inc. High speed timing generator
US6073259A (en) * 1997-08-05 2000-06-06 Teradyne, Inc. Low cost CMOS tester with high channel density

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5260948A (en) * 1991-03-13 1993-11-09 Ncr Corporation Bidirectional boundary-scan circuit
US5835506A (en) * 1997-04-29 1998-11-10 Credence Systems Corporation Single pass doublet mode integrated circuit tester
US6268753B1 (en) * 1998-04-15 2001-07-31 Texas Instruments Incorporated Delay element that has a variable wide-range delay capability
US6420888B1 (en) * 2000-09-29 2002-07-16 Schlumberger Technologies, Inc. Test system and associated interface module
EP1370882A2 (en) * 2001-03-19 2003-12-17 Nptest, Inc. Test system formatters

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5321700A (en) * 1989-10-11 1994-06-14 Teradyne, Inc. High speed timing generator
US6073259A (en) * 1997-08-05 2000-06-06 Teradyne, Inc. Low cost CMOS tester with high channel density

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CHAPMAN J ET AL: "A LOW-COST HIGH-PERFORMANCE CMOS TIMING VERNIER FOR ATE", PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE (ITC). WASHINGTON, OCT. 21 - 25, 1995, NEW YORK, IEEE, US, 21 October 1995 (1995-10-21), pages 459 - 468, XP000552849, ISBN: 0-7803-2992-9 *

Also Published As

Publication number Publication date
US7203875B2 (en) 2007-04-10
US20050022080A1 (en) 2005-01-27
US7266739B2 (en) 2007-09-04
US20050022081A1 (en) 2005-01-27
WO2004102216A2 (en) 2004-11-25

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