WO2004090975A1 - Method of manufacturing semiconductor devices - Google Patents

Method of manufacturing semiconductor devices Download PDF

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Publication number
WO2004090975A1
WO2004090975A1 PCT/IB2004/050365 IB2004050365W WO2004090975A1 WO 2004090975 A1 WO2004090975 A1 WO 2004090975A1 IB 2004050365 W IB2004050365 W IB 2004050365W WO 2004090975 A1 WO2004090975 A1 WO 2004090975A1
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WIPO (PCT)
Prior art keywords
substrate
layer
bottom face
pattern
array
Prior art date
Application number
PCT/IB2004/050365
Other languages
French (fr)
Inventor
Wibo D. Van Noort
Ronald Dekker
Original Assignee
Koninklijke Philips Electronics N.V.
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Filing date
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Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2004090975A1 publication Critical patent/WO2004090975A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73253—Bump and layer connectors
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Definitions

  • the present invention relates in a first aspect to a method of manufacturing semiconductor devices.
  • the present invention relates to an array of semiconductor devices and to a semiconductor device obtainable with the method according to the present invention.
  • the present invention relates to an array of separable semiconductor devices and to an individual semiconductor device.
  • Thermal resistance is a critical factor in many modern semiconductor devices such as ICs (integrated circuits), LDMOS (laterally diffused metal-oxide semiconductor), BJT, TRENCHMOSFET, etc.
  • a substrate such as a wafer comprising a plurality of electronic elements is usually thinned before dicing and packaging in order to have the heat sink (i.e. lead frame or package) as close as possible to the place where power is actually dissipated (i.e. at the top of the wafer). In this way the thermal resistance of the semiconductor devices obtained by dicing the wafer is minimized.
  • the heat sink i.e. lead frame or package
  • a problem that often occurs when thinning the wafer or other substrate is that the substrate becomes too thin and fragile. This problem is particularly pertinent for wafers having a large diameter.
  • dicing the thin and fragile substrate by e.g. sawing low yields are achieved, because of the damages along the resultant semiconductor devices.
  • Known methods for the preparation of semiconductor devices allow a minimal thickness of about 100 ⁇ m to be achieved.
  • a method for the manufacturing of semiconductor devices comprises the steps of: providing a substrate, the substrate having a top face and a bottom face, and the substrate being provided with a plurality of electronic elements on the top face of said substrate; applying a releasable support to the top face of the substrate, thereby covering the plurality of electronic elements; thinning the substrate by treating the bottom face of the substrate; applying a layer of a patternable material to the bottom face of the thinned substrate, the top face of the layer of the patternable material being in contact with the bottom face of the thinned substrate; patterning the layer of patternable material leaving a pattern of the patternable material on the bottom face of the substrate; applying a layer of an electronically conducting material to the bottom face of the substrate, thereby at least partially filling up the pattern of patternable material on the bottom face of the substrate; releasing the releas
  • the method according to the present invention allows in a surprisingly simple and cost-effective manner a semiconductor device having a substrate thickness of less than 100 ⁇ m to be produced.
  • a further advantage of the method according to the present invention is that during e.g. 'wafer dicing' the need for sawing the substrate is avoided thereby allowing more freedom as to the shape of the individual semiconductor device.
  • the present invention it is possible to provide semiconductor components with arbitrary die shapes (e.g. a different area to edge ratio than according to the prior art). This creates the possibility of achieving a better wafer fill factor (e.g. by using a pattern of hexagons).
  • the space on the substrate needed for 'saw lanes' may be minimized, resulting in an improved and cost- effective utilization of the space on the substrate.
  • the saw lanes may function as separation lines between the semiconductor devices on the array eventually produced.
  • the saw lanes may have a width as small as ⁇ 20 ⁇ m, preferably ⁇ 10 ⁇ m.
  • An even further advantage of the method relates to the devices obtained therein. With the trend towards miniaturization and increased functionality of integrated circuits in particular, heat dissipation is an increasingly important problem.
  • the resulting semiconductor device may be assembled with the heatsink on the carrier.
  • it may be assembled with the heatsink away from the carrier, particularly if glue or bumps are used for contacting the device to the carrier. This allows to provide the heat dissipation in the most appropriate manner.
  • a heat pipe may be used, or a second, thermally conducting carrier may be used, so as to ensure optimal heat dissipation.
  • a substrate such as a wafer is provided, the substrate being provided with a plurality of electronic elements such as integrated circuits (ICs), discrete transistors, filters such as an acoustic wave filter, a MEMS (micro-electromechanical system), or any other suitable electronic element. Also a combination of different electronic elements may be used.
  • the substrate comprises silicon.
  • the substrate may also be made of other suitable materials, such as germanium, GaAs or InP.
  • a releasable support is connected to the top face of the substrate by any suitable means.
  • the releasable support is preferably planar and provides mechanical stability to the substrate.
  • this connection can be achieved in a known manner using STT (Substrate Transfer Technology) technology.
  • STT Substrate Transfer Technology
  • the releasable support is removed later on in the method of the present invention, it functions as a temporary or provisional support.
  • the releasable support may be made of e.g. glass, metal, plastic, etc..
  • step (c) the substrate is thinned by suitably treating the bottom face of the substrate.
  • suitably treat the substrate e.g. by etching, grinding or polishing.
  • the thinning of the substrate may be done in a relatively aggressive manner. According to the present invention it is preferred to thin the substrate by etching.
  • a patternable material is applied to the bottom face of the thinned substrate.
  • Any suitable material may be used as a patternable material, provided the material may be patterned.
  • a thick layer (> 100 ⁇ m) of a photosensitive material is used.
  • the patternable material is patterned. The person skilled in the art will readily understand how to pattern the patternable material thereby leaving a pattern on the bottom face of the substrate.
  • the patternable material is patterned by photolithography.
  • step (f) a layer of an electronically conducting (and preferably also thermally conductive) material is applied to the bottom face of the substrate, thereby filling up the spaces between the pattern of patternable material.
  • electronically conducting material e.g. copper, silver, nickel, or any other suitable metal may be used.
  • step (g) the temporary, releasable support, which has been applied in step
  • (b) is removed, e.g. thermally and/or chemically by dissolving or modifying any adhesive or additional layer used.
  • a suitable technique for removing the releasable support is using laser ablation (see e.g. Narayan et al., IEEE trans, on components, packaging and manufacturing technology, Part B, Vol. 18, no. 1, February 1995, pp. 42-46).
  • step (h) one or more semiconductor devices are separated from the array of semiconductor devices obtained in step (g).
  • the devices are separated by sawing through the saw lanes which are covered with the pattern of the patternable material.
  • the patternable material may be removed before sawing. Then, only a very thin layer remains, which can be removed easily and without a high pressure.
  • a second option is that a separation is achieved at the interface between the patternable material and the conducting material.
  • the substrate of semiconductor material may be separated without much effort, or even by mechanical pressure only (i.e. it will break).
  • step (h) may comprise further processing steps before or after step (h), if desired.
  • a barrier layer is applied to the bottom face of the thinned substrate.
  • Any suitable conducting material that prevents direct contact between the substrate and the electronically conducting material to be applied in step (f) may be used as the barrier material.
  • the barrier layer may further improve adhesion between the substrate and the electronically conducting material to be applied in step (f).
  • the barrier layer may comprise e.g. tantalum, tantalum nitride, titanium nitride, etc. If the electronically conducting material comprises copper, the barrier layer preferably comprises tantalum or tantalum nitride. If the electronically conducting material comprises aluminum, the barrier layer preferably comprises titanium nitride.
  • the barrier layer has a thickness of 5 - 40 nm, more preferably 10 - 20 nm.
  • a seed layer is applied.
  • the person skilled in the art will readily understand what is meant by a seed layer.
  • the seed layer improves the adhesion between the barrier layer and the electronically conducting material to be applied in step (f).
  • the seed layer may comprise for example copper, silver, nickel etc.
  • the seed layer will comprise the same material as the electronically conducting material to be applied in step (f).
  • the seed layer has a thickness of 100 - 200 ⁇ m.
  • the substrate is thinned in the thinning step of step (c) to a thickness of less than 100 ⁇ m, preferably less than 50 ⁇ m, more preferably less than 20 ⁇ m, even more preferably less than 20 ⁇ m, most preferably less than 10 ⁇ m.
  • the patternable material comprises a photosensitive material.
  • the patternable material can be easily and efficiently patterned in step (e).
  • Suitable photosensitive materials are benzocyclobutene (BCB), etc.
  • An epoxy resin such as SU8 is particularly preferred, because it exhibits low RF (radio frequent) losses.
  • a pattern of patternable material is provided on the bottom face of the substrate layer, which pattern comprises a unit form selected from the group consisting of triangles, tetragons, pentagons, hexagons, heptagons, octagons, circles and a combination thereof.
  • a unit form selected from the group consisting of triangles, tetragons, pentagons, hexagons, heptagons, octagons, circles and a combination thereof.
  • squares, rectangles, other polygons or other forms may be used as a unit form.
  • the layer of electronically conducting material is applied by electroplating.
  • the layer of electronically conducting material to be applied in step (f) comprises copper. Copper provides for an excellent heat sink, in particular if the substrate is thinned to thickness of less than 10 ⁇ m.
  • the device is provided with an encapsulating layer and with contact pads at its top face before separation into individual dies.
  • a packaging approach is generally known as wafer-scale packaging.
  • the encapsulating layer is a layer of benzocyclobutene.
  • bumps are placed on the contact pads before separation.
  • the semiconductor device of this embodiment may be an integrated circuit, but is alternatively a (semi)-discrete device with for instance 6 to 8 contact pads.
  • step (h) at least one semiconductor device is separated.
  • this may be achieved by applying a force to the bottom face of the layer of electronically conducting material obtained in step (f).
  • the present invention relates to an array of semiconductor devices and an individual semiconductor device obtainable in the method according to the present invention.
  • the present invention relates to an array of separable semiconductor devices, the array comprising: a substrate having a thickness of less than 100 ⁇ m, preferably less than 50 ⁇ m, more preferably less than 20 ⁇ m, most preferably less than 10 ⁇ m, and the substrate having a top face and a bottom face, the substrate being provided with a plurality of electronic elements on the top face of said substrate; a pattern of a patternable material, preferably a photosensitive material, applied to the bottom face of the substrate; and a layer of an electronically conducting material, preferably an electroplatable material, on the bottom face of the substrate, at least partially filling up the pattern of the patternable material.
  • the array further comprises a barrier layer between the bottom face of the substrate and the pattern of patternable material.
  • the array further comprises a seed layer between the bottom face of the barrier layer and the pattern of patternable material.
  • the pattern of a patternable material comprises a pattern of saw lanes, at least one of the saw lanes having a width ⁇ 60 ⁇ m 5 preferably ⁇ 40 ⁇ m, more preferably ⁇ 20 ⁇ m, most preferably ⁇ 10 ⁇ m. A significant reduction of lost area on the wafers can be obtained herewith.
  • the present invention relates to a semiconductor device described as part of the array according to the invention, each semiconductor device comprising at least one electronic element.
  • FIG. 1 - 9 schematic cross-sectional views of different stages of semiconductor devices, being produced by the method according to the present invention
  • Fig. 10 a schematic bottom view of a pattern applied in Fig. 5 according to a first embodiment
  • Fig. 11 a schematic bottom view of a pattern applied in Fig. 5 according to a second embodiment.
  • Figures 1 - 9 show schematic cross-sectional views of different stages of the method according to the present invention.
  • Figure 1 shows a 725 ⁇ m thick silicon substrate 1, e.g. a wafer, having a top face 2 and a bottom face 3.
  • the substrate 1 has a diameter of 200 mm.
  • the substrate 1 has on its top face 2 a plurality of electronic elements 4, such as ICs.
  • the electronic elements may be the same or different, as desired.
  • a temporary, releasable support 5 is applied to the top face 2 of the substrate 1.
  • the support 5 is connected to the substrate 1 by STT using a layer of an adhesive 6.
  • the person skilled in the art will readily understand that the support 5, which may e.g. comprise metal, glass, plastics, etc., may also be provided using any other suitable means.
  • the bottom face of the support 5 being connected to the top face 2 of the substrate is preferably as planar as possible and provides mechanical stability to the substrate 1.
  • the thinning of the substrate layer 1 is shown.
  • the substrate layer 1 is thinned by etching to a thickness of less than 100 ⁇ m.
  • the person skilled in the art will understand that also other thinning methods may be used. If desired the substrate 1 may be thinned to a thickness of less than 10 ⁇ m.
  • Figure 4 shows the applying of a barrier layer 7 and a seed layer 8, to the bottom face 3 of the substrate 1, e.g. by electroplating.
  • the barrier layer 7 comprises tantalum nitride and has a thickness of 20 nm.
  • the barrier layer 7 prevents direct contact between the substrate 1 and the electronically conducting material to be applied in figure 6.
  • the provision of the seed layer 8 is known per se.
  • a 200 ⁇ m thick copper seed layer is used.
  • a pattern is applied to the bottom face 9 of the seed layer 8.
  • a > 100 ⁇ m thick layer of a photosensitive material 10 such as SU8 or BCB is deposited.
  • the photosensitive material 10 is then ' patterned (i.e.
  • a 100 ⁇ m thick layer 11 of copper (or any other electronically conducting material such as silver, nickel, etc.) is applied to the bottom face of the substrate assembly shown in figure 5, thereby filling up the spaces between the pattern of photosensitive material 10, as shown in figure 6.
  • the copper layer 11 is applied by electroplating. The plating of copper only occurs in those areas where the copper seed layer 8 is exposed (i.e. not covered by the photosensitive material 10).
  • the copper layer 11 serves as a heat sink and as an electrical ground plane. Furthermore, the copper layer 11 provides mechanical stability for the substrate 1.
  • the releasable support can be removed, as shown in figure 7.
  • the substrate assembly shown in figure 7 comprises an array of semiconductor devices 12 which are connected by the substrate 1.
  • the semiconductor devices 12 may be separated (as shown in figure 8) or further processed in the connected state as shown in figure 7.
  • the removed releasable support 5 may be reused.
  • the individual semiconductor devices 12 are separated, e.g. by applying a force to the bottom face of the copper layer 11. Instead, e.g. a pair of tweezers or any other conventional 'pick and place' technique may be used.
  • the thin substrate layer 1 breaks locally, thus disconnecting the individual device 12 from the rest of the substrate 1.
  • the individual device 12 may be further processed, e.g. soldered into or onto a package 13 and subsequently connected (e.g. wire bonding, flip chip and other conventional packaging techniques, etc.).
  • Figures 10 and 11 both show a schematic bottom view of a pattern of photosensitive material 10, as applied in figure 5.
  • Figure 10 shows a pattern of triangles;
  • figure 11 shows a pattern of tetragons.
  • the person skilled in the art will readily understand that other patterns may be obtained according to the present invention.

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Abstract

Method of manufacturing of semiconductor devices, comprising the steps of: providing a substrate with a plurality of electronic elements on the top face; applying a releasable support to the top face of the substrate; applying a layer of a patternable material to the bottom face of the thinned substrate; patterning the layer of patternable material leaving a pattern of the patternable material on the bottom face of the substrate; applying a layer of an electronically conducting material to the bottom face of the substrate, thereby at least partially filling up said pattern; releasing the releasable support on the top face of the substrate, thereby providing an array of semiconductor devices, each comprising at least one electric element; and separating at least one semiconductor device from the array of semiconductor devices.

Description

Method of manufacturing semiconductor devices
The present invention relates in a first aspect to a method of manufacturing semiconductor devices. In a further aspect, the present invention relates to an array of semiconductor devices and to a semiconductor device obtainable with the method according to the present invention. In yet a further aspect the present invention relates to an array of separable semiconductor devices and to an individual semiconductor device.
Thermal resistance is a critical factor in many modern semiconductor devices such as ICs (integrated circuits), LDMOS (laterally diffused metal-oxide semiconductor), BJT, TRENCHMOSFET, etc.
In the manufacture of semiconductor devices, a substrate such as a wafer comprising a plurality of electronic elements is usually thinned before dicing and packaging in order to have the heat sink (i.e. lead frame or package) as close as possible to the place where power is actually dissipated (i.e. at the top of the wafer). In this way the thermal resistance of the semiconductor devices obtained by dicing the wafer is minimized.
A problem that often occurs when thinning the wafer or other substrate is that the substrate becomes too thin and fragile. This problem is particularly pertinent for wafers having a large diameter. When dicing the thin and fragile substrate by e.g. sawing, low yields are achieved, because of the damages along the resultant semiconductor devices. Known methods for the preparation of semiconductor devices allow a minimal thickness of about 100 μm to be achieved.
It is an object of the present invention to avoid one or more of the above- mentioned or other problems.
It is a further object of the present invention to provide a method for the manufacture of semiconductor devices (such as chips), the method allowing a substrate thickness of less than 100 μm to be achieved. It is a still further object to provide an array of semiconductor devices or a semiconductor device having a substrate thickness of less than 100 μm.
It is yet a further object to provide a method allowing semiconductor devices having arbitrary die shapes to be produced. One or more of the above objects are achieved by a method for the manufacturing of semiconductor devices, wherein the method comprises the steps of: providing a substrate, the substrate having a top face and a bottom face, and the substrate being provided with a plurality of electronic elements on the top face of said substrate; applying a releasable support to the top face of the substrate, thereby covering the plurality of electronic elements; thinning the substrate by treating the bottom face of the substrate; applying a layer of a patternable material to the bottom face of the thinned substrate, the top face of the layer of the patternable material being in contact with the bottom face of the thinned substrate; patterning the layer of patternable material leaving a pattern of the patternable material on the bottom face of the substrate; applying a layer of an electronically conducting material to the bottom face of the substrate, thereby at least partially filling up the pattern of patternable material on the bottom face of the substrate; releasing the releasable support on the top face of the substrate, thereby providing an array of semiconductor devices, each comprising at least one electric element; and separating at least one semiconductor device from the array of semiconductor devices.
The method according to the present invention allows in a surprisingly simple and cost-effective manner a semiconductor device having a substrate thickness of less than 100 μm to be produced.
A further advantage of the method according to the present invention is that during e.g. 'wafer dicing' the need for sawing the substrate is avoided thereby allowing more freedom as to the shape of the individual semiconductor device. According to the present invention it is possible to provide semiconductor components with arbitrary die shapes (e.g. a different area to edge ratio than according to the prior art). This creates the possibility of achieving a better wafer fill factor (e.g. by using a pattern of hexagons). Furthermore, it is possible to provide an array of semiconductor components of varying sizes.
Another advantage of the method of the present invention is that the space on the substrate needed for 'saw lanes' may be minimized, resulting in an improved and cost- effective utilization of the space on the substrate. The person skilled in the art will readily understand what is meant with 'saw lanes'. For example, the saw lanes may function as separation lines between the semiconductor devices on the array eventually produced. According to the present invention, the saw lanes may have a width as small as < 20 μm, preferably < 10 μm. An even further advantage of the method relates to the devices obtained therein. With the trend towards miniaturization and increased functionality of integrated circuits in particular, heat dissipation is an increasingly important problem. Generally, this is counteracted by a heat sink which is implemented in the leadframe, such as with the well- known HVQFN package. Dissipation of heat is then dependent on the resistance of the substrate, and of the glue used for coupling substrate to the carrier. By thinning the substrate and providing the heat sink directly onto the substrate, this resistance is reduced considerably.
Moreover, the resulting semiconductor device may be assembled with the heatsink on the carrier. Alternatively, it may be assembled with the heatsink away from the carrier, particularly if glue or bumps are used for contacting the device to the carrier. This allows to provide the heat dissipation in the most appropriate manner. On the side away from the carrier, a heat pipe may be used, or a second, thermally conducting carrier may be used, so as to ensure optimal heat dissipation.
In step (a) of the method of the present invention a substrate such as a wafer is provided, the substrate being provided with a plurality of electronic elements such as integrated circuits (ICs), discrete transistors, filters such as an acoustic wave filter, a MEMS (micro-electromechanical system), or any other suitable electronic element. Also a combination of different electronic elements may be used. Usually the substrate comprises silicon. However, the substrate may also be made of other suitable materials, such as germanium, GaAs or InP.
In step (b) a releasable support is connected to the top face of the substrate by any suitable means. The releasable support is preferably planar and provides mechanical stability to the substrate. For example, this connection can be achieved in a known manner using STT (Substrate Transfer Technology) technology. As the releasable support is removed later on in the method of the present invention, it functions as a temporary or provisional support. The releasable support may be made of e.g. glass, metal, plastic, etc..
In step (c) the substrate is thinned by suitably treating the bottom face of the substrate. The person skilled in the art will readily understand how to suitably treat the substrate, e.g. by etching, grinding or polishing. As the releasable support ensures the mechanical stability of the substrate, the thinning of the substrate may be done in a relatively aggressive manner. According to the present invention it is preferred to thin the substrate by etching.
In step (d) a patternable material is applied to the bottom face of the thinned substrate. Any suitable material may be used as a patternable material, provided the material may be patterned. Preferably a thick layer (> 100 μm) of a photosensitive material is used. In step (e) the patternable material is patterned. The person skilled in the art will readily understand how to pattern the patternable material thereby leaving a pattern on the bottom face of the substrate. Preferably the patternable material is patterned by photolithography.
In step (f) a layer of an electronically conducting (and preferably also thermally conductive) material is applied to the bottom face of the substrate, thereby filling up the spaces between the pattern of patternable material. As electronically conducting material e.g. copper, silver, nickel, or any other suitable metal may be used. In step (g) the temporary, releasable support, which has been applied in step
(b), is removed, e.g. thermally and/or chemically by dissolving or modifying any adhesive or additional layer used. Hereby the plurality of electronic elements are exposed. A suitable technique for removing the releasable support is using laser ablation (see e.g. Narayan et al., IEEE trans, on components, packaging and manufacturing technology, Part B, Vol. 18, no. 1, February 1995, pp. 42-46).
Finally, in step (h) one or more semiconductor devices are separated from the array of semiconductor devices obtained in step (g). There are several options for this separation step. A first option is that the devices are separated by sawing through the saw lanes which are covered with the pattern of the patternable material. In order to facilitate such sawing process, the patternable material may be removed before sawing. Then, only a very thin layer remains, which can be removed easily and without a high pressure. A second option is that a separation is achieved at the interface between the patternable material and the conducting material. As the thickness of the conducting material is generally much larger after the thinning step than that of the semiconductor material, and the adhesion of the conducting material to the semiconductor material can be very good, the substrate of semiconductor material may be separated without much effort, or even by mechanical pressure only (i.e. it will break).
It goes without saying that the method of the present invention may comprise further processing steps before or after step (h), if desired.
According to a preferred embodiment of the method according to the present invention, before applying the layer of patternable material in step (d) a barrier layer is applied to the bottom face of the thinned substrate. Any suitable conducting material that prevents direct contact between the substrate and the electronically conducting material to be applied in step (f) may be used as the barrier material. The barrier layer may further improve adhesion between the substrate and the electronically conducting material to be applied in step (f). The barrier layer may comprise e.g. tantalum, tantalum nitride, titanium nitride, etc. If the electronically conducting material comprises copper, the barrier layer preferably comprises tantalum or tantalum nitride. If the electronically conducting material comprises aluminum, the barrier layer preferably comprises titanium nitride. Preferably the barrier layer has a thickness of 5 - 40 nm, more preferably 10 - 20 nm.
It is even more preferred that after applying the barrier layer but before applying the layer of patternable material in step (d), a seed layer is applied. The person skilled in the art will readily understand what is meant by a seed layer. The seed layer improves the adhesion between the barrier layer and the electronically conducting material to be applied in step (f). The seed layer may comprise for example copper, silver, nickel etc. Preferably, the seed layer will comprise the same material as the electronically conducting material to be applied in step (f). Preferably, the seed layer has a thickness of 100 - 200 μm. Advantageously, the substrate is thinned in the thinning step of step (c) to a thickness of less than 100 μm, preferably less than 50 μm, more preferably less than 20 μm, even more preferably less than 20 μm, most preferably less than 10 μm.
According to a preferred embodiment, the patternable material comprises a photosensitive material. Herewith the patternable material can be easily and efficiently patterned in step (e). The person skilled in the art will readily understand how to select the proper conditions to leave a pattern of the photosensitive material on the bottom face of the substrate or on the seed layer, as the case may be. Suitable photosensitive materials are benzocyclobutene (BCB), etc. An epoxy resin such as SU8 is particularly preferred, because it exhibits low RF (radio frequent) losses. As mentioned above, according to the present invention it is possible to provide semiconductor components with an arbitrary die shape. Furthermore it is possible to provide an array of semiconductor components with varying sizes. In a preferred embodiment, in the patterning step of step (e) a pattern of patternable material is provided on the bottom face of the substrate layer, which pattern comprises a unit form selected from the group consisting of triangles, tetragons, pentagons, hexagons, heptagons, octagons, circles and a combination thereof. Of course also squares, rectangles, other polygons or other forms may be used as a unit form.
According to another preferred embodiment of the present invention, in step (f) the layer of electronically conducting material is applied by electroplating. Preferably the layer of electronically conducting material to be applied in step (f) comprises copper. Copper provides for an excellent heat sink, in particular if the substrate is thinned to thickness of less than 10 μm.
In an advantageous embodiment, the device is provided with an encapsulating layer and with contact pads at its top face before separation into individual dies. Such a packaging approach is generally known as wafer-scale packaging. For example, the encapsulating layer is a layer of benzocyclobutene. Preferably, bumps are placed on the contact pads before separation. The semiconductor device of this embodiment may be an integrated circuit, but is alternatively a (semi)-discrete device with for instance 6 to 8 contact pads.
In step (h) at least one semiconductor device is separated. In a surprisingly elegant and simple manner this may be achieved by applying a force to the bottom face of the layer of electronically conducting material obtained in step (f).
In a further aspect the present invention relates to an array of semiconductor devices and an individual semiconductor device obtainable in the method according to the present invention.
In an even further aspect, the present invention relates to an array of separable semiconductor devices, the array comprising: a substrate having a thickness of less than 100 μm, preferably less than 50 μm, more preferably less than 20 μm, most preferably less than 10 μm, and the substrate having a top face and a bottom face, the substrate being provided with a plurality of electronic elements on the top face of said substrate; a pattern of a patternable material, preferably a photosensitive material, applied to the bottom face of the substrate; and a layer of an electronically conducting material, preferably an electroplatable material, on the bottom face of the substrate, at least partially filling up the pattern of the patternable material.
Preferably the array further comprises a barrier layer between the bottom face of the substrate and the pattern of patternable material.
Furthermore it is preferred that the array further comprises a seed layer between the bottom face of the barrier layer and the pattern of patternable material.
Also it is preferred that the pattern of a patternable material comprises a pattern of saw lanes, at least one of the saw lanes having a width < 60 μm5 preferably < 40 μm, more preferably < 20 μm, most preferably < 10 μm. A significant reduction of lost area on the wafers can be obtained herewith.
Finally the present invention relates to a semiconductor device described as part of the array according to the invention, each semiconductor device comprising at least one electronic element. These and other aspects of the present invention will be apparent from and elucidated with reference to the non-limiting embodiment(s) described hereinafter.
Hereinafter the present invention will be illustrated in more detail by a drawing. Herein shows:
Figs. 1 - 9 schematic cross-sectional views of different stages of semiconductor devices, being produced by the method according to the present invention;
Fig. 10 a schematic bottom view of a pattern applied in Fig. 5 according to a first embodiment; and Fig. 11 a schematic bottom view of a pattern applied in Fig. 5 according to a second embodiment.
Identical reference numbers indicate similar structural components. Figures 1 - 9 show schematic cross-sectional views of different stages of the method according to the present invention.
Figure 1 shows a 725 μm thick silicon substrate 1, e.g. a wafer, having a top face 2 and a bottom face 3. The substrate 1 has a diameter of 200 mm. The substrate 1 has on its top face 2 a plurality of electronic elements 4, such as ICs. The electronic elements may be the same or different, as desired.
As is shown in figure 2, a temporary, releasable support 5 is applied to the top face 2 of the substrate 1. In the embodiment shown in figure 2 the support 5 is connected to the substrate 1 by STT using a layer of an adhesive 6. The person skilled in the art will readily understand that the support 5, which may e.g. comprise metal, glass, plastics, etc., may also be provided using any other suitable means. The bottom face of the support 5 being connected to the top face 2 of the substrate is preferably as planar as possible and provides mechanical stability to the substrate 1. In figure 3 the thinning of the substrate layer 1 is shown. The substrate layer 1 is thinned by etching to a thickness of less than 100 μm. The person skilled in the art will understand that also other thinning methods may be used. If desired the substrate 1 may be thinned to a thickness of less than 10 μm.
Figure 4 shows the applying of a barrier layer 7 and a seed layer 8, to the bottom face 3 of the substrate 1, e.g. by electroplating. In the embodiment shown the barrier layer 7 comprises tantalum nitride and has a thickness of 20 nm. The barrier layer 7 prevents direct contact between the substrate 1 and the electronically conducting material to be applied in figure 6. The provision of the seed layer 8 is known per se. In the embodiment shown, a 200 μm thick copper seed layer is used. After applying the barrier layer 7 and the seed layer 8, a pattern is applied to the bottom face 9 of the seed layer 8. In the embodiment shown, a > 100 μm thick layer of a photosensitive material 10 such as SU8 or BCB is deposited. The photosensitive material 10 is then' patterned (i.e. partially removed) e.g. using photolithography providing a pattern of the photosensitive material 10 to the bottom face 9 of the copper seed layer 8. In figure 5 the pattern of photosensitive material 10 is schematically indicated by reference number 10. In figures 10 and 11 two different patterns of the photosensitive material 10 are shown. The person skilled in the art will readily understand that also other techniques for obtaining a pattern may be used.
Thereafter, a 100 μm thick layer 11 of copper (or any other electronically conducting material such as silver, nickel, etc.) is applied to the bottom face of the substrate assembly shown in figure 5, thereby filling up the spaces between the pattern of photosensitive material 10, as shown in figure 6. Preferably the copper layer 11 is applied by electroplating. The plating of copper only occurs in those areas where the copper seed layer 8 is exposed (i.e. not covered by the photosensitive material 10). The copper layer 11 serves as a heat sink and as an electrical ground plane. Furthermore, the copper layer 11 provides mechanical stability for the substrate 1.
After the copper layer has been applied, the releasable support can be removed, as shown in figure 7. Hereby the plurality of electronic elements 4 are exposed again. The substrate assembly shown in figure 7 comprises an array of semiconductor devices 12 which are connected by the substrate 1. Next, the semiconductor devices 12 may be separated (as shown in figure 8) or further processed in the connected state as shown in figure 7. The removed releasable support 5 may be reused.
In figure 8 the individual semiconductor devices 12 are separated, e.g. by applying a force to the bottom face of the copper layer 11. Instead, e.g. a pair of tweezers or any other conventional 'pick and place' technique may be used. When the semiconductor device is separated, the thin substrate layer 1 breaks locally, thus disconnecting the individual device 12 from the rest of the substrate 1.
Next, as shown in figure 9, the individual device 12 may be further processed, e.g. soldered into or onto a package 13 and subsequently connected (e.g. wire bonding, flip chip and other conventional packaging techniques, etc.).
Figures 10 and 11 both show a schematic bottom view of a pattern of photosensitive material 10, as applied in figure 5. Figure 10 shows a pattern of triangles; figure 11 shows a pattern of tetragons. The person skilled in the art will readily understand that other patterns may be obtained according to the present invention.
The person skilled in the art will understand that many modifications may be made without departing from the scope of the appended claims.

Claims

CLAIMS:
1. Method of manufacturing semiconductor devices, characterized in that the method comprises the steps of: providing a substrate, the substrate having a top face and a bottom face, and the substrate being provided with a plurality of electronic elements on the top face of said substrate; applying a releasable support to the top face of the substrate, thereby covering the plurality of electronic elements; thinning the substrate by treating the bottom face of the substrate; applying a layer of a patternable material to the bottom face of the thinned substrate, the top face of the layer of the patternable material being in contact with the bottom face of the thinned substrate; patterning the layer of patternable material leaving a pattern of the patternable material on the bottom face of the substrate; applying a layer of an electronically conducting material to the bottom face of the substrate, thereby at least partially filling up the pattern of patternable material on the bottom face of the substrate; releasing the releasable support on the top face of the substrate, thereby providing an array of semiconductor devices, each comprising at least one electric element; and separating at least one semiconductor device from the array of semiconductor devices.
2. Method according to claim 1, wherein before applying the layer of patternable material in step (d) a barrier layer is applied to the bottom face of the thinned substrate.
3. Method according to claim 3, wherein after applying the barrier layer but before applying the layer of patternable material in step (d) a seed layer is applied.
4. Method according to claim 1, wherein the substrate is thinned in the thinning step of step (c) to a thickness of less than 100 μm, preferably less than 50 μm, more preferably less than 20 μm, even more preferably less than 20 μm, most preferably less than 10 μm.
5. Method according to claim 1, wherein in the patterning step of step (e) a pattern of patternable material is provided on the bottom face of the substrate layer, which pattern comprises a unit form selected from the group consisting of triangles, tetragons, pentagons, hexagons, heptagons, octagons, circles and a combination thereof.
6. Method according to claim 1, wherein in step (f) the layer of electronically conducting material is applied by electroplating.
7. Array of semiconductor devices obtainable in the method according to claim 1
8. Semiconductor device obtainable in the method according to claim 1.
9. Array of separable semiconductor devices, the array comprising: a substrate having a thickness of less than 100 μm, preferably less than 50 μm, more preferably less than 20 μm, most preferably less than 10 μm, and the substrate having a top face and a bottom face, the substrate being provided with a plurality of electronic elements on the top face of said substrate; a pattern of a patternable material, preferably a photosensitive material, applied to the bottom face of the substrate; and a layer of an electronically conducting material, preferably an electroplatable material, applied to the bottom face of the substrate, at least partially filling up the pattern of the patternable material.
10. Array according to claim 9, wherein the array further comprises a barrier layer between the bottom face of the substrate and the pattern of patternable material.
11. Array according to claim 10, wherein the array further comprises a seed layer between the bottom face of the barrier layer and the pattern of patternable material.
12. Array according to claim 13 , wherein the pattern of a patternable material comprises a pattern of saw lanes, at least one of the saw lanes having a width < 60 μm, preferably < 40 μm, more preferably < 20 μm, most preferably < 10 μm.
13. A semiconductor device comprising a substrate of a semiconductor material with a first and an opposed second side, at which first side at least one semiconductor element is defined and at which second side a heat sink is present, characterized in that said heat sink has equal lateral dimensions as the substrate.
14. A device as claimed in claim 13, characterized in that the substrate and the heatsink have laterally a form selected from the group consisting of triangles, tetragons, hexagons, heptagons, octagons, circles and a combination thereof.
15. A device as claimed in claim 13, characterized in that a contact pad is defined at the first side of the substrate, which contact pad is exposed at a side face extending substantially transversal to the first side, such that the resulting device is a surface mountable device.
PCT/IB2004/050365 2003-04-08 2004-03-31 Method of manufacturing semiconductor devices WO2004090975A1 (en)

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