WO2004090973A1 - Power integrated circuits - Google Patents

Power integrated circuits Download PDF

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Publication number
WO2004090973A1
WO2004090973A1 PCT/GB2004/001387 GB2004001387W WO2004090973A1 WO 2004090973 A1 WO2004090973 A1 WO 2004090973A1 GB 2004001387 W GB2004001387 W GB 2004001387W WO 2004090973 A1 WO2004090973 A1 WO 2004090973A1
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Prior art keywords
integrated circuit
isolation
substrate
region
isolation region
Prior art date
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PCT/GB2004/001387
Other languages
French (fr)
Inventor
Thomas Starke
Petar Igic
Paul Holland
Wissam Jamal
Shahzad Hussein
Philip Mamby
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Power Electronics Design Centre
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Publication of WO2004090973A1 publication Critical patent/WO2004090973A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Definitions

  • This invention relates to semiconductor devices and, more precisely, to power integrated circuit technology. Specifically, the present invention relates to active junction isolation in power integrated circuits and, more particularly, to active junction isolation for protection of low voltage devices from high voltage devices in power integrated circuits.
  • Power integrated circuits consist of high-voltage power devices and low- voltage control circuitry integrated onto the same semiconductor substrate (usually silicon). Lateral devices have generally been used for this type of application as they are easily integrated into existing processes and have all of their terminals available at the surface. For example, the Lateral Double Diffused power MOSFET (LDMOSFET) transistors or the lateral IGBT are typically used.
  • LDMOSFET Lateral Double Diffused power MOSFET
  • the main issues concerning the development of power integrated circuits are the performance of the power transistors (breakdown voltage and specific on-state resistance) and their isolation from the low- voltage CMOS circuitry.
  • the present invention is primarily concerned with the latter, namely the design of isolation structures needed for power integrated circuits.
  • isolation There are currently four main types of isolation commonly used; these are 1) passive junction isolation; 2) active junction isolation; 3) SOI (silicon on insulator) isolation; and 4) partial SOI isolation.
  • the SOI technique (which is known in the art and will not be described in any detail herein) provides excellent static isolation between devices since the active devices are completely surrounded by a non-conducting dielectric layer.
  • a significant disadvantage of this technique is that the dielectric is a poor thermal conductor and so cooling of the power devices becomes a significant issue, i.e. self-heating becomes a limiting factor.
  • This problem can be partially overcome by using a partial SOI process.
  • the problem is only partially overcome and the cost of SOI wafers is significantly higher than that of standard silicon wafers.
  • Junction isolation does not suffer such serious self-heating problems, however the resultant electrical isolation is much poorer than that using the SOI processes.
  • Figure 1 of the drawings is a schematic cross-sectional view of a typical passive junction isolated structure for a power integrated circuit.
  • the power device (LDMOSFET, in this case) 1 is shown on the left-hand side of the device (S - source, G - gate, D - drain), and the low voltage device 5 (represented as n+ contact) is located on the right-hand side and is connected to a positive voltage.
  • the N-type Guard Ring 3 (NGR) is positioned between the high and low voltage devices 1,5 and it is connected to the highest possible potential.
  • the P + -sinker 2 is grounded and, since the drain (D) of the lateral MOSFET normally has a positive potential, this provides a reverse biased p-n junction used for the isolation.
  • the P + -sinker 4 can be grounded or left floating since the substrate is already grounded through the left P + -sinker 2. However, a substrate current will occur if the drain of the LDMOSFET is biased with a negative voltage. Then the p-n junction isolation diode becomes forward biased, swiftly generating a large current.
  • the positively biased N Guard Ring 3 is intended to collect this substrate current and to stop carriers from reaching the low voltage device 5.
  • the main concern is that, under inductive loads, the drain of the power transistor might become forward biased under transient conditions. If this happens, the junction will inject large numbers of minority carriers into the substrate. The injected current may flow long distances (up to distances of several mm) and will disrupt the operation of any control circuitry within a diffusion length of the junction.
  • FIG. 1 is a schematic cross-sectional view of a Multi-ring Active Analogic Protection (MAAP) structure.
  • MAAP Multi-ring Active Analogic Protection
  • the wide NGR 3 which changes the polarity of this region, i.e. it will become negatively biased.
  • This potential will be transferred through the wire 8 into the P + -sinker 4 and it will be added to a negative built-in potential (-0.6 V) which exists in the P + -diffusion 4 when no external bias is applied.
  • the surface potential in the right PXsinker 4 can be as low as -1.2 V.
  • a power integrated circuit comprising a substrate on which is provided a high voltage power device and low voltage control circuitry, the integrated circuit further comprising an isolation region located between said high voltage power device and said low voltage control circuitry, said isolation region being separated at least from said low voltage control circuitry by a first portion of said substrate, and said isolation region being connected to said first and/or second portion of said substrate from said high voltage power device by a second portion of said substrate, by means of an electrically conductive region provided on said integrated circuit.
  • a method of providing junction isolation in a power integrated circuit comprising a substrate on which is provided a high voltage power device and low voltage control circuitry, the method comprising the steps of providing an isolation region between said high voltage power device and said low voltage control circuitry with said isolation region being separated from at least said low voltage circuitry and said high voltage power device by first and second respective portions of said substrate, and connecting said isolation region to said first and/or second portion of said substrate by means of an electrically conductive region provided on said integrated circuit.
  • an on-chip connection is provided between the isolation region and the portion of the substrate separating the isolation region and the low voltage control circuitry, which minimises the value of Rvia referred to with reference to the MAAP structure illustrated in Figure 2 of the drawings, thereby significantly improving the current blocking capability of the overall structure.
  • the electrically conductive region connecting the isolation region to the portion of the substrate separating the isolation region from the low voltage control circuitry is preferably provided by on-chip metallisation.
  • the isolation region is preferably an N-type Guard Ring (NGR).
  • a lifetime control region is provided on the integrated circuit, beneficially extending across the isolation region and the substrate.
  • the isolation region is separated from the low voltage control circuitry, which may comprise CMOS, by a P + -sinker .
  • the isolation region is preferably separated from the high voltage device by a second P + -sinker. The second P + -sinker is preferably grounded.
  • an electrically conductive region (preferably provided by on-chip metallization) is provided between the isolation region and the portion of the substrate between the isolation region and the high voltage device, which provides negative feedback activated junction isolation
  • the isolation region may comprise two or more isolation devices, such as NGR's or the like.
  • a first isolation device may be connected to the portion of the substrate between said isolation region and the high voltage device by means of an electrically conductive region (e.g. on-chip metallisation)
  • the second or last isolation device provided in the isolation region may be connected to the portion of the substrate or sinker between that device and the low voltage control circuitry, also by means of an electrically conductive region (e.g. on-chip metallisation).
  • the electrically conductive regions may be short-circuited by means of, for example, on-chip metallization or external wiring.
  • Figure 1 is a schematic cross-sectional view of a passive junction isolated structure for a power integrated circuit in accordance with the prior art
  • FIG. 2 is a schematic cross-sectional view of a Multi-ring Analogic Protection (MAAP) structure in accordance with the prior art
  • Figure 3 is a schematic cross-sectional view of an Active Junction Isolation (AJI) structure according to a first exemplary embodiment of the present invention
  • Figure 4 is a schematic cross-sectional view of aNegative Feedback Activated (NFA) Junction Isolation structure according to a second exemplary embodiment of the present invention
  • Figure 5 is a schematic cross-sectional view of an extended NFA structure according to a third exemplary embodiment of the present invention.
  • Figure 6 is a schematic cross-sectional view of an active junction isolation structure according to a fourth exemplary embodiment of the present invention.
  • Figure 7 is a schematic cross-sectional view of an extended NFA structure according to a fifth exemplary embodiment of the present invention.
  • the power device (LDMOSFET, in this case) 1 is shown on the left-hand side of the device (S - source, G - gate, D - drain), and the low voltage device 5 (represented as n+ contact) is located on the right-hand side and is connected to a positive voltage.
  • the N-type Guard Ring 3 (NGR) is positioned between the high and low voltage devices 1,5 and it is connected to the highest possible potential.
  • the P + -sinker 2 is grounded and, since the drain (D) of the lateral MOSFET normally has a positive potential, this provides a reverse biased p-n junction used for the isolation.
  • the P + -sinker 4 can be grounded or left floating since the substrate is already grounded through the left P + -sinker 2.
  • NGR N-Guard Ring
  • one of the standard lifetime control techniques such as proton implantation, is used to reduce carrier lifetime inside the region 6, which provides even better isolation since the lower lifetime region 6 reduces the diffusion length of electrons - again reducing their ability to reach the low voltage circuitry (CMOS) 5.
  • CMOS low voltage circuitry
  • the exemplary embodiment of the present invention illustrated in Figure 4 provides even more effective blocking efficiency toward the low voltage devices 5, with a significantly expanded voltage range for the carrier injection bias for the current that comes from the high voltage device 1.
  • the structure is similar in many respects to that of Figure 3, and the same reference numbers are used for like components.
  • the NGR 3 is connected to the left P + - sinker 2 using on-chip metallization 6 (rather than using an external wire).
  • the right P + - sinker 4 is, in this embodiment, grounded. Charge carriers arriving at the NGR 3 are transferred to the left P + - sinker 2, lowering its potential and limiting the current passing through that junction. Due to the blocking of the current before it reaches the NGR 3, the saturation of the device is delayed. Hence, it will block current over a wider range of bias voltages on the device 1 than will the MAAP.
  • the exemplary embodiment of the present invention illustrated in Figure 5 provides even more effective current blocking capability, with a surface area no larger than a comparable MAAP or NFA device.
  • the structure is similar in many respects to the Negative Feedback Activated (NFA) Junction Isolation Structure of Figure 4, and the same reference numbers are used for like components, however, in this case, there is provided an additional NGR 9 and P + -sinker 8 connected with on-chip metallisation 10.
  • the widths of the NGR's 3, 9 are reduced (compared with the NGR 3 of the structure of Figure 4) to provide a smaller size of the overall structure.
  • the regions 2, 3 and 4 act in the same way as the NFA structure described with reference to Figure 4, and the regions 4, 9 and 8 act in the same way as the AJI structure described with reference to Figure 3.
  • an Active Junction Isolation structure (Self-Supported Hybrid Active Junction Isolation) according to the invention, which has higher current blocking capability and a surface area no larger than a comparable MAAP or NFA device. It consists of an NFA structure with an additional NGR (9) and P - (sinker) (8) connected with on-chip metallization (10). In other words, the two N-(guard) ring regions 3,9 are connected to the P - (sinker) regions 2,8. The middle P - (sinker) 4 (P2) is grounded. The widths of NGR (3) and (9) are reduced to provide a smaller size of the overall structure.
  • the first p-n junction 2,3 is short- circuited with the on-chip metallization or external wiring 7, and acts as a Negative Feedback Active Junction Isolation device (NFA).
  • the second p-n junction 8,9 is short-circuited with on-chip netallization or external wiring 10, which actively suppresses the inj ection current that is not blocked by the first p-n region and forces charge carriers to go to the first N-(guard) ring 3 which makes the NFA even more effective.
  • the regions 7 and 10 are short-circuited with on-chip metallization or external wiring 11. Therefore, the number of electrons able to pass from region 1 to region 5 is further reduced.
  • regions (2), (3),(4) act in the same way as the NFA structure described above with reference to Figure 4 and regions (4), (9) and (8) act in the same way as the AJI structure of Figure 5.
  • Carriers collected by the first N- region 3 will reduce its potential and activate NFA mechanism and, at the same time, its negative potential will be transferred to a region 10 activating the AJI structure (4), (9) and (8).
  • This structure (AJI) will then force more carriers through N-(guard) ring (3) making the NFA structure even more effective.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

A power integrated circuit comprising a high voltage device (1) and low voltage control circuitry (5) on a substrate. The devices (1, 5) are separated by an N-type ring guard (NGR) (3) which is connected to an adjacent P+-sinker (4) by means of on-chip metallisation (7) so as to provide Active Junction Isolation (AJI).

Description

Power Integrated Circuits
This invention relates to semiconductor devices and, more precisely, to power integrated circuit technology. Specifically, the present invention relates to active junction isolation in power integrated circuits and, more particularly, to active junction isolation for protection of low voltage devices from high voltage devices in power integrated circuits.
In recent years, power integrated circuits have gained huge interest in system integrations. Power integrated circuits (PICs) consist of high-voltage power devices and low- voltage control circuitry integrated onto the same semiconductor substrate (usually silicon). Lateral devices have generally been used for this type of application as they are easily integrated into existing processes and have all of their terminals available at the surface. For example, the Lateral Double Diffused power MOSFET (LDMOSFET) transistors or the lateral IGBT are typically used.
The main issues concerning the development of power integrated circuits are the performance of the power transistors (breakdown voltage and specific on-state resistance) and their isolation from the low- voltage CMOS circuitry. The present invention is primarily concerned with the latter, namely the design of isolation structures needed for power integrated circuits.
There are currently four main types of isolation commonly used; these are 1) passive junction isolation; 2) active junction isolation; 3) SOI (silicon on insulator) isolation; and 4) partial SOI isolation.
The SOI technique (which is known in the art and will not be described in any detail herein) provides excellent static isolation between devices since the active devices are completely surrounded by a non-conducting dielectric layer. However, a significant disadvantage of this technique is that the dielectric is a poor thermal conductor and so cooling of the power devices becomes a significant issue, i.e. self-heating becomes a limiting factor. This problem can be partially overcome by using a partial SOI process. However, as stated above, the problem is only partially overcome and the cost of SOI wafers is significantly higher than that of standard silicon wafers. Junction isolation, on the other hand, does not suffer such serious self-heating problems, however the resultant electrical isolation is much poorer than that using the SOI processes.
Figure 1 of the drawings is a schematic cross-sectional view of a typical passive junction isolated structure for a power integrated circuit. The power device (LDMOSFET, in this case) 1 is shown on the left-hand side of the device (S - source, G - gate, D - drain), and the low voltage device 5 (represented as n+ contact) is located on the right-hand side and is connected to a positive voltage.
The N-type Guard Ring 3 (NGR) is positioned between the high and low voltage devices 1,5 and it is connected to the highest possible potential. The P+-sinker 2 is grounded and, since the drain (D) of the lateral MOSFET normally has a positive potential, this provides a reverse biased p-n junction used for the isolation. The P+-sinker 4 can be grounded or left floating since the substrate is already grounded through the left P+-sinker 2. However, a substrate current will occur if the drain of the LDMOSFET is biased with a negative voltage. Then the p-n junction isolation diode becomes forward biased, swiftly generating a large current. The positively biased N Guard Ring 3 is intended to collect this substrate current and to stop carriers from reaching the low voltage device 5.
Thus, as explained above, the main concern is that, under inductive loads, the drain of the power transistor might become forward biased under transient conditions. If this happens, the junction will inject large numbers of minority carriers into the substrate. The injected current may flow long distances (up to distances of several mm) and will disrupt the operation of any control circuitry within a diffusion length of the junction.
To prevent this from happening, active junction isolation techniques act to remove the injected minority carriers as close to their point of injection as possible, thereby minimising the chance of them causing disruption to the control circuitry. One key device in this regard is the Multi- ring Active Analogic Protection (MAAP) structure, which is able to reduce the current reaching the control circuitry by several orders of magnitude. Figure 2 of the drawings is a schematic cross-sectional view of a Multi-ring Active Analogic Protection (MAAP) structure. The only significant difference between this structure and the standard passive junction isolation structure described above with reference to Figure 1 is that the NGR is now a short connected to the right P+-sinker 4 by external metal bonding (wire 8).
When the substrate current flows, some of the electrons will be collected by the wide NGR 3 and which changes the polarity of this region, i.e. it will become negatively biased. This potential will be transferred through the wire 8 into the P+-sinker 4 and it will be added to a negative built-in potential (-0.6 V) which exists in the P+-diffusion 4 when no external bias is applied. The surface potential in the right PXsinker 4 can be as low as -1.2 V.
Now a voltage drop of about 0.6 volts exists in the substrate part between the two P+-sinkers 2, 4. This electric field acts as a barrier for the electrons flowing through the substrate, i.e. the MAAP effect. The MAAP effect is primarily controlled by the resistance Rvia 10 of the external metal wire (ideally very small) and the resistance of the substrate Psub (ideally very large).
We have now devised an improved arrangement which overcomes the primary disadvantages of the MAAP structure described above.
In accordance with the present invention, there is provided a power integrated circuit comprising a substrate on which is provided a high voltage power device and low voltage control circuitry, the integrated circuit further comprising an isolation region located between said high voltage power device and said low voltage control circuitry, said isolation region being separated at least from said low voltage control circuitry by a first portion of said substrate, and said isolation region being connected to said first and/or second portion of said substrate from said high voltage power device by a second portion of said substrate, by means of an electrically conductive region provided on said integrated circuit.
Also in accordance with the present invention, there is provided a method of providing junction isolation in a power integrated circuit comprising a substrate on which is provided a high voltage power device and low voltage control circuitry, the method comprising the steps of providing an isolation region between said high voltage power device and said low voltage control circuitry with said isolation region being separated from at least said low voltage circuitry and said high voltage power device by first and second respective portions of said substrate, and connecting said isolation region to said first and/or second portion of said substrate by means of an electrically conductive region provided on said integrated circuit.
In one embodiment of the invention, an on-chip connection is provided between the isolation region and the portion of the substrate separating the isolation region and the low voltage control circuitry, which minimises the value of Rvia referred to with reference to the MAAP structure illustrated in Figure 2 of the drawings, thereby significantly improving the current blocking capability of the overall structure.
The electrically conductive region connecting the isolation region to the portion of the substrate separating the isolation region from the low voltage control circuitry is preferably provided by on-chip metallisation. The isolation region is preferably an N-type Guard Ring (NGR).
In one preferred embodiment, a lifetime control region is provided on the integrated circuit, beneficially extending across the isolation region and the substrate. Beneficially, the isolation region is separated from the low voltage control circuitry, which may comprise CMOS, by a P+-sinker . h addition, the isolation region is preferably separated from the high voltage device by a second P+-sinker. The second P+-sinker is preferably grounded.
In one exemplary embodiment of the invention, an electrically conductive region (preferably provided by on-chip metallization) is provided between the isolation region and the portion of the substrate between the isolation region and the high voltage device, which provides negative feedback activated junction isolation
In another exemplary embodiment of the present invention, the isolation region may comprise two or more isolation devices, such as NGR's or the like. In this case, a first isolation device may be connected to the portion of the substrate between said isolation region and the high voltage device by means of an electrically conductive region (e.g. on-chip metallisation), and the second or last isolation device provided in the isolation region may be connected to the portion of the substrate or sinker between that device and the low voltage control circuitry, also by means of an electrically conductive region (e.g. on-chip metallisation).
The electrically conductive regions may be short-circuited by means of, for example, on-chip metallization or external wiring.
These and other aspects of the present invention will be apparent from, and elucidated with reference to, embodiments of the invention described hereinafter.
Embodiments of the present invention will now be described by way of examples only and with reference to the accompanying drawings, in which:
Figure 1 is a schematic cross-sectional view of a passive junction isolated structure for a power integrated circuit in accordance with the prior art;
Figure 2 is a schematic cross-sectional view of a Multi-ring Analogic Protection (MAAP) structure in accordance with the prior art;
Figure 3 is a schematic cross-sectional view of an Active Junction Isolation (AJI) structure according to a first exemplary embodiment of the present invention;
Figure 4 is a schematic cross-sectional view of aNegative Feedback Activated (NFA) Junction Isolation structure according to a second exemplary embodiment of the present invention;
Figure 5 is a schematic cross-sectional view of an extended NFA structure according to a third exemplary embodiment of the present invention;
Figure 6 is a schematic cross-sectional view of an active junction isolation structure according to a fourth exemplary embodiment of the present invention; and Figure 7 is a schematic cross-sectional view of an extended NFA structure according to a fifth exemplary embodiment of the present invention.
Referring to Figure 3 of the drawings, and as described with reference to the structure illustrated in Figure 1 , the power device (LDMOSFET, in this case) 1 is shown on the left-hand side of the device (S - source, G - gate, D - drain), and the low voltage device 5 (represented as n+ contact) is located on the right-hand side and is connected to a positive voltage.
The N-type Guard Ring 3 (NGR) is positioned between the high and low voltage devices 1,5 and it is connected to the highest possible potential. The P+-sinker 2 is grounded and, since the drain (D) of the lateral MOSFET normally has a positive potential, this provides a reverse biased p-n junction used for the isolation. The P+-sinker 4 can be grounded or left floating since the substrate is already grounded through the left P+-sinker 2.
In this case, however, the N-Guard Ring (NGR) region 3 is connected to the right P+-sinker 4 using on-chip metallisation 7 (as opposed to the external wire 8 used in the structure of Figure 2) so as to minimise Rvia.
In addition, one of the standard lifetime control techniques, such as proton implantation, is used to reduce carrier lifetime inside the region 6, which provides even better isolation since the lower lifetime region 6 reduces the diffusion length of electrons - again reducing their ability to reach the low voltage circuitry (CMOS) 5. The left P+-sinker 2 remains grounded.
The exemplary embodiment of the present invention illustrated in Figure 4 provides even more effective blocking efficiency toward the low voltage devices 5, with a significantly expanded voltage range for the carrier injection bias for the current that comes from the high voltage device 1. The structure is similar in many respects to that of Figure 3, and the same reference numbers are used for like components.
However in this case, the NGR 3 is connected to the left P+- sinker 2 using on-chip metallization 6 (rather than using an external wire). The right P+ - sinker 4 is, in this embodiment, grounded. Charge carriers arriving at the NGR 3 are transferred to the left P+ - sinker 2, lowering its potential and limiting the current passing through that junction. Due to the blocking of the current before it reaches the NGR 3, the saturation of the device is delayed. Hence, it will block current over a wider range of bias voltages on the device 1 than will the MAAP.
The exemplary embodiment of the present invention illustrated in Figure 5 provides even more effective current blocking capability, with a surface area no larger than a comparable MAAP or NFA device. The structure is similar in many respects to the Negative Feedback Activated (NFA) Junction Isolation Structure of Figure 4, and the same reference numbers are used for like components, however, in this case, there is provided an additional NGR 9 and P+-sinker 8 connected with on-chip metallisation 10. The widths of the NGR's 3, 9 are reduced (compared with the NGR 3 of the structure of Figure 4) to provide a smaller size of the overall structure.
In this device, the regions 2, 3 and 4 act in the same way as the NFA structure described with reference to Figure 4, and the regions 4, 9 and 8 act in the same way as the AJI structure described with reference to Figure 3.
Current leaking through the NFA Structure 2, 3, 4 will activate the AJI Structure 4, 9, 8. This Structure will then force further leakage current through NGR 3 making the NFA Structure more effective. This will limit the charge carriers arriving at NGR 9 and delay saturation of the AJI Structure.
Referring to Figure 6 of the drawings, there is illustrated yet another exemplary embodiment of an Active Junction Isolation structure (Self-Supported Hybrid Active Junction Isolation) according to the invention, which has higher current blocking capability and a surface area no larger than a comparable MAAP or NFA device. It consists of an NFA structure with an additional NGR (9) and P - (sinker) (8) connected with on-chip metallization (10). In other words, the two N-(guard) ring regions 3,9 are connected to the P - (sinker) regions 2,8. The middle P - (sinker) 4 (P2) is grounded. The widths of NGR (3) and (9) are reduced to provide a smaller size of the overall structure. As explained above, the first p-n junction 2,3 is short- circuited with the on-chip metallization or external wiring 7, and acts as a Negative Feedback Active Junction Isolation device (NFA). The second p-n junction 8,9 is short-circuited with on-chip netallization or external wiring 10, which actively suppresses the inj ection current that is not blocked by the first p-n region and forces charge carriers to go to the first N-(guard) ring 3 which makes the NFA even more effective. The regions 7 and 10 are short-circuited with on-chip metallization or external wiring 11. Therefore, the number of electrons able to pass from region 1 to region 5 is further reduced. In this device regions (2), (3),(4) act in the same way as the NFA structure described above with reference to Figure 4 and regions (4), (9) and (8) act in the same way as the AJI structure of Figure 5. Carriers collected by the first N- region 3 will reduce its potential and activate NFA mechanism and, at the same time, its negative potential will be transferred to a region 10 activating the AJI structure (4), (9) and (8). This structure (AJI) will then force more carriers through N-(guard) ring (3) making the NFA structure even more effective.
It will be appreciated by a person skilled in the art that the present invention, and the exemplary embodiments thereof described herein, are equally
Figure imgf000010_0001
semiconductor wafers, as to the -substrate/π-epi structures illustrated herein by way of examples only. Referring to Figure 7, for example, there is illustrated an exemplary equivalent structure to that illustrated in Figure 5, for 7-substrate/p-epi type wafers, with equivalent elements thereof being denoted by like reference numerals.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. The invention may be implemented by means of hardware comprising several distinct elements. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:
1. A power integrated circuit comprising a substrate on which is provided a high voltage power device and low voltage control circuitry, the integrated circuit further comprising an isolation region located between said high voltage power device and said low voltage control circuitry, said isolation region being separated at least from said low voltage control circuitry by a first portion of said substrate and from said high voltage power device by a second portion of said substrate, said isolation region being connected to said first and/or second portion of said substrate by means of an electrically conductive region provided on said integrated circuit.
2. A power integrated circuit according to claim 1, wherein an electrically conductive region is provided to connect the isolation region to the portion of the substrate separating the isolation region from the low voltage control circuitry.
3. A power integrated circuit according to claim 1 or claim 2, wherein an electrically conductive region is provided to connect the isolation region to the portion of the substrate separating the isolation region from the high voltage power device.
4. A power integrated circuit according to any one of claims 1 to 3, wherein said electrically conductive region is provided by on-chip metallization.
5. A power integrated circuit according to any one of the preceding claims, wherein the isolation region is an N-type Guard Ring (NGR).
6. A power integrated circuit according to any one of the preceding claims, wherein a lifetime control region is provided on the integrated circuit.
7. A power integrated circuit according to claim 6, wherein the lifetime control region extends across the isolation region and the substrate.
8. A power integrated circuit according to any one of claims 1 to 7, wherein the isolation region is separated from the low voltage control circuitry by a P+ - sinker.
9. A power integrated circuit according to claim 6, wherein the isolation region is separated from the high voltage power device by a second P+-sinker.
10. A power integrated circuit according to claim 2, wherein the portion of the substrate separating the isolation region from the high voltage power device is grounded.
11. A power integrated circuit according to claim 3, wherein the portion of the substrate separating the isolation region from the low voltage circuitry is grounded.
12. A power integrated circuit according to any one of the preceding claims, wherein the isolation region comprises two or more isolation devices, which isolation devices are separated from each other by another portion of the substrate.
13. A power integrated circuit according to claim 12, comprising a first isolation device connected to a sinker between it and the high voltage power device by means of an electrically conductive region and a second isolation device connected to a sinker between it and the low voltage control circuitry by means of an electrically conductive region.
14. A power integrated circuit according to claim 13 , wherein said electrically conductive regions are short-circuited.
15. A power integrated circuit according to claim 14, wherein said electrically conductive regions are short-circuited by means of on-chip metallization or external wiring.
16. A power integrated circuit substantially as herein described with reference to Figures 3, 4, 5 and 6 of the drawings.
17. A method of providing junction isolation in a power integrated circuit comprising a substrate on which is provided a high voltage power device and low voltage control circuitry, the method comprising the steps of providing an isolation region between said high voltage device and said low voltage control circuitry with said isolation region being separated from at least said low voltage circuitry and said high voltage power device by first and second respective portions of said substrate, and connecting said isolation region to said first and/or second portion of said substrate by means of an electrically conductive region provided on said integrated circuit.
18. A method of providing junction isolation in a power integrated circuit, the method being substantially as herein described with reference to Figures 3, 4 and 5 of the drawings.
PCT/GB2004/001387 2003-04-11 2004-03-26 Power integrated circuits WO2004090973A1 (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006033692A1 (en) * 2006-07-20 2008-01-31 Austriamicrosystems Ag Laterally diffused metal oxide semiconductor transistor for use as high voltage transistor, has structured dielectric zone coated on semiconductor body over drift zone and under gate, where dielectric zone has adapted edge profile
DE102008004682A1 (en) * 2008-01-16 2009-09-10 Infineon Technologies Ag Integrated switching arrangement, has protection structure, whose one of semiconductor zones of conducting type is arranged in semiconductor substrate and attached at connecting zone in electrical conducting manner
US7943960B2 (en) 2008-02-01 2011-05-17 Infineon Technologies Ag Integrated circuit arrangement including a protective structure
US8110868B2 (en) 2005-07-27 2012-02-07 Infineon Technologies Austria Ag Power semiconductor component with a low on-state resistance
DE102011087845A1 (en) * 2011-12-06 2013-06-06 Infineon Technologies Ag LATERAL TRANSISTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
US8461648B2 (en) 2005-07-27 2013-06-11 Infineon Technologies Austria Ag Semiconductor component with a drift region and a drift control region
DE102011122988B3 (en) 2011-12-06 2022-08-11 Infineon Technologies Ag Lateral transistor device and method of making same
CN117673063A (en) * 2023-11-30 2024-03-08 海信家电集团股份有限公司 Intelligent power module and electronic equipment

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3931634A (en) * 1973-06-14 1976-01-06 Rca Corporation Junction-isolated monolithic integrated circuit device with means for preventing parasitic transistor action
EP0544048A1 (en) * 1991-11-25 1993-06-02 STMicroelectronics S.r.l. Integrated bridge device optimising conduction power losses
EP0709889A2 (en) * 1994-10-31 1996-05-01 STMicroelectronics, Inc. Structure to protect against below ground current injection
US5545917A (en) * 1994-05-17 1996-08-13 Allegro Microsystems, Inc. Separate protective transistor
US6248616B1 (en) * 1996-12-09 2001-06-19 Stmicroelectronics S.R.L. Method for suppressing parasitic effects in a junction-isolation integrated circuit
WO2003005449A1 (en) * 2001-07-03 2003-01-16 Tripath Technology, Inc. Substrate connection in an integrated power circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3931634A (en) * 1973-06-14 1976-01-06 Rca Corporation Junction-isolated monolithic integrated circuit device with means for preventing parasitic transistor action
EP0544048A1 (en) * 1991-11-25 1993-06-02 STMicroelectronics S.r.l. Integrated bridge device optimising conduction power losses
US5545917A (en) * 1994-05-17 1996-08-13 Allegro Microsystems, Inc. Separate protective transistor
EP0709889A2 (en) * 1994-10-31 1996-05-01 STMicroelectronics, Inc. Structure to protect against below ground current injection
US6248616B1 (en) * 1996-12-09 2001-06-19 Stmicroelectronics S.R.L. Method for suppressing parasitic effects in a junction-isolation integrated circuit
WO2003005449A1 (en) * 2001-07-03 2003-01-16 Tripath Technology, Inc. Substrate connection in an integrated power circuit

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8643086B2 (en) 2005-07-27 2014-02-04 Infineon Technologies Austria Ag Semiconductor component with high breakthrough tension and low forward resistance
US8110868B2 (en) 2005-07-27 2012-02-07 Infineon Technologies Austria Ag Power semiconductor component with a low on-state resistance
US9190511B2 (en) 2005-07-27 2015-11-17 Infineon Technologies Austria Ag Semiconductor component with a drift region and a drift control region
US8461648B2 (en) 2005-07-27 2013-06-11 Infineon Technologies Austria Ag Semiconductor component with a drift region and a drift control region
DE102006033692B4 (en) * 2006-07-20 2011-01-05 Austriamicrosystems Ag A method of fabricating a patterned dielectric for an LDMOS transistor
DE102006033692A1 (en) * 2006-07-20 2008-01-31 Austriamicrosystems Ag Laterally diffused metal oxide semiconductor transistor for use as high voltage transistor, has structured dielectric zone coated on semiconductor body over drift zone and under gate, where dielectric zone has adapted edge profile
DE102008004682A1 (en) * 2008-01-16 2009-09-10 Infineon Technologies Ag Integrated switching arrangement, has protection structure, whose one of semiconductor zones of conducting type is arranged in semiconductor substrate and attached at connecting zone in electrical conducting manner
US7943960B2 (en) 2008-02-01 2011-05-17 Infineon Technologies Ag Integrated circuit arrangement including a protective structure
CN103151377A (en) * 2011-12-06 2013-06-12 英飞凌科技股份有限公司 Lateral transistor component and method for producing same
DE102011087845B4 (en) * 2011-12-06 2015-07-02 Infineon Technologies Ag LATERAL TRANSISTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
US9166039B2 (en) 2011-12-06 2015-10-20 Infineon Technologies Ag Lateral transistor component and method for producing same
DE102011087845A1 (en) * 2011-12-06 2013-06-06 Infineon Technologies Ag LATERAL TRANSISTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
CN103151377B (en) * 2011-12-06 2016-01-06 英飞凌科技股份有限公司 Lateral transistor component and manufacture method thereof
DE102011122988B3 (en) 2011-12-06 2022-08-11 Infineon Technologies Ag Lateral transistor device and method of making same
CN117673063A (en) * 2023-11-30 2024-03-08 海信家电集团股份有限公司 Intelligent power module and electronic equipment

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