WO2004084606A3 - Enhanced boolean processor - Google Patents

Enhanced boolean processor Download PDF

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Publication number
WO2004084606A3
WO2004084606A3 PCT/US2004/008059 US2004008059W WO2004084606A3 WO 2004084606 A3 WO2004084606 A3 WO 2004084606A3 US 2004008059 W US2004008059 W US 2004008059W WO 2004084606 A3 WO2004084606 A3 WO 2004084606A3
Authority
WO
WIPO (PCT)
Prior art keywords
normal form
boolean
operations
boolean expression
conjunct
Prior art date
Application number
PCT/US2004/008059
Other languages
French (fr)
Other versions
WO2004084606A2 (en
Inventor
Kenneth E Koch Iii
Original Assignee
Univ North Carolina
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ North Carolina filed Critical Univ North Carolina
Publication of WO2004084606A2 publication Critical patent/WO2004084606A2/en
Publication of WO2004084606A3 publication Critical patent/WO2004084606A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Algebra (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Storage Device Security (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

A (processors36) having a Boolean logic unit is operable for performing short-circuit evaluation of Conjunctive Normal Form Boolean expressions/operations, Disjunctive Normal Form Boolean expression/operations, or both. Each processor (36) also includes a plurality of I/O interfaces, operable to receive a plurality of compiled Boolean expressions/operations and transmitting a plurality of compiled results, and a plurality of registers. And, operation related to a Conjunctive Normal form Boolean expression comprising a conjunct or related to a Disjunctive Normal Form Boolean expression comprising a disjunct, evaluating the conjunct or disjunct, and selectively short-circuiting a portion of the Boolean expression.
PCT/US2004/008059 2003-03-17 2004-03-17 Enhanced boolean processor WO2004084606A2 (en)

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US45468403P 2003-03-17 2003-03-17
US60/454,684 2003-03-17
US47958603P 2003-06-19 2003-06-19
US60/479,586 2003-06-19
US48306103P 2003-06-30 2003-06-30
US60/483,061 2003-06-30
US49582203P 2003-08-18 2003-08-18
US60/495,822 2003-08-18
US52039503P 2003-11-17 2003-11-17
US60/520,395 2003-11-17
US53735004P 2004-01-20 2004-01-20
US60/537,350 2004-01-20

Publications (2)

Publication Number Publication Date
WO2004084606A2 WO2004084606A2 (en) 2004-10-07
WO2004084606A3 true WO2004084606A3 (en) 2005-11-03

Family

ID=33102619

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/008059 WO2004084606A2 (en) 2003-03-17 2004-03-17 Enhanced boolean processor

Country Status (1)

Country Link
WO (1) WO2004084606A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4559609A (en) * 1983-02-07 1985-12-17 At&T Bell Laboratories Full adder using transmission gates
US5805462A (en) * 1995-08-18 1998-09-08 Vlsi Technology, Inc. Automatic synthesis of integrated circuits employing boolean decomposition
US6470480B2 (en) * 2000-12-14 2002-10-22 Tharas Systems, Inc. Tracing different states reached by a signal in a functional verification system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4559609A (en) * 1983-02-07 1985-12-17 At&T Bell Laboratories Full adder using transmission gates
US5805462A (en) * 1995-08-18 1998-09-08 Vlsi Technology, Inc. Automatic synthesis of integrated circuits employing boolean decomposition
US6470480B2 (en) * 2000-12-14 2002-10-22 Tharas Systems, Inc. Tracing different states reached by a signal in a functional verification system

Also Published As

Publication number Publication date
WO2004084606A2 (en) 2004-10-07

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