WO2004084313A1 - Semiconductor device having high dielectric film neutralizing fixed charge - Google Patents

Semiconductor device having high dielectric film neutralizing fixed charge Download PDF

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Publication number
WO2004084313A1
WO2004084313A1 PCT/JP2003/003445 JP0303445W WO2004084313A1 WO 2004084313 A1 WO2004084313 A1 WO 2004084313A1 JP 0303445 W JP0303445 W JP 0303445W WO 2004084313 A1 WO2004084313 A1 WO 2004084313A1
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film
semiconductor device
insulating film
component
gate electrode
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PCT/JP2003/003445
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French (fr)
Japanese (ja)
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Yoshiaki Tanida
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Fujitsu Limited
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Priority to AU2003221174A priority Critical patent/AU2003221174A1/en
Priority to PCT/JP2003/003445 priority patent/WO2004084313A1/en
Publication of WO2004084313A1 publication Critical patent/WO2004084313A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H01L21/02222—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2

Definitions

  • the present invention generally relates to a semiconductor device, and more particularly to a semiconductor device having a high dielectric insulating film made of a metal oxide or a metal silicate and a method of manufacturing the same.
  • MOSFET field effect transistor
  • a limiting force S is also applied to the thickness of the gate insulating film due to a request from the scaling law. It is required to reduce it below that.
  • a silicon oxide film having good leakage current characteristics and a low interface density has been generally used as a gate insulating film.
  • the tunnel current directly increases with a decrease in the physical thickness of the good insulation film, and therefore, the thickness of the gate insulation film is further reduced from the above value. Then, the gate leakage current due to the tunnel current becomes a serious problem.
  • the gate leak current increases, a substantial leak current occurs when, for example, the gate is turned off, which causes a problem that a circuit of the semiconductor device does not operate normally or that power consumption increases.
  • high dielectric film such as a metal oxide or a metal silicate having a high dielectric constant as a material for the gate insulating film is being studied.
  • These high dielectric film is commonly referred to as high-K dielectric film, Z r 0 2, H f O 2, T i 0 2, and the like ⁇ a 2 0 5, A ⁇ 2 ⁇ 3.
  • the HfO2 film has a higher crystallization temperature than the ZrO2 film, and is a very promising material as a gate insulating film in next-generation ultra-high-speed semiconductor devices.
  • Non-Patent Document 1 ⁇ S. Lin, et al., Appl. Phys. Lett. 81, 2041, 2002
  • Non-Patent Document 2 H. Harris, et al., Appl. Phys. Lett. 81, 1065 (2002)
  • the H f 0 2 film or Z r 0 2 film the positive fixed charges are present in the film It has been known.
  • the mechanism by which such fixed charges are generated is not clear, but when the Mgh-K dielectric film having such positive fixed charges is used as it is as the gate insulating film of a MOS transistor, a negative flat band shift Is induced, and the carrier mobility is greatly reduced in the channel region.
  • a high-speed semiconductor device that uses a gate insulating film is conventional H f 0 2 film
  • the thickness of the gut insulating film had to be set to such a relatively large value, but the positive fixed charge existing in the HfO2 film
  • the ti direct voltage fluctuates and it is difficult to realize a large carrier mobility in a channel region. Disclosure of the invention
  • a more specific object of the present invention is to suppress the fluctuations of M g hK in a semiconductor device using a dielectric film for the gate insulating film, lowering and operating characteristics of Kiyaria mobility by the fixed charge in the film .
  • Another object of the present invention in the high-K dielectric film having a positive fixed charge, by adding the components of different M g hK dielectric film having a negative fixed charge, the whole and to film
  • An object of the present invention is to provide a high-K dielectric film in which fixed charges therein are neutralized, and a semiconductor device using such a high-K dielectric film.
  • the gate insulating film is to provide a semiconductor device characterized by consisting of H f 0 2 film containing A 1 2O3 component 6-1 2% proportion in atomic percent of A 1.
  • the medium of the A 1 2O3 ingredient in H f O2 membrane by introducing at a rate of 6 to 1 2% in atomic percent of A 1, fixed charge H f 0 2 film are substantially And the carrier mobility in the channel is greatly improved.
  • the fixed charges contained in the gut insulating film are removed, the problem of the flat band voltage shift and the problem of the change of the threshold value associated therewith are suppressed.
  • Figure 1 is a diagram showing the invention's relationship with the underlying found in experiments, the equivalent oxide thickness and a flat band voltage shift of H f 0 2 film formed silicon down on the substrate of the present invention of the present invention ;
  • FIG. 4 is a diagram for explaining the principle of the first embodiment of the present invention.
  • FIG. 8 is a diagram showing the configuration of the flash memory according to the third embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
  • the sacrificial oxidation used during the formation of the element isolation insulating film 22 is formed on the silicon substrate 21 in which the element region 21 A is defined by the element isolation insulating film 22 having the LOCOS structure.
  • the exposed silicon surface was treated with HC 1 and H 2 0 2, with thickness a chemical oxide film 2 3 of about 1 nm is formed I have.
  • the MO CVD method using a chromatic genus raw material organic metal raw material and A 1 of the H f comprises A 1 2 Os ingredients into probably film
  • a hafnium oxide film 24 on which hafnium aluminate (HfA12O5) is formed is formed to a thickness of about 5 to 1 Onm.
  • Hf (t-OC4H9) 4 is used as the organometallic raw material for Hf
  • A1 (t-C4Hg) 3 is used as the organometallic raw material for A1.
  • the process is performed by supplying oxygen gas together with the organometallic raw material to a process space on the surface of the substrate to be processed at a substrate temperature of 500 ° C. under the above pressure.
  • a 1 formed by 2 0 3 component containing hafnium oxide film 24 is further nitrogen atmosphere, after being heat-treated for 30 seconds at 800 ° C, performing the plasma CVD process at a substrate temperature of 610 ° C Is covered with the polysilicon film. Further, by patterning the polysilicon film thus formed corresponding to each element region 21A, a polysilicon electrode pattern 25 is formed.
  • the H f O 2 component contains 93% by atomic percent of H f in the H f O 2 film. That is, when the atomic fraction of H f is included at a ratio of 0.93, the flat band voltage shift AVFB becomes almost zero regardless of the enzyme d of the H f O 2 film.
  • the composition represented by the atomic fraction of H f in the H f O 2 film containing the A 12 ⁇ 3 component and where ⁇ ⁇ is d [nm] is 0.93-0.1 9 * (AVFB-O 005) Zd or more, 0.93 + 0.19 * (AVFB + O. 005)
  • the proportions of the components H f in high-K dielectric film containing a H f O2 as a main component A 12 0 3 component formed on a silicon substrate in the present invention minimize the size of the flat band flff shift by a range of 94%, and sets a ratio of a 1 2 0 3 component in the film to correspond to the range 12 to 6% in atomic percent of a 1 can be suppressed to limit, in particular the ratio of the H f 0 2 component about 93% by atomic percent H f, also by setting the ratio of the a 1203 component 7% atomic percent of a 1, the H
  • the flat band voltage shift in the high-K dielectric film containing f O2 as the main component can be suppressed to the range of approximately 5 OmV on the earth. This makes it possible to substantially completely neutralize the positive fixed charges in the film.
  • a channel-doped region 11a is formed in the element region 11A immediately below the gate electrode 13G, and an n-type source is provided on both sides of the gate electrode 13 in the silicon substrate 11.
  • Extension regions 11b and 11c are formed.
  • an n + type pocket which suppresses the short channel effect by suppressing the extension of the depletion layer from the drain end so as to face each other. Injection areas lid and lie are formed respectively.
  • the element region 11A has an n + type source region 11S substantially corresponding to the outside of the gate side wall insulating film 13A, and n corresponds substantially to the outside of the gate side wall insulating film 13B.
  • a + type drain region 11D is formed.
  • H f 0 2 film 1 2 B comprising the A 1 2O3 component in this embodiment is similar to the previous embodiments, the fixed charge in the film are substantially neutralized, fixed charges in the gate insulating film As a result, the decrease in mobility in the channel area of the channel is suppressed, and the fluctuation of the threshold characteristic is suppressed.
  • the natural oxide film was removed from the surface of the silicon substrate 11 with an HF aqueous solution, and then the silicon substrate 11 from which the natural oxide film of FIG. 7A was removed in the process of FIG. 7B.
  • a chemical oxide film 12A is formed on about 1 SU $.
  • the substrate on which the chemical oxide film 12A is formed is further introduced into the MOCVD apparatus, and Hf and an organic metal material of A1, for example, Hf (t-OC4H9) 4 and A 1 (t one C4 H9) 3 was supplied under a pressure of 65 P a with oxygen gas, .5 00 ° to the chemical oxide film 12 a at a substrate temperature of C, a 1 2 .theta.3 component of a 1 atoms per 5% to 10% Hf 02 membrane containing 6 to 12%, preferably 7% in cents
  • the H f ⁇ 2 film 12 ⁇ thus formed is heat-treated at a temperature of 800 ° C. for 30 seconds in a nitrogen atmosphere to improve the film quality. Since the Hf02 film 12 ⁇ contains a substantial proportion of the A12O3 component, it does not crystallize even at a temperature of 800 ° C.
  • As + or P + is further introduced into the surface of the silicon substrate 11 by ion implantation to form a channel-doped region 11a, and a polysilicon film 13 is further deposited by the step 610.
  • the polysilicon film 13 thus deposited in the step of FIG.7D is patterned to form a gate electrode 13G. Further, using the gate electrode 13G as a mask, As + or P + is introduced obliquely by ion implantation to form the p + -type pocket implantation regions 11 d and 11 e on both sides of the gate electrode 13 G.
  • n + type source extension region 11b and a drain extension region 11c having shallow junctions are formed on both sides of the substrate so as to partially overlap the pocket injection regions 11d and lie.
  • the gate electrode 13 G and the side wall insulating films 13 A and 13 B are masked.
  • + or P + is introduced into the device region 11A by ion implantation, and an n + type having a deep junction is formed so as to partially overlap the source extension region 11b and the drain extension region 11c.
  • Source area 11 S And a drain region 11D is formed.
  • the high-K dielectric film 12B mainly composed of HfO2
  • the fixed charge in the gate insulating film is small, and the carrier mobility in the channel is greatly increased.
  • the flat band voltage shift is reduced, even if a high-K dielectric film 12B having a large thickness is used, the element characteristics of the semiconductor device do not change. 0 2 film 1 2 B can be used. Accordingly, a leak current flowing through the Hf02 film 12B is suppressed.
  • the semiconductor device 10 in FIG. 6 is an ⁇ -channel MOS transistor
  • a ⁇ -channel MOS transistor having a similar configuration can be manufactured by inverting the conductivity type of the impurity element introduced in each ion implantation step. Is also possible.
  • the semiconductor device 10 is formed on a strained SiGe layer formed on a silicon substrate or on a strained Si layer formed on a SiGe layer. It is also possible.
  • H f 0 2 film that neutralized fixed charge comprises A 1 2 0 3 ingredients according TsutomuAkira is also possible to use the tunnel insulating film of the flash memory.
  • FIG. 8 shows a configuration of a flash memory 30 having a laminated Gut structure according to a third embodiment of the present invention.
  • the flash memory 30 is formed on a p-type silicon substrate 31 in which an element region 31A is defined by an element isolation structure 31B. Contains 7% of the AI 2 O 3 component in atomic percent of A 1 through the silicon thermal oxide film 3 2 A with a film thickness of about 0.8 nm.H f 0 2 film 3 3 8 is a physical film with 7 11 111 It is formed thick. The silicon thermal oxide film 32A and the HfO2 film thus formed form a tunnel insulating film 32 of a flash memory.
  • the on the tunnel insulating film 3 2 is a polysilicon floating gate electrode 3 3 formed further on the polysilicon floating gate electrode 3 3 C VD - the S i 0 2 intermediate insulating film 3 4 including, for example, Through control gate electrode 35 are formed.
  • an n-type source region 31S and a drain region 3ID are formed on both sides of a stacked gate structure 35G including the floating gate electrode 33 and the control gate electrode 35 by an ion implantation process. Is formed.
  • the fixed charge in the Hf 02 film 32B is neutralized by introducing A Iota2omikuron3 component, as a result, the Hf 0 2 film 32 ⁇ tunica 32 beta also increase the Eff The operating characteristics of the flash memory are not affected by these charges.
  • the Ri by the increasing the thickness of the Hf ⁇ 2 film 32 B, the charge accumulated in the floating gate Ichito electrode 33 that solve the problem of leakage.
  • the present invention is not limited to such a specific production method, for example, as a raw material for H f H f (N (CH3 ) 2) 4, Hf (N ( CHs) (C 2 H5)) 4, Hf and (N (C2H5) 2) 4 and the like, can also be used a 1 (C2H5) 3, Al (CH 3) 3 or the like as a raw material of a 1. Further in the present invention is formed by the A 1 2 ⁇ 3 MOCVD method including Hf 0 2 membrane components, but it is also possible that this is formed by ALD (atomic layer deposition) process.
  • ALD atomic layer deposition
  • chemical oxide film is omitted 12 A, can also form H f O2 membrane directly on the surface of the silicon substrate 11 including the A 12 ⁇ 3 components. ,Ah .
  • the present invention has been described with reference to preferred embodiments, the present invention is not limited to the above-described specific embodiments, and various modifications and changes can be made within the scope of the claims. .
  • Industrial applicability the medium of the A 1 2O3 ingredient in H f O2 membrane by introducing at a rate of 6-1 2% atomic percent of A 1, fixed charge H f 0 2 film are substantially And the carrier mobility in the channel is greatly improved.
  • the fixed charges contained in the gate insulating film are removed, the problem of the flat band voltage shift and the problem of the threshold change accompanying the flat band voltage shift are suppressed.

Abstract

A semiconductor device having a high dielectric gate insulation film principally comprising HfO2 in which fixed charges in the film are neutralized by introducing Al2O3 component into the high dielectric gate insulation film at a rate of 6-12 atm% of Al.

Description

固定電荷を中和した高誘電体膜を有する半導体装置 技術分野  Semiconductor device having high dielectric film neutralizing fixed charge
本発明は一般に半導体装置に係り、 特に金属酸化物あるいは金属シリケ一トよ りなる高誘電体絶縁膜を有する半導体装置およびその製造方法に関する。 背景技術  The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device having a high dielectric insulating film made of a metal oxide or a metal silicate and a method of manufacturing the same. Background art
超高速動作が要求される CMO S _ L S Iなどの半導 積回路装置では、 半 導体集積回路装置を構成する電界効果型トランジスタ （MO S F E T) が非常に 短いゲート長を有することが要求されており、 このため MO S F E Tの微細化に 対して多大の努力がなされている。  In semiconductor circuit devices such as CMO S_LSIs that require ultra-high-speed operation, the field effect transistor (MO SFET) that constitutes the semiconductor integrated circuit device must have a very short gate length. Therefore, a great deal of effort is being made to reduce the size of MOS FETs.
このように微細化された MO S F E Tでは、 スケーリング則による要請からゲ 一ト絶縁膜の膜厚に対しても制限力 S加えられ、 例えばゲート絶縁膜の を酸化 膜換算 ^で 2 · O n mあるいはそれ以下に減少させることが求められている。 従来、 ゲート絶縁膜としてはリーク電流特性が良好で界面 立密度の低いシリ コン酸化膜が一般に使用されている。 しかしシリコン酸化膜よりなる従来のグー ト絶縁膜では、 グート絶縁膜の物理膜厚の減少に伴い直接トンネル電流が増加し てしまい、 このためゲート絶縁膜の膜厚が上記の値よりもさらに減少すると、 ト ンネル電流によるゲートリーク電流が大きな問題になる。 ゲートリーク電流が增 大すると、 例えばゲートオフ時において実質的なリーク電流が生じ、 半導体装置 の回路が正常に動作しな 、、 あるいは消費電力が増加する等の問題が生じてしま う。  In such a miniaturized mosfet, a limiting force S is also applied to the thickness of the gate insulating film due to a request from the scaling law. It is required to reduce it below that. Conventionally, a silicon oxide film having good leakage current characteristics and a low interface density has been generally used as a gate insulating film. However, in the case of a conventional good insulation film made of a silicon oxide film, the tunnel current directly increases with a decrease in the physical thickness of the good insulation film, and therefore, the thickness of the gate insulation film is further reduced from the above value. Then, the gate leakage current due to the tunnel current becomes a serious problem. When the gate leak current increases, a substantial leak current occurs when, for example, the gate is turned off, which causes a problem that a circuit of the semiconductor device does not operate normally or that power consumption increases.
そこで上記の問題を解消するため、 ゲート絶縁膜の材料として高い誘電率を有 する金属酸化物や金属シリケートなどの高誘電体膜を使用することが検討されて いる。 これらの高誘電体膜は一般に high-K誘電体膜と呼ばれ、 Z r 02, H f O 2， T i 02， Τ a 205, A Ι 2Ο3などが含まれる。 これらの： high-K材料のうち特 に Z r 02および H f O2はパンドギヤップが大きく、 またシリコン基板との相性 も良く、 短チャネル効果を抑制できる適度な値の比誘電率を有しているため、 ゲ 一ト長が 0 - 1 μ mを切る超高速半導体装置のグート絶縁膜として特に有望と考 えられている。 特に H f O2膜は Z r O2膜よりも結晶化温度が高く、 次世代の超 高速半導体装置においてゲート絶縁膜として非常に有望な材料である。 Therefore, in order to solve the above problem, the use of a high dielectric film such as a metal oxide or a metal silicate having a high dielectric constant as a material for the gate insulating film is being studied. These high dielectric film is commonly referred to as high-K dielectric film, Z r 0 2, H f O 2, T i 0 2, and the like Τ a 2 0 5, A Ι 2Ο3. These: especially of high-K material Z r 0 2 and H f O2 is large Pandogiyappu, also may be compatible with the silicon substrate, a dielectric constant of moderate values that can suppress the short channel effect Because It is considered to be particularly promising as a gut insulating film for ultra-high-speed semiconductor devices with a length of less than 0-1 µm. In particular, the HfO2 film has a higher crystallization temperature than the ZrO2 film, and is a very promising material as a gate insulating film in next-generation ultra-high-speed semiconductor devices.
非特許文献 1 Υ· S. Lin, et al., Appl. Phys. Lett. 81, 2041, 2002  Non-Patent Document 1 ΥS. Lin, et al., Appl. Phys. Lett. 81, 2041, 2002
非特許文献 2 H. Harris, et al., Appl. Phys. Lett. 81, 1065 (2002) 一方、 H f 02膜や Z r 02膜では、 膜中に正の固定電荷が存在することが知ら れている。 このような固定電荷が生じるメカニズムは明らかではないが、 このよ うな正の固定電荷を有する Mgh-K誘電体膜をそのまま MO Sトランジスタのゲ ート絶縁膜に使った場合、 負のフラットパンド シフトが誘起され、 またチヤ ネノ^ R域においてキヤリァの移動度が大きく低下する問題が生じる。 Non-Patent Document 2 H. Harris, et al., Appl. Phys. Lett. 81, 1065 (2002) On the other hand, the H f 0 2 film or Z r 0 2 film, the positive fixed charges are present in the film It has been known. The mechanism by which such fixed charges are generated is not clear, but when the Mgh-K dielectric film having such positive fixed charges is used as it is as the gate insulating film of a MOS transistor, a negative flat band shift Is induced, and the carrier mobility is greatly reduced in the channel region.
図 1は本発明の兖明者が、 本発明の基礎となる研究において見出したフラット バンド電圧シフトと H f 02膜の膜厚との関係を示す。 ただし図 1中、 縦軸はフ ラットバンド電圧シフト Δ VFBを、 横軸は H f 02膜の酸化膜換算膜厚 Ε Ο Τを 示す。 1兖明's invention, showing the relationship between the thickness of the flat band voltage shift and H f 0 2 film was found in the studies underlying the present invention. In FIG. 1, the vertical axis represents the flat band voltage shift ΔVFB, and the horizontal axis represents the equivalent oxide thickness of the H f O 2 film Ε Ο は.
図 1を参照するに、 H f O2膜の酸化膜換算膜厚 Ε Ο Τが 1 n m程度であれば フラットパンド電圧シフト Δ VFBはほとんどゼ口ポルトであるのに対し、 EOT が增大すると Δ VFBは負の値をとり、膜厚の増大と共に大きさが負方向に増大す ることがわかる。 フラットバンド シフトは膜中の固定電荷を反映しており、 図 1の関係は、 H f 02膜中、 特にシリコン基板との界面近傍に正の固定電荷が 存在することを示唆している。 Referring to Fig. 1, when the equivalent oxide thickness of the HfO2 film Ε Ο 程度 is about 1 nm, the flat band voltage shift Δ VFB is almost zero-port, whereas when the EOT is large, Δ It can be seen that V FB takes a negative value and the magnitude increases in the negative direction as the film thickness increases. Flat band shift reflects the fixed charge in the film, the relationship of FIG. 1, in H f 0 2 film, suggesting that positive fixed charges are present particularly in the vicinity of the interface between the silicon substrate.
図 1の関係は、 H f 02膜中にこのような正の固定電荷が生じていても、 酸化 膜換算膜厚 E O Tが 1 n m程度の膜をゲート絶縁膜として使った場合には、 フラ ットバンド電圧シフト Δ VFBはほぼゼロになり、 チャネルにおける移動度の低下 の問題も回避できることを意味する。 しかし実際には、 このように H f 02膜の 膜厚を酸化膜換算膜厚にして 1 n m程度あるいはそれ以下に減少させた場合、 膜 中のリーク電流が増大してしまう問題が生じる。 このリーク電流は H f 02膜の 物理膜厚が比較的大きいため、 S i θ2膜の場合にように電子のトンネリング機 構により生じるものではないが、 そのメカ-ズムは現状では解明されていない。 いずれにせよ、従来の H f 02膜をゲート絶縁膜に使った高速半導体装置では、 H f Oa膜を介したリーク電流を抑制するためにグート絶縁膜の膜厚をこのよう に比較的大きな値に設定する必要があつたが、 H f O2膜中に存在する正の固定 電荷の影響で、 このような厚いゲート絶縁膜を使った半導体装置では、 ti直電圧 が変動し、 またチヤネノ 域において大きなキヤリァ移動度を実現するのが困難 である問題が生じていた。 発明の開示 Relationship shown in FIG. 1, when such positive fixed charge in H f 0 2 film even has occurred, the equivalent oxide thickness EOT is used a film of about 1 nm as a gate insulating film, Hula The cut-band voltage shift ΔVFB is almost zero, which means that the problem of reduced mobility in the channel can be avoided. However, in practice, thus when to the thickness of the H f 0 2 film equivalent oxide thickness is reduced to or below about 1 nm, a problem that the leakage current in the film increases occurs. Thus leakage current is relatively large physical thickness of H f 0 2 film, but not caused by electron tunneling Organization as in the case of S i .theta.2 film, its mechanical - rhythm is being elucidated at present Absent. In any case, a high-speed semiconductor device that uses a gate insulating film is conventional H f 0 2 film, In order to suppress the leakage current through the HfOa film, the thickness of the gut insulating film had to be set to such a relatively large value, but the positive fixed charge existing in the HfO2 film As a result, in a semiconductor device using such a thick gate insulating film, there has been a problem that the ti direct voltage fluctuates and it is difficult to realize a large carrier mobility in a channel region. Disclosure of the invention
そこで本発明は上記の問題点を解決した新規で有用な半導体装置を提供するこ とを概括的目的とする。  Accordingly, it is a general object of the present invention to provide a new and useful semiconductor device which solves the above problems.
本発明のより具体的な目的は、 Mgh-K誘電体膜をゲート絶縁膜に使った半導体 装置において、 膜中の固定電荷によるキヤリァ移動度の低下および動作特性の変 動を抑制することにある。 A more specific object of the present invention is to suppress the fluctuations of M g hK in a semiconductor device using a dielectric film for the gate insulating film, lowering and operating characteristics of Kiyaria mobility by the fixed charge in the film .
本発明の他の目的は、 正の固定電荷を有する high-K誘電体膜中に、 負の固定 電荷を有する別の Mgh-K誘電体膜の構成成分を添加することにより、 全体とし て膜中の固定電荷が中和された high-K誘電体膜、およびかかる high-K誘電体膜 を使った半導体装置を提供することにある。 Another object of the present invention, in the high-K dielectric film having a positive fixed charge, by adding the components of different M g hK dielectric film having a negative fixed charge, the whole and to film An object of the present invention is to provide a high-K dielectric film in which fixed charges therein are neutralized, and a semiconductor device using such a high-K dielectric film.
本 明の他の目的は、  Other objectives of the present invention are:
チャネルを構成するシリコン層と、  A silicon layer constituting a channel;
前記シリコン層上に形成されたゲート絶縁膜と、  A gate insulating film formed on the silicon layer;
前記グート絶縁膜上に形成されたゲート電極と、  A gate electrode formed on the gut insulating film;
前記シリコン層中、 前記前記ゲート電極の両側に形成されたソース領域および ドレイン領域とよりなる半導体装置において、  In a semiconductor device comprising a source region and a drain region formed on both sides of the gate electrode in the silicon layer,
前記ゲート絶縁膜は、 A 1 2O3成分を A 1の原子パーセントで 6〜 1 2 %の割 合で含む H f 02膜よりなることを特徴とする半導体装置を提供することにある。 本発明によれば、 H f O2膜中に A 1 2O3成分を A 1の原子パーセントで 6〜1 2 %の割合で導入することにより、 H f 02膜中の固定電荷が実質的に中和され、 チャネル中におけるキヤリァの移動度が大きく向上する。 またグート絶縁膜中に 含まれる固定電荷が除去されるため、 フラットバンド電圧シフトの問題、 および これに伴う閾値 ®ΐの変ィ匕の問題が抑制される。 本発明のその他の課題おょぴ特徴は、 以下に図面を参照しながら行う本発明の 羊細な説明より明らかとなろう。 図面の簡単な説明 The gate insulating film is to provide a semiconductor device characterized by consisting of H f 0 2 film containing A 1 2O3 component 6-1 2% proportion in atomic percent of A 1. According to the present invention, the medium of the A 1 2O3 ingredient in H f O2 membrane by introducing at a rate of 6 to 1 2% in atomic percent of A 1, fixed charge H f 0 2 film are substantially And the carrier mobility in the channel is greatly improved. In addition, since the fixed charges contained in the gut insulating film are removed, the problem of the flat band voltage shift and the problem of the change of the threshold value associated therewith are suppressed. Other objects and features of the present invention will become apparent from the detailed description of the present invention given below with reference to the drawings. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明の発明者が本発明の基礎となる実験において見出した、 シリコ ン基板上に形成した H f 02膜の酸化膜換算膜厚とフラットバンド電圧シフトと の関係を示す図； Figure 1 is a diagram showing the invention's relationship with the underlying found in experiments, the equivalent oxide thickness and a flat band voltage shift of H f 0 2 film formed silicon down on the substrate of the present invention of the present invention ;
図 2は、 本発明の第 1実施例による、 A 1 203成分を含んだ H f O2膜の酸化 膜 ,とフラットパンド シフトとの関係を示す図；  FIG. 2 is a diagram showing the relationship between the oxide film of the H f O 2 film containing the A 1203 component and the flat band shift according to the first embodiment of the present invention;
図 3は、 本発明の第 1実施例において使われた MO Sキャパシタの構成を示す 図；  FIG. 3 is a diagram showing a configuration of a MOS capacitor used in the first embodiment of the present invention;
図 4は、 本発明第 1実施例の原理を説明する図；  FIG. 4 is a diagram for explaining the principle of the first embodiment of the present invention;
図 5は、 A 1 2Os膜の酸化膜換算魔窟とフラットバンド電圧シフトとの関係を 示す図； Figure 5, showing the relationship between the oxide film equivalent brothel and the flat band voltage shift of A 1 2 Os film;
図 6は、 本発明第 2実施例による MO S トランジスタの構成を示す図； 図 7 Α〜 7 Fは、 図 6の MO Sトランジスタの製造工程を示す図；  6 is a diagram showing a configuration of a MOS transistor according to a second embodiment of the present invention; FIGS. 7A to 7F are diagrams showing manufacturing steps of the MOS transistor of FIG. 6;
図 8は、 本発明第 3実施例によるフラッシュメモリの構成を示す図である。 発明を実施するための最良の態様  FIG. 8 is a diagram showing the configuration of the flash memory according to the third embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
[第 1実施例]  [First embodiment]
図 2は、本発明の発明者が本発明の基礎となる研究において見出した、 H f O2 一 A 1 2Os系の high-K誘電体膜を使ってシリコン基板上に形成した MO Sキヤ パシタにおける、 フラットバンド mi£シフト Δ VPBと前記 high-K誘電体膜の酸 化膜換算膜厚との関係を示す。 ただし図 2の関係、 および先に説明した図 1の関 係は、 図 3に示す試料について求められたものである。 2, the inventors of the present invention has been found in the studies underlying the present invention, MO S Canon Pashita formed on a silicon substrate with a H f O2 one A 1 2 Os-based high-K dielectric film 4 shows the relationship between the flat band mi-shift ΔVPB and the equivalent oxide thickness of the high-K dielectric film in FIG. However, the relationship in FIG. 2 and the relationship in FIG. 1 described above were obtained for the sample shown in FIG.
図 3を参照するに、 LOCOS構造の素子分離絶縁膜 2 2により素子領域 2 1 A が画成されたシリコン基板 2 1上には、 前記素子分離絶縁膜 2 2の形成時に使わ れた犠牲酸化膜を 0 · 5 %H F水溶液にて除去した後、 露出したシリコン表面を HC 1と H202により処理し、 膜厚が 1 n m程度の化学酸化膜 2 3が形成されて いる。 Referring to FIG. 3, the sacrificial oxidation used during the formation of the element isolation insulating film 22 is formed on the silicon substrate 21 in which the element region 21 A is defined by the element isolation insulating film 22 having the LOCOS structure. after removal of the film by 0 · 5% HF aqueous solution, the exposed silicon surface was treated with HC 1 and H 2 0 2, with thickness a chemical oxide film 2 3 of about 1 nm is formed I have.
さらにこのようにして形成された化学酸化膜 23上には、 H f の有機金属原料 と A 1の有 属原料を使った MO CVD法により、 A 12Os成分を含み、 おそ らく膜中にアルミン酸ハフニウム (H f A 12O5) が形成された酸化ハフニウム 膜 24が約 5〜1 On mの膜厚に形成される。 例えば前記 H f の有機金属原料と しては H f ( t -OC4H9) 4が、 前記 A 1の有機金属原料としては A 1 (t -C4 Hg) 3が使われ、 MOCVD工程は 65 P aの圧力下、 500°Cの基板温度にお いて、 酸素ガスを前記有機金属原料と共に被処理基板表面上のプロセス空間に供 給することにより、 実行される。 Further in this manner on the chemical oxide film 23 formed in, the MO CVD method using a chromatic genus raw material organic metal raw material and A 1 of the H f, comprises A 1 2 Os ingredients into probably film A hafnium oxide film 24 on which hafnium aluminate (HfA12O5) is formed is formed to a thickness of about 5 to 1 Onm. For example, Hf (t-OC4H9) 4 is used as the organometallic raw material for Hf, and A1 (t-C4Hg) 3 is used as the organometallic raw material for A1. The process is performed by supplying oxygen gas together with the organometallic raw material to a process space on the surface of the substrate to be processed at a substrate temperature of 500 ° C. under the above pressure.
このようにして形成された A 1203成分含有酸化ハフニウム膜 24はさらに窒 素雰囲気中、 800°Cで 30秒間熱処理された後、 610°Cの基板温度でプラズ マ CVD処理を行うことにより、 ポリシリコン膜により覆われる。 さらに、 この ようにして形成されたポリシリコン膜を各素子領域 21 Aに対応してパターニン グすることにより、 ポリシリコン電極パターン 25が形成される。 During this way A 1 formed by 2 0 3 component containing hafnium oxide film 24 is further nitrogen atmosphere, after being heat-treated for 30 seconds at 800 ° C, performing the plasma CVD process at a substrate temperature of 610 ° C Is covered with the polysilicon film. Further, by patterning the polysilicon film thus formed corresponding to each element region 21A, a polysilicon electrode pattern 25 is formed.
図 2のフラットパンド電圧シフト AVFBは、 このようにして作製された MOS キャパシタのうち、 特に H f 02膜 24が H f を原子パーセントで 80%含む、 換言すると前記 H f O2膜が A 1を原子パーセントで 20 %含み H f を原子パー セントで 80%含む試料 (H f ： A 1 =80 ： 20) について得られたものであ る。 Flat Pando voltage shift AVFB in Figure 2, this way of fabricated MOS capacitors, in particular H f 0 2 film 24 containing 80% H f in atomic percent, wherein the other words H f O2 membrane A 1 Was obtained for a sample containing 20% by atomic percent and 80% by atomic percent Hf (Hf: A1 = 80: 20).
図 2を再び参照するに、 A 12θ3成分を A 1にして 20原子％含む H f O2膜の 場合、 膜中には負の固定電荷が生じており、 これに伴ってフラットパンド電圧シ フト Δ VFBは H f O2膜の酸化膜換算膜厚 EOTに対して正の勾配を有すること がわかる。すなわち、 このような A 1203成分を含む H f 02膜の場合、酸化膜換 算膜厚 EOTが 1 nm程度の場合にはブラットバンド電圧シフト Δ VFBはほと んどゼロであるのに対し、 酸化膜換算 が増加するにつれて前記フラッ トパンド電圧シフトの値は正 側に増大する。 Referring again to FIG. 2, when the H f O2 film containing 20 atomic% and the A 12θ 3 components A 1, is in the film has negative fixed charge occurs, flat Pando voltage shift along with this It can be seen that ΔVFB has a positive gradient with respect to the equivalent oxide thickness EOT of the HfO2 film. That is, in the case of H f 0 2 film containing such A 1 2 0 3 component, is Bratt band voltage shift delta VFB is provided for most zero if oxidation Maku換SanmakuAtsu EOT of about 1 nm On the other hand, as the oxide film conversion increases, the value of the flat band voltage shift increases to the positive side.
図 4は、図 1の関係と図 2の関係とを同一のダラフ上にプロットした図である。 図 4を参照するに、 A 1を含まない H f 02膜に A 1203成分力 A 1原子にし て 20原子0 /0 (Al (Hf +Al) =0. 2) 程度添加されることにより、 フ ラットバンド ®ΐシフト A VFBの傾きが、 当初の一 0 · 2 3から + 0 . 3 1へと 反転するのがわかる。 FIG. 4 is a diagram in which the relationship of FIG. 1 and the relationship of FIG. 2 are plotted on the same rough. Referring to FIG. 4, in the A 1 2 0 3 component force A 1 atom H f 0 2 film containing no A 1 20 atoms 0/0 (Al (Hf + Al) = 0. 2) are added degree By doing so, Rat band ® ΐ shift A It can be seen that the slope of the VFB reverses from the initial value of 0.23 to +0.31.
図 4の関係からは、 特に添加される A 1の割合を A 1の原子パーセントで約 7 %、 すなわち膜中の H f組成を 9 3 %に設定した場合、 膜中の固定電荷を実質 的に中和し、 フラットバンド電圧シフトを H f 02膜の物理膜厚 dに無関係に、 ± 5 0 m V以內に抑制することができることが推定される。  From the relationship in Fig. 4, it can be seen that the fixed charge in the film is substantially reduced when the ratio of added A1 is set to about 7% in atomic percent of A1, that is, when the Hf composition in the film is set to 93%. It is estimated that the flat band voltage shift can be suppressed to ± 50 mV or less regardless of the physical thickness d of the Hf02 film.
すなわち、このように H f O2膜中に含まれる A 1 2O3成分の割合力 A 1原子 の原子パーセントで 2 0 %程度までは、 フラットバンド と酸化膜„ と の関係は直線的であり、 この組成範囲であれば内挿により、 膜中の固定電荷が実 質的に中和される糸且成を求めることが可能であると考えられる。  In other words, the relationship between the flat band and the oxide film で is linear up to about 20% in atomic percentage of A 1 atom of A 1 O 2 component contained in the H f O 2 film. Within the composition range, it is considered that it is possible to obtain a thread composition in which the fixed charges in the film are substantially neutralized by interpolation.
—方、 図 3の試料において H f 02膜あるいは A 1 2O3成分を含んだ H f 02膜 2 4の代わりに A 1 2O3膜を使った場合には、 ブラットバンド電圧シフト Δ VFB と A 1 203膜の酸化膜換算膜厚との関係は図 5に示すように変化する。 この にはフラットバンド miEと酸化膜換算 との間に線形性は成立しておらず、 ま た固定電荷は A 1 2O3膜中、 主にポリシリコン電極との界面近傍に存在している ものと考えられる。 - How, when using A 1 2O3 film instead of H f 0 2 film 2 4 containing H f 0 2 film or A 1 2O3 component in a sample 3, Bratt band voltage shift delta VFB and A relationship between the 1 2 0 3 film equivalent oxide thickness of the changes as shown in FIG. No linearity is established between the flat band miE and the oxide film equivalent, and the fixed charge exists mainly in the vicinity of the interface with the polysilicon electrode in the A12O3 film. Conceivable.
このように図 5の関係は、 H f 02膜中の A 1 2θ3成分の割合をさらに増大させ た場合、 膜中に何らかの構造変化が生じ、 得られるフラットバンド電圧と酸化膜 換算膜厚との関係を、 図 4の関係から外挿するのは困難であることを示唆してい る。 さらに A 1 203膜のフラットバンド電圧特性から、 Α Ι 2Ο3成分を少 ん だ H f 02膜のフラットバンド flffi特性を推測するのも困難であると考えられる。 Thus the relationship of FIG. 5, when further increasing the proportion of A 1 2 [Theta] 3 component of H f 0 2 film, some structural changes occur in the film, resulting flat band voltage and the equivalent oxide thickness This suggests that it is difficult to extrapolate the relationship from Fig. 4. Furthermore the flat band voltage characteristic of A 1 2 0 3 film is also believed that it is difficult to guess the flat band flffi characteristics of Α Ι 2Ο3 I small I component H f 0 2 film.
H f O2膜中の A 1 2O3成分の割合が A 1原子パーセントにして 2 0 %以内で あれば、上記図 4の関係を内挿することにより、前記 A 1 2〇3成分を含む H f O2 膜中における H f組成とフラットパンド電圧シフト AFBの関係は、 H f 02膜の Hff dをパラメータとして、 一般式 If the proportion of A 1 2O3 component of H f O2 film is within 2 0% in the A 1 atomic percent, by interpolating the relation of FIG 4, H f containing the A 1 2_Rei three components relationship H f composition and flat Pando voltage shift AFB in O2 film is a Hff d of H f 0 2 film as the parameter, the general formula
A VFB^ A ( 0 . 9 3 -H f ) X d + B (H f - 0 . 9 3 )  A VFB ^ A (0.93 -H f) X d + B (H f-0.93)
により表現することができると考えられる。 ここで A, Bは定数、 H f は H f の 原子分率である。 It is thought that it can be expressed by Where A and B are constants, and H f is the atomic fraction of H f.
例えば H f 02成分が前記 H f O2膜中に H f の原子パーセントで 9 3 %すな わち H f の原子分率で 0. 93の割合で含まれている場合、 フラットパンド電圧 シフト AVFBは H f 02膜の酵 dに係らずほぼゼロとなる。 また前記 H f O2膜 中における H f O2成分の割合が H f の原子パーセントで 93 %を超える場合に は、 d = 0の場合における AFBの切片は正の傖を有するが、 AFBの値は膜厚 dと 共に負の方向に增大する。 さらに H f O2成分の割合が H f の原子パーセン卜で 93 %未満の場合には d = 0の切片は負の値を有するが、 AFBの値は膜厚 dと共 に Ϊ泉的に正の方向に増大する。 For example, the H f O 2 component contains 93% by atomic percent of H f in the H f O 2 film. That is, when the atomic fraction of H f is included at a ratio of 0.93, the flat band voltage shift AVFB becomes almost zero regardless of the enzyme d of the H f O 2 film. When the proportion of the HfO2 component in the HfO2 film exceeds 93% by atomic percent of Hf, the intercept of AFB at d = 0 has a positive 傖, but the value of AFB is Increases in the negative direction together with the film thickness d. Further, when the proportion of the HfO2 component is less than 93% in atomic percentage of Hf, the intercept at d = 0 has a negative value, but the value of AFB is positively positive with the film thickness d. In the direction of.
本発明ではかかる A 12θ3成分を含み ^ΙΪが d [nm]の H f 02膜中における H f の原子分率で表した組成を、 0. 93-0. 1 9 * (AVFB-O. 005) Zd以上、 0. 93 + 0. 1 9 * (AVFB+O. 005) Zd以下の範囲に設定 することにより、 フラットバンド mi£シフトの値を土 AVFB (ボルト） 以内に納 めることができる。 In the present invention, the composition represented by the atomic fraction of H f in the H f O 2 film containing the A 12θ 3 component and where ^ ΙΪ is d [nm] is 0.93-0.1 9 * (AVFB-O 005) Zd or more, 0.93 + 0.19 * (AVFB + O. 005) By setting the value to Zd or less, the value of the flat band mi £ shift is kept within the soil AVFB (volt). be able to.
特に本発明においてはシリコン基板上に形成される H f O2を主成分とし A 12 03成分を含む high-K誘電体膜中の H f 02成分の割合を H f の原子パーセント で 88〜94%の範囲に、 またこれに対応して膜中の A 1203成分の割合を A 1 の原子パーセントで 12〜 6 %の範囲に設定することによりフラットバンド flff シフトの大きさを最小限に抑制でき、 特に前記 H f 02成分の割合を H f の原子 パーセントで約 93 %に、また前記 A 1203成分の割合を A 1の原子パーセント で 7 %に設定することにより、前記 H f O2を主成分とする high-K誘電体膜中に おけるフラットパンド電圧シフトを、 ほぼ土 5 OmVの範囲に抑制することが可 能になる。 これにより、 膜中の正の固定電荷を実質的に完全に中和することが可 能になる。 Especially 88 to in atomic percent of H f 0 2 The proportions of the components H f in high-K dielectric film containing a H f O2 as a main component A 12 0 3 component formed on a silicon substrate in the present invention minimize the size of the flat band flff shift by a range of 94%, and sets a ratio of a 1 2 0 3 component in the film to correspond to the range 12 to 6% in atomic percent of a 1 can be suppressed to limit, in particular the ratio of the H f 0 2 component about 93% by atomic percent H f, also by setting the ratio of the a 1203 component 7% atomic percent of a 1, the H The flat band voltage shift in the high-K dielectric film containing f O2 as the main component can be suppressed to the range of approximately 5 OmV on the earth. This makes it possible to substantially completely neutralize the positive fixed charges in the film.
このようにして膜中の正の固定電荷が中和された Hf 02膜を MOSトランジ スタのゲート絶縁膜に使うことにより、 チヤネ 域中におけるキヤリァの移動 度を大きく向上させ、 またかかる MOSトランジスタにおける閾値特性の変動を 効果的に捕償することが可能になる。 By using this way a positive fixed charge is neutralized Hf 0 2 film in the film in the gate insulating film of the MOS transistors, greatly improves the mobility of Kiyaria during Chiyane zone, also according MOS transistor It is possible to effectively compensate for fluctuations in the threshold characteristics at.
[第 2実施例] [Second embodiment]
図 6は、 本発明の第 2実施例による MO Sトランジスタ 10の構成を示す。 図 6を参照するに、 MO Sトランジスタ 1 0は S T I型の素子分離構造 1 1 B わにより ( 1 0 0 ) 面方位を有する p型シリコン基板 1 1中に画成された素子領 域 1 1 A上に形成されており、 前記素子領域 1 1 A上には厚さが 0 . 8〜 1 . 0 n mの化学酸化膜 1 2 Aと、 前記ィ匕学酸化膜 1 2 A上に形成された A 1 2O3成分 を A 1の原子％にして約 7 %の割合で含む厚さが 2 0 n mの H f 02膜 1 2 Bと を積層したグート絶縁膜 1 2が形成される。 FIG. 6 shows a configuration of the MOS transistor 10 according to the second embodiment of the present invention. Referring to FIG. 6, the MOS transistor 10 has an STI type element isolation structure 11 1 B and an element region 11 1 defined in a p-type silicon substrate 11 having a (100) plane orientation. A, a chemical oxide film 12A having a thickness of 0.8 to 1.0 nm on the element region 11A, and a chemical oxide film 12A on the element region 11A. and a 1 2O3 Gut insulating film 1 2 the components were laminated and H f 0 2 film 1 2 B with a thickness of 2 0 nm in a proportion of about 7% by atomic% of a 1 is formed.
さらに前記ゲート絶縁膜 1 2上にはポリシリコンあるいは金属よりなるゲート 電極 1 3 Gが形成され、 前記ゲート電極 1 3 Gの側壁面上には、 側壁絶縁膜 1 3 A, 1 3 Bが形成されている。  Further, a gate electrode 13 G made of polysilicon or metal is formed on the gate insulating film 12, and side wall insulating films 13 A and 13 B are formed on a side wall surface of the gate electrode 13 G. Have been.
さらに前記素子領域 1 1 Aには前記ゲート電極 1 3 Gの直下にチャネルドープ 領域 1 1 aが形成されており、 さらに前記シリコン基板 1 1中、 前記ゲート電極 1 3の両側には n型ソースエクステンション領域 1 1 bおよび 1 1 cが形成され ている。また前記ソースエクステンション領域 1 1 bおよび 1 1 cの下端部には、 互いに対向するように、 ドレイン端からの空乏層の延在を抑制することで短チヤ ネル効果を抑制する n +型のボケット注入領域 l i d , l i eがそれぞれ形成さ れている。 また前記素子領域 1 1 Aには前記ゲート側壁絶縁膜 1 3 Aの外側に略 対応して n+型ソース領域 1 1 Sが、 また前記ゲート側壁絶縁膜 1 3 Bの外側に 略対応して n +型ドレイン領域 1 1 Dが形成されている。 前記ゲート電極 1 3 G としてメタル電極を使う場合には、 前記チャネルドープ領域 1 1 aにチャネルと は逆導電型のカウンタードープ領域を形成する。  Further, a channel-doped region 11a is formed in the element region 11A immediately below the gate electrode 13G, and an n-type source is provided on both sides of the gate electrode 13 in the silicon substrate 11. Extension regions 11b and 11c are formed. Further, at the lower ends of the source extension regions 11b and 11c, an n + type pocket which suppresses the short channel effect by suppressing the extension of the depletion layer from the drain end so as to face each other. Injection areas lid and lie are formed respectively. The element region 11A has an n + type source region 11S substantially corresponding to the outside of the gate side wall insulating film 13A, and n corresponds substantially to the outside of the gate side wall insulating film 13B. A + type drain region 11D is formed. When a metal electrode is used as the gate electrode 13G, a counter-doped region having a conductivity type opposite to that of the channel is formed in the channel-doped region 11a.
本実施例では前記 A 1 2O3成分を含む H f 02膜 1 2 Bは先の実施例と同様に、 膜中の固定電荷が実質的に中和されており、 ゲート絶縁膜中における固定電荷に よるチヤネノ^ S域における移動度の減少が抑制され、 また閾値特性の変動が抑制 される。 H f 0 2 film 1 2 B comprising the A 1 2O3 component in this embodiment is similar to the previous embodiments, the fixed charge in the film are substantially neutralized, fixed charges in the gate insulating film As a result, the decrease in mobility in the channel area of the channel is suppressed, and the fluctuation of the threshold characteristic is suppressed.
次に図 7 A- 7 Fを参照しながら、 図 6の MO Sトランジスタ 1 0の製造工程 を説明する。  Next, the manufacturing process of the MOS transistor 10 of FIG. 6 will be described with reference to FIGS. 7A to 7F.
図 7 Aを参照するに、 前記シリコン基板 1 1の表面から自然酸化膜が H F水溶 液により除去され、 次に図 7 Bの工程において図 7 Aの自然酸化膜を除去された シリコン基板 1 1上に好ましくは H C 1と Η2θ2を使つた低温の酸化処理により、 化学酸化膜 12 Aを 1 程度の SU¥に形成する。 Referring to FIG. 7A, the natural oxide film was removed from the surface of the silicon substrate 11 with an HF aqueous solution, and then the silicon substrate 11 from which the natural oxide film of FIG. 7A was removed in the process of FIG. 7B. Above, preferably by a low-temperature oxidation treatment using HC 1 and Η2θ 2 , A chemical oxide film 12A is formed on about 1 SU $.
図 7 Bの工程では、 さらに前記化学酸化膜 12Aを形成された基板を MO C V D装置中に導入し、 H f と A 1の有機金属原料、 例えば H f ( t -OC4H9) 4お ょぴ A 1 (t一 C4H9) 3を酸素ガスと共に 65 P aの圧力下において供給し、.5 00 °Cの基板温度で前記化学酸化膜 12 A上に、 A 12θ3成分を A 1の原子パー セントで 6〜12%、 好ましくは 7%の割合で含む Hf 02膜 12Βを 5〜10In the step of FIG. 7B, the substrate on which the chemical oxide film 12A is formed is further introduced into the MOCVD apparatus, and Hf and an organic metal material of A1, for example, Hf (t-OC4H9) 4 and A 1 (t one C4 H9) 3 was supplied under a pressure of 65 P a with oxygen gas, .5 00 ° to the chemical oxide film 12 a at a substrate temperature of C, a 1 2 .theta.3 component of a 1 atoms per 5% to 10% Hf 02 membrane containing 6 to 12%, preferably 7% in cents
ΠΠ1程度の,に形成する。 に Form about 1
次に図 7 Cの工程においてこのようにして形成された H f 〇2膜 12 Βを窒素 雰囲気中、 800°Cの温度で 30秒間熱処理し、 膜質の改善を行う。 H f 02膜 12 Βは A 12O3成分を実質的な割合で含んでいるため、 このように 800°Cの 温度で熱処理しても結晶化することはなレ、。  Next, in the process of FIG. 7C, the H f {2 film 12} thus formed is heat-treated at a temperature of 800 ° C. for 30 seconds in a nitrogen atmosphere to improve the film quality. Since the Hf02 film 12Β contains a substantial proportion of the A12O3 component, it does not crystallize even at a temperature of 800 ° C.
図 7 Cの工程では前記シリコン基板 1 1の表面にさらに As +あるいは P +を イオン注入により導入し、 チャネルドープ領域 11 aを形成し、 さらにポリシリ コン膜 13を 610 の で堆積する。  In the step of FIG. 7C, As + or P + is further introduced into the surface of the silicon substrate 11 by ion implantation to form a channel-doped region 11a, and a polysilicon film 13 is further deposited by the step 610.
さらに図 7Dの工程においてこのようにして堆積されたポリシリコン膜 13を パターユングしてゲート電極 13 Gを形成し、 さらにかかるゲート電極 13Gを マスクに前記素子領域 1 1 A中に A s +あるいは P +を斜め方向にィォン注入に より導入し、 前記 p+型ポケット注入領域 11 d， 11 eを前記ゲート電極 13 Gの両側に形成する。  Further, the polysilicon film 13 thus deposited in the step of FIG.7D is patterned to form a gate electrode 13G. Further, using the gate electrode 13G as a mask, As + or P + is introduced obliquely by ion implantation to form the p + -type pocket implantation regions 11 d and 11 e on both sides of the gate electrode 13 G.
さらに図 7 Eの工程において図 7 Dの構造に対し、 シリコン基板 11に対して 実質的に垂直に、前記素子領域 11 A中に As +あるいは P+をイオン注入により 導入し、 前記ゲート電極 13 Gの両側に、 前記ポケット注入領域 11 d, l i e に一部重複するように、 浅い接合を有する n+型ソースェクステンション領域 1 1 bおよびドレインェクステンション領域 11 cをそれぞれ形成する。  Further, in the step of FIG. 7E, As + or P + is introduced into the element region 11A by ion implantation substantially perpendicularly to the silicon substrate 11 with respect to the structure of FIG. An n + type source extension region 11b and a drain extension region 11c having shallow junctions are formed on both sides of the substrate so as to partially overlap the pocket injection regions 11d and lie.
さらに図 7 Fの工程において前記ゲート電極 13 Gの側壁面上に側壁絶縁膜 1 3 A, 13 Bを形成した後、 前記ゲート電極 13 Gおよぴ側壁絶縁膜 13 A, 1 3 Bをマスクに前記素子領域 11 A中に A s +あるいは P +をイオン注入により 導入し、 前記ソースエクステンション領域 11 bおよびドレインェクステンショ ン領域 11 cに一部重複するように、 深い接合を有する n+型ソース領域 11 S およびドレイン領域 1 1 Dを形成する。 Further, after forming the side wall insulating films 13 A and 13 B on the side wall surface of the gate electrode 13 G in the step of FIG. 7F, the gate electrode 13 G and the side wall insulating films 13 A and 13 B are masked. As + or P + is introduced into the device region 11A by ion implantation, and an n + type having a deep junction is formed so as to partially overlap the source extension region 11b and the drain extension region 11c. Source area 11 S And a drain region 11D is formed.
本実施例においても、歸己 H f O2を主成分とする high-K誘電体膜 1 2Bが A Also in this embodiment, the high-K dielectric film 12B mainly composed of HfO2
1 2O3成分を含むため、 ゲート絶縁膜中の固定電荷が少なく、 チャネル中におけ るキヤリァの移動度が大きく増大する。 またフラットパンド電圧シフトが小さく なるため、 大きな膜厚の high-K誘電体膜 1 2Bを使つても半導体装置の素子特 性が変化せず、 このため比較的大きな酸化膜換算膜厚の H f 02膜 1 2 Bを使う ことができる。 これに伴い、 前記 H f 02膜 1 2 B中を流れるリーク電流が抑制 される。 Since it contains the 12O3 component, the fixed charge in the gate insulating film is small, and the carrier mobility in the channel is greatly increased. In addition, since the flat band voltage shift is reduced, even if a high-K dielectric film 12B having a large thickness is used, the element characteristics of the semiconductor device do not change. 0 2 film 1 2 B can be used. Accordingly, a leak current flowing through the Hf02 film 12B is suppressed.
図 6の半導体装置 1 0は ηチャネル MO S トランジスタであるが、 各イオン注 入工程において導入される不純物元素の導電型を反転させることにより、 同様な 構成の ρチャネル MO Sトランジスタを作製することも可能である。  Although the semiconductor device 10 in FIG. 6 is an η-channel MOS transistor, a ρ-channel MOS transistor having a similar configuration can be manufactured by inverting the conductivity type of the impurity element introduced in each ion implantation step. Is also possible.
また前記半導体装置 1 0を、 図示は省略するが、 シリコン基板上に形成された 歪み S i G e層上に、 あるいは S i G e層上に形成された歪み S i層上に形成す ることも可能である。  Although not shown, the semiconductor device 10 is formed on a strained SiGe layer formed on a silicon substrate or on a strained Si layer formed on a SiGe layer. It is also possible.
[第 3実施例] [Third embodiment]
本努明による A 1 203成分を含み固定電荷を中和した H f 02膜は、フラッシュ メモリのトンネル絶縁膜に使うことも可能である。 H f 0 2 film that neutralized fixed charge comprises A 1 2 0 3 ingredients according TsutomuAkira is also possible to use the tunnel insulating film of the flash memory.
図 8は、 本発明の第 3実施例による積層グート構造を有するフラッシュメモリ 3 0の構成を示す。  FIG. 8 shows a configuration of a flash memory 30 having a laminated Gut structure according to a third embodiment of the present invention.
図 8を参照するに、 フラッシュメモリ 3 0は素子分離構造 3 1 Bにより素子領 域 3 1 Aが画成された p型シリコン基板 3 1上に形成されており、 前記素子領域 3 1 A上には膜厚が 0. 8 nm程度のシリコン熱酸化膜 3 2 Aを介して A I 2O3 成分を A 1の原子パーセントにして 7 %含む H f 02膜 3 3 8が7 11 111の物理膜 厚に形成されている。 このようにして形成されたシリコン熱酸化膜 3 2 Aと H f O2膜とはフラッシュメモリのトンネル絶縁膜 3 2を形成する。 Referring to FIG. 8, the flash memory 30 is formed on a p-type silicon substrate 31 in which an element region 31A is defined by an element isolation structure 31B. Contains 7% of the AI 2 O 3 component in atomic percent of A 1 through the silicon thermal oxide film 3 2 A with a film thickness of about 0.8 nm.H f 0 2 film 3 3 8 is a physical film with 7 11 111 It is formed thick. The silicon thermal oxide film 32A and the HfO2 film thus formed form a tunnel insulating film 32 of a flash memory.
さらに前記トンネル絶縁膜 3 2上にはポリシリコンフローテイングゲート電極 3 3が形成され、 さらに前記ポリシリコンフローティングゲート電極 3 3上には C VD - S i 02などよりなる中間絶縁膜 3 4を介してコントロールゲート電極 35が形成されている。 Further, the on the tunnel insulating film 3 2 is a polysilicon floating gate electrode 3 3 formed further on the polysilicon floating gate electrode 3 3 C VD - the S i 0 2 intermediate insulating film 3 4 including, for example, Through control gate electrode 35 are formed.
また前記素子領域 31 A中、 前記フローティングゲ一ト電極 33とコントロー ルゲート電極 35とを含む積層ゲート構造 35 Gの両側には、 イオン注入工程に より、 n型ソース領域 31 Sおよびドレイン領域 3 IDが形成される。  In the element region 31A, an n-type source region 31S and a drain region 3ID are formed on both sides of a stacked gate structure 35G including the floating gate electrode 33 and the control gate electrode 35 by an ion implantation process. Is formed.
かかる構成のフラッシュメモリ 30では、 前記 Hf 02膜 32B中の固定電荷 が A Ι2Ο3成分を導入することにより中和され、その結果、前記 Hf 02膜 32Β の Effを増大させても膜 32 Β中の電荷により、 フラッシュメモリの動作特性が 影響されることがない。 また前記 Hf 〇2膜 32 Bの膜厚を増大させることによ り、 フローティングゲ一ト電極 33に蓄積された電荷がリークする問題が解消す る。 In flash memory 30 of the above configuration, the fixed charge in the Hf 02 film 32B is neutralized by introducing A Iota2omikuron3 component, as a result, the Hf 0 2 film 32Β tunica 32 beta also increase the Eff The operating characteristics of the flash memory are not affected by these charges. The Ri by the increasing the thickness of the Hf 〇 2 film 32 B, the charge accumulated in the floating gate Ichito electrode 33 that solve the problem of leakage.
なお、以上の説明では、前記 A 1203成分を含む H f 02膜を、 H f の原料とし て Hf(t— OC4H9) 4を、 A 1の原料として A 1 (t - C4H9) 3を使った MO CVD法により形成したが、 本発明はかかる特定の製造方法に限定されるもので はなく、 例えば H f の原料として H f (N (CH3) 2) 4, Hf (N (CHs) (C2 H5)) 4, Hf (N (C2H5) 2) 4等を、 また A 1の原料として A 1 (C2H5) 3, Al (CH3) 3等を使うこともできる。 さらに本発明では前記 A 12〇3成分を含 む Hf 02膜を MOCVD法により形成したが、 これを ALD (原子層堆積） 法 により形成することも可能である。 In the above description, the A 1 2 0 3 and H f 0 2 film containing the component, the Hf (t- OC4H9) 4 as the raw material for H f, A 1 as a raw material of A 1 (t - C4H9) was formed by MO CVD method using 3, the present invention is not limited to such a specific production method, for example, as a raw material for H f H f (N (CH3 ) 2) 4, Hf (N ( CHs) (C 2 H5)) 4, Hf and (N (C2H5) 2) 4 and the like, can also be used a 1 (C2H5) 3, Al (CH 3) 3 or the like as a raw material of a 1. Further in the present invention is formed by the A 1 2 〇 3 MOCVD method including Hf 0 2 membrane components, but it is also possible that this is formed by ALD (atomic layer deposition) process.
さらに正の固定電荷は Hf 02膜のみならず、 Z r 02膜においても生じるため、 Z r02膜中に A 1203成分を適量導入することにより、膜中の固定電荷を中和す ることも可能である。 Further positive fixed charges not only Hf 0 2 retina, since also occurs in Z r 0 2 film, by a suitable amount introducing A 1 2 0 3 component Z r0 2 film, a fixed charge in the film It is also possible to make a sum.
さらに、 図.6の半導体装置 10において、 化学酸化膜 12 Aを省略し、 直接に シリコン基板 11の表面に A 12θ3成分を含む H f O2膜を形成することも可能 。、あ 。 Further, in the semiconductor device 10 of FIG .6, chemical oxide film is omitted 12 A, can also form H f O2 membrane directly on the surface of the silicon substrate 11 including the A 12θ 3 components. ,Ah .
以上、 本発明を好ましい実施例について説明したが、 本発明は上記の特定の実 施例に限定されるものではなく、 特許請求の範囲に記載した要旨内において様々 な変形 ·変更が可能である。 産業上の利用可能性 本発明によれば、 H f O2膜中に A 1 2O3成分を A 1の原子パーセントで 6〜 1 2 %の割合で導入することにより、 H f 02膜中の固定電荷が実質的に中和され、 チャネル中におけるキヤリァの移動度が大きく向上する。 またゲート絶縁膜中に 含まれる固定電荷が除去されるため、 フラットパンド電圧シフトの問題、 および これに伴う閾値 の変化の問題が抑制される。 Although the present invention has been described with reference to preferred embodiments, the present invention is not limited to the above-described specific embodiments, and various modifications and changes can be made within the scope of the claims. . Industrial applicability According to the present invention, the medium of the A 1 2O3 ingredient in H f O2 membrane by introducing at a rate of 6-1 2% atomic percent of A 1, fixed charge H f 0 2 film are substantially And the carrier mobility in the channel is greatly improved. In addition, since the fixed charges contained in the gate insulating film are removed, the problem of the flat band voltage shift and the problem of the threshold change accompanying the flat band voltage shift are suppressed.

Claims

請求の範囲 The scope of the claims
1 . チャネルを構成するシリコン層と、 1. The silicon layer that constitutes the channel,
ttif己シリコン層上に形成されたゲ一ト絶縁膜と、  a gate insulating film formed on the self-silicon layer;
前記グート絶縁膜上に形成されたゲート電極と、  A gate electrode formed on the gut insulating film;
前記シリコン層中、 前記前記ゲート電極の両側に形成されたソース領域およぴ ドレイン領域とよりなる半導体装置において、  A semiconductor device comprising: a source region and a drain region formed on both sides of the gate electrode in the silicon layer.
前記ゲート絶縁膜は、 A 1 2O3成分を A 1の原子パーセントで 6〜 1 2 %の割 合で含む H f 02膜よりなることを特徴とする半導体装置。 The gate insulating film, a semiconductor device characterized by consisting of H f 0 2 film containing A 1 2O3 component 6-1 2% proportion in atomic percent of A 1.
2 . 前記 H f O2膜は、 A 1 2O3成分を、 A 1の原子パーセントで 7 %の割合 で含むことを特徴とする請求項 1記載の半導体装置。 2. The H f O 2 film, the A 1 2O3 component, the semiconductor device according to claim 1, characterized in that it comprises a proportion of 7% in atomic percent of A 1.
3. 前記半導体装置は、 ± 5 0 mV以下フラットバンド電圧シフトを有する ことを特徴とする請求項 2記載の半導体装置。  3. The semiconductor device according to claim 2, wherein the semiconductor device has a flat band voltage shift of ± 50 mV or less.
4. 前記グート絶縁膜は、 さらに前記 A 1 203成分を含む H f 02膜と前記シ リコン層との間に酸化膜を含むことを特徴とする請求項 1記載の半導体装置。 4. The Gut insulating film further semiconductor device according to claim 1, wherein the oxide-containing film between the H f 0 2 film and the divorced layer comprising the A 1 2 0 3 component.
5 . 前記 A 1 2θ3成分を含む H f 02膜は、膜中にアルミン酸ハフニウムを含 むことを特徴とする請求項 1記載の半導体装置。 5. The A 1 2 θ3 H f 0 2 film containing component, a semiconductor device according to claim 1, wherein the free Mukoto aluminate hafnium in the film.
6 . シリコン基板と、  6. Silicon substrate and
前記シリコン基板上に形成されたトンネル絶縁膜と、  A tunnel insulating film formed on the silicon substrate,
前記トンネル絶縁膜上に形成されたフローティングゲ一ト電極と、  A floating gate electrode formed on the tunnel insulating film;
前記フローティングゲ一ト電極上に絶縁膜を介して形成されたコントロールゲ ート電極と、 - 前記シリコン基板中、 前記コントロールゲート電極の両側に形成された一対の 拡散領域とよりなるフラッシュメモリ素子において、  A flash memory device comprising: a control gate electrode formed on the floating gate electrode via an insulating film; and-a pair of diffusion regions formed on both sides of the control gate electrode in the silicon substrate. ,
前記トンネル絶縁膜は、 A 1 2O3成分を A 1の原子パーセントで 6 ~ 1 2 %の 割合で含む H f 02膜よりなることを特徴 するフラッシュメモリ素子。 The tunnel insulating film, a flash memory device which characterized by consisting of H f 0 2 film containing A 1 2O3 component at a ratio of 6 -1 2% in atomic percent of A 1.
7. 前記 H f O2膜は、 A 1 203成分を、 A 1の原子パーセントで 7 %の割合 で含むことを特徴とする請求項 6記載の半導体装置。 7. The H f O 2 film, A 1 2 0 3 component, a semiconductor device according to claim 6, characterized in that it comprises a proportion of 7% in atomic percent of A 1.
8 . シリコン層と、 前記シリコン層上に形成された、 正の固定電荷を含む誘電体膜よりなるゲート 絶縁膜と、 8. Silicon layer, A gate insulating film formed on the silicon layer and made of a dielectric film containing a positive fixed charge;
前記誘電体膜上に形成されたゲート電極と、  A gate electrode formed on the dielectric film,
前記シリコン層中、 前記ゲート電極の両側に形成されたソース領域おょぴドレ ィン領域とよりなる半導体装置において、  A semiconductor device comprising a source region and a drain region formed on both sides of the gate electrode in the silicon layer;
前記ゲート絶縁膜は、 前記固定電荷を実質的に中和する量の A 1 2O3成分を含 むことを特徴とする半導体装置。  The semiconductor device, wherein the gate insulating film contains an amount of A12O3 component that substantially neutralizes the fixed charge.
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