WO2004064139A3 - Halbleiterchipstapel und verfahren zur passivierung eines halbleiterchipstapels - Google Patents

Halbleiterchipstapel und verfahren zur passivierung eines halbleiterchipstapels Download PDF

Info

Publication number
WO2004064139A3
WO2004064139A3 PCT/DE2003/003961 DE0303961W WO2004064139A3 WO 2004064139 A3 WO2004064139 A3 WO 2004064139A3 DE 0303961 W DE0303961 W DE 0303961W WO 2004064139 A3 WO2004064139 A3 WO 2004064139A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor chip
chip stack
passivating
spacer
chip
Prior art date
Application number
PCT/DE2003/003961
Other languages
English (en)
French (fr)
Other versions
WO2004064139A2 (de
Inventor
Holger Huebner
Original Assignee
Infineon Technologies Ag
Holger Huebner
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Holger Huebner filed Critical Infineon Technologies Ag
Priority to EP03788833A priority Critical patent/EP1581965A2/de
Publication of WO2004064139A2 publication Critical patent/WO2004064139A2/de
Publication of WO2004064139A3 publication Critical patent/WO2004064139A3/de
Priority to US11/180,039 priority patent/US7229851B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

Bei dem Halbleiterchipstapel ist ein zwischen den Halbleiterchips (1, 2) vorhandener Zwischenraum zumindest längs eines Randes der Oberseite des Top-Chips (2) durch einen Spacer (7) aus einem fotostrukturierbaren Polymer, einem Fotolack, einer Vergussmasse oder einem Klebstoff gefüllt und so nach außen verschlossen. Dabei sind die Anschlusskontaktflächen (5) für Bonddrähte (6) oder andere externe Anschlüsse auf der Oberseite des Bottom-Chips (1) von dem Material dieses Spacers frei gehalten.
PCT/DE2003/003961 2003-01-10 2003-12-02 Halbleiterchipstapel und verfahren zur passivierung eines halbleiterchipstapels WO2004064139A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP03788833A EP1581965A2 (de) 2003-01-10 2003-12-02 Halbleiterchipstapel und verfahren zur passivierung eines halbleiterchipstapels
US11/180,039 US7229851B2 (en) 2003-01-10 2005-07-11 Semiconductor chip stack

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10300711A DE10300711B4 (de) 2003-01-10 2003-01-10 Verfahren zur Passivierung eines Halbleiterchipstapels
DE10300711.3 2003-01-10

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/180,039 Continuation US7229851B2 (en) 2003-01-10 2005-07-11 Semiconductor chip stack

Publications (2)

Publication Number Publication Date
WO2004064139A2 WO2004064139A2 (de) 2004-07-29
WO2004064139A3 true WO2004064139A3 (de) 2005-04-21

Family

ID=32519818

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/003961 WO2004064139A2 (de) 2003-01-10 2003-12-02 Halbleiterchipstapel und verfahren zur passivierung eines halbleiterchipstapels

Country Status (4)

Country Link
US (1) US7229851B2 (de)
EP (1) EP1581965A2 (de)
DE (1) DE10300711B4 (de)
WO (1) WO2004064139A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1688997B1 (de) 2005-02-02 2014-04-16 Infineon Technologies AG Elektronisches Bauteil mit gestapelten Halbleiterchips
KR100699807B1 (ko) * 2006-01-26 2007-03-28 삼성전자주식회사 적층 칩 및 그를 갖는 적층 칩 패키지
TWI303874B (en) * 2006-08-08 2008-12-01 Via Tech Inc Multi-chip structure
US8618670B2 (en) * 2008-08-15 2013-12-31 Qualcomm Incorporated Corrosion control of stacked integrated circuits

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0348972A2 (de) * 1988-07-01 1990-01-03 Sharp Kabushiki Kaisha Halbleiteranordnung und Verfahren zum Herstellen derselben
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
US5930599A (en) * 1996-02-19 1999-07-27 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US20020115233A1 (en) * 2000-12-26 2002-08-22 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
WO2002095817A2 (de) * 2001-05-21 2002-11-28 Infineon Technologies Ag Halbleiterbauelement mit zumindest einem halbleiterchip auf einem als substrat dienenden basischip und verfahren zu dessen herstellung

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6337265B1 (en) * 1999-09-03 2002-01-08 Teraconnect, Inc. Method for integration of integrated circuit devices
AU1821101A (en) * 1999-10-13 2001-04-23 Teraconnect, Inc. Method of equalizing device heights on a chip
CN1251318C (zh) * 2002-02-25 2006-04-12 精工爱普生株式会社 半导体芯片、半导体装置和它们的制造方法以及使用它们的电路板和仪器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0348972A2 (de) * 1988-07-01 1990-01-03 Sharp Kabushiki Kaisha Halbleiteranordnung und Verfahren zum Herstellen derselben
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
US5930599A (en) * 1996-02-19 1999-07-27 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US20020115233A1 (en) * 2000-12-26 2002-08-22 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
WO2002095817A2 (de) * 2001-05-21 2002-11-28 Infineon Technologies Ag Halbleiterbauelement mit zumindest einem halbleiterchip auf einem als substrat dienenden basischip und verfahren zu dessen herstellung

Also Published As

Publication number Publication date
US20060001177A1 (en) 2006-01-05
WO2004064139A2 (de) 2004-07-29
EP1581965A2 (de) 2005-10-05
DE10300711B4 (de) 2007-10-04
DE10300711A1 (de) 2004-07-22
US7229851B2 (en) 2007-06-12

Similar Documents

Publication Publication Date Title
US7507603B1 (en) Etch singulated semiconductor package
US9362210B2 (en) Leadframe and semiconductor package made using the leadframe
US8194896B2 (en) Packaging structure and method of a MEMS microphone
US7473584B1 (en) Method for fabricating a fan-in leadframe semiconductor package
TWI268628B (en) Package structure having a stacking platform
WO2002086970A3 (en) Semiconductor device and method of manufacturing the same
US6798047B1 (en) Pre-molded leadframe
WO2004034433A3 (en) Semiconductor stacked multi-package module having inverted second package
WO2003017327A3 (en) A method and apparatus for die stacking
WO2004004005A1 (ja) 半導体装置およびその製造方法
EP1089335A4 (de) Halbleitervorrichtung
WO2007050287A3 (en) Semiconductor structure and method of assembly
WO2005059967A3 (en) Multiple chip package module having inverted package stacked over die
WO2007050422A3 (en) Plastic packaged device with die interface layer
US20080003718A1 (en) Singulation Process for Block-Molded Packages
US20130157414A1 (en) Stacked-die package and method therefor
WO2004027823A3 (en) Semiconductor multi-package module having wire bond interconnection between stacked packages
EP1906452A4 (de) Halbleiterbauelement und verfahren zu seiner herstellung
KR20050089825A (ko) 오버몰드된 플라스틱 패키지를 위한 히트싱크 또는플래그용 소형 몰드로크들
WO2004070792A3 (en) Thin multiple semiconductor die package
WO2004100261A3 (de) Halbleiterwafer, nutzen und elektronisches bauteil mit gestapelten halbleiterchips, sowie verfahren zur herstellung derselben
EP0886313A4 (de) Harzversiegelte halbleitervorrichtung und herstellungsverfahren
WO2004064139A3 (de) Halbleiterchipstapel und verfahren zur passivierung eines halbleiterchipstapels
WO2006023184A3 (en) Qfn package and method therefor
TW200504900A (en) A semiconductor device and the manufacturing method thereof

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): BR CN IN JP KR MX RU UA US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 11180039

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2003788833

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2003788833

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 11180039

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP

WWW Wipo information: withdrawn in national office

Ref document number: 2003788833

Country of ref document: EP