WO2004040768A1 - Phase comparison gain detecting circuit, erroneous synchronization detecting circuit and pll circuit - Google Patents
Phase comparison gain detecting circuit, erroneous synchronization detecting circuit and pll circuit Download PDFInfo
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- WO2004040768A1 WO2004040768A1 PCT/JP2002/011319 JP0211319W WO2004040768A1 WO 2004040768 A1 WO2004040768 A1 WO 2004040768A1 JP 0211319 W JP0211319 W JP 0211319W WO 2004040768 A1 WO2004040768 A1 WO 2004040768A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Definitions
- Phase comparison gain detection circuit Phase comparison gain detection circuit, false synchronization detection circuit, and PLL circuit
- the present invention relates to a phase comparison gain detection circuit, a false synchronization detection circuit, and a PLL circuit, and particularly to a PLL circuit that can be applied to a case where a reference cook signal is extracted from received data in an optical transceiver for optical communication, and
- the present invention relates to a phase comparison gain detection circuit and a false synchronization detection circuit that can be applied thereto.
- FIG. 1A shows a general configuration of a PLL circuit for clock extraction.
- the phase difference between the clock signal CL, which is the output of the VCO (voltage controlled oscillation circuit) 40, and the input data DA is detected by the phase comparator 10, and the charge pump 20 is driven according to the detected output.
- a current proportional to the output of the phase comparator is supplied to the loop filter 30.
- the supply current is smoothed by the loop filter 30, and the result is fed back to VC400.
- FIG. 1B is a circuit diagram showing an example of the configuration of the loop filter 30.
- the loop filter 30 is composed of a series circuit of a resistor R and a capacitor C, and has a function of smoothing an input current and converting it into an output voltage.
- the PLL circuit can obtain the clock signal CL synchronized with the input data signal DA.
- the phase comparison gain in phase comparator 10 is Kp
- the current amplitude in charge pump 20 is Ic
- the transfer function of loop filter 30 is F (s)
- the gain of VCO KV.
- Open loop gain [ ⁇ ⁇ I c ⁇ F (s) ⁇ Kv] / s
- open loop gain [Kp ⁇ Ic ⁇ R ⁇ KvZs] ⁇ [1 + 1 / s CR]
- closed loop gain [ ⁇ ⁇ Ic ⁇ R ⁇ ⁇ ⁇ (1 + s CR)] / [s ⁇ 2 ⁇ CR + Kp ⁇ Ic ⁇ R ⁇ Kv ⁇ (1 + sCR)]
- the closed loop gain power-off frequency is a frequency at which the open loop gain becomes 0 dB, and is proportional to the respective gains of the phase comparator 10, the charge pump 20, and the VC040 (Fig. 2A). See).
- the cutoff frequency becomes high, and as a result, the output jitter tends to increase.
- the cutoff frequency is low, which tends to reduce the phase margin and increase peaking. In that case, the phase error response tends to be poor.
- the closed-loop characteristic as the jitter characteristic of PLL is equivalent to a so-called jitter transfer, and is represented by the amplification factor of the output jitter with respect to the input jitter when the PLL is locked. This value is better as the response speed of PLL is slower.
- jitter tolerance which is an index of how much jitter the PLL can withstand in a licked state, conversely, the higher the response speed of the PLL, the greater the tolerance. Therefore, they are in a trade-off relationship with each other.
- FIG. 3 is a block diagram showing an example of an identification timing signal extraction circuit to which the PLL method is applied.
- the data of the input data signal DA is extracted by the identification circuit 100 based on the clock signal CL extracted by the PLL circuit function as described above.
- a PLL circuit in such an optical transmitting and receiving circuit unlike a PLL circuit used in a general frequency synthesizer, random data is input as an input data signal. Therefore, when the frequency of the input signal fluctuates greatly, the level of the frequency component value to be extracted relatively decreases, and as a result, the PLL loop gain decreases and the operation becomes unstable.
- FIG. 4 shows a well-known half-rate clock Bang— A circuit example when a Bang circuit is applied is shown.
- two D-FF (D-flip-flop) circuits detect the input data signal DA and detect the edge of the clock signal for data identification by delaying it by ⁇ / 2 phase.
- the data identification operation is performed by the clock signals CL and.
- the exclusive OR circuit EXOR performs an exclusive OR operation on the resulting signals Da and Db to obtain a signal Dc.
- the exclusive OR sum Dc becomes an intermittent signal as shown in FIG.
- the exclusive logical sum output Dc is likely to be a continuous signal.
- the level of the signal obtained through such a low-pass filter by the charge pump 20 and the loop filter 30 with respect to such a phase comparison result is, as shown in FIG.
- the output level of the low-pass filter becomes high.
- the oscillation frequency of VCO 40 is controlled according to the output level of the low-pass filter.
- the VCO oscillation frequency is reduced to act to delay the phase of the clock signal CL in accordance with the phase of the data signal.
- the VCO oscillation frequency increases, and acts to advance the phase of the clock signal with respect to the data signal.
- FIGS. 14A and 14B show examples of output waveforms of the phase comparator 10 having the configuration as shown in FIG.
- the ideal output characteristic shown by the broken line is actually shown by the solid line due to the input jitter, the effect of the setup and hold operation characteristics of the D-FF circuit in the phase comparator, etc.
- the waveform is rounded as described above.
- the waveform becomes rounded depending on the edge ratio of the input data.
- the loop gain of the PLL circuit fluctuates, thereby causing the above-mentioned unstable circuit operation. Disclosure of the invention
- an object of the present invention is to provide a PLL circuit capable of providing a stable PLL circuit operation irrespective of fluctuations in the edge ratio and duty of input data, effects of circuit characteristics, and the like.
- phase comparison operations are performed with different phase conditions with respect to identification of an input data signal, and the phase comparison gain is detected by comparing the respective phase comparison results. Therefore, it is possible to detect the on-time phase comparison gain in consideration of the fluctuation factors of the phase comparison gain such as the edge ratio and duty of the input data signal and the setup and hold characteristics of the discriminator. As a result, on-time and accurate loop gain compensation control can be realized by controlling the loop gain of the PLL circuit based on the phase comparison detection result.
- FIGS. 1A and 1B are diagrams showing a configuration of a conventional PLL circuit.
- FIGS. 2A and 2B are diagrams illustrating the loop gain of the PLL circuit.
- FIG. 3 is an explanatory diagram of the operation of the conventional PLL circuit.
- FIG. 4 is a diagram showing a circuit example of a conventional half-rate clock Bang-Bang phase comparator.
- FIG. 5 is a diagram for explaining the data identification phase.
- FIG. 6 is a time chart (part 1) of each signal in the circuit of FIG.
- FIG. 7 is a time chart (part 2) of each signal in the circuit of FIG.
- FIG. 8 is a time chart (part 3) of each signal in the circuit of FIG.
- FIG. 9 is a time chart (part 4) of each signal in the circuit of FIG.
- FIG. 10 is a time chart (part 5) of each signal in the circuit of FIG.
- FIG. 11 is a time chart (part 6) of each signal in the circuit of FIG.
- FIG. 12 is a time chart (part 7) of each signal in the circuit of FIG.
- FIG. 13 is a time chart (No. 8) of each signal in the circuit of FIG.
- FIGS. 1A and 4B are diagrams (part 1) for explaining the state of deterioration of the phase comparison characteristic.
- FIG. 15 is a circuit block diagram of an example of a PLL circuit having a phase comparison gain compensation function.
- FIG. 16 is a circuit diagram showing an example of the phase comparison gain detection circuit.
- FIG. 17 is a diagram (part 2) for explaining the state of deterioration of the phase comparison characteristic.
- FIG. 18 is a block diagram of one embodiment of the present invention.
- FIG. 19 is a diagram for explaining the principle of detecting the phase comparison gain by the configuration shown in FIG.
- FIG. 20 is a circuit diagram of one embodiment of the present invention.
- FIG. 21 is a time chart of each signal in the circuit shown in FIG.
- FIG. 22 is a diagram for explaining the principle of phase comparison gain detection by the configuration shown in FIG. 20.
- FIG. 23 is a circuit diagram of a P-mode according to an embodiment of the present invention using the phase comparison detection circuit having the configuration shown in FIG.
- FIG. 25 is a diagram for explaining the principle of phase comparison gain detection by the configuration shown in FIG.
- FIG. 26 is a circuit diagram of a false synchronization detecting circuit according to still another embodiment of the present invention.
- FIG. 27 is a diagram for explaining the principle of false synchronization detection by the configuration shown in FIG. Description of the preferred embodiment
- the gain change of the PLL circuit (for example, the circuit shown in FIG. 15) as described above is compensated by detecting the gain of VC040, the gain of phase comparator 10 is detected based on the edge rate of data DA. Then, a method of adjusting the output current of the charge pump 20 based on the detection result, or adjusting the capacitance value or the resistance value of the filter 30 and compensating the same can be considered.
- the gain of the phase comparison note 10 is detected by the phase comparison gain circuit 210, and the characteristics of the charge pump are controlled by the control circuit 220 based on the detection result.
- the phase comparator 10 has a sawtooth phase comparison characteristic (see FIG. 17) like a well-known Hogge phase comparator as shown in FIG. 16, for example, the phase period is determined.
- the output amplitude determines the gain.
- the phase comparison gain compensating circuit as shown in FIG. 15 the fluctuation of the amplitude due to the fluctuation of the edge ratio of the data is detected. That is, in this case, the output of the EXOR circuit 21 3 becomes “H” when the data has an edge, that is, “H” when the data changes, and “L” when there is no data.
- the edge rate of the data can be detected by averaging this with L PF (a circuit using R and C).
- the control circuit 220 compensates for the fluctuation of the output amplitude of the phase detector by adjusting the current of the charge pump 20.
- phase comparison gain is determined according to the stochastic fluctuation of the phase comparator output.
- the fluctuation factors of the phase comparison gain include, in addition to the fluctuation of the data edge ratio, (1) the jitter of the input data, and (2) the input data.
- the jitter of the input data, the duty of the input data, and the setup / hold characteristics of the discriminator (FF) of the phase comparator vary.
- a circuit for accurately detecting a change in the phase comparison gain due to the change and the like is also possible.
- FIG. 18 is a principle diagram of one embodiment of the present invention.
- the phase comparison detector 300 includes a phase comparator 311, which receives a clock signal CL for identifying the data DA as an input, and delays the data identification clock signal CL by a predetermined time to generate a clock signal CL. It comprises a delay unit 313 for outputting, a phase comparator 312 having the delayed clock signal CL, as an input, LPFs 314 and 315 for smoothing the output, and a difference voltage detection circuit 316.
- the data identification operation is performed by the two clock signals CL and CL having different phases, respectively.
- a desired phase comparison gain is detected from the time difference between each of the phase comparator outputs D 1 and D 2 and the clock signals CL and CL ′, that is, from the predetermined delay time. This makes it possible to detect the phase comparison gain that incorporates the setup and hold time of the phase comparator, the edge rate and jitter of the input data, and the fluctuation of the duty and the parallelism, etc. Therefore, by controlling based on the detection output, the loop gain of the entire PLL circuit can be compensated so as to be constant. Therefore, a stable response characteristic is obtained, and a PLL circuit satisfying a desired jitter transfer characteristic can be provided.
- FIG. 19 shows the output levels of the phase comparators 311 and 312 for explaining the principle of the embodiment of the present invention.
- the phase comparison characteristics in FIG. 19 correspond to those shown in FIGS. 14A and 14B. I do.
- the phase comparison output is The rate of change, that is, AVZ ( ⁇ t / T), corresponds to the phase comparison gain Kp.
- AV is the difference voltage between the values D 1 and D 2 obtained by smoothing the phase comparison output under different phase conditions
- ⁇ t is the delay unit 313 that provides the difference in the phase conditions.
- T is the signal period of the clock signal.
- FIG. 20 shows a configuration of a phase comparison detection circuit according to an embodiment of the present invention, which further embodies the configuration of FIG.
- This circuit is a phase comparison gain detection circuit to which a Bang-Bang phase comparator using a half-rate clock is applied.
- the circuit is provided with data discriminators 411, 412, data edge detection discriminator 413, and phase comparison gain detection discriminator 414 as discriminators (FF).
- a circuit 431 that performs a logic operation between the data identification FF output DO a and the data edge detection FF output DOc as an OR circuit (EX OR). Similarly, a logic between the data identification FF output DO b and the data edge detection FF output DO c.
- the appearance probability of the H level at the output P h1 of the EXOR circuit 441 is approximately equal to the appearance probability of the H level at the output P h 2 of the EXOR 442. Become equal.
- the appearance probability of the H level is higher than each of the former. That is, EXOR circuit
- the probability that DO a and DO d as inputs of 443 match is the probability that DO a and DO c as inputs of EXOR circuit 441 match or DO b and DO c as inputs of EXOR circuit 442 This is because the probability of matching is lower.
- the occurrence probability of the A-system data in the signal DO d is smaller than the appearance probability of the A-system data in the signal DO c, and similarly, the occurrence probability of the B-system data in the signal DO c This is because the appearance probability of A-system data in DO d is smaller.
- the clock signal C Lb intentionally delayed by a predetermined time ⁇ t is generated to perform data identification, and the identification result data is identified by the clock CL not delayed by At.
- Exclusive OR with the data of the identified result.
- an exclusive OR of the identification result data obtained by performing the data identification using the edge detection clock signal CLa and the identification result data obtained by using the clock CL which is not delayed by ⁇ t is calculated.
- the result of these two types of exclusive OR is smoothed by LPF, and the level difference is divided by the phase obtained by standardizing the delay amount ⁇ t with the period T to obtain the phase comparison gain Kp.
- a delay ⁇ t is intentionally generated after synchronization is established, and a clock signal (signal C Lb in the examples of FIGS. 20 and 21) is generated in a pseudo manner in synchronization with the data signal DA.
- Pseudo-synchronous shift The same data signal DA is identified by the clock signal. Then, the exclusive OR output between the identification data obtained therefrom and the data identified by the clock signal CLa delayed by ⁇ / 2 is smoothed to obtain a “pseudo synchronization shift” phase comparison detection value.
- the exclusive data between the identification data identified by the clock signal CL in the synchronized state and the data identified by the clock signal CLa also delayed by ⁇ 2 The value obtained by smoothing the logical sum output, that is, "the phase comparison detection value at the time of synchronization" is compared. It can be said that the larger the difference between the comparison results, the higher the phase comparison detection sensitivity to the phase difference between the data signal DA and the clock signal CL, which is synonymous with the higher phase comparison gain.
- the phase comparison gain incorporating all of the current edge ratio, duty, setup / hold characteristics of each discriminator (FF), and the like is obtained, and therefore, it is very accurately turned on. Effective phase comparison gain of time Is possible.
- FIG. 23 shows an example of a PLL circuit having a phase comparison gain compensation function according to an embodiment of the present invention.
- the phase comparison output Ph 1 and Ph 3 of the phase comparator detection circuit 400 having the configuration of FIG. A / D converter 510 that converts the difference voltage between the two into a digital signal, compares the digital difference voltage with a predetermined reference value, adjusts the output current of the charge pump based on the comparison result, and thereby adjusts the PL. It has a configuration to compensate for the loop gain of the L circuit.
- the data outputs D Oa and DOb of the phase comparison detection circuit 400 shown in FIG. 20 can be used as they are as the reproduction data of the input data. That is, these data outputs DOa and DOb correspond to the outputs of the identification circuit 100 in FIG.
- the loop gain of the PLL circuit is determined based on the phase comparison output difference voltage between the “pseudo-synchronization” identification signal and the “synchronization” identification signal obtained by the phase comparison detection circuit 400. For control, it is possible to provide a PLL circuit having an accurate loop gain compensation function taking into account the current input signal characteristics and phase comparison circuit characteristics.
- the control circuit 520 is not limited to the circuit configuration shown in FIG. 23, and the transfer function F (s) of the filter 30 and the gain of the VC040, which determine the loop gain of the PLL circuit other than the output current amplitude Ic of the charge pump, It goes without saying that a configuration may be adopted in which the loop gain of the PLL circuit is compensated by controlling Kv and the like.
- the Bang-angang phase comparator using the half-rate clock is applied to the phase comparison detection circuit 400.
- the phase comparison characteristic using the full-rate clock has a sawtooth waveform.
- the present invention can be applied to a phase comparator as shown in FIG. FIG. 24 shows a circuit configuration example of the phase comparison detection circuit in that case.
- the discriminator 611 that identifies the data signal DA at the timing of the clock signal C and the data signal DA are delayed by a predetermined amount by the delay signal 622 from the clock signal CL.
- a discriminator 612 for discriminating by.
- EXO which takes the exclusive OR of each of the discrimination outputs DO 1 and DO 2 by these discriminators 611 and 612 and the data signal DA R631, 632 are provided, and low-pass filters 641, 642 for smoothing the outputs of these EXORs 631, 632 are provided.
- FIG. 25 is a diagram for explaining the difference voltage obtained in that case.
- the difference voltage ⁇ between the outputs Ph 1, Ph 2 of the LPFs 64 1, 642 detected here and Ph 2 is the delay phase amount obtained by standardizing ⁇ t, which is the delay amount by the delay unit 622, with the period T.
- ⁇ t / T which represents, the phase comparison gain Kp can be obtained (see the following equation).
- the control circuit 520 shown in FIG. 23 determines the loop gain determining factor parameters such as the current amplitude value Ic of the charge pump 20. By compensating the loop gain, the loop gain of the PLL circuit is compensated.
- the phase comparison gain can be compensated even when there is a gain variation due to factors other than the edge rate of the input data.
- the phase comparator may have another configuration, and has a function of delaying or advancing the phase of the clock signal CL or the phase of the input data signal DA by a predetermined amount, and has a circuit configuration similar to the phase comparator.
- a PLL circuit may be configured by incorporating the detection circuit. As described above, according to the present invention, the phase comparison gain is compensated for in accordance with the variation of the phase comparator of the PLL circuit and the jitter of the input data, etc. It is possible to stabilize the jitter frequency characteristics while maintaining the same, thereby improving the performance of the PLL circuit.
- FIG. 26 and FIG. 27 are diagrams for explaining an erroneous synchronization detection device according to another embodiment of the present invention.
- FIG. 26 is substantially the same as the circuit configuration of FIG. 18, and the corresponding components are denoted by the same reference numerals, and redundant description will be omitted.
- a sawtooth wave characteristic as shown by a broken line in FIG. 27 is used as a phase comparator of the PLL circuit. It is assumed that there is a property. That is, it has a characteristic that a detection voltage output according to the detected phase difference changes in a sawtooth waveform according to the detected phase difference.
- a phase lock is applied at an intermediate portion of the rising ramp portion of the sawtooth wave, that is, at a point P in the figure, so that a central portion between signal change points of the input data signal DA, that is, The phase of the clock signal CL can be locked so that data can be identified at the timing of the center of the clock (see Fig. 5).
- the waveform distortion as shown by the solid line in FIG. 27 may occur in the sawtooth characteristic due to the fluctuation of the duty of the input data signal DA, and the like.
- the PLL circuit may erroneously lock the phase at point Q in Fig. 27.
- erroneous synchronization occurs, and the clock signal performs data identification at the timing of the crosspoint of the data eye pattern, so that the identification data is likely to be erroneous.
- the phase comparison detection output of the phase comparator It depends on the delay amount ⁇ t given by 3 1 3 and 6 2 2.
- the amount of change has a characteristic that depends on the absolute phase between the data signal DA and the clock signal CL. That is, when the phase difference between the data signal DA and the clock signal CL is near zero, that is, when the data is identified at the timing of the center of the eye pattern of the data signal DA (see FIG. 5), the data can be correctly identified.
- the exclusive OR result of the identification signal and the data signal DA indicates that even if the data identification timing is delayed by the delay device 3 13, as long as the delay ⁇ t is somewhat smaller than the period T, the delay Only a difference approximately proportional to the amount occurs.
- the possibility of identifying correct data is about 50%.
- the delay is delayed by the predetermined amount ⁇ t from that timing, and the delay amount At exceeds the above-mentioned indeterminate state (dead zone) and is large enough to be an identification timing at which data can be identified almost accurately, correct data identification is performed. Is nearly 100%.
- the discrimination result based on such a discrimination timing is significantly different from the discrimination result when there is no delay (that is, when the discrimination rate is about 50% in an undefined state). The difference is much larger than in the case of the above-described identification near the center of the eye pattern.
- the present invention includes the following configurations.
- Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection circuit for detecting gain
- First phase comparing means for detecting a phase relationship between the input data signal and the identification timing signal
- Phase relationship shifting means for shifting the phase relationship between the input data signal and the identification timing signal by a predetermined amount
- Second phase comparing means for detecting a phase relation between the input data signal shifted by the phase relation shifting means and the identification timing signal
- a phase comparison gain detecting means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparing means and a predetermined amount by which the phase relation shifting means shifts the phase relation; circuit. (Configuration 2)
- the first phase comparison means detects a phase relationship between the input data signal and the identification timing signal in a substantially synchronized state
- the second phase comparison means is a phase comparison gain detection circuit configured to detect a phase relationship between the input data signal and the identification timing signal in a state where the input data signal and the identification timing signal are shifted by a predetermined amount from a state where they are substantially synchronized.
- phase relationship between the input data signal and the identification timing signal is determined.
- a phase comparison gain detection circuit for detecting a phase comparison gain when comparing phases
- Phase comparison gain detecting means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparing means and a second predetermined amount for shifting the identification timing. And a phase comparison gain detection circuit.
- Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection circuit for detecting gain
- the phase is detected by detecting the data correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal.
- a phase comparison gain detection circuit comprising phase comparison gain detection means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparison means and a predetermined amount for shifting the identification timing of the identification timing signal.
- phase comparison gain detecting circuit according to the above configuration 3 or 4, wherein the data correlation detection between the data in the first and second phase comparing means has a configuration realized by an exclusive OR operation.
- phase comparison gain detection circuit according to the above configuration 5, wherein the exclusive OR output is smoothed and input to the phase comparison gain detection means.
- phase comparison gain detection circuit according to any one of the above configurations 3 to 6, wherein each data is identified by a flip-flop circuit.
- An erroneous synchronization detecting circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal
- First phase comparing means for detecting a phase relationship between the input data signal and the identification timing signal
- Phase relationship shifting means for shifting the phase relationship between the input data signal and the identification timing signal by a predetermined amount
- Second phase comparing means for detecting a phase relation between the input data signal shifted by the phase relation shifting means and the identification timing signal
- An erroneous synchronization state is detected based on a difference between respective outputs of the first and second phase comparison means. Erroneous synchronization detection circuit.
- An erroneous synchronization detecting circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal
- a false synchronization detection means for detecting a false synchronization state based on the difference between the outputs of the first and second phase comparison means.
- An erroneous synchronization detecting circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal
- First phase comparing means for comparing phases by detecting a correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal.
- the phase is detected by detecting the correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal.
- An erroneous synchronization detection circuit comprising erroneous synchronization detection means for detecting an erroneous synchronization state based on a difference between respective outputs of the first and second phase comparison means.
- a PLL circuit comprising at least one of the phase comparison gain detection circuit of any of the above configurations 1 to 7 and the false synchronization detection circuit of any of the above configurations 8 to 11.
- a control circuit for controlling the loop gain of the PLL circuit based on the phase comparison detection gain of the phase comparison gain detection circuit, and a control for controlling the phase lock operation based on the false synchronization detection result of the false synchronization detection circuit A PLL circuit further comprising at least one control circuit of the circuits.
- the control circuit is configured to change at least one of a current amplitude of a charge pump constituting the PLL circuit, a transfer function of a loop filter, and a control gain of a VCO;
- the PLL circuit having the above configuration 11.
- Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection method for detecting gain
- a phase comparison gain detection step for detecting a phase comparison gain based on a difference between output values obtained in each of the first and second phase comparison steps and a predetermined amount for shifting the phase relation in the phase relation shift step.
- Phase comparison gain detection method Phase comparison gain detection method.
- the input data signal and the identification timing signal are substantially synchronized. Detect the phase relationship between the two states,
- a phase comparison detection method configured to detect a phase relationship between the input data signal and the identification timing signal in a state where the input data signal and the identification timing signal are shifted by a predetermined amount from a state where they are substantially synchronized.
- phase relationship between the input data signal and the identification timing signal is determined.
- a phase comparison step of detecting a phase comparison gain based on a difference between comparison output values in each of the first and second phase comparison steps and a second predetermined amount that shifts the identification timing is compared.
- a phase comparison gain detection method comprising a gain detection step.
- Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection method for detecting gain
- a first phase for comparing phases by detecting data correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal.
- the data of the input data signal is obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal.
- An erroneous synchronization detection method for detecting an erroneous synchronization between an input data signal and an identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal
- An erroneous synchronization detection method configured to detect an erroneous synchronization state based on a difference between respective outputs in the first and second phase comparison stages.
- An erroneous synchronization detection method for detecting an erroneous synchronization between an input data signal and an identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal
- An error synchronization detection method including an error synchronization detection step of detecting.
- An erroneous synchronization detection circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal
- a first phase comparison step of comparing phases by detecting a correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal;
- the phase is detected by detecting the correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal.
- An erroneous synchronization detection method comprising: an erroneous synchronization detection step of detecting an erroneous synchronization state based on a difference between outputs in each of the first and second phase comparison steps.
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Abstract
A phase comparison gain detecting circuit of PLL in which the phase is compared between a data signal DA and a clock signal CL, the phase is compared between the data signal DA and a clock signal CL’ obtained by delaying the clock signal CL by a specified amount, and a phase comparison gain is detected based the difference between respective phase comparison results and the specified amount of delay.
Description
明細書 位相比較利得検出回路、 誤同期検出回路及び P L L回路 技術分野 Description Phase comparison gain detection circuit, false synchronization detection circuit, and PLL circuit
本発明は位相比較利得検出回路、 誤同期検出回路及び P L L回路に係り、 特に 光通信用の光送受信器において受信データから基準ク口ック信号を抽出する場合 等に適用され得る P L L回路、 並びにそこに適用され得る位相比較利得検出回路、 及び誤同期検出回路に関する。 従来の技術 The present invention relates to a phase comparison gain detection circuit, a false synchronization detection circuit, and a PLL circuit, and particularly to a PLL circuit that can be applied to a case where a reference cook signal is extracted from received data in an optical transceiver for optical communication, and The present invention relates to a phase comparison gain detection circuit and a false synchronization detection circuit that can be applied thereto. Conventional technology
図 1 Aは、 クロック抽出用 P L L回路の一般的構成を示す。 周構成において、 VCO (電圧制御発振回路) 40の出力であるクロック信号 C Lと入力データ D Aとの間の位相差を位相比較器 1 0で検出し、 当該検出出力に応じてチャージポ ンプ 2 0が充電され、 その結果当該位相比較器出力に比例した電流がループフィ ルタ 3 0に供給される。 そしてループフィルタ 30にて上記供給電流が平滑化さ れ、 その結果が VC04 0にフィードバックされる。 又図 1 Bは上記ループフィ ルタ 3 0の構成の一例を示す回路図である。 同図に示す如く、 この例の場合ルー プフィルタ 3 0は抵抗 Rとコンデンサ Cとの直列回路よりなり、 入力電流を平滑 化して出力電圧に変換する機能を有する。 上述の動作により、 当該 P L L回路で は入力データ信号 D Aに同期したクロック信号 C Lを得ることが可能となる。 ここで位相比較器 1 0における位相比較利得を K p、 チャージポンプ 2 0にお ける電流振幅を I c、 ループフィルタ 3 0の伝達関数を F ( s) 、. VCOの利得 を K Vとした場合、 当該? L L回路のループ利得は周知の以下の式にて表される。 開ループ利得 = [Κρ · I c · F ( s ) · Kv] /s FIG. 1A shows a general configuration of a PLL circuit for clock extraction. In the peripheral configuration, the phase difference between the clock signal CL, which is the output of the VCO (voltage controlled oscillation circuit) 40, and the input data DA is detected by the phase comparator 10, and the charge pump 20 is driven according to the detected output. As a result, a current proportional to the output of the phase comparator is supplied to the loop filter 30. Then, the supply current is smoothed by the loop filter 30, and the result is fed back to VC400. FIG. 1B is a circuit diagram showing an example of the configuration of the loop filter 30. As shown in the figure, in this example, the loop filter 30 is composed of a series circuit of a resistor R and a capacitor C, and has a function of smoothing an input current and converting it into an output voltage. By the above operation, the PLL circuit can obtain the clock signal CL synchronized with the input data signal DA. Here, the phase comparison gain in phase comparator 10 is Kp, the current amplitude in charge pump 20 is Ic, the transfer function of loop filter 30 is F (s), and the gain of VCO is KV. The pertinent? The loop gain of the L L circuit is expressed by the following known equation. Open loop gain = [Κρ · I c · F (s) · Kv] / s
閉ループ利得 = i η/ o u t Closed loop gain = iη / out
= [K · I c · F ( s ) · Kv] / [ s + p · I c · F ( s ) · K v]
又、 ループフィルタとして、 完全 2次形のものを使用した場合、 開ループ利得 = [Kp · I c · R · KvZs] · [1 + 1/s CR] 閉ループ利得 = [Κρ · I c · R · Κ ν · (1 + s CR) ] / [s ^ 2 · CR +Kp · I c · R · K v · (1 + s CR) ] の各ループ利得が得られる。 = [K · Ic · F (s) · Kv] / [s + p · Ic · F (s) · Kv] When a perfect quadratic filter is used as the loop filter, open loop gain = [Kp · Ic · R · KvZs] · [1 + 1 / s CR] closed loop gain = [Κρ · Ic · R · Κ ν · (1 + s CR)] / [s ^ 2 · CR + Kp · Ic · R · Kv · (1 + sCR)]
上式から閉ループ利得の力ットオフ周波数は開ループ利得が 0 d Bになる周波 数であり、 位相比較器 10、 チヤ ジポンプ 20、 VC040の夫々の利得に比 例十ることが分かる (図 2 A参照) 。 ここで、 各部の利得が大きい場合このカツ トオフ周波数は高くなり、 その結果出カジッタが増加する傾向にある。 他方これ らの利得が小さい場合には (図 2B参照) 、 カットオフ周波数が低くなり、 その 結果位相余裕が減少してピーキングが増加する傾向にある。 又その場合、 位相誤 差応答が悪くなる傾向にある。 From the above equation, it can be seen that the closed loop gain power-off frequency is a frequency at which the open loop gain becomes 0 dB, and is proportional to the respective gains of the phase comparator 10, the charge pump 20, and the VC040 (Fig. 2A). See). Here, when the gain of each part is large, the cutoff frequency becomes high, and as a result, the output jitter tends to increase. On the other hand, when these gains are small (see Fig. 2B), the cutoff frequency is low, which tends to reduce the phase margin and increase peaking. In that case, the phase error response tends to be poor.
ここで P L Lのジッタ特性としての閉ループ特性は所謂ジッタトランスファに 相当するものであり、 PLLがロックした状態における入力ジッタに対する出力 ジッタの増幅率で表される。 この値は PL Lの応答速度が遅いほど良い。 他方、 P LLが口ックした状態でどの位のジッタに耐えられるかの指標である所謂ジッ タトレランスの見地から考えた場合、 逆に PL Lの応答速度が速いほど耐力が大 きい。 従って両者は互いにトレードオフの関係にある。 Here, the closed-loop characteristic as the jitter characteristic of PLL is equivalent to a so-called jitter transfer, and is represented by the amplification factor of the output jitter with respect to the input jitter when the PLL is locked. This value is better as the response speed of PLL is slower. On the other hand, from the viewpoint of the so-called jitter tolerance, which is an index of how much jitter the PLL can withstand in a licked state, conversely, the higher the response speed of the PLL, the greater the tolerance. Therefore, they are in a trade-off relationship with each other.
図 3は、 PL L方式を適用した識別タイミング信号抽出回路の一例を示すプロ ック図である。 上記の如くの P L L回路機能によって抽出されたクロック信号 C Lによって、 識別回路 100にて入力データ信号 D Aのデータが抽出される。 このような光送受信回路等における P L L回路では、 一般の周波数シンセサイ ザで使用される PLL回路とは異なり、 入力データ信号としてランダムなデータ が入力される。 従って、 入力信号の周波数の変動が大きい場合、 抽出すべき周波 数成分値のレベルが相対的に低下し、 結果的に上記 P L Lループ利得が低下して その動作が不安定になる。 FIG. 3 is a block diagram showing an example of an identification timing signal extraction circuit to which the PLL method is applied. The data of the input data signal DA is extracted by the identification circuit 100 based on the clock signal CL extracted by the PLL circuit function as described above. In a PLL circuit in such an optical transmitting and receiving circuit, unlike a PLL circuit used in a general frequency synthesizer, random data is input as an input data signal. Therefore, when the frequency of the input signal fluctuates greatly, the level of the frequency component value to be extracted relatively decreases, and as a result, the PLL loop gain decreases and the operation becomes unstable.
図 4は上記位相比較回路 10として、 周知のハーフレートクロック B a n g—
B a n g回路を適用した場合の回路例を示す。 同図中、 入力データ信号 D Aに対 し、 二つの D— F F (D—フリップフロップ) 回路にて、 夫々データ識別用クロ ック信号じしと、 これを π / 2位相分遅らせたェッジ検出用クロック信号 C L, とによってデータ識別動作を行う。 そしてその結果得られる夫々の信号 D a, D bに対して排他的論理和回路 E X O Rにて排他的論理和演算を行い、 信号 D cを 得る。 FIG. 4 shows a well-known half-rate clock Bang— A circuit example when a Bang circuit is applied is shown. In the figure, two D-FF (D-flip-flop) circuits detect the input data signal DA and detect the edge of the clock signal for data identification by delaying it by π / 2 phase. The data identification operation is performed by the clock signals CL and. The exclusive OR circuit EXOR performs an exclusive OR operation on the resulting signals Da and Db to obtain a signal Dc.
その結果、 データ信号 D Aの位相が識別ク口ック信号 C Lの位相に対して遅れ ていた場合、 確率的に、 図 6に示す如く、 排他的論路和出力 D cは間欠的な信号 となり、 他方、 データ信号 D Aの位相が識別クロック信号 C Lの位相に対して進 んでいた場合、 図 7に示す如く、 排他的論路和出力 D cは連続的な信号となる可 能性が高い。 As a result, if the phase of the data signal DA is behind the phase of the discrimination signal CL, the exclusive OR sum Dc becomes an intermittent signal as shown in FIG. On the other hand, when the phase of the data signal DA is advanced with respect to the phase of the identification clock signal CL, as shown in FIG. 7, the exclusive logical sum output Dc is likely to be a continuous signal.
その結果、 このような位相比較結果に対してチャージポンプ 2 0とループフィ ルタ 3 0とによる低域通過フィルタを通して得られた信号のレベルは、 図 6のよ うに位相比較出力が間欠的な信号の場合低く、 他方図 7の場合のように連続的と なる可能性が高い位相比較出力の場合、 上記低域通過フィルタの出力レベルは高 くなる。 そしてこの低域通過フィルタの出力レベルに応じて V C O 4 0の発振周 波数が制御される。 As a result, the level of the signal obtained through such a low-pass filter by the charge pump 20 and the loop filter 30 with respect to such a phase comparison result is, as shown in FIG. In the case of a phase comparison output that is likely to be continuous as in the case of FIG. 7, the output level of the low-pass filter becomes high. The oscillation frequency of VCO 40 is controlled according to the output level of the low-pass filter.
即ち、 データ信号の位相が遅れている場合には V O C入力レベルが下がり、 そ の結果 V C O発振周波数が低下してデータ信号の位相に応じてクロック信号 C L の位相を遅らせるよう作用する。 逆にデータ信号の位相が進んでいる場合には V C O発振周波数が上昇し、 データ信号に対してクロック信号の位相を進ませるよ う作用する。 That is, when the phase of the data signal is delayed, the VOC input level is reduced, and as a result, the VCO oscillation frequency is reduced to act to delay the phase of the clock signal CL in accordance with the phase of the data signal. Conversely, when the phase of the data signal is advanced, the VCO oscillation frequency increases, and acts to advance the phase of the clock signal with respect to the data signal.
ここで図 6の場合において入力データ信号の内の A系統のデータの符号が変化 すると位相比較出力においてクロック信号の 1 Z 4周期の H信号が出力される。 他方 A系統のデータの符号が連続した場合、 その間、 H信号が出力されないこと となる。 この様子を図 8乃至図 1 0に示す。 Here, in the case of FIG. 6, when the sign of the A-system data in the input data signal changes, an H signal of 1Z4 cycle of the clock signal is output in the phase comparison output. On the other hand, if the sign of the data of the A system continues, the H signal will not be output during that time. This situation is shown in FIGS.
又、 図 7の場合、 即ちデータ信号の位相が進んでいる場合、 図 7に示す如く同 じデータ間の排他的論理和が発生することが無いため、 統計的には位相比較出力 として H信号と L信号とは半分ずつ発生することとなる。 しかしながら、 A系統
と B系統共、 同符号が連続するような場合には L信号が出力され、 他方異符号の 繰り返しが続くと H信号が出力される事となる。 この様子を図 1 1乃至図 1 3に 示す。 In addition, in the case of FIG. 7, that is, when the phase of the data signal is advanced, since the exclusive OR between the same data does not occur as shown in FIG. 7, the H signal is statistically used as the phase comparison output. And the L signal are generated by half. However, system A If the same code is continuous in both and the B system, the L signal is output, and if the repetition of the different code continues, the H signal is output. This situation is shown in FIGS. 11 to 13.
このように、 位相比較出力は必ずしもデータ信号とクロック信号との間の位相 差のみでなく、 データ信号の内容そのもの (この場合所謂エッジ率、 デューティ 一等) によっても影響を受けることとなる。 その結果、 上記位相比較器 1 0の利 得 K pが変動し、 もつて上記 P L L回路全体のループ利得が変動することとなる。 図 1 4 Α·, 図 1 4 Βは、 図 4に示す如くの構成を有する位相比較器 1 0の出力 波形の例を示す。 図 1 4 Aに示す如く、 破線で示す理想的な出力特性に対し、 入 カジッタ、 位相比較回路中の D— F F回路のセットアップホールド動作特性によ る影響等により、 実際には実線で示される如く波形になまりが生ずる。 又、 図 1 4 Βに示す如く、 上記入力データのエッジ率によっても波形になまりが生ずる。 その結果 P L L回路のループ利得が変動し、 もって上述の如くの回路動作不安定 要因となる。 発明の開示 As described above, the phase comparison output is not necessarily affected by not only the phase difference between the data signal and the clock signal but also the content of the data signal itself (in this case, the so-called edge rate, duty 1, etc.). As a result, the gain Kp of the phase comparator 10 fluctuates, and the loop gain of the entire PLL circuit also fluctuates. FIGS. 14A and 14B show examples of output waveforms of the phase comparator 10 having the configuration as shown in FIG. As shown in Fig. 14A, the ideal output characteristic shown by the broken line is actually shown by the solid line due to the input jitter, the effect of the setup and hold operation characteristics of the D-FF circuit in the phase comparator, etc. The waveform is rounded as described above. In addition, as shown in FIG. 14 波形, the waveform becomes rounded depending on the edge ratio of the input data. As a result, the loop gain of the PLL circuit fluctuates, thereby causing the above-mentioned unstable circuit operation. Disclosure of the invention
本発明は上記問題点に鑑み、 入力データのエッジ率、 デューティー等の変動、 回路特性による影響等によらず、 安定した P L L回路動作を提供し得る P L L回 路を提供する事を目的とする。 SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a PLL circuit capable of providing a stable PLL circuit operation irrespective of fluctuations in the edge ratio and duty of input data, effects of circuit characteristics, and the like.
本発明では、 入力データ信号の識別に関して位相条件が異ならせて複数の位相 比較動作を行い、 夫々の位相比較結果を比較することによって位相比較利得を検 出する。 従って入力データ信号のエッジ率、 デューティー、 更に識別器のセット アップ'ホールド特性等の位相比較利得の変動要因を加味したオンタイムの位相 比較利得を検出出来る。 その結果、 当該位相比較検出結果に基づいて P L L回路 のループ利得を制御することによってオンタイムで正確なループ利得捕償制御が 実現可能である。 図面の簡単な説明 In the present invention, a plurality of phase comparison operations are performed with different phase conditions with respect to identification of an input data signal, and the phase comparison gain is detected by comparing the respective phase comparison results. Therefore, it is possible to detect the on-time phase comparison gain in consideration of the fluctuation factors of the phase comparison gain such as the edge ratio and duty of the input data signal and the setup and hold characteristics of the discriminator. As a result, on-time and accurate loop gain compensation control can be realized by controlling the loop gain of the PLL circuit based on the phase comparison detection result. BRIEF DESCRIPTION OF THE FIGURES
図 1 A、 1 Bは従来の P L L回路の構成を示す図である
図 2 A、 2 Bは、 P L L回路のループ利得についての説明図である。 1A and 1B are diagrams showing a configuration of a conventional PLL circuit. FIGS. 2A and 2B are diagrams illustrating the loop gain of the PLL circuit.
図 3は従来の P L L回路の動作説明図である。 FIG. 3 is an explanatory diagram of the operation of the conventional PLL circuit.
図 4は、 従来のハーフレートクロック B a n g - B a n g位相比較器の回路例 を示す図である。 FIG. 4 is a diagram showing a circuit example of a conventional half-rate clock Bang-Bang phase comparator.
図 5はデータ識別位相について説明するための図である。 FIG. 5 is a diagram for explaining the data identification phase.
図 6は図 4の回路における各信号のタイムチャート (その 1 ) である。 FIG. 6 is a time chart (part 1) of each signal in the circuit of FIG.
図 7は図 4の回路における各信号のタイムチャート (その 2 ) である。 FIG. 7 is a time chart (part 2) of each signal in the circuit of FIG.
図 8は図 4の回路における各信号のタイムチャート (その 3 ) である。 FIG. 8 is a time chart (part 3) of each signal in the circuit of FIG.
図 9は図 4の回路における各信号のタイムチャート (その 4 ) である。 FIG. 9 is a time chart (part 4) of each signal in the circuit of FIG.
図 1 0は図 4の回路における各信号のタイムチャート (その 5 ) である。 図 1 1は図 4の回路における各信号のタイムチャート (その 6 ) である。 図 1 2は図 4の回路における各信号のタイムチャート (その 7 ) である。 図 1 3は図 4の回路における各信号のタイムチャート (その 8 ) である。 図 1 A, 4 Bは、 位相比較特性の劣化状態を説明するための図 (その 1 ) である o FIG. 10 is a time chart (part 5) of each signal in the circuit of FIG. FIG. 11 is a time chart (part 6) of each signal in the circuit of FIG. FIG. 12 is a time chart (part 7) of each signal in the circuit of FIG. FIG. 13 is a time chart (No. 8) of each signal in the circuit of FIG. FIGS. 1A and 4B are diagrams (part 1) for explaining the state of deterioration of the phase comparison characteristic.
図 1 5は、 位相比較利得補償機能付き P L L回路の一例の回路プロック図であ る。 FIG. 15 is a circuit block diagram of an example of a PLL circuit having a phase comparison gain compensation function.
図 1 6は、 位相比較利得検出回路の一例を示す回路図である。 FIG. 16 is a circuit diagram showing an example of the phase comparison gain detection circuit.
図 1 7は、 位相比較特性の劣化状態を説明するための図 (その 2 ) である。 図 1 8は、 本発明の一実施例のプロック図である。 FIG. 17 is a diagram (part 2) for explaining the state of deterioration of the phase comparison characteristic. FIG. 18 is a block diagram of one embodiment of the present invention.
図 1 9は、 図 1 8に示す構成による位相比較利得検出原理を説明するための図 である ο FIG. 19 is a diagram for explaining the principle of detecting the phase comparison gain by the configuration shown in FIG.
図 2 0は、 本発明の一実施例の回路図である。 FIG. 20 is a circuit diagram of one embodiment of the present invention.
図 2 1は、 図 2 0に示す回路における各信号のタイムチヤ一トである。 FIG. 21 is a time chart of each signal in the circuit shown in FIG.
図 2 2は、 図 2 0に示す構成による位相比較利得検出原理を説明するための図 である o FIG. 22 is a diagram for explaining the principle of phase comparison gain detection by the configuration shown in FIG. 20.
図 2 3は、 図 2 0に示す構成を有する位相比較検出回路を用いた本発明の一実 施例による P FIG. 23 is a circuit diagram of a P-mode according to an embodiment of the present invention using the phase comparison detection circuit having the configuration shown in FIG.
図 2 4は、
図 2 5は、 図 2 4に示す構成による位相比較利得検出原理を説明するための図 である。 Figure 24 shows FIG. 25 is a diagram for explaining the principle of phase comparison gain detection by the configuration shown in FIG.
図 2 6は、 本発明の更に他の実施例による誤同期検出回路の回路図である。 図 2 7は、 図 2 6に示す構成による誤同期検出原理を説明するための図である。 好ましい実施例の説明 FIG. 26 is a circuit diagram of a false synchronization detecting circuit according to still another embodiment of the present invention. FIG. 27 is a diagram for explaining the principle of false synchronization detection by the configuration shown in FIG. Description of the preferred embodiment
以下に本発明の実施例の構成について図面と共に説明する。 Hereinafter, the configuration of an embodiment of the present invention will be described with reference to the drawings.
上述の如くの P L L回路 (例えば図 1 5に示す回路) の利得変化を、 V C 0 4 0の利得を検出して補償するものとして、 位相比較器 1 0の利得をデータ D Aの エッジ率によって検出し、 その検出結果に基づいてチャージポンプ 2 0の出力電 流を調整し、 或いはフィルタ 3 0の容量値又は抵抗値を調整して補償する等の方 法が考えられる。 図 1 5の場合、 位相比較利得回路 2 1 0にて位相比較記 1 0の 利得を検出し、 その検出結果に基づいて制御回路 2 2 0にてチャージポンプの特 性を制御する。 Assuming that the gain change of the PLL circuit (for example, the circuit shown in FIG. 15) as described above is compensated by detecting the gain of VC040, the gain of phase comparator 10 is detected based on the edge rate of data DA. Then, a method of adjusting the output current of the charge pump 20 based on the detection result, or adjusting the capacitance value or the resistance value of the filter 30 and compensating the same can be considered. In the case of FIG. 15, the gain of the phase comparison note 10 is detected by the phase comparison gain circuit 210, and the characteristics of the charge pump are controlled by the control circuit 220 based on the detection result.
この場合、 位相比較記 1 0が例えば図 1 6に示す如くの周知の H o g g e位相 比較器のように鋸波位相比較特性 (図 1 7参照) を持つ位相比較器の場合、 位相 周期が決まった値であり、 その出力振幅で利得が決まる。 そして図 1 5に示す如 くの位相比較利得補償回路においては、 データのエッジ率変動による振幅の変動 を検出する。 即ちこの場合、 E X O R回路 2 1 3の出力は、 データにエッジが有 る場合、 即ちデータの変化時に" H" 、 無い場合には" L" となる。 これを L P F (R, Cによる回路) で平均化することによりデータのエッジ率が検出出来る。 そして制御回路 2 2 0によって位相検出器の出力振幅の変動分をチャージポンプ 2 0の電流を調整することで補償する方法である。 In this case, if the phase comparator 10 has a sawtooth phase comparison characteristic (see FIG. 17) like a well-known Hogge phase comparator as shown in FIG. 16, for example, the phase period is determined. The output amplitude determines the gain. Then, in the phase comparison gain compensating circuit as shown in FIG. 15, the fluctuation of the amplitude due to the fluctuation of the edge ratio of the data is detected. That is, in this case, the output of the EXOR circuit 21 3 becomes “H” when the data has an edge, that is, “H” when the data changes, and “L” when there is no data. The edge rate of the data can be detected by averaging this with L PF (a circuit using R and C). Then, the control circuit 220 compensates for the fluctuation of the output amplitude of the phase detector by adjusting the current of the charge pump 20.
他方、 識別器および分周器を位相比較器の一部として構成可能であるため構成 部品が少なくてすむ周知の B n a g - B a n g位相比較器を適用する場合、 この 位相比較器では位相比較特性がステップ関数 (B a n g—B a n g位相比較特 性) で表され (例えば図 1 4 Aの破線の特性) 、 位相比較器出力の確率的変動に 応じて位相比較利得値が決まる特性を有する。 この場合の位相比較利得の変動要 因としては、 データのエッジ率の変動に加え、 ①入力データのジッタ、 ②入力デ
ータのデューティ、 ③位相比較器中の識別器 (FF) のセットアップ 'ホールド 特性等のバラツキ及ぴ変動等が挙げられる。 従ってこの場合位相比較利得に対す る設計は図 16, 17の場合に比較して複雑であり、 該当するシステム中に位相 比較回路を組み込んだ後に位相比較利得を含んだ P L L全体のループ利得を調整 する必要がある。 On the other hand, when a well-known B nag -Bang phase comparator, which requires fewer components because the discriminator and the frequency divider can be configured as a part of the phase comparator, is applied. Is represented by a step function (Bang-Bang phase comparison characteristic) (for example, the characteristic of the broken line in FIG. 14A), and has a characteristic in which the phase comparison gain value is determined according to the stochastic fluctuation of the phase comparator output. In this case, the fluctuation factors of the phase comparison gain include, in addition to the fluctuation of the data edge ratio, (1) the jitter of the input data, and (2) the input data. Data duty, (3) Variations and variations in the setup and hold characteristics of the discriminator (FF) in the phase comparator. Therefore, in this case, the design for the phase comparison gain is more complicated than in the cases of Figs. 16 and 17, and the loop gain of the entire PLL including the phase comparison gain is adjusted after installing the phase comparison circuit in the relevant system. There is a need to.
そこで、 本 明では、 上記の B a n g-B a n g位相比較器等を備えた P L L 回路において、 これら入力データのジッタ、 入力データのデューティ、 位相比較 器の識別器 (FF) のセットアップ 'ホールド特性のバラツキ及び変動等による 位相比較利得の変動を正確に検出する回路を提供する。 Therefore, in the present invention, in the PLL circuit having the above-described BangBang phase comparator, the jitter of the input data, the duty of the input data, and the setup / hold characteristics of the discriminator (FF) of the phase comparator vary. And a circuit for accurately detecting a change in the phase comparison gain due to the change and the like.
図 18は、 本発明の一実施例の原理図である。 同図は、 上記 B a n g-B a n g位相比較器を用いた位相比較利得検出器を示す。 同図に示す通り、 この位相比 較検出器 300は、 データ DAを識別するクロック信号 CLを入力とする位相比 較器 311、 データ識別用クロック信号 CLを所定時間遅延させてクロック信号 CL, として出力する遅延器 313、 この遅延クロック信号 CL, を入力とする 位相比較器 312、 出力を平滑化する LPF314, 315、 及び差電圧検出回 路 316とで構成される。 FIG. 18 is a principle diagram of one embodiment of the present invention. This figure shows a phase comparison gain detector using the above-mentioned Bang-Bang phase comparator. As shown in the figure, the phase comparison detector 300 includes a phase comparator 311, which receives a clock signal CL for identifying the data DA as an input, and delays the data identification clock signal CL by a predetermined time to generate a clock signal CL. It comprises a delay unit 313 for outputting, a phase comparator 312 having the delayed clock signal CL, as an input, LPFs 314 and 315 for smoothing the output, and a difference voltage detection circuit 316.
同図の回路では、 データ信号 D Aとクロック信号 CLとが同期している間、 即 ち入力データ識別用クロック同期時、 異なる位相の二つのクロック信号 CL, C L, によって夫々データ識別動作を行い、 夫々の位相比較器出力 D 1, D2と、 両クロック信号 CL, CL' 間の時間差、 即ち上記所定の遅延時間から、 所望の 位相比較利得を検出する。 これにより、 位相比較器のセットァップ'ホールド時 間、 入力データのエツジ率およぴジッタ並びにデューティ変動ゃパラッキ等があ つた場合であつても、 これらを織り込み済みの位相比較利得が検出可能であるた め、 当該検出出力に基づいて制御することにより、 PLL回路全体のループ利得 を一定となるように補償し得る。 従って、 安定な応答特性が得られ、 所望のジッ タトランスファ特性を満足する P L L回路を提供可能である。 In the circuit shown in the figure, while the data signal DA and the clock signal CL are synchronized, that is, when the input data identification clock is synchronized, the data identification operation is performed by the two clock signals CL and CL having different phases, respectively. A desired phase comparison gain is detected from the time difference between each of the phase comparator outputs D 1 and D 2 and the clock signals CL and CL ′, that is, from the predetermined delay time. This makes it possible to detect the phase comparison gain that incorporates the setup and hold time of the phase comparator, the edge rate and jitter of the input data, and the fluctuation of the duty and the parallelism, etc. Therefore, by controlling based on the detection output, the loop gain of the entire PLL circuit can be compensated so as to be constant. Therefore, a stable response characteristic is obtained, and a PLL circuit satisfying a desired jitter transfer characteristic can be provided.
図 19は上記本発明の一実施例の原理を説明するための各位相比較器 311, 312の出力レベルを示し、 同図の位相比較特性は、 図 14 A, 14 Bに示すも のに相当する。 同図に示す如く、 位相比較出力は位相比較結果としての位相差に
応じて変化し、 その変化率即ち、 AVZ (Δ t/T) が位相比較利得 Kpに相当 する。 上式において、 AVは、 異なる位相条件による位相比較出力を平滑ィ匕した 値 D 1と D 2との間の差電圧であり、 Δ tは、 当該位相条件の差異を提供する遅 延器 313による遅延量であり、 Tはクロック信号の信号周期を示す。 FIG. 19 shows the output levels of the phase comparators 311 and 312 for explaining the principle of the embodiment of the present invention. The phase comparison characteristics in FIG. 19 correspond to those shown in FIGS. 14A and 14B. I do. As shown in the figure, the phase comparison output is The rate of change, that is, AVZ (Δt / T), corresponds to the phase comparison gain Kp. In the above equation, AV is the difference voltage between the values D 1 and D 2 obtained by smoothing the phase comparison output under different phase conditions, and Δt is the delay unit 313 that provides the difference in the phase conditions. T is the signal period of the clock signal.
図 20は図 18の構成を更に具体化した本発明の一実施例による位相比較検出 回路の構成を示す。 同回路はハーフレートクロックを用いた B a n g— B a n g 位相比較器を適用した位相比較利得検出回路である。 図に示す如く、 同回路は、 識別器 (FF) として、 データ識別用識別器 411、 412、 データエッジ検出 用識別器 413、 更に位相比較利得検出用識別器 414とを設け、 更に、 排他的 論理和回路 (EX OR) として、 データ識別 FF出力 DO aとデータエッジ検出 用 FF出力 DOcとの論理をとる回路 431、 同じくデータ識別 FF出力 DO b とデータエッジ検出用 FF出力 DO cとの論理をとる回路 432、 データ識別 F F出力 DObと位相比較利得検出用 FF出力 DO dとの論理をとる回路 433と が設けられている。 そしてこれらの出力は夫々 LPF 441, 442, 443で 平滑化されて位相比較出力 Ph 1, Ph 2, Ph 3として出力される。 FIG. 20 shows a configuration of a phase comparison detection circuit according to an embodiment of the present invention, which further embodies the configuration of FIG. This circuit is a phase comparison gain detection circuit to which a Bang-Bang phase comparator using a half-rate clock is applied. As shown in the figure, the circuit is provided with data discriminators 411, 412, data edge detection discriminator 413, and phase comparison gain detection discriminator 414 as discriminators (FF). A circuit 431 that performs a logic operation between the data identification FF output DO a and the data edge detection FF output DOc as an OR circuit (EX OR). Similarly, a logic between the data identification FF output DO b and the data edge detection FF output DO c. And a circuit 433 for performing logic between the data identification FF output DOb and the phase comparison gain detection FF output DOd. These outputs are smoothed by LPFs 441, 442, and 443, respectively, and output as phase comparison outputs Ph1, Ph2, and Ph3.
この図 20の回路では、 図 21の波形図で示す如く、 データ信号 D Aとクロッ ク信号 CLとの同期がとれている状態で、 識別器 411の出力 DO aとしては A 系統のデータが得られ、 識別器 412の出力 DObとしては B系統のデータが得 られる。 他方、 エッジ検出用識別器 413の出力 DOcとしては、 クロック信号 の立ち上がりタイミングがデータ信号 D Aの変化点と一致するため、 上記タイミ ングによって A系統のデータが得られる確率と B系統のデータが得られる確率と が等しくなる。 他方、 位相比較利得検出用識別器 414の出力としては、 クロッ ク信号の立ち上がりタイミングがデータ信号 D Aの変化点より若干遅れているた め、 上記タイミングによって A系統のデータが得られる確率よりも B系統のデー タが得れる確立の方が大きくなる。 In the circuit of FIG. 20, as shown in the waveform diagram of FIG. 21, in a state where the data signal DA and the clock signal CL are synchronized, data of the A system is obtained as the output DO a of the discriminator 411. As the output DOb of the discriminator 412, data of the B system is obtained. On the other hand, as the output DOc of the edge detection discriminator 413, the rising timing of the clock signal coincides with the transition point of the data signal DA. Is equal to the probability. On the other hand, as the output of the phase comparison gain detection discriminator 414, the rising timing of the clock signal is slightly delayed from the changing point of the data signal DA. The probability of obtaining system data is greater.
その結果、 これらのデータの間の排他的論理和の結果として、 EXOR回路 4 41の出力 P h 1における Hレベルの出現確率は EX OR 442の出力 P h 2に おける Hレベルの出現確率と略等しくなる。 他方、 EXOR回路 443の出力 P h 3では、 Hレベルの出現確率は前者の各々より高くなる。 即ち、 EXOR回路
443の入力である DO aと DO dとが一致する確率が、 EXOR回路 441の 入力である DO aと DO cとが一致する確率又は EXOR回路 442の入力であ る DO bと DO cとが一致する確率より低いからである。 これは、 上記の如く、 信号 DO cにおける A系統データの出現確率よりも信号 DO dにおける A系統デ ータの出現確率のほうが小さく、 同様に信号 DO cにおける B系統データの出現 確率よりも信号 DO dにおける A系統データの出現確率のほうが小さいことによ る。 As a result, as a result of the exclusive OR between these data, the appearance probability of the H level at the output P h1 of the EXOR circuit 441 is approximately equal to the appearance probability of the H level at the output P h 2 of the EXOR 442. Become equal. On the other hand, at the output P h 3 of the EXOR circuit 443, the appearance probability of the H level is higher than each of the former. That is, EXOR circuit The probability that DO a and DO d as inputs of 443 match is the probability that DO a and DO c as inputs of EXOR circuit 441 match or DO b and DO c as inputs of EXOR circuit 442 This is because the probability of matching is lower. This is because, as described above, the occurrence probability of the A-system data in the signal DO d is smaller than the appearance probability of the A-system data in the signal DO c, and similarly, the occurrence probability of the B-system data in the signal DO c This is because the appearance probability of A-system data in DO d is smaller.
このように、 本実施例では、 意図的に所定時間 Δ t遅延させたクロック信号 C Lbを発生させてデータ識別を行い、 その識別結果のデータと、 A t遅延させて いないクロック C Lにて識別された識別結果のデータとの排他的論理和をとる。 更にエッジ検出用クロック信号 C L aにてデータ識別を行なった識別結果データ と、 同じく Δ t遅延させていないクロック CLにて識別された識別結果データと の排他的論理和をとる。 そしてこれら 2種類の排他的論理和の結果を L P Fにて 平滑化してそのレベル差を、 上記遅延量 Δ tを周期 Tで基準化した位相で割るこ とによつて位相比較利得 K pが得られる。 As described above, in the present embodiment, the clock signal C Lb intentionally delayed by a predetermined time Δt is generated to perform data identification, and the identification result data is identified by the clock CL not delayed by At. Exclusive OR with the data of the identified result. Further, an exclusive OR of the identification result data obtained by performing the data identification using the edge detection clock signal CLa and the identification result data obtained by using the clock CL which is not delayed by Δt is calculated. The result of these two types of exclusive OR is smoothed by LPF, and the level difference is divided by the phase obtained by standardizing the delay amount Δt with the period T to obtain the phase comparison gain Kp. Can be
即ち、 ここでは同期確立後に意図的に遅延量 Δ tを発生させて擬似的にデータ 信号 D Aと同期がずれたクロック信号 (図 20, 21の例では信号 C Lb) を生 成し、 その 「疑似同期ズレ」 クロック信号によって同じデータ信号 D Aの識別を 行なう。 そしてそこで得られる識別データと、 π/2遅延させたクロック信号 C L aで識別されたデータとの間の排他的論理和出力を平滑化して 「疑似同期ズ レ」 位相比較検出値を得る。 そしてこの疑似同期ズレ位相比較検出値に対し、 同 期状態のクロック信号 CLにて識別された識別データと、 同じく πノ 2遅延させ たクロック信号 C L aで識別されたデータとの間の排他的論理和出力を平滑化し て得られた値、 即ち 「同期時位相比較検出値」 とを比較する。 この比較結果の差 異が大きい程、 データ信号 D Aに対するクロック信号 CLとの間の位相差に対す る位相比較検出感度が高いと言え、 もって位相比較利得が高いことと同義である。 このように当該実施例では、 現時点でのデータのエッジ率、 デューティー、 各 識別器 (FF) のセットアップ ·ホールド特性等を全て織り込み済みの位相比較 利得を求めることとなるため、 非常に正確にオンタイムの実効的な位相比較利得
を求めることが可能である。 In other words, here, a delay Δt is intentionally generated after synchronization is established, and a clock signal (signal C Lb in the examples of FIGS. 20 and 21) is generated in a pseudo manner in synchronization with the data signal DA. Pseudo-synchronous shift ”The same data signal DA is identified by the clock signal. Then, the exclusive OR output between the identification data obtained therefrom and the data identified by the clock signal CLa delayed by π / 2 is smoothed to obtain a “pseudo synchronization shift” phase comparison detection value. Then, for the pseudo-synchronization phase comparison detection value, the exclusive data between the identification data identified by the clock signal CL in the synchronized state and the data identified by the clock signal CLa also delayed by π 2 The value obtained by smoothing the logical sum output, that is, "the phase comparison detection value at the time of synchronization" is compared. It can be said that the larger the difference between the comparison results, the higher the phase comparison detection sensitivity to the phase difference between the data signal DA and the clock signal CL, which is synonymous with the higher phase comparison gain. As described above, in the present embodiment, the phase comparison gain incorporating all of the current edge ratio, duty, setup / hold characteristics of each discriminator (FF), and the like is obtained, and therefore, it is very accurately turned on. Effective phase comparison gain of time Is possible.
図 23は、 本発明の一実施例による位相比較利得補償機能を備えた PL L回路 例を示し、 図 20の構成を有する位相比較器検出回路 400の位相比較出力 Ph 1と P h 3との間の差電圧をディジタル信号に変換する A/D変換器 510と、 当該ディジタル差電圧と所定の基準値とを比較し、 その比較結果に基づいてチヤ ージポンプの出力電流を調整し、 もって当該 PL L回路のループ利得を補償する 構成を有する。 FIG. 23 shows an example of a PLL circuit having a phase comparison gain compensation function according to an embodiment of the present invention. The phase comparison output Ph 1 and Ph 3 of the phase comparator detection circuit 400 having the configuration of FIG. A / D converter 510 that converts the difference voltage between the two into a digital signal, compares the digital difference voltage with a predetermined reference value, adjusts the output current of the charge pump based on the comparison result, and thereby adjusts the PL. It has a configuration to compensate for the loop gain of the L circuit.
又、 図 23の構成では、 図 20に示す位相比較検出回路 400のデータ出力 D Oa、 DObは、 そのまま入力データの再生データとして使用可能である。 即ち、 これらデータ出力 DO a、 DObは、 図 3における識別回路 100の出力に相当 する。 In the configuration of FIG. 23, the data outputs D Oa and DOb of the phase comparison detection circuit 400 shown in FIG. 20 can be used as they are as the reproduction data of the input data. That is, these data outputs DOa and DOb correspond to the outputs of the identification circuit 100 in FIG.
即ち、 図 23の PLL回路では、 位相比較検出回路 400で得られた 「疑似同 期ズレ」 識別信号と 「同期」 識別信号との間の位相比較出力差電圧に基づいて P L L回路のループ利得を制御するため、 現時点での入力信号の特性及び位相比較 回路特性を加味した正確なループ利得補償機能を有する P L L回路を提供可能で ある。 That is, in the PLL circuit of FIG. 23, the loop gain of the PLL circuit is determined based on the phase comparison output difference voltage between the “pseudo-synchronization” identification signal and the “synchronization” identification signal obtained by the phase comparison detection circuit 400. For control, it is possible to provide a PLL circuit having an accurate loop gain compensation function taking into account the current input signal characteristics and phase comparison circuit characteristics.
尚、 図 23の回路構成に限らず、 制御回路 520はチャージポンプの出力電流 振幅 I c以外の P LL回路のループ利得の決定要因であるフィルタ 30の伝達関 数 F (s) 、 VC040の利得 Kv等を制御して P LL回路のループ利得を補償 する構成としても良いことは言うまでも無い。 The control circuit 520 is not limited to the circuit configuration shown in FIG. 23, and the transfer function F (s) of the filter 30 and the gain of the VC040, which determine the loop gain of the PLL circuit other than the output current amplitude Ic of the charge pump, It goes without saying that a configuration may be adopted in which the loop gain of the PLL circuit is compensated by controlling Kv and the like.
上述の実施例では、 位相比較検出回路 400においてハーフレートクロックを 用いた B a n g -Β a n g位相比較器を適用しているが、 これ以外にもフルレー トクロックを用いた、 位相比較特性が鋸波状 (図 25参照) となる位相比較器に 対して本発明を適用することも可能である。 図 24はその場合の位相比較検出回 路の回路構成例を示す。 同図の回路では、 データ信号 D Aをクロック信号 Cしの タイミングで識別する識別器 611とデータ信号 D Aを、 クロック信号 CLを遅 延器 622にて所定量遅延させた遅延クロック信号 C L' のタイミングで識別す る識別器 612とが設けられている。 そしてこれら識別器 611, 612による 識別出力 DO 1, DO 2の夫々とデータ信号 D Aとの排他的論理和をとる EXO
R 631, 632を設け、 これら EXOR631, 632の出力を平滑ィ匕する低 域通過フィルタ 641, 642を設けている。 In the above-described embodiment, the Bang-angang phase comparator using the half-rate clock is applied to the phase comparison detection circuit 400. However, in addition to this, the phase comparison characteristic using the full-rate clock has a sawtooth waveform. The present invention can be applied to a phase comparator as shown in FIG. FIG. 24 shows a circuit configuration example of the phase comparison detection circuit in that case. In the circuit shown in the figure, the discriminator 611 that identifies the data signal DA at the timing of the clock signal C and the data signal DA are delayed by a predetermined amount by the delay signal 622 from the clock signal CL. And a discriminator 612 for discriminating by. EXO which takes the exclusive OR of each of the discrimination outputs DO 1 and DO 2 by these discriminators 611 and 612 and the data signal DA R631, 632 are provided, and low-pass filters 641, 642 for smoothing the outputs of these EXORs 631, 632 are provided.
図 24の位相比較検出回路によれば、 図 20の場合同様、 識別ク口ック信号 C L, CL, の位相差による識別結果信号 DO 1, DO 2間の差異を、 これら識別 結果信号 DO 1, DO 2と元のデータ信号 DAとの排他論理和演算を行ってそれ ら EXOR演算結果を夫々平滑化して差を得ることで検出する。 図 25は、 その 場合に得られる差電圧を説明するための図である。 ここで検出される LPF 64 1, 642の出力 Ph l, と Ph 2, との間の差電圧 Δνを、 遅延器 622によ る遅延量である Δ tを周期 Tで基準化した遅延位相量を表す Δ t/Tで割ること で、 位相比較利得である Kpが得られる (下式参照) 。 According to the phase comparison detection circuit of FIG. 24, as in the case of FIG. 20, the difference between the identification result signals DO 1 and DO 2 due to the phase difference between the identification cook signals CL, CL, and these identification result signals DO 1 , DO 2 and the original data signal DA, perform an exclusive OR operation, and smooth the EXOR operation results to obtain the difference, thereby detecting the difference. FIG. 25 is a diagram for explaining the difference voltage obtained in that case. The difference voltage Δν between the outputs Ph 1, Ph 2 of the LPFs 64 1, 642 detected here and Ph 2 is the delay phase amount obtained by standardizing Δt, which is the delay amount by the delay unit 622, with the period T. By dividing by Δt / T, which represents, the phase comparison gain Kp can be obtained (see the following equation).
Kp = AV/ (Δ t/T) このようにして得られた位相比較検出値を基にして図 23に示す制御回路 52 0がチャージポンプ 20の電流振幅値 I c等のループ利得決定要因パラメータを 調整制御することで P L L回路のループ利得を補償する。 Kp = AV / (Δt / T) Based on the phase comparison detection value obtained in this way, the control circuit 520 shown in FIG. 23 determines the loop gain determining factor parameters such as the current amplitude value Ic of the charge pump 20. By compensating the loop gain, the loop gain of the PLL circuit is compensated.
尚この場合では、 図 16の例に比較して、 入力データのエッジ率以外の要因に よる利得変動があつた場合にも位相比較利得を捕償可能である。 In this case, as compared with the example of FIG. 16, the phase comparison gain can be compensated even when there is a gain variation due to factors other than the edge rate of the input data.
又、 位相比較器を他の構成としても良く、 クロック信号 C Lの位相又は入力デ ータ信号 DAの位相を所定量遅延させ又は進ませる機能を有する、 位相比較器同 様の回路構成を有する位相検出回路と組み込んで P L L回路を構成しても良い。 以上説明したように、 本発明によれば P L L回路の位相比較器の変動'バラッ キ及び入力データのジッタ等に応じて位相比較利得を補償するため、 P L Lのル ープ利得を精度良く一定に保つことが可能であると共にジッタ周波数特性を安定 化することが出来、 もって P LL回路の性能の向上が可能である。 Further, the phase comparator may have another configuration, and has a function of delaying or advancing the phase of the clock signal CL or the phase of the input data signal DA by a predetermined amount, and has a circuit configuration similar to the phase comparator. A PLL circuit may be configured by incorporating the detection circuit. As described above, according to the present invention, the phase comparison gain is compensated for in accordance with the variation of the phase comparator of the PLL circuit and the jitter of the input data, etc. It is possible to stabilize the jitter frequency characteristics while maintaining the same, thereby improving the performance of the PLL circuit.
図 26、 図 27は本発明の他の実施例による誤同期検出装置を説明するための 図である。 図 26は図 1 8の回路構成と実質的に同様であり、 対応構成部分には 同一符号を付し、 重複説明を省く。 FIG. 26 and FIG. 27 are diagrams for explaining an erroneous synchronization detection device according to another embodiment of the present invention. FIG. 26 is substantially the same as the circuit configuration of FIG. 18, and the corresponding components are denoted by the same reference numerals, and redundant description will be omitted.
この場合、 P L L回路の位相比較器として図 27の破線にて示す如くの鋸波特
性を有するものを想定する。 即ち、 検出位相差に応じて出力される検出電圧が検 出位相差に応じて鋸波状に変化する特性を有するものである。 このような P L L 回路では、 この鋸波の上昇ランプ部の中間部、 即ち図中 P点にて位相ロックを掛 けることにより、 入力データ信号 D Aの信号変化点間の中央部分、 即ちアイバタ —ンの中心部のタイミングでデータを識別し得るようにクロック信号 C Lの位相 をロックし得る (図 5参照) 。 In this case, a sawtooth wave characteristic as shown by a broken line in FIG. 27 is used as a phase comparator of the PLL circuit. It is assumed that there is a property. That is, it has a characteristic that a detection voltage output according to the detected phase difference changes in a sawtooth waveform according to the detected phase difference. In such a PLL circuit, a phase lock is applied at an intermediate portion of the rising ramp portion of the sawtooth wave, that is, at a point P in the figure, so that a central portion between signal change points of the input data signal DA, that is, The phase of the clock signal CL can be locked so that data can be identified at the timing of the center of the clock (see Fig. 5).
ところが、 実際には入力データ信号 D Aのデューティーの変動等により、 鋸波 特性に図 2 7の実線で示す如くの波形の歪が生ずることがある。 その場合、 P L L回路では、 図 2 7中の Q点にて誤って位相ロックを掛けてしまう場合がある。 この場合誤同期となり、 クロック信号はデータのアイパ ーンのクロスポイント のタイミングでデータ識別を行なうことになり、 識別データが誤りとなる可能性 が高い。 However, in practice, the waveform distortion as shown by the solid line in FIG. 27 may occur in the sawtooth characteristic due to the fluctuation of the duty of the input data signal DA, and the like. In that case, the PLL circuit may erroneously lock the phase at point Q in Fig. 27. In this case, erroneous synchronization occurs, and the clock signal performs data identification at the timing of the crosspoint of the data eye pattern, so that the identification data is likely to be erroneous.
このような誤同期を防止するため、 本発明の他の実施例による誤同期検出装置 では、 例えば図 2 0乃至図 2 5と共に述べたように、 位相比較器の位相比較検出 出力は、 遅延器 3 1 3, 6 2 2によって与えられる遅延量△ tによって変化する。 しかしながら、 その変化量は、 データ信号 D Aとクロック信号 C Lとの間の絶対 位相に依存する特性を有する。 即ち、 データ信号 D Aとクロック信号 C Lとの間 の位相差がゼロ近辺、 即ちデータ信号 D Aのアイパターンの中心部のタイミング (図 5参照) でデータを識別する状態では、 正しくデータを識別できるため、 そ の識別信号とデータ信号 D Aとの排他的論理和結果には、 データ識別タイミング を遅延器 3 1 3にて遅延させても、 その遅延量 Δ tが周期 Tよりある程度小さい 限り、 その遅延量に略比例した程度の差異しか生じない。 In order to prevent such erroneous synchronization, in the erroneous synchronization detection device according to another embodiment of the present invention, as described with reference to FIGS. 20 to 25, for example, the phase comparison detection output of the phase comparator It depends on the delay amount Δt given by 3 1 3 and 6 2 2. However, the amount of change has a characteristic that depends on the absolute phase between the data signal DA and the clock signal CL. That is, when the phase difference between the data signal DA and the clock signal CL is near zero, that is, when the data is identified at the timing of the center of the eye pattern of the data signal DA (see FIG. 5), the data can be correctly identified. The exclusive OR result of the identification signal and the data signal DA indicates that even if the data identification timing is delayed by the delay device 3 13, as long as the delay Δt is somewhat smaller than the period T, the delay Only a difference approximately proportional to the amount occurs.
逆にアイパターンのクロスポイントのタイミング, 即ちデータ信号 D Aの値が 不定状態でデータ識別する場合正しいデータを識別できる可能性は 5 0 %程度で ある。 他方、 そのタイミングから上記所定量 Δ t遅延させ、 その遅延量 A tが上 記不定状態 (不感帯) を超えて略正確にデータ識別が可能な識別タイミングとな る程度に大きい場合、 正しいデータ識別の可能性は 1 0 0 %近くとなる。 その結 果、 そのような識別タイミングによる識別結果は、 遅延無しの場合 (即ち不定状 態で識別率 5 0 %程度の場合) の識別結果とは大きく異なることとなり、 その差
異は上記のアイパターンの中心付近での識別の場合に比してかなり大きくなる。 この点を図 2 7と共に再度説明するに、 アイパターンの中心付近でのデータ識 別の場合、 即ち同図の P点の場合の遅延有り無しの位相比較出力は夫々 D 1, D 2であり、 その差は A Vである。 他方、 アイパターンのクロスポイント付近での 場合、 即ち Q点の場合の遅延有り無しの位相比較出力は夫々 D 1, 、 D 2 ' であ り、 その差は Δ ν ' となる。 図示の如く、 明らかに Conversely, when data is identified with the timing of the eye pattern cross point, that is, the value of the data signal DA being undefined, the possibility of identifying correct data is about 50%. On the other hand, if the delay is delayed by the predetermined amount Δt from that timing, and the delay amount At exceeds the above-mentioned indeterminate state (dead zone) and is large enough to be an identification timing at which data can be identified almost accurately, correct data identification is performed. Is nearly 100%. As a result, the discrimination result based on such a discrimination timing is significantly different from the discrimination result when there is no delay (that is, when the discrimination rate is about 50% in an undefined state). The difference is much larger than in the case of the above-described identification near the center of the eye pattern. This point will be described again with reference to FIG. 27. In the case of data identification near the center of the eye pattern, that is, the phase comparison output with and without delay at point P in FIG. 27 is D 1 and D 2, respectively. , The difference is AV. On the other hand, in the vicinity of the eye pattern cross point, that is, in the case of point Q, the phase comparison outputs with and without delay are D1, D2 ', respectively, and the difference is Δν'. As shown, clearly
Δ V < Δ V である。 従って A Vが所定の基準値を超えて大きくなつたことを検出することに よつて誤同期を検出可能である。 ΔV <ΔV. Therefore, erroneous synchronization can be detected by detecting that AV has increased beyond a predetermined reference value.
尚本発明は上記実施例に限られず、 本発明の基本思想に従"?た様々な変形例が 実施可能であり、 それらの変形例も本発明の範囲に含まれることは言うまでも無 い。 It should be noted that the present invention is not limited to the above embodiment, and various modifications in accordance with the basic idea of the present invention can be implemented, and it goes without saying that these modifications are also included in the scope of the present invention. .
本発明は、 以下の構成を含む。 The present invention includes the following configurations.
(構成 1 ) (Configuration 1)
入力データ信号に対する、 そのデータを識別するための識別タイミング信号の 位相関係を所定の位相関係にするための P L L回路における、 入力データ信号と 識別タイミング信号との間の位相を比較する際の位相比較利得を検出する位相比 較利得検出回路であって、 Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection circuit for detecting gain,
入力データ信号と識別タイミング信号との間の位相関係を検出する第 1の位相 比較手段と、 First phase comparing means for detecting a phase relationship between the input data signal and the identification timing signal;
入力データ信号と識別タイミング信号との間の位相関係を所定量シフトさせる 位相関係シフト手段と、 Phase relationship shifting means for shifting the phase relationship between the input data signal and the identification timing signal by a predetermined amount;
位相関係シフト手段によってシフトされた入力データ信号と識別タイミング信 号との間の位相関係を検出する第 2の位相比較手段と、 Second phase comparing means for detecting a phase relation between the input data signal shifted by the phase relation shifting means and the identification timing signal;
第 1及び第 2の位相比較手段の夫々の出力の差及び上記位相関係シフト手段が 位相関係をシフトさせる所定量に基づいて位相比較利得を検出する位相比較利得 検出手段とよりなる位相比較利得検出回路。
(構成 2 ) A phase comparison gain detecting means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparing means and a predetermined amount by which the phase relation shifting means shifts the phase relation; circuit. (Configuration 2)
上記構成 1の位相比較利得検出回路において、 In the phase comparison gain detection circuit of the above configuration 1,
第 1の位相比較手段は入力データ信号と識別タイミング信号とが略同期した状 態の両者間の位相関係を検出し、 The first phase comparison means detects a phase relationship between the input data signal and the identification timing signal in a substantially synchronized state,
第 2の位相比較手段は入力データ信号と識別タイミング信号とが略同期した状 態から所定量シフトした状態における両者間の位相関係を検出する構成の位相比 較利得検出回路。 The second phase comparison means is a phase comparison gain detection circuit configured to detect a phase relationship between the input data signal and the identification timing signal in a state where the input data signal and the identification timing signal are shifted by a predetermined amount from a state where they are substantially synchronized.
(構成 3 ) (Configuration 3)
所定周期でデータが切り替わる入力データ信号に対する、 そのデータを識別す るための識別タイミング信号の位相関係を所定の位相関係にするための P L L回 路における、 入力データ信号と識別タイミング信号との間の位相を比較する際の 位相比較利得を検出する位相比較利得検出回路であって、 In the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data to the predetermined phase relationship with respect to the input data signal whose data is switched at a predetermined cycle, the phase relationship between the input data signal and the identification timing signal is determined. A phase comparison gain detection circuit for detecting a phase comparison gain when comparing phases,
入力データ信号のデータを識別するデータ識別部のデータ識別出力と、 データ 識別タイミングを第 1の所定量ずらすことのよつて入力データ信号のデータの切 り替え検出する切り替え検出部のデータ識別出力との間のデータ相関を検出する ことによつて両者の位相を比較する第 1の位相比較手段と、 A data identification output of a data identification unit for identifying data of the input data signal; and a data identification output of a switching detection unit for detecting switching of the data of the input data signal by shifting the data identification timing by a first predetermined amount. First phase comparing means for comparing the phases of the two by detecting the data correlation between
上記データ識別部のデータ識別出力と、 上記切り替え検出部におけるデータ識 別タイミングを更に第 2の所定量ずらせた際のデータ識別出力との間のデータ相 関を検出することによって両者の位相を比較する第 2の位相比較手段と、 第 1及ぴ第 2の位相比較手段の夫々の出力の差及び上記識別タイミングをずら す第 2の所定量に基づいて位相比較利得を検出する位相比較利得検出手段とより なる位相比較利得検出回路。 By detecting a data correlation between the data identification output of the data identification unit and the data identification output when the data identification timing of the switching detection unit is further shifted by a second predetermined amount, the two phases are compared. Phase comparison gain detecting means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparing means and a second predetermined amount for shifting the identification timing. And a phase comparison gain detection circuit.
(構成 4 ) (Configuration 4)
入力データ信号に対する、 そのデータを識別するための識別タイミング信号の 位相関係を所定の位相関係にするための P L L回路における、 入力データ信号と 識別タイミング信号との間の位相を比較する際の位相比較利得を検出する位相比 較利得検出回路であって、 Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection circuit for detecting gain,
入力データ信号のデータと、 入力データ信号を上記識別タイミング信号によつ て識別することによって得られた識別出力のデータとの間のデータ相関を検出す
ることで位相を比較する第 1の位相比較手段と、 The data correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal by the identification timing signal is detected. First phase comparing means for comparing phases by
入力データ信号のデータと、 入力データ信号を上記識別タイミング信号の識別 タイミングから所定量をずらせたタイミングにて識別することによって得られた 識別出力のデータとの間のデータ相関を検出することで位相を比較する第 2の位 相比較手段と、 The phase is detected by detecting the data correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal. A second phase comparison means for comparing
第 1及び第 2の位相比較手段の夫々の出力の差及ぴ上記識別タイミング信号の 識別タイミングをずらす所定量に基づいて位相比較利得を検出する位相比較利得 検出手段とよりなる位相比較利得検出回路。 A phase comparison gain detection circuit comprising phase comparison gain detection means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparison means and a predetermined amount for shifting the identification timing of the identification timing signal. .
(構成 W (Configuration W
第 1及び第 2の位相比較手段におけるデータ間のデータ相関検出は、 排他的論 理和演算によつて実現される構成を有してなる上記構成 3又は 4の位相比較利得 検出回路。 The phase comparison gain detecting circuit according to the above configuration 3 or 4, wherein the data correlation detection between the data in the first and second phase comparing means has a configuration realized by an exclusive OR operation.
(構成 6 ) (Configuration 6)
排他論理和出力は平滑化されて位相比較利得検出手段に入力される構成よりな る上記構成 5の位相比較利得検出回路。 The phase comparison gain detection circuit according to the above configuration 5, wherein the exclusive OR output is smoothed and input to the phase comparison gain detection means.
(構成 7 ) (Configuration 7)
各々のデータ識別はフリップフロップ回路によって実行される構成とされてな る上記構成 3乃至 6のうちのいずれかの位相比較利得検出回路。 The phase comparison gain detection circuit according to any one of the above configurations 3 to 6, wherein each data is identified by a flip-flop circuit.
(構成 8 ) (Configuration 8)
入力データ信号に対し、 そのデータを識別するための識別タイミング信号を同 期させる P L L回路において入力データ信号と識別タイミング信号との間の誤同 期を検出するための誤同期検出回路であって、 An erroneous synchronization detecting circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal,
入力データ信号と識別タイミング信号との間の位相関係を検出する第 1の位相 比較手段と、 First phase comparing means for detecting a phase relationship between the input data signal and the identification timing signal;
入力データ信号と識別タイミング信号との間の位相関係を所定量シフトさせる 位相関係シフト手段と、 Phase relationship shifting means for shifting the phase relationship between the input data signal and the identification timing signal by a predetermined amount;
位相関係シフト手段によってシフトされた入力データ信号と識別タイミング信 号との間の位相関係を検出する第 2の位相比較手段と、 Second phase comparing means for detecting a phase relation between the input data signal shifted by the phase relation shifting means and the identification timing signal;
第 1及び第 2の位相比較手段の夫々の出力の差に基づいて誤同期状態を検出す
る構成の誤同期検出回路。 An erroneous synchronization state is detected based on a difference between respective outputs of the first and second phase comparison means. Erroneous synchronization detection circuit.
(構成 9 ) (Configuration 9)
入力データ信号に対し、 そのデータを識別するための識別タイミング信号を同 期させる P L L回路において入力データ信号と識別タイミング信号との間の誤同 期を検出するための誤同期検出回路であって、 An erroneous synchronization detecting circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal,
入力データ信号のデータを識別するデータ識別部のデータ識別出力と、 データ 識別タイミングを第 1の所定量ずらすことのよつて入力データ信号のデータの切 り替え検出する切り替え検出部のデータ識別出力との間のデータ相関を検出する ことによつて両者の位相を比較する第 1の位相比較手段と、 A data identification output of a data identification unit for identifying data of the input data signal; and a data identification output of a switching detection unit for detecting switching of the data of the input data signal by shifting the data identification timing by a first predetermined amount. First phase comparing means for comparing the phases of the two by detecting the data correlation between
上記データ識別部のデータ識別出力と、 上記切り替え検出部におけるデータ識 別タイミングを更に第 2の所定量ずらせた際のデータ識別出力との間のデータ相 関を検出することによつて両者の位相を比較する第 2の位相比較手段と、 第 1及び第 2の位相比較手段の夫々の出力の差に基づいて誤同期状態を検出す る誤同期検出手段とよりなる . By detecting a data correlation between the data identification output of the data identification unit and the data identification output when the data identification timing of the switching detection unit is further shifted by a second predetermined amount, the phase of both is detected. And a false synchronization detection means for detecting a false synchronization state based on the difference between the outputs of the first and second phase comparison means.
誤同期検出回路。 False sync detection circuit.
(構成 1 0 ) (Configuration 10)
入力データ信号に対し、 そのデータを識別するための識別タイミング信号を同 期させる P L L回路において入力データ信号と識別タイミング信号との間の誤同 期を検出するための誤同期検出回路であって、 An erroneous synchronization detecting circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal,
入力データ信号のデータと、 入力データ信号を上記識別タイミング信号によつ て識別することによって得られた識別出力のデータとの間の相関を検出すること で位相を比較する第 1の位相比較手段と、 First phase comparing means for comparing phases by detecting a correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal. When,
入力データ信号のデータと、 入力データ信号を上記識別タイミング信号の識別 タイミングから所定量をずらせたタイミングにて識別することによって得られた 識別出力のデータとの間の相関を検出することで位相を比較する第 2の位相比較 手段と、 The phase is detected by detecting the correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal. Second phase comparing means for comparing;
第 1及び第 2の位相比較手段の夫々の出力の差に基づいて誤同期状態を検出す る誤同期検出手段よりなる誤同期検出回路。 An erroneous synchronization detection circuit comprising erroneous synchronization detection means for detecting an erroneous synchronization state based on a difference between respective outputs of the first and second phase comparison means.
(構成 1 1 )
上記構成 1乃至 7のうちのいずれかの位相比較利得検出回路及び上記構成 8乃 至 1 1のうちのいずれかの誤同期検出回路のうちの少なくとも一方の回路を備え た P L L回路であって、 (Configuration 1 1) A PLL circuit comprising at least one of the phase comparison gain detection circuit of any of the above configurations 1 to 7 and the false synchronization detection circuit of any of the above configurations 8 to 11.
該位相比較利得検出回路の位相比較検出利得に基づいて P L L回路のループ利 得を制御する制御回路、 及び上記誤同期検出回路の誤同期検出結果に基づいて位 相口ック動作を制御する制御回路のうちの少なくとも一方の制御回路を更に有す る P L L回路。 A control circuit for controlling the loop gain of the PLL circuit based on the phase comparison detection gain of the phase comparison gain detection circuit, and a control for controlling the phase lock operation based on the false synchronization detection result of the false synchronization detection circuit A PLL circuit further comprising at least one control circuit of the circuits.
(構成 1 2 ) (Configuration 1 2)
前記制御回路は、 当該 P L L回路を構成するチャージポンプの電流振幅、 ルー プフィルタの伝達関数、 V C Oの制御利得のうちの少なくともいずれかを変化さ せることによって; P L L回路のループ利得を制御する構成よりなる上記構成 1 1 の P L L回路。 The control circuit is configured to change at least one of a current amplitude of a charge pump constituting the PLL circuit, a transfer function of a loop filter, and a control gain of a VCO; The PLL circuit having the above configuration 11.
(構成 1 3 ) (Configuration 13)
入力データ信号に対する、 そのデータを識別するための識別タイミング信号の 位相関係を所定の位相関係にするための P L L回路における、 入力データ信号と 識別タイミング信号との間の位相を比較する際の位相比較利得を検出する位相比 較利得検出方法であって、 Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection method for detecting gain,
入力データ信号と識別タイミング信号との間の位相関係を検出する第 1の位相 比較段階と、 A first phase comparing step of detecting a phase relationship between the input data signal and the identification timing signal;
入力データ信号と識別タイミング信号との間の位相関係を所定量シフトさせる 位相関係シフト段階と、 Shifting a phase relationship between the input data signal and the identification timing signal by a predetermined amount;
位相関係シフト手段によってシフトされた入力データ信号と識別タイミング信 号との間の位相関係を検出する第 2の位相比較段階と、 A second phase comparing step of detecting a phase relationship between the input data signal shifted by the phase relationship shifting means and the identification timing signal;
第 1及び第 2の位相比較段階の夫々で得られる出力値の差及び上記位相関係シ フト段階にて位相関係をシフトさせる所定量に基づいて位相比較利得を検出する 位相比較利得検出段階とよりなる位相比較利得検出方法。 A phase comparison gain detection step for detecting a phase comparison gain based on a difference between output values obtained in each of the first and second phase comparison steps and a predetermined amount for shifting the phase relation in the phase relation shift step. Phase comparison gain detection method.
(構成 1 4 ) (Configuration 14)
上記構成 1 3の位相比較検出方法において、 In the phase comparison detection method of the above configuration 13,
第 1の位相比較方法では入力データ信号と識別タイミング信号とが略同期した
状態の両者間の位相関係を検出し、 In the first phase comparison method, the input data signal and the identification timing signal are substantially synchronized. Detect the phase relationship between the two states,
第 2の位相比較段階では入力データ信号と識別タイミング信号とが略同期した 状態から所定量シフトした状態における両者間の位相関係を検出する構成の位相 比較検出方法。 In a second phase comparison step, a phase comparison detection method configured to detect a phase relationship between the input data signal and the identification timing signal in a state where the input data signal and the identification timing signal are shifted by a predetermined amount from a state where they are substantially synchronized.
(構成 1 5 ) (Configuration 15)
所定周期でデータが切り替わる入力データ信号に対する、 そのデータを識別す るための識別タイミング信号の位相関係を所定の位相関係にするための P L L回 路における、 入力データ信号と識別タイミング信号との間の位相を比較する際の 位相比較利得を検出する位相比較利得検出方法であって、 In the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data to the predetermined phase relationship with respect to the input data signal whose data is switched at a predetermined cycle, the phase relationship between the input data signal and the identification timing signal is determined. A phase comparison gain detection method for detecting a phase comparison gain when comparing phases,
入力データ信号のデータを識別するデータ識別部のデータ識別出力と、 データ 識別タイミングを第 1の所定量ずらすことのよつて入力データ信号のデータの切 り替え検出する切り替え検出部のデータ識別出力との聞のデータ相関を検出する ことによって両者の位相を比較する第 1の位相比較段階と、 A data identification output of a data identification unit for identifying data of the input data signal; and a data identification output of a switching detection unit for detecting switching of the data of the input data signal by shifting the data identification timing by a first predetermined amount. A first phase comparison step of comparing the two phases by detecting the data correlation of the
上記データ識別部のデータ識別出力と、 上記切り替え検出部におけるデータ識 別タイミングを更に第 2の所定量ずらせた際のデータ識別出力との間のデータ相 関を検出することによって両者の位相を比較する第 2の位相比較段階と、 第 1及び第 2の位相比較段階の夫々における比較出力値の差及ぴ上記識別タイ ミングをずらす第 2の所定量に基づいて位相比較利得を検出する位相比較利得検 出段階とよりなる位相比較利得検出方法。 By detecting a data correlation between the data identification output of the data identification unit and the data identification output when the data identification timing of the switching detection unit is further shifted by a second predetermined amount, the two phases are compared. A phase comparison step of detecting a phase comparison gain based on a difference between comparison output values in each of the first and second phase comparison steps and a second predetermined amount that shifts the identification timing. A phase comparison gain detection method comprising a gain detection step.
(構成 1 6 ) . (Configuration 16).
入力データ信号に対する、 そのデータを識別するための識別タイミング信号の 位相関係を所定の位相関係にするための P L L回路における、 入力データ信号と 識別タイミング信号との間の位相を比較する際の位相比較利得を検出する位相比 較利得検出方法であって、 Phase comparison when comparing the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship A phase comparison gain detection method for detecting gain,
入力データ信号のデータと、 入力データ信号を上記識別タイミング信号によつ て識別することによって得られた識別出力のデータとの間のデータ相関を検出す ることで位相を比較する第 1の位相比較段階と、 A first phase for comparing phases by detecting data correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal. A comparison stage,
入力データ信号のデータと、 入力データ信号を上記識別タイミング信号の識別 タイミングから所定量をずらせたタイミングにて識別することによって得られた
識別出力のデータとの間のデータ相関を検出するこどで位相を比較する第 2の位 相比較段階と、 The data of the input data signal is obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal. A second phase comparison step of comparing phases by detecting a data correlation between the data of the identification output and
第 1及び第 2の位相比較段階の夫々における比較出力の差及び上記識別タイミ ング信号の識別タイミングをずらす所定量に基づいて位相比較利得を検出する位 相比較利得検出段階とよりなる位相比較利得検出方法。 A phase comparison gain detecting step of detecting a phase comparison gain based on a difference between comparison outputs in each of the first and second phase comparison steps and a predetermined amount for shifting the identification timing of the identification timing signal. Detection method.
(構成 1 7 ) (Configuration 17)
入力データ信号に対し、 そのデータを識別するための識別タイミング信号を同 期させる P L L回路において入力データ信号と識別タイミング信号との間の誤同 期を検出するための誤同期検出方法であって、 An erroneous synchronization detection method for detecting an erroneous synchronization between an input data signal and an identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal,
入力データ信号と識別タイミング信号との間の位相関係を検出する第 1の位相 比較段階と、 A first phase comparing step of detecting a phase relationship between the input data signal and the identification timing signal;
入力データ信号と識別タイミング信号との間の位相関係を所定量シフトさせる 位相関係シフト段階と、 Shifting a phase relationship between the input data signal and the identification timing signal by a predetermined amount;
位相関係シフト手段によってシフトされた入力データ信号と識別タイミング信 号との間の位相関係を検出する第 2の位相比較段階と、 A second phase comparing step of detecting a phase relationship between the input data signal shifted by the phase relationship shifting means and the identification timing signal;
第 1及び第 2の位相比較段階における夫々の出力の差に基づいて誤同期状態を 検出する構成の誤同期検出方法。 An erroneous synchronization detection method configured to detect an erroneous synchronization state based on a difference between respective outputs in the first and second phase comparison stages.
(構成 1 8 ) (Configuration 18)
入力データ信号に対し、 そのデータを識別するための識別タイミング信号を同 期させる P L L回路において入力データ信号と識別タイミング信号との間の誤同 期を検出するための誤同期検出方法であって、 An erroneous synchronization detection method for detecting an erroneous synchronization between an input data signal and an identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal,
入力データ信号のデータを識別するデータ識別部のデータ識別出 と、 データ 識別タイミングを第 1の所定量ずらすことのよつて入力データ信号のデータの切 り替え検出する切り替え検出部のデータ識別出力との間のデータ相関を検出する ことによつて両者の位相を比較する第 1の位相比較段階と、 The data identification output of the data identification unit that identifies the data of the input data signal, and the data identification output of the switching detection unit that detects the switching of the data of the input data signal by shifting the data identification timing by the first predetermined amount. A first phase comparison step of comparing the phases of the two by detecting the data correlation between
上記データ識別部のデータ識別出力と、 上記切り替え検出部におけるデータ識 別タイミングを更に第 2の所定量ずらせた際のデータ識別出力との間のデータ相 関を検出することによって両者の位相を比較する第 2の位相比較段階と、 第 1及び第 2の位相比較段階の夫々における出力の差に基づいて誤同期状態を
P T/JP2002/011319 By detecting a data correlation between the data identification output of the data identification unit and the data identification output when the data identification timing of the switching detection unit is further shifted by a second predetermined amount, the two phases are compared. Error synchronizing state based on the output difference in each of the second phase comparing step and the first and second phase comparing steps. PT / JP2002 / 011319
20 20
検出する誤同期検出段階とよりなる誤同期検出方法。 An error synchronization detection method including an error synchronization detection step of detecting.
(構成 1 9 ) (Configuration 19)
入力データ信号に対し、 そのデータを識別する めの識別タイミング信号を同 期させる P L L回路において入力データ信号と識別タイミング信号との間の誤同 期を検出するための誤同期検出回路であって、 An erroneous synchronization detection circuit for detecting an erroneous synchronization between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with respect to the input data signal,
入力データ信号のデータと、 入力データ信号を上記識別タイミング信号によつ て識別することによって得られた識別出力のデータとの間の相関を検出すること で位相を比較する第 1の位相比較段階と、 A first phase comparison step of comparing phases by detecting a correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal; When,
入力データ信号のデータと、 入力データ信号を上記識別タイミング信号の識別 タイミングから所定量をずらせたタイミングにて識別することによって得られた 識別出力のデータとの間の相関を検出することで位相を比較する第 2の位相比較 段階と、 The phase is detected by detecting the correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal. A second phase comparison stage to compare;
第 1及び第 2の位相比較段階の夫々における出力の差に基づいて誤同期状態を 検出する誤同期検出段階とよりなる誤同期検出方法。
An erroneous synchronization detection method comprising: an erroneous synchronization detection step of detecting an erroneous synchronization state based on a difference between outputs in each of the first and second phase comparison steps.
Claims
1 . 入力データ信号に対する、 そのデータを識別するための識別タイミング信 号の位相関係を所定の位相関係にするための P L L回路における、 入力データ信 号と識別タイミング信号との間の位相を比較する際の位相比較利得を検出する位 相比較利得検出回路であって、 1. Compare the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship. A phase comparison gain detection circuit for detecting the phase comparison gain at the time of
入力データ信号と識別タイミング信号との間の位相関係を検出する第 1の位相 比較手段と、 First phase comparing means for detecting a phase relationship between the input data signal and the identification timing signal;
入力データ信号と識別タイミング信号との間の位相関係を所定量シフトさせる 位相関係シフト手段と、 Phase relationship shifting means for shifting the phase relationship between the input data signal and the identification timing signal by a predetermined amount;
位相関係シフト手段によってシフトされた入力データ信号と識別タイミング信 号との間の位相関係を検出する第 2の位相比較手段と、 Second phase comparing means for detecting a phase relation between the input data signal shifted by the phase relation shifting means and the identification timing signal;
第 1及び第 2の位相比較手段の夫々の出力の差及び上記位相関係シフト手段が 位相関係をシフトさせる所定量に基づいて位相比較利得を検出する位相比較利得 検出手段とよりなる位相比較利得検出回路。 A phase comparison gain detecting means for detecting a phase comparison gain based on a difference between respective outputs of the first and second phase comparing means and a predetermined amount by which the phase relation shifting means shifts the phase relation; circuit.
2 . 所定周期でデータが切り替わる入力データ信号に対する、 そのデータを識 別するための識別タイミング信号の位相関係を所定の位相関係にするための P L L回路における、 入力データ信号と識別タイミング信号との間の位相を比較する 際の位相比較利得を検出する位相比較利得検出回路であって、 2. Between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal whose data switches at a predetermined cycle to the predetermined phase relationship. A phase comparison gain detection circuit for detecting a phase comparison gain when comparing the phases of
入力データ信号のデータを識別するデータ識別部のデータ識別出力と、 データ 識別タイミングを第 1の所定量ずらすことのよつて入力データ信号のデータの切 り替え検出する切り替え検出部のデータ識別出力との間のデータ相関を検出する ことによつて两者の位相を比較する第 1の位相比較手段と、 A data identification output of a data identification unit for identifying data of the input data signal; and a data identification output of a switching detection unit for detecting switching of the data of the input data signal by shifting the data identification timing by a first predetermined amount. First phase comparing means for comparing the phases of the users by detecting the data correlation between
上記データ識別部のデータ識別出力と、 上記切り替え検出部におけるデータ識 別タイミングを更に第 2の所定量ずらせた際のデータ識別出力との間のデータ相 関を検出することによって两者の位相を比較する第 2の位相比較手段と、 第 1及ぴ第 2の位相比較手段の夫々の出力の差及び上記識別タイミングをずら す第 2の所定量に基づいて位相比較利得を検出する位相比較利得検出手段とより
なる位相比較利得検出回路。 The phase of the user is detected by detecting a data correlation between the data identification output of the data identification unit and the data identification output when the data identification timing of the switching detection unit is further shifted by a second predetermined amount. A phase comparison gain for detecting a phase comparison gain based on a difference between respective outputs of the second phase comparison means to be compared and the first and second phase comparison means and a second predetermined amount for shifting the identification timing. Detection means and more Phase comparison gain detection circuit.
3 . 入力データ信号に対する、 そのデータを識別するための識別タイミング信 号の位相関係を所定の位相関係にするための P L L回路における、 入力データ信 号と識別タイミング信号との間の位相を比較する際の位相比較利得を検出する位 相比較利得検出回路であって、 3. Compare the phase between the input data signal and the identification timing signal in the PLL circuit for setting the phase relationship of the identification timing signal for identifying the data with respect to the input data signal to a predetermined phase relationship. A phase comparison gain detection circuit for detecting the phase comparison gain at the time of
入力データ信号のデータと、 入力データ信号を上記識別タイミング信号によつ て識別することによって得られた識別出力のデータとの間のデータ相関を検出す ることで位相を比較する第 1の位相比較手段と、 A first phase for comparing phases by detecting data correlation between data of an input data signal and data of an identification output obtained by identifying the input data signal by the identification timing signal. Means of comparison;
入力データ信号のデータと、 入力データ信号を上記識別タイミング信号の識別 タイミングから所定量をずらせたタイミングにて識別することによって得られた 識別出力のデータとの間のデータ相関を検出することで位相を比較する第 2の位 相比較手段と、 The phase is detected by detecting the data correlation between the data of the input data signal and the data of the identification output obtained by identifying the input data signal at a timing shifted by a predetermined amount from the identification timing of the identification timing signal. A second phase comparison means for comparing
第 1及び第 2の位相比較手段の夫々の出力値の差及び上記識別タイミング信号 の識別タイミングをずらす所定量に基づいて位相比較利得を検出する位相比較 J 得検出手段とよりなる位相比較利得検出回路。 A phase comparison gain detecting means for detecting a phase comparison gain based on a difference between respective output values of the first and second phase comparing means and a predetermined amount for shifting the identification timing of the identification timing signal; circuit.
4 . 入力データ信号に対し、 そのデータを識別するための識別タイミング信号 を同期させる P L L回路において入力データ信号と識別タイミング信号との間の 誤同期状態を検出するための誤同期検出回路であって、 4. An erroneous synchronization detection circuit for detecting an erroneous synchronization state between the input data signal and the identification timing signal in a PLL circuit for synchronizing an identification timing signal for identifying the data with the input data signal. ,
入力データ信号と識別タイミング ϊί言号との間の位相関係を検出する第 1の位相 比較手段と、 First phase comparing means for detecting a phase relationship between the input data signal and the identification timing ϊί symbol,
入力データ信号と識別タイミング信号との間の位相関係を所定量シフトさせる 位相関係シフト手段と、 Phase relationship shifting means for shifting the phase relationship between the input data signal and the identification timing signal by a predetermined amount;
位相関係シフト手段によってシフトされた入力データ信号と識別タイミング信 号との間の位相関係を検出する第 2の位相比較手段と、 Second phase comparing means for detecting a phase relation between the input data signal shifted by the phase relation shifting means and the identification timing signal;
第 1及び第 2の位相比較手段の夫々の出力値のに基づいて誤同期状態を検出す る構成の誤同期検出回路。
An erroneous synchronization detection circuit configured to detect an erroneous synchronization state based on respective output values of the first and second phase comparison means.
5 . 上記請求の範囲 1乃至 3のうちのいずれか一項に記載の位相比較利得検出 回路又は請求の範囲 4に記載の誤同期検出回路のうちの少なくともいずれかの回 路を備えた P L L回路であって、 5. A PLL circuit comprising at least one of the phase comparison gain detection circuit according to any one of claims 1 to 3 and the false synchronization detection circuit according to claim 4. And
該位相比較利得検出回路の位相比較検出利得に基づいて P L L回路のループ利 得を制御する制御回路又は誤同期検出回路の誤同期検出出力に基づいて位相口ッ ク動作を制御する制御回路を更に備えた P L L回路。
A control circuit for controlling loop gain of the PLL circuit based on the phase comparison detection gain of the phase comparison gain detection circuit or a control circuit for controlling a phase lock operation based on a false synchronization detection output of the false synchronization detection circuit. Equipped PLL circuit.
Priority Applications (2)
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PCT/JP2002/011319 WO2004040768A1 (en) | 2002-10-30 | 2002-10-30 | Phase comparison gain detecting circuit, erroneous synchronization detecting circuit and pll circuit |
JP2004547995A JP3908764B2 (en) | 2002-10-30 | 2002-10-30 | Phase comparison gain detection circuit, false synchronization detection circuit, and PLL circuit |
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PCT/JP2002/011319 WO2004040768A1 (en) | 2002-10-30 | 2002-10-30 | Phase comparison gain detecting circuit, erroneous synchronization detecting circuit and pll circuit |
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WO2004040768A1 true WO2004040768A1 (en) | 2004-05-13 |
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PCT/JP2002/011319 WO2004040768A1 (en) | 2002-10-30 | 2002-10-30 | Phase comparison gain detecting circuit, erroneous synchronization detecting circuit and pll circuit |
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WO (1) | WO2004040768A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007053414A2 (en) * | 2005-10-31 | 2007-05-10 | Teradyne, Inc. | Method and apparatus for adjustment of synchronous clock signals |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01215122A (en) * | 1988-02-24 | 1989-08-29 | Hitachi Ltd | Phase synchronizing signal generating circuit |
JPH0730415A (en) * | 1993-07-12 | 1995-01-31 | Oki Electric Ind Co Ltd | Pll circuit |
WO2001054283A1 (en) * | 2000-01-17 | 2001-07-26 | Fujitsu Limited | Pll circuit |
-
2002
- 2002-10-30 JP JP2004547995A patent/JP3908764B2/en not_active Expired - Fee Related
- 2002-10-30 WO PCT/JP2002/011319 patent/WO2004040768A1/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01215122A (en) * | 1988-02-24 | 1989-08-29 | Hitachi Ltd | Phase synchronizing signal generating circuit |
JPH0730415A (en) * | 1993-07-12 | 1995-01-31 | Oki Electric Ind Co Ltd | Pll circuit |
WO2001054283A1 (en) * | 2000-01-17 | 2001-07-26 | Fujitsu Limited | Pll circuit |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007053414A2 (en) * | 2005-10-31 | 2007-05-10 | Teradyne, Inc. | Method and apparatus for adjustment of synchronous clock signals |
WO2007053414A3 (en) * | 2005-10-31 | 2007-09-13 | Teradyne Inc | Method and apparatus for adjustment of synchronous clock signals |
JP2009514361A (en) * | 2005-10-31 | 2009-04-02 | テラダイン、 インコーポレイテッド | Method and apparatus for adjusting a synchronous clock signal |
US7593497B2 (en) | 2005-10-31 | 2009-09-22 | Teradyne, Inc. | Method and apparatus for adjustment of synchronous clock signals |
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JPWO2004040768A1 (en) | 2006-03-02 |
JP3908764B2 (en) | 2007-04-25 |
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