WO2004036650A1 - High frequency semiconductor device and producing the same - Google Patents

High frequency semiconductor device and producing the same Download PDF

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Publication number
WO2004036650A1
WO2004036650A1 PCT/KR2002/001476 KR0201476W WO2004036650A1 WO 2004036650 A1 WO2004036650 A1 WO 2004036650A1 KR 0201476 W KR0201476 W KR 0201476W WO 2004036650 A1 WO2004036650 A1 WO 2004036650A1
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WO
WIPO (PCT)
Prior art keywords
forming
porous silicon
oxide film
semiconductor device
high frequency
Prior art date
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PCT/KR2002/001476
Other languages
French (fr)
Inventor
Choong-Mo Nam
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Telephus Inc.
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Publication date
Application filed by Telephus Inc. filed Critical Telephus Inc.
Priority to AU2002324005A priority Critical patent/AU2002324005A1/en
Priority to PCT/KR2002/001476 priority patent/WO2004036650A1/en
Publication of WO2004036650A1 publication Critical patent/WO2004036650A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind

Definitions

  • the present invention relates to a high frequency semiconductor device and method for manufacturing the same, and more specially, to a high frequency semiconductor device comprising a CMOS and a passive device and method for manufacturing the same.
  • CMOS processing with silicon substrate is widely used for manufacturing an integrated circuit and there are developed and applied various processing methods for increasing degree of integration. Moreover, it is already equipped with the facilities to manufacture CMOS integrated circuits in large scale production. There has been, however, no efficient method for applying such a CMOS processing to high frequency bandwidth.
  • CMOS processing aggravation of stress on the silicon substrate to form a silicon oxide film with sufficient thickness, when the CMOS or the CMOS and the passive device is integrated; and requirement of an additional processing to lessen the stress.
  • a problem is a parasitic capacitance between an inductor and a silicon substrate in the application of the CMOS processing including silicon substrates and inductors to the integrated circuit for high frequency region. Namely, it is considered to decrease the parasitic capacitance between the inductor and the silicon substrate to implement the inductor with proper resonant frequency (IEEE Electron Device Letters, Vol. 14(5), pp. 246 248 (1993))
  • the porous silicon layer with sufficient thickness is formed on the silicon substrate by anodizing method and the dielectric layer is formed on the porous silicon layer.
  • the passive device such as inductor and so on is also described, consequently a method for lessening capacitive and inductive coupling with the silicon substrate is disclosed.
  • the integrated circuit of this invention should limit the degree of integration, since the excessively thick porous silicon layer is a substantial restriction in the degree of integration of device on the substrate.
  • the Korean Patent Publication No. 1994-034390 discloses that a substrate structure and method for forming a porous silicon layer by anodizing reaction, oxidizing it and forming a porous silicon oxide film in order to manufacture the HBT (Hetero junction Bipolar Transistor).
  • the Korean Patent Publication No. 1994-034390 provides some advantage for lowering the loss of the substrate occu ⁇ ing in the invention disclosed in the Korean Patent Publication No. 1998-042536.
  • Korean Patent Publication No. 1994-034390 it is disclosed that in order to prevent the anodizing reaction of the region in which the HBT is formed, the trench surrounding this region is formed. This trench can relieve the stress and device isolation characteristic, which occur in the processing for forming thick porous silicon oxide film.
  • a nitride film is used as shielding layer in order to prevent the upper part of substrate of region in which the HBT will be formed from anodizing and N-silicon epitaxial layer is used as a shielding layer from anodizing reaction in order to prevent the lower part of HBT not to be shielded by the trench from anodizing.
  • the substrate structure and manufacturing method disclosed in the Koran Patent Publication No. 1994-034390 has the limitation to CMOS processing because it is proper for the processing for using bipolar transistor structurally on the assumption as the epitaxial layer of N type silicon with several layer including buried N+ layer. Namely, in order to use a porous silicon oxide film and integrate the inductor in the CMOS processing, the method for manufacturing the device disclosed in the prior cannot be used as it is and, the simple and efficient manufacturing method which considers characteristic of the CMOS processing is highly demanded.
  • the present invention is devised to solve the above mentioned problems.
  • An object of the present invention is to provide a method for integrating efficiently a passive with device inductor in consideration of CMOS processing and compatibility.
  • Another object of the present invention is to provide a method for performing anodizing processing as formation of trench and deposition processing of dielectric layer for filling it etc is removed and stress of substrate is minimized.
  • Still another object of the present invention is to provide a porous silicon oxidation processing for relieving stress produced during the porous silicon oxidation processing carried under H 2 /0 2 atmosphere at more than 900 ° C . Also, another object of the present invention is to provide a condition of a porous silicon oxidation processing for minimizing the stress of substrate.
  • the present invention does not require a processing for forming a trench in order to relieve the stress of substrate by performing this porous silicon oxidation processing and may provide a high frequency semiconductor device by the simple method adequate to a CMOS processing.
  • a high frequency semiconductor device comprising: a porous silicon substrate; a first and a second conductive well formed on the porous silicon substrate selectively; a porous silicon oxide film with a thickness of more than 15 m which is selectively formed on the region of the porous silicon substrate where the first and the second conductive well is not formed ; each source, a drain and a gate respectively formed on the first and the second conductive well each; a first dielectric layer formed on the porous silicon oxide film to cover the source, the gate, the drain thoroughly in which a first plug is formed on the source and the drain; and a plurality of a first pad formed on the first plug.
  • said porous silicon oxide film can comprise; a first oxide film with a thickness of 700 A formed at 350T) ; and a second oxide film formed at 850 ° C and said plug and said pad can be comprised of at least one selected form Ti, W or Al.
  • a contact surface between said source and said drain and said plug can comprise one selected from a metal silicide layer and a barrier metal layer and an inductor layer formed on the first dielectric layer can selectively be included further.
  • Said inductor layer can be comprised of a plurality of layers, and a capacitor selectively formed on the first dielectric layer can be further included wherein an dielectric of the capacitor is preferable to be silicon nitride.
  • a resistance conductor on the porous silicon oxide film can be selectively included further and it is preferable for said resistance conductor to be poly silicon.
  • a method for manufacturing a high frequency semiconductor device comprising the steps of: forming a first and a second conductive well selectively on a silicon substrate doped uniformly by the first impurity; injecting and diffusing the second impurity into the first and the second conductive well; forming a porous silicon layer selectively on the silicon substrate in which the first and the second conductive well is not formed; forming a porous silicon oxide film having a thickness of more than 15 ⁇ m by oxidation of the porous silicon layer; forming a source, a drain and a gate respectively in the first and the second conductive well; forming a first dielectric layer on the porous silicon oxide film to cover the source, the drain and the gate thoroughly; forming a first via hole in the region corresponding to the source and the drain of the first dielectric layer; forming a first plug on the first via hole; and forming a first pad on the first plug.
  • said step for the porous silicon layer and said step for forming the porous silicon oxide film can further comprise the steps of: injecting ions with ion implantation of more than 1012/c ⁇ f; and activating injected ions at a temperature of more than 900 T).
  • said step for forming the porous silicon layer and said step for forming the porous silicon oxide film can be performed without forming mask patterns on the region in which the first and the second conductive well is formed and said oxidation of the porous silicon layer can comprise the steps of: forming a first oxide film of a thickness of 700 A at 350 ° C; and forming a second oxide film at 850 ° C.
  • the step of forming a first inductor pattern on the first dielectric layer can be included further and a plurality of inductor patterns can be formed on the first inductor pattern.
  • the present invention can further comprise the steps of: forming an lower electrode on the first dielectric layer; forming a dielectric on the upper electrode; and forming an upper electrode on the dielectric. And according to still another preferred embodiment of the present invention, the present invention can further comprise the steps of: forming a resistance conductor on the porous silicon oxide film; forming a first resistance plug on the resistance conductor; and forming a first resistance pad on the first resistance plug.
  • the present invention can provide new conditions of the porous silicon oxidation processing for minimizing the stress of the substrate and based on this, can also provide a simple method for integrating inductor in a high frequency integrated circuit, which is suitable for the CMOS processing unlike the prior art, wherein the trench is formed to relieve the stress of the substrate.
  • the anodizing reaction does not occur in the N-type region doped with impurities with more than a particular concentration. Therefore, The stress of the substrate is minimized by forming a thin oxide film more than 15 ⁇ m in a CMOS manufacturing processing which don't have to include complicate structure, that is to say, accumulation structure like buried N+ layer and so on.
  • the present invention can manufacture a semiconductor device by the above mentioned method and provide a method for integrating a passive device suitable for the manufacture processing of the semiconductor device and a semiconductor device manufactured by the method.
  • the present invention can provide the method for integrating semiconductor device and a passive device in semiconductor device
  • FIG. 1 is a flowchart showing a method for integrating a high frequency semiconductor device including a CMOS and an inductor according to the one preferred embodiment of the present invention
  • FIG. 2a to FIG. 2k are sectional views of the semiconductor device corresponding to each step in the flowchart of FIG. 1;
  • FIG. 3 is a flowchart showing a method for integrating a high frequency semiconductor device including a CMOS and an inductor according to another preferred embodiment of the present invention;
  • FIG. 4a to FIG. 4k are sectional views of the semiconductor device corresponding to each step in the flowchart of FIG 3;
  • FIG. 5a to FIG. 5d are sectional views of the semiconductor device including a CMOS and a capacitor according to the one preferred embodiment of the present invention;
  • FIG. 6a to FIG. 6e are sectional views of the semiconductor device including a CMOS and a resistor according to the one preferred embodiment of the present invention
  • FIG. 7a and FIG. 7b are flowcharts showing sectional view of the semiconductor device including a CMOS and a inductor, a capacitor and a resistor according to the one preferred embodiment of the present invention.
  • P type silicon substrate 20 the region in which P well will be formed
  • electrode material 50 porous silicon layer
  • the first pad 145 the second dielectric layer
  • FIG. 1 is a flowchart showing a method for integrating a high frequency semiconductor device including a CMOS and an inductor according to the one preferred embodiment of the present invention and FIG. 2a to FIG. 2k are sectional views of the semiconductor device corresponding to each step in the flowchart of FIG. 1.
  • the region of N- and P-well to be formed 20, 30 is defined by lithography on a silicon substrate 10 doped uniformly with P-type impurities and N-type impurities are injected and diffused into the region of N- and P-well to be formed (S10).
  • the electrode material 40 is deposited on the backside of the silicon substrate and a porous silicon layer 50 is formed by the anodizing reaction on the remaining region in which the N-type impurities are injected (S20).
  • a porous silicon oxide film 60 having at least 15 ⁇ m of a thickness is formed by oxidizing the porous silicon layer 50 (S30). And P-type impurities are injected and diffused into the region of the P-well to be formed 70 (S40).
  • the gate 80 is formed by the lithography and the etching processing and the source and the drain 90, 100 are formed by lithography and ion implantation (S45).
  • a silicon nitride film 110 and a BPSG filml20 for polishing is deposited, the first dielectric layer 110, 120 including the silicon nitride film 110 and BPSG film 120 is formed by reflow processing, the first via holel30 is formed by lithography and etching (Hereinafter, the reference number of a via hole will be illustrated with an arrow in order to prevent confusion of the via hole and a plug).
  • the first plug 135 is formed by an etch back processing, the first pad 140 of an metal layer is formed by the deposition, lithography and etching of Ti/Al-Cu/TiN (S50).
  • the pad can be formed with signal line transmission.
  • the pad will be illustrated as including section view of circuit.
  • the second dielectric layer 145 is formed by depositing the dielectric layer like PE-TEOS and so on
  • the second via hole 150 and the second plug 155 are formed by depositing the dielectric layer like PE-TEOS and so on.
  • the second pad 160 and the first inductor layer 161 can be formed simultaneously by deposition, lithography and etching of Ti/Al-Cu/TiN (S60).
  • the turn number is increased even in the small area to obtain high inductance and consequently improve the degree of integration in circuit by accumulating the inductor with several layers 220.
  • the third dielectric layer 170 is formed by depositing the dielectric layer like PE-TEOS and so on and the third via hole 180 is formed by the lithography and etching.
  • the third plug 185 is formed by the deposition of Ti/Al-Cu/TiN, the third pad 190 and the second inductor layer 192 can be formed simultaneously by the lithography and etching(S70).
  • the fourth dielectric layer 200 is formed for the passivation, the fourth via hole 200 and the fourth plug 230 for the input/output are formed by the lithography and etching.
  • the fourth pad 240 for the input/output can be formed by the lithography and etching of Ti/Al-Cu/TiN. Also, if metal and silicon is contacted directly, a resistor becomes great and an adhesive strength becomes low due to movements between atoms on the contact surface. Therefore, an additional process to form metal silicide or barrier metal in the contact surface can be included.
  • the N- and P-well have the sufficient Implanting concentration and diffusion depth not to make the anodizing reaction because the porous silicon layer is formed without mask pattern, in the step of injecting and diffusing N-type impurities into the region of N- and P-well to be formed (S10).
  • the implanting concentration and diffusion depth more than 1012/c ⁇ not to make the anodizing reaction in the step for forming the porous silicon layer (S20) to prevent the anodizing reaction on the surface and the lower part thereof corresponding to the region of N- and P-well to be formed.
  • the step of forming the porous silicon layer (S20) can be performed without an additional mask layer on the region of N- and P-well to be formed.
  • an aluminium film can be used as the electrode material 40 for the anodizing reaction.
  • the aluminium film can be generally deposited by PVD (Physical Vapor Deposition) method.
  • the porous silicon is formed by the depth of l ⁇ m per minute when the metal electrode is formed by about 1000 A on the backside of the silicon substrate, and immersed into reaction solution, and then bias is provided and current is supplied.
  • the step for forming the porous silicon oxide film (S30) can be performed without additional mask pattern as well. While all of the porous silicon layer 50 is oxidized and changed to porous silicon oxide film 60, thin oxide film can be formed on the surface of the silicon crystal 20, 30 because there is great difference between the porous silicon layer 50 and the silicon crystal 20, 30 in the velocity of oxidation
  • the processing for manufacturing the semiconductor device according to the present invention can be lessened and high productivity can be obtained.
  • the step for forming the porous silicon oxide film S30 is performed under the condition of steam atmosphere and less than 850 °C in order to relieve the stress of the silicon substrate. More specifically, the oxidation reaction is carried for 30 minutes at 350 ° C to produce a thin oxide film with the depth of about 700 A , the oxidation reaction is carried for 30 minutes at 850 "C to give a porous silicon oxide film with the depth of more than 15 m.
  • the oxidation processing is carried at a temperature of 900 to 1000 ° C, the oxidation reaction in this high temperature is a main cause for the stress of the substrate. Therefore, trench and additional process need to be carried in the prior art to relive the stress.
  • the present invention can eliminate the stress by employing a simple and efficient CMOS processing.
  • the inductor pattern is formed on the second dielectric layer.
  • FIG. 3 is a flowchart showing a method for integrating high frequency semiconductor device including a CMOS and an inductor according to the another preferred embodiment of the present invention and FIG. 4a to FIG. 4k are sectional views of the semiconductor device corresponding to each step in the flowchart of FIG3.
  • the silicon nitride film is deposited on the silicon substrate 310 doped with P-type impurities, first of all (S110).
  • the region of N- and P-well to be formed is defined on the silicon nitride film by lithography and a silicon nitride film mask pattern 320 can be formed by etching the silicon nitride film (S120).
  • the silicon nitride film mask pattern it is preferable for the silicon nitride film mask pattern to have sufficient margin in size of the mask in comparison with the size of N- and P-well region, considering the isotropy in the anodizing processing
  • the electrode material 340 is deposited on the backside of the silicon substrate and a porous silicon layer 350 is formed by the anodizing reaction on exposed part and adjacent part of the silicon substrate surface (S130).
  • an electrode material 340 is removed by the etching processing. Then, a porous silicon oxide film 60 with a thickness of at least 15 ⁇ m is formed by oxidizing the porous silicon layer 350 (S140) and the silicon nitride film mask pattern 320 is removed (S145). After this, the region 370 of P-well to be formed is defined by lithography and P-type impurities are injected and diffused into the region. Then the region 372 of N-well to be formed is defined by lithography and N-type impurities are injected and diffused into the region
  • the gate 380 is formed by the lithography processing and etching processing, the source and the drain
  • 390, 400 are formed by the lithography and Implanting processing (S155).
  • a silicon nitride film 410 and a BPSG film 420 for polishing are deposited, the first dielectric layer 410, 420 including the silicon nitride film 410 and BPSG film 420 is formed by the reflow processing, the first via hole 430 is formed by the lithography and etching processing. Then, the first via hole 430 is filled with tungsten and so on (Ti/TiN/W), the first plug 435 is formed by an etch back processing, the first pad 440 of an metal layer is formed by deposition, lithography and etching of Ti/Al-Cu/TiN (S160).
  • the second dielectric layer 445 is formed by the deposition of the dielectric layer like PE-TEOS etc on the first dielectric layer, and further, the second via hole 450 and the second plug 455 are formed by the lithography and etching. Then, the second pad 460 and the first inductor layer 461 can be formed by the deposition, lithography and etching of Ti/Al-Cu/TiN .
  • the third dielectric layer 470 is formed by the deposition of the dielectric layer like PE-TEOS and so on, the third via hole 480 and the third plug 485 are formed by the lithography and etching processing, and the third pad 490 and the second inductor layer 492 can be formed by the deposition, lithography and etching of Ti/Al-Cu/TiN .
  • the turn number is increased even in the small area to obtain high inductance and consequently improve the degree of integration in circuit by accumulating the inductor with several layers 520.
  • FIG. 5a to FIG. 5d are sectional views of a semiconductor device including a CMOS and a capacitance device according to the one preferred embodiment of the present invention.
  • the processing is same or similar to the method for manufacturing the semiconductor device including the CMOS and inductance device and the above mentioned in FIG. 1 to FIG. 4k will be omitted.
  • the processing is same to the step for forming the first plug in the first dielectric layer 135, forming the first pad 140 of the metal layer by the deposition, lithography and etching of Ti/Al-Cu TiN (S50) or the step for forming the first pad 440 of the metal layer on the first plug 435 in the first dielectric layer by the deposition of Ti/Al-Cu/TiN, the lithography and etching.
  • the first pad 140, 440 and the capacitor 510 can be formed simultaneously (S60).
  • the capacitor 510 is formed as follows. A lower electrode 505 is formed and a dielectric layer (503) is formed on the lower electrode.
  • the dielectric layer 503 is about 500 A of a thickness and is composed of silicon nitride.
  • an upper electrode 500 is formed on the dielectric layer,
  • the second dielectric layer can be formed on the first dielectric layer to cover the first pad 140, 440 and the capacitor thoroughly.
  • the second dielectric layer 545 is formed by the deposition of the dielectric layer like PE-TEOS and so on, the second via hole 550 and the second plug 555 are formed by the deposition of the dielectric layer, the second pads 560 can be formed simultaneously by the deposition, lithography and etching of Ti/Al-Cu/TiN.
  • the fourth dielectric layer 570 is formed for the passivation, the fourth via hole 580 and the fourth plug 590 for the input/output are formed by the lithography and etching. And the fourth pad 595 for the input/output can be formed by the lithography and etching of Ti/Al- Cu/TiN.
  • FIG. 6a to FIG. 6e are sectional views of the semiconductor device including CMOS and resistance device according to the one preferred embodiment of the present invention.
  • the processing is same or similar to the method for manufacturing the semiconductor device including the CMOS and inductance device and thus, the description in FIG. 1 to FIG. 4k will be omitted.
  • the method for integrating device including CMOS and resistance device is same upto the step for forming the gate 380 by the lithography and etching processing by depositing the gate oxide film, the gate material and the dielectric layer, forming the gate 80 by the lithography and etching processing as mentioned in FIG. 1, and depositing the gate oxide film, the gate material and the dielectric layer as mentioned in FIG. 3.
  • a resistance conductor is selectively formed on the porous silicon oxide film and the resistance conductor can be comprised of poly silicon.
  • the source and the drain 600, 605 are formed by the lithography and ion Implantation.
  • a silicon nitride film 610 and BPSG film 620 for polishing are deposited, and the first dielectric layer 110, 120 including the silicon nitride film 610 and the BPSG film 620 is formed by the reflow processing.
  • the first via hole 630 is formed by the lithography and etching processing, the first via hole 630 is filled with tungsten and so on (Ti/TiN/W) and the first plug 635 is formed by an etch back processing.
  • the first pad 640 of a metal layer is formed by the deposition, lithography and etching of Ti/Al-Cu/TiN on the first plug 635.
  • the second dielectric layer 645 is formed by the deposition of the dielectric layer like PE-TEOS and so on, the second via hole 650 and the second plug 655 are formed by the deposition of the dielectric layer, the second pads 660 can be formed simultaneously by the deposition, lithography and etching of Ti/Al-Cu/TiN.
  • the fourth dielectric layer 670 is formed for the passivation, the fourth via hole 680 and the fourth plug 690 for the input/output are formed by the lithography and etching .
  • the fourth pad 695 for the input/output can be formed by the lithography and etching of Ti/Al- Cu/TiN.
  • FIG. 7a and FIG. 7b are flowcharts showing sectional view of the semiconductor device including CMOS and inductor, capacitor and resistance device according to the one preferred embodiment of the present invention.
  • the CMOS is integrated into a plurality of passive devices . It is natural for the present invention not to be limited to the embodiment of the passive device illustrated in FIG. 7a and FIG. 7b and various modification and adjustment of a passive device will be apparent by the manufacturing method according to the present invention. Namely, one of each resistor, inductor and capacitor is integrated in the drawing, a plurality of resistors, capacitors or inductors can be coupled and integrated variously.
  • FIG. 7a and FIG. 7b shows a manufacturing method for coupling the processing illustrated in FIG. 1 to FIG. 6e. Since the manufacturing processing of the device is explained in FIG. 1 to FIG. 6e, further explanation will be omitted.
  • the present invention can provide a method for integrating a semiconductor device and a passive device in the semiconductor device. Namely, when a high frequency integrated circuit is implemented by CMOS processing, the present invention can provide a simple and efficient processing method in consideration of compatibility between a passive device processing and CMOS processing.
  • the present invention can provide a method for integrating efficiently a passive device like inductor on the porous silicon oxide film and the device manufactured by the method with maintenance of high compatibility with the process for manufacturing CMOS integrated circuit,
  • the present invention can provide a CMOS high frequency integrated circuit with high productivity by simplifying the processing steps.
  • the present invention can increase the reliability of the CMOS high frequency integrated circuit by providing the processing condition to lessen the stress of substrate when the porous silicon oxide film is formed.

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Abstract

The present invention relates to a high frequency semiconductor device and method for manufacturing the same, and more specially, to a high frequency semiconductor device including a CMOS and a passive device and method for manufacturing the same. In accordance with one aspect of the present invention, there is provided with a high frequency semiconductor device comprising: a porous silicon substrate; a first and a second conductive well formed on the porous silicon substrate selectively; a porous silicon oxide film of the thickness more than 15µm which is selectively formed on the region which the first and the second conductive well is not formed on the porous silicon substrate; a source, a drain and a gate formed on the first and the second conductive well, respectively; a first dielectric layer formed on the porous silicon oxide film to cover the source, the gate, the drain thoroughly in which a first plug is formed on the source and the drain; and a plurality of a first pad formed on the first plug.

Description

HIGH FREQUENCY SEMICONDUCTOR DEVICE AND PRODUCING THE SAME
Technical Field
The present invention relates to a high frequency semiconductor device and method for manufacturing the same, and more specially, to a high frequency semiconductor device comprising a CMOS and a passive device and method for manufacturing the same.
Background Art
Recently, a CMOS processing with silicon substrate is widely used for manufacturing an integrated circuit and there are developed and applied various processing methods for increasing degree of integration. Moreover, it is already equipped with the facilities to manufacture CMOS integrated circuits in large scale production. There has been, however, no efficient method for applying such a CMOS processing to high frequency bandwidth.
Therefore, there are some drawbacks in production of conventional high frequency integrated circuits comprising various single chips with maintaining high productivity by the
CMOS processing; aggravation of stress on the silicon substrate to form a silicon oxide film with sufficient thickness, when the CMOS or the CMOS and the passive device is integrated; and requirement of an additional processing to lessen the stress.
Hereinafter, the problems associated with the prior art will be described with reference to high frequency semiconductor devices including CMOS and inductor. A problem is a parasitic capacitance between an inductor and a silicon substrate in the application of the CMOS processing including silicon substrates and inductors to the integrated circuit for high frequency region. Namely, it is considered to decrease the parasitic capacitance between the inductor and the silicon substrate to implement the inductor with proper resonant frequency (IEEE Electron Device Letters, Vol. 14(5), pp. 246 248 (1993))
It is also considered to decrease the resistance loss of material composing inductor and the eddy current loss by inductive coupling of silicon substrate for obtaining a high Q coefficient, in the prior art, to remove the above mentioned parasitic capacitance and eddy current, has it been disclosed in the Korean Patent Publication Nos. 1998-042536 and 1994- 034390.
According to the Korean Patent Publication No. 1998-042536, the porous silicon layer with sufficient thickness (at least more than 200/ΛII) is formed on the silicon substrate by anodizing method and the dielectric layer is formed on the porous silicon layer. Further, the passive device such as inductor and so on is also described, consequently a method for lessening capacitive and inductive coupling with the silicon substrate is disclosed.
However, it requires to form an excessively thick porous silicon layer in this invention since it is difficult to obtain sufficient resistance only with a porous silicon layer.
Also, according to this invention, sufficient margin is required in size of the mask for the isotropy in anodizing processing. However, the integrated circuit of this invention should limit the degree of integration, since the excessively thick porous silicon layer is a substantial restriction in the degree of integration of device on the substrate.
The Korean Patent Publication No. 1994-034390 discloses that a substrate structure and method for forming a porous silicon layer by anodizing reaction, oxidizing it and forming a porous silicon oxide film in order to manufacture the HBT (Hetero junction Bipolar Transistor). The Korean Patent Publication No. 1994-034390 provides some advantage for lowering the loss of the substrate occuπing in the invention disclosed in the Korean Patent Publication No. 1998-042536.
In Korean Patent Publication No. 1994-034390, it is disclosed that in order to prevent the anodizing reaction of the region in which the HBT is formed, the trench surrounding this region is formed. This trench can relieve the stress and device isolation characteristic, which occur in the processing for forming thick porous silicon oxide film.
Also, there are some considerations such that a nitride film is used as shielding layer in order to prevent the upper part of substrate of region in which the HBT will be formed from anodizing and N-silicon epitaxial layer is used as a shielding layer from anodizing reaction in order to prevent the lower part of HBT not to be shielded by the trench from anodizing.
However, the substrate structure and manufacturing method disclosed in the Koran Patent Publication No. 1994-034390 has the limitation to CMOS processing because it is proper for the processing for using bipolar transistor structurally on the assumption as the epitaxial layer of N type silicon with several layer including buried N+ layer. Namely, in order to use a porous silicon oxide film and integrate the inductor in the CMOS processing, the method for manufacturing the device disclosed in the prior cannot be used as it is and, the simple and efficient manufacturing method which considers characteristic of the CMOS processing is highly demanded.
Disclosure of the Invention
The present invention is devised to solve the above mentioned problems.
An object of the present invention is to provide a method for integrating efficiently a passive with device inductor in consideration of CMOS processing and compatibility.
Also, another object of the present invention is to provide a method for performing anodizing processing as formation of trench and deposition processing of dielectric layer for filling it etc is removed and stress of substrate is minimized.
Also, Still another object of the present invention is to provide a porous silicon oxidation processing for relieving stress produced during the porous silicon oxidation processing carried under H2/02 atmosphere at more than 900 °C . Also, another object of the present invention is to provide a condition of a porous silicon oxidation processing for minimizing the stress of substrate. The present invention does not require a processing for forming a trench in order to relieve the stress of substrate by performing this porous silicon oxidation processing and may provide a high frequency semiconductor device by the simple method adequate to a CMOS processing. To achieve the above mentioned object, in accordance with one aspect of the present invention, there is provided with a high frequency semiconductor device comprising: a porous silicon substrate; a first and a second conductive well formed on the porous silicon substrate selectively; a porous silicon oxide film with a thickness of more than 15 m which is selectively formed on the region of the porous silicon substrate where the first and the second conductive well is not formed ; each source, a drain and a gate respectively formed on the first and the second conductive well each; a first dielectric layer formed on the porous silicon oxide film to cover the source, the gate, the drain thoroughly in which a first plug is formed on the source and the drain; and a plurality of a first pad formed on the first plug.
According to another preferred embodiment of the present invention, said porous silicon oxide film can comprise; a first oxide film with a thickness of 700 A formed at 350T) ; and a second oxide film formed at 850 °C and said plug and said pad can be comprised of at least one selected form Ti, W or Al.
Further, a contact surface between said source and said drain and said plug can comprise one selected from a metal silicide layer and a barrier metal layer and an inductor layer formed on the first dielectric layer can selectively be included further.
Said inductor layer can be comprised of a plurality of layers, and a capacitor selectively formed on the first dielectric layer can be further included wherein an dielectric of the capacitor is preferable to be silicon nitride.
According to still another preferred embodiment of the present invention, a resistance conductor on the porous silicon oxide film can be selectively included further and it is preferable for said resistance conductor to be poly silicon.
In accordance with another aspect of the present invention, there is provided with a method for manufacturing a high frequency semiconductor device, the method comprising the steps of: forming a first and a second conductive well selectively on a silicon substrate doped uniformly by the first impurity; injecting and diffusing the second impurity into the first and the second conductive well; forming a porous silicon layer selectively on the silicon substrate in which the first and the second conductive well is not formed; forming a porous silicon oxide film having a thickness of more than 15μm by oxidation of the porous silicon layer; forming a source, a drain and a gate respectively in the first and the second conductive well; forming a first dielectric layer on the porous silicon oxide film to cover the source, the drain and the gate thoroughly; forming a first via hole in the region corresponding to the source and the drain of the first dielectric layer; forming a first plug on the first via hole; and forming a first pad on the first plug.
Here, said step for the porous silicon layer and said step for forming the porous silicon oxide film can further comprise the steps of: injecting ions with ion implantation of more than 1012/cπf; and activating injected ions at a temperature of more than 900 T).
According to another preferred embodiment of the present invention, said step for forming the porous silicon layer and said step for forming the porous silicon oxide film can be performed without forming mask patterns on the region in which the first and the second conductive well is formed and said oxidation of the porous silicon layer can comprise the steps of: forming a first oxide film of a thickness of 700 A at 350 °C; and forming a second oxide film at 850 °C.
According to still another preferred embodiment of the present invention, the step of forming a first inductor pattern on the first dielectric layer can be included further and a plurality of inductor patterns can be formed on the first inductor pattern.
According to still another preferred embodiment of the present invention, the present invention can further comprise the steps of: forming an lower electrode on the first dielectric layer; forming a dielectric on the upper electrode; and forming an upper electrode on the dielectric. And According to still another preferred embodiment of the present invention, the present invention can further comprise the steps of: forming a resistance conductor on the porous silicon oxide film; forming a first resistance plug on the resistance conductor; and forming a first resistance pad on the first resistance plug.
The present invention can provide new conditions of the porous silicon oxidation processing for minimizing the stress of the substrate and based on this, can also provide a simple method for integrating inductor in a high frequency integrated circuit, which is suitable for the CMOS processing unlike the prior art, wherein the trench is formed to relieve the stress of the substrate.
During the anodizing processing, the anodizing reaction does not occur in the N-type region doped with impurities with more than a particular concentration. Therefore, The stress of the substrate is minimized by forming a thin oxide film more than 15 μm in a CMOS manufacturing processing which don't have to include complicate structure, that is to say, accumulation structure like buried N+ layer and so on.
The present invention can manufacture a semiconductor device by the above mentioned method and provide a method for integrating a passive device suitable for the manufacture processing of the semiconductor device and a semiconductor device manufactured by the method.
The present invention can provide the method for integrating semiconductor device and a passive device in semiconductor device
Brief Description of the Drawings
The above objects and other advantages of the present invention will become more apparent in detailed descriptions of the preferred embodiments thereof with reference to the attached drawings, in which: FIG. 1 is a flowchart showing a method for integrating a high frequency semiconductor device including a CMOS and an inductor according to the one preferred embodiment of the present invention;
FIG. 2a to FIG. 2k are sectional views of the semiconductor device corresponding to each step in the flowchart of FIG. 1; FIG. 3 is a flowchart showing a method for integrating a high frequency semiconductor device including a CMOS and an inductor according to another preferred embodiment of the present invention;
FIG. 4a to FIG. 4k are sectional views of the semiconductor device corresponding to each step in the flowchart of FIG 3; FIG. 5a to FIG. 5d are sectional views of the semiconductor device including a CMOS and a capacitor according to the one preferred embodiment of the present invention;
FIG. 6a to FIG. 6e are sectional views of the semiconductor device including a CMOS and a resistor according to the one preferred embodiment of the present invention;
FIG. 7a and FIG. 7b are flowcharts showing sectional view of the semiconductor device including a CMOS and a inductor, a capacitor and a resistor according to the one preferred embodiment of the present invention.
< The description of the reference characters of the major parts of the drawings>
10: P type silicon substrate 20: the region in which P well will be formed
30: the region in which N well will be formed
40: electrode material 50: porous silicon layer
60: porous silicon oxide film layer 70: P well
80: gate 90: NMOS the source and the drain region 100: PMOS the source and the drain region
110, 120: the first dielectric layerBO: the first via hole
140: the first pad 145: the second dielectric layer
150: the second via hole 160: the second pad
161: the first inductor layer 170: the third dielectric layer
180: the third via hole 190: the third pad
192: the second inductor layer
200: the fourth dielectric layer (passivation)
210: pad
The Best Modes for carrying out the Invention
Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings, but it is understood that the present invention should not be limited to the following embodiments. FIG. 1 is a flowchart showing a method for integrating a high frequency semiconductor device including a CMOS and an inductor according to the one preferred embodiment of the present invention and FIG. 2a to FIG. 2k are sectional views of the semiconductor device corresponding to each step in the flowchart of FIG. 1.
Referring to FIG. 1 to FIG. 2k, the method for integrating the inductor in the CMOS high frequency integrated circuit will be explained. First of all, the region of N- and P-well to be formed 20, 30 is defined by lithography on a silicon substrate 10 doped uniformly with P-type impurities and N-type impurities are injected and diffused into the region of N- and P-well to be formed (S10).
And then, the electrode material 40 is deposited on the backside of the silicon substrate and a porous silicon layer 50 is formed by the anodizing reaction on the remaining region in which the N-type impurities are injected (S20).
After the electrode material 40 on the substrate backside is removed by the etching processing, a porous silicon oxide film 60 having at least 15μm of a thickness is formed by oxidizing the porous silicon layer 50 (S30). And P-type impurities are injected and diffused into the region of the P-well to be formed 70 (S40).
After the gate oxide film, gate material and dielectric layer are deposited, the gate 80 is formed by the lithography and the etching processing and the source and the drain 90, 100 are formed by lithography and ion implantation (S45).
And, a silicon nitride film 110 and a BPSG filml20 for polishing is deposited, the first dielectric layer 110, 120 including the silicon nitride film 110 and BPSG film 120 is formed by reflow processing, the first via holel30 is formed by lithography and etching (Hereinafter, the reference number of a via hole will be illustrated with an arrow in order to prevent confusion of the via hole and a plug).
After the first via hole 130 is filled with tungsten and so on (Ti TiN/W), the first plug 135 is formed by an etch back processing, the first pad 140 of an metal layer is formed by the deposition, lithography and etching of Ti/Al-Cu/TiN (S50).
The pad can be formed with signal line transmission. Hereinafter, the pad will be illustrated as including section view of circuit.
After this, the second dielectric layer 145 is formed by depositing the dielectric layer like PE-TEOS and so on, the second via hole 150 and the second plug 155 are formed by depositing the dielectric layer like PE-TEOS and so on.
And then, the second pad 160 and the first inductor layer 161 can be formed simultaneously by deposition, lithography and etching of Ti/Al-Cu/TiN (S60).
According to the present invention, the turn number is increased even in the small area to obtain high inductance and consequently improve the degree of integration in circuit by accumulating the inductor with several layers 220. Namely, the third dielectric layer 170 is formed by depositing the dielectric layer like PE-TEOS and so on and the third via hole 180 is formed by the lithography and etching. Then the third plug 185 is formed by the deposition of Ti/Al-Cu/TiN, the third pad 190 and the second inductor layer 192 can be formed simultaneously by the lithography and etching(S70).
After this, the fourth dielectric layer 200 is formed for the passivation, the fourth via hole 200 and the fourth plug 230 for the input/output are formed by the lithography and etching. And the fourth pad 240 for the input/output can be formed by the lithography and etching of Ti/Al-Cu/TiN. Also, if metal and silicon is contacted directly, a resistor becomes great and an adhesive strength becomes low due to movements between atoms on the contact surface. Therefore, an additional process to form metal silicide or barrier metal in the contact surface can be included.
Hereinafter, referring to FIG. 2a to FIG. 2k, each step will be explained in great detail. According to the present invention, it is noted that the N- and P-well have the sufficient Implanting concentration and diffusion depth not to make the anodizing reaction because the porous silicon layer is formed without mask pattern, in the step of injecting and diffusing N-type impurities into the region of N- and P-well to be formed (S10).
Namely, it has the sufficient Implanting concentration and diffusion depth more than 1012/cπ not to make the anodizing reaction in the step for forming the porous silicon layer (S20) to prevent the anodizing reaction on the surface and the lower part thereof corresponding to the region of N- and P-well to be formed.
According to embodiment of the present invention, it is necessary to perform the diffusion processing at more than 900 "C for the activation of injected ions. Under the processing condition, the step of forming the porous silicon layer (S20) can be performed without an additional mask layer on the region of N- and P-well to be formed.
Also, according to one embodiment of the present invention, an aluminium film can be used as the electrode material 40 for the anodizing reaction. The aluminium film can be generally deposited by PVD (Physical Vapor Deposition) method. According to the one embodiment of the anodizing reaction in the present invention, the porous silicon is formed by the depth of lμm per minute when the metal electrode is formed by about 1000 A on the backside of the silicon substrate, and immersed into reaction solution, and then bias is provided and current is supplied.
And then, the step for forming the porous silicon oxide film (S30) can be performed without additional mask pattern as well. While all of the porous silicon layer 50 is oxidized and changed to porous silicon oxide film 60, thin oxide film can be formed on the surface of the silicon crystal 20, 30 because there is great difference between the porous silicon layer 50 and the silicon crystal 20, 30 in the velocity of oxidation
By removing the mask processing by the above mentioned method, the processing for manufacturing the semiconductor device according to the present invention can be lessened and high productivity can be obtained.
According to the one embodiment of the present invention, the step for forming the porous silicon oxide film S30 is performed under the condition of steam atmosphere and less than 850 °C in order to relieve the stress of the silicon substrate. More specifically, the oxidation reaction is carried for 30 minutes at 350 °C to produce a thin oxide film with the depth of about 700 A , the oxidation reaction is carried for 30 minutes at 850 "C to give a porous silicon oxide film with the depth of more than 15 m.
In the prior art, the oxidation processing is carried at a temperature of 900 to 1000 °C, the oxidation reaction in this high temperature is a main cause for the stress of the substrate. Therefore, trench and additional process need to be carried in the prior art to relive the stress. However the present invention can eliminate the stress by employing a simple and efficient CMOS processing.
According to the above mentioned FIG. 1 to FIG. 2k, the inductor pattern is formed on the second dielectric layer. However, it is possible to form the inductor pattern in the first dielectric layer for high the degree of integration,
FIG. 3 is a flowchart showing a method for integrating high frequency semiconductor device including a CMOS and an inductor according to the another preferred embodiment of the present invention and FIG. 4a to FIG. 4k are sectional views of the semiconductor device corresponding to each step in the flowchart of FIG3.
Hereinafter, referring to FIG. 3 and FIG. 4a to FIG. 4k, the method for integrating inductor in the CMOS high frequency integrated circuit will be explained.
Referring FIG. 3, in order to integrate the inductor in the CMOS high frequency integrated circuit according to the present invention, the silicon nitride film is deposited on the silicon substrate 310 doped with P-type impurities, first of all (S110).
Then, the region of N- and P-well to be formed is defined on the silicon nitride film by lithography and a silicon nitride film mask pattern 320 can be formed by etching the silicon nitride film (S120).
According to the one embodiment of the present invention, it is preferable for the silicon nitride film mask pattern to have sufficient margin in size of the mask in comparison with the size of N- and P-well region, considering the isotropy in the anodizing processing
(S130) in the step for forming the silicon nitride film mask pattern (S120).
And then, the electrode material 340 is deposited on the backside of the silicon substrate and a porous silicon layer 350 is formed by the anodizing reaction on exposed part and adjacent part of the silicon substrate surface (S130).
After the porous silicon layer 350 is formed, an electrode material 340 is removed by the etching processing. Then, a porous silicon oxide film 60 with a thickness of at least 15μm is formed by oxidizing the porous silicon layer 350 (S140) and the silicon nitride film mask pattern 320 is removed (S145). After this, the region 370 of P-well to be formed is defined by lithography and P-type impurities are injected and diffused into the region. Then the region 372 of N-well to be formed is defined by lithography and N-type impurities are injected and diffused into the region
(S150).
After the gate oxide film, the gate material and dielectric layer are deposited. The gate 380 is formed by the lithography processing and etching processing, the source and the drain
390, 400 are formed by the lithography and Implanting processing (S155).
A silicon nitride film 410 and a BPSG film 420 for polishing are deposited, the first dielectric layer 410, 420 including the silicon nitride film 410 and BPSG film 420 is formed by the reflow processing, the first via hole 430 is formed by the lithography and etching processing. Then, the first via hole 430 is filled with tungsten and so on (Ti/TiN/W), the first plug 435 is formed by an etch back processing, the first pad 440 of an metal layer is formed by deposition, lithography and etching of Ti/Al-Cu/TiN (S160).
The second dielectric layer 445 is formed by the deposition of the dielectric layer like PE-TEOS etc on the first dielectric layer, and further, the second via hole 450 and the second plug 455 are formed by the lithography and etching. Then, the second pad 460 and the first inductor layer 461 can be formed by the deposition, lithography and etching of Ti/Al-Cu/TiN .
After the third dielectric layer 470 is formed by the deposition of the dielectric layer like PE-TEOS and so on, the third via hole 480 and the third plug 485 are formed by the lithography and etching processing, and the third pad 490 and the second inductor layer 492 can be formed by the deposition, lithography and etching of Ti/Al-Cu/TiN .
As mentioned above, the turn number is increased even in the small area to obtain high inductance and consequently improve the degree of integration in circuit by accumulating the inductor with several layers 520.
Hereinafter, the processing for forming the fourth dielectric layer (passivation), plug and pad for the input/output will be omitted because it is same to FIG. 1.
FIG. 5a to FIG. 5d are sectional views of a semiconductor device including a CMOS and a capacitance device according to the one preferred embodiment of the present invention.
For the description of the present invention, the processing is same or similar to the method for manufacturing the semiconductor device including the CMOS and inductance device and the above mentioned in FIG. 1 to FIG. 4k will be omitted.
The processing is same to the step for forming the first plug in the first dielectric layer 135, forming the first pad 140 of the metal layer by the deposition, lithography and etching of Ti/Al-Cu TiN (S50) or the step for forming the first pad 440 of the metal layer on the first plug 435 in the first dielectric layer by the deposition of Ti/Al-Cu/TiN, the lithography and etching.
Hereinafter, referring to FIG. 5a to FIG. 5d, method for integrating a device including CMOS and capacitance device will be explained.
The first pad 140, 440 and the capacitor 510 can be formed simultaneously (S60).
The capacitor 510 is formed as follows. A lower electrode 505 is formed and a dielectric layer (503) is formed on the lower electrode. The dielectric layer 503 is about 500 A of a thickness and is composed of silicon nitride. And then an upper electrode 500 is formed on the dielectric layer, The second dielectric layer can be formed on the first dielectric layer to cover the first pad 140, 440 and the capacitor thoroughly.
The second dielectric layer 545 is formed by the deposition of the dielectric layer like PE-TEOS and so on, the second via hole 550 and the second plug 555 are formed by the deposition of the dielectric layer, the second pads 560 can be formed simultaneously by the deposition, lithography and etching of Ti/Al-Cu/TiN.
The fourth dielectric layer 570 is formed for the passivation, the fourth via hole 580 and the fourth plug 590 for the input/output are formed by the lithography and etching. And the fourth pad 595 for the input/output can be formed by the lithography and etching of Ti/Al- Cu/TiN.
Other processing will be omitted because it is same to the step explained in FIG. 1 to FIG. 4k.
FIG. 6a to FIG. 6e are sectional views of the semiconductor device including CMOS and resistance device according to the one preferred embodiment of the present invention.
For the description of the present invention, the processing is same or similar to the method for manufacturing the semiconductor device including the CMOS and inductance device and thus, the description in FIG. 1 to FIG. 4k will be omitted. The method for integrating device including CMOS and resistance device is same upto the step for forming the gate 380 by the lithography and etching processing by depositing the gate oxide film, the gate material and the dielectric layer, forming the gate 80 by the lithography and etching processing as mentioned in FIG. 1, and depositing the gate oxide film, the gate material and the dielectric layer as mentioned in FIG. 3. After this process, a resistance conductor is selectively formed on the porous silicon oxide film and the resistance conductor can be comprised of poly silicon.
The source and the drain 600, 605 are formed by the lithography and ion Implantation.
A silicon nitride film 610 and BPSG film 620 for polishing are deposited, and the first dielectric layer 110, 120 including the silicon nitride film 610 and the BPSG film 620 is formed by the reflow processing. Then, the first via hole 630 is formed by the lithography and etching processing, the first via hole 630 is filled with tungsten and so on (Ti/TiN/W) and the first plug 635 is formed by an etch back processing. And then, the first pad 640 of a metal layer is formed by the deposition, lithography and etching of Ti/Al-Cu/TiN on the first plug 635.
The second dielectric layer 645 is formed by the deposition of the dielectric layer like PE-TEOS and so on, the second via hole 650 and the second plug 655 are formed by the deposition of the dielectric layer, the second pads 660 can be formed simultaneously by the deposition, lithography and etching of Ti/Al-Cu/TiN.
The fourth dielectric layer 670 is formed for the passivation, the fourth via hole 680 and the fourth plug 690 for the input/output are formed by the lithography and etching . And the fourth pad 695 for the input/output can be formed by the lithography and etching of Ti/Al- Cu/TiN.
Other processing will be omitted because it is same to the step explained in FIG. 1 to FIG. 4k.
FIG. 7a and FIG. 7b are flowcharts showing sectional view of the semiconductor device including CMOS and inductor, capacitor and resistance device according to the one preferred embodiment of the present invention.
Referring to FIG. 7a and FIG. 7b, the CMOS is integrated into a plurality of passive devices . It is natural for the present invention not to be limited to the embodiment of the passive device illustrated in FIG. 7a and FIG. 7b and various modification and adjustment of a passive device will be apparent by the manufacturing method according to the present invention. Namely, one of each resistor, inductor and capacitor is integrated in the drawing, a plurality of resistors, capacitors or inductors can be coupled and integrated variously.
The section view illustrated in FIG. 7a and FIG. 7b shows a manufacturing method for coupling the processing illustrated in FIG. 1 to FIG. 6e. Since the manufacturing processing of the device is explained in FIG. 1 to FIG. 6e, further explanation will be omitted.
Although the semiconductor device and method for manufacturing the same according to the present invention has been described in terms of various embodiments, it is not intended that the invention be limited to these embodiments. Modification within the spirit of the invention will be apparent to those experienced in giving or receiving counseling.
Industrial Applicability
As mentioned above, the present invention can provide a method for integrating a semiconductor device and a passive device in the semiconductor device. Namely, when a high frequency integrated circuit is implemented by CMOS processing, the present invention can provide a simple and efficient processing method in consideration of compatibility between a passive device processing and CMOS processing.
Also, the present invention can provide a method for integrating efficiently a passive device like inductor on the porous silicon oxide film and the device manufactured by the method with maintenance of high compatibility with the process for manufacturing CMOS integrated circuit,
Also, the present invention can provide a CMOS high frequency integrated circuit with high productivity by simplifying the processing steps.
Also, the present invention can increase the reliability of the CMOS high frequency integrated circuit by providing the processing condition to lessen the stress of substrate when the porous silicon oxide film is formed.
Although the present invention has been described in terms of various embodiments, it is not intended that the invention be limited to these embodiments and is defined by the claims and their full scope of equivalents.

Claims

Claims
1. A high frequency semiconductor device comprising: a porous silicon substrate; a first and a second conductive well selectively formed on the porous silicon substrate; a porous silicon oxide film having a thickness of more than 15 ffli which is selectively formed on the region in which the first and the second conductive well is not formed on the porous silicon substrate; a source, a drain and a gate formed on the first and the second conductive well, respectively; a first dielectric layer formed on the porous silicon oxide film to cover the source, the gate, the drain thoroughly in which a first plug is formed on the source and the drain; and a plurality of a first pads formed on the first plug.
2. The high frequency semiconductor device of claim 1, wherein said porous silicon oxide film comprises; a first oxide film having a thickness of 700 A formed at 350 °C ; and a second oxide film formed at 850 "C.
3. The high frequency semiconductor device of claim 1, wherein said plug and said pad are comprised of at least one selected from the group consisting of Ti, W and AL.
4. The high frequency semiconductor device of claim 1, wherein a contact surface between said source and drain and said plug further comprises one selected from a metal silicide layer and a barrier metal layer.
5. The high frequency semiconductor device of any one of claim 1 to claim 4, further comprising an inductor layer selectively formed on the first dielectric layer.
6. The high frequency semiconductor device of claim 5, wherein said inductor layer is comprised of a plurality of layers.
7. The high frequency semiconductor device of any one of claim 1 to claim 4, further comprising a capacitor selectively formed on the first dielectric layer.
8. The high frequency semiconductor device of claim 7, wherein an dielectric of the capacitor is silicon nitride.
9. The high frequency semiconductor device of any one of claim 1 to claim 4, further comprising a resistance conductor selectively formed on the porous silicon oxide film.
10. The high frequency semiconductor device of claim 9, wherein said resistance conductor is poly silicon.
11. A method for manufacturing the high frequency semiconductor device, the method comprising the steps of: forming a first and a second conductive well selectively on a silicon substrate doped uniformly by the first the impurity; injecting and diffusing a second the impurity into the first and the second conductive well; forming a porous silicon layer selectively on the silicon substrate in which the first and the second conductive wells are not formed; forming a porous silicon oxide film having a thickness of more than 15 m by oxidation of the porous silicon layer; forming a source, a drain and a gate in the first and the second conductive well, repectively; forming a first dielectric layer on the porous silicon oxide film to cover the source, the drain and the gate thoroughly; forming a first via hole in the region corresponding to the source and the drain of the first dielectric layer and forming a first plug on the first via hole; and forming a first pad on the first plug.
12. The method of claim 11, wherein said step for forming the porous silicon layer and said step for forming the porous silicon oxide film comprise the steps of: Implanting ions with more than 1012/cnf; and activating injected ions at a temperature of more than 900 °C .
13. The method of claim 11, wherein said step for forming the porous silicon layer and said step for forming the porous silicon oxide film is performed on the region in which the first and the second conductive well is formed without the formation of mask pattern.
14. The method of claim 11, wherein said oxidation of the porous silicon layer comprises the steps of: forming a first oxide film having a thickness of 700 A at 350 °C ; and forming a second oxide film at 850 °C .
15. The method of any one of claim 11 to claim 14, further comprising the step of: forming a first inductor pattern on the first dielectric layer
16. The method of claim 11, at least one inductor pattern is formed on said first inductor pattern.
17. The method of any one of claim 11 to claim 14, further comprising the steps of: forming an lower electrode on the first dielectric layer; forming a dielectric on the upper electrode; and forming an upper electrode on the a dielectric
18. The method of any one of claim 11 to claim 14, further comprising the steps of: forming a resistance conductor on the porous silicon oxide film; forming a first resistance plug on the resistance conductor; and forming a first resistance pad on the first resistance plug.
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