WO2004015868A1

WO2004015868A1 - Calibration technique for locked loop circuit leakage current

Info

Publication number: WO2004015868A1
Application number: PCT/US2003/024093
Authority: WO
Inventors: Claude R. Gauthier; Pradeep Trivedi; Brian W. Amick; Dean Liu
Original assignee: Sun Microsystems, Inc.
Priority date: 2002-08-13
Filing date: 2003-08-01
Publication date: 2004-02-19
Also published as: AU2003265339A1

Abstract

A method and apparatus for post-fabrication calibration and adjustment of a locked loop circuit leakage current is provided. The calibration and adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the locked loop circuit. Such control of the leakage current in the locked loop circuit allows a designer to achieve a desired locked loop circuit operating characteristic after the locked loop circuit has been fabricated A representative value of the amount of compensation desired in the leakage current may be stored and subsequently read to adjust the locked loop circuit.

Description

CALIBRATION TECHNIQUE FOR LOCKED LOOP CIRCUIT

LEAKAGE CURRENT

Background of Invention

[0001] As shown in Figure 1, a typical computer system 10 has, among other components, a microprocessor 12, one or more forms of memory 14, integrated circuits 16 having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths 19, e.g., wires, buses, etc., to accomplish the various tasks of the computer system 10.

[0002] In order to properly accomplish such tasks, the computer system 10 relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator 18 generates a system clock signal (referred to and known in the art as "reference clock" and shown in Figure 1 as SYS_CLK) to various parts of the computer system 10. Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock signal, and thus, it becomes important to ensure that operations involving the microprocessor 12 and the other components of the computer system 10 use a proper and accurate reference of time.

[0003] One component used within the computer system 10 to ensure a proper reference of time among the system clock signal and a microprocessor clock signal, i.e., "chip clock signal" or CHIP CLK, is a type of clock generator locked loop circuit known as a phase locked loop (PLL) 20. The PLL 20 is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to the system clock signal. Referring to Figure 1, the PLL 20 has as its input the system clock signal, which is its reference signal, and outputs a chip clock signal (shown in Figure 1 as CHLP_CLK) to the microprocessor 12. The system clock signal and chip clock signal have a specific phase and frequency relationship controlled by the PLL 20. This relationship between the phases and frequencies of the system clock signal and chip clock signal ensures that the various components within the microprocessor 12 use a controlled and accounted for reference of time. When this relationship is not maintained by the PLL 20, however, the operations within the computer system 10 become non-deterministic.

[0004] Figure 2 shows a block diagram of a typical PLL 200. The PLL 200 includes a PLL core 250, buffers 212, 214, 216, 218, and a feedback loop signal 221 on a feedback loop path. The buffers 212, 214 increase the drive strength of an output clock signal 215 to supply other circuits of the microprocessor (12 in Figure 1) with a chip clock signal 217. The buffers 216, 218 buffer the chip clock signal 217 to additional circuits of the microprocessor (12 in Figure 1). The time delay created by the buffers 212, 214, 216, 218 is accounted for in the feedback signal 221 that is supplied to the PLL core 250.

[0005] The PLL core 250 is designed to output the chip clock signal 217, which is a multiple of the system clock signal 201. When the PLL is in "lock," the chip clock signal 217 and system clock signal 201 maintain a specific phase relationship. To allow different multiplication ratios, the PLL core 250 may use several "divide by" circuits. A "divide by" circuit reduces the frequency of the input to the "divide by" circuit at its output by a specified factor. For example, the PLL core 250 uses a divide by A circuit 220 with the system clock signal 201, a divide by C circuit 222 with a voltage-controlled oscillator 210 output signal 213, and a divide by B circuit 224 with the feedback loop signal 221.

[0006] A phase-frequency detector 202 aligns the transition edge and frequency of a clock A signal 221 and a clock B signal 223. The phase-frequency detector 202 adjusts its output frequency in order to zero any phase and frequency difference between the clock A signal 221 and the clock B signal 223. The phase-frequency detector 202 produces signals that control charge pumps 204, 234. The phase-frequency detector 202 controls the charge pumps 204, 234 to increase or decrease their output using control signals up, U 203, and down, D 205. The charge pump 204 adds or removes charge from a capacitor 206 that changes the voltage potential at the input of a bias- generator 208. The capacitor 206 is connected between a power supply N_DD and a control voltage V_CTRL 207. The charge pump 234 adds or removes charge from a bias voltage N_Bp 209 of a bias-generator 208.

[0007] The bias-generator 208 produces bias voltages N_Bp 209 and V_BΝ 211 in response to the control voltage 207. The PLL core 250 may be self-biased by adding the charge pump 234 to the bias-generator 208 bias voltage N_Bp 209. The addition of a second charge pump 234 allows the removal of a resistor in series with the capacitor 206. A voltage-controlled oscillator 210 produces an output signal 213 that has a frequency related to the bias voltages N_Bp 209 and VB_Ν 211.

[0008] The "divide by" circuits 220, 222, 224 determine the frequency multiplication factor provided by the PLL core 250. The addition of "divide by" circuits 220, 222, 224 enables the PLL core 250 to multiply the system clock signal 201. Multiplying the system clock signal 201 is useful when the chip clock signal 217 must have a higher frequency than the system clock signal 201.

[0009] For example, during normal operation, the variables A and C may both be set to one in the divide by A circuit 220 and divide by C circuit 222, respectively. The variable B may be set to 10 in the divide by B circuit 224. The phase-frequency detector 202 aligns the transition edge and frequency of the clock A signal 221 and the clock B signal 223. The phase-frequency detector 202 adjusts PLL core 250 output clock signal 215 frequency in order to zero any phase and frequency difference between the clock A signal 221 and the clock B signal 223. Because the clock B signal 223 has a divide by B circuit 224 that reduces its input frequency by 10, the phase-frequency detector 202 adjusts the voltage-controlled oscillator 210 output signal 213 to a frequency 10 times greater than the clock A signal 221. Accordingly, the chip clock signal 217 is 10 times higher in frequency than the system clock signal 201.

[0010] The power consumption of a microprocessor is of concern. Reducing the frequency of the chip clock signal 217 reduces the switching rate of other circuits in the microprocessor (12 in Figure 1). A low power mode may be entered when there is no activity in the microprocessor for an extended period of time. A slower switching rate typically reduces the power consumption of a microprocessor (12 in Figure 1).

[0011] A change in the frequency of the chip clock signal 217 is accomplished by changing the ratio in the divide by circuits 220, 222, 224. For example, during reduced power operation, the variable A may be set to 16 in the divide by A circuit 220; the variable B may be set to 5 in the divide by B circuit 224; and the variable C may be set to 32 in the divide by C circuit 222. In this example, the frequency of the chip clock signal 217 is 5/16 times the system clock signal 201. Also, the phase-frequency detector 202 updates 16 times less frequently compared to the non-reduced power example above.

[0012] Proper operation of the microprocessor (12 shown in Figure 1) depends on the PLL 200 maintaining a constant phase and frequency relationship between the system clock signal 201 and the chip clock signal 217.

[0013] As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, a clock signal is often sent to help recover the data. The clock signal determines when the data should be sampled or latched by a receiver circuit.

[0014] The clock signal may transition at the beginning of the time the data is valid. The receiver circuit, however, may require that the clock signal transition during the middle of the time the data is valid. Also, the transmission of the clock signal may degrade as it travels from its transmission point. In both circumstances, a type of locked loop circuit known as a delay locked loop, or "DLL," can regenerate a copy of the clock signal at a fixed phase shift with respect to the original clock signal.

[0015] Figure 3 shows a section of a typical computer system component 1100.

Data 1014 that is K bits wide is transmitted from circuit A 1012 to circuit B 1034 (also referred to as the "receiver circuit"). To aid in the recovery of the transmitted data, a clock signal 1016 is also transmitted with the data 1014. The circuits could also have a path to transmit data from circuit B 1034 to circuit A 1012 along with an additional clock (not shown). The clock signal 1016 may transition from one state to another at the beginning of the data transmission. Circuit B 1034 requires a clock signal temporally located some time after the beginning of the valid data. Furthermore, the clock signal 1016 may have degraded during transmission. The DLL has the ability to regenerate the clock signal 1016 to a valid state and to create a phase shifted version of the clock signal 1016 to be used by other circuits. For example, the receiver circuit 1034 may use the phase shifted version of the clock signal 1016 as the receiver circuit's sampling signal. The receiver circuit's sampling signal determines when the input to the receiver circuit should be sampled. The performance of a DLL is critical, and the DLL must maintain a proper reference of time on the CPU, or generically, an integrated circuit.

[0016] Figure 4 shows a block diagram of a typical DLL 1200. Clock signal

1201 is input to the DLL 1200 to create a phased (i.e., delayed) output. Clock signal 1201 is input to a voltage-controlled delay line 1210 and to a phase detector 1202. The phase detector 1202 measures whether a phase difference between the clock signal 1201 and an output signal, clk_out 1217, of the voltage-controlled delay line 1210 has the desired amount of delay. The phase detector 1202 produces signals that control a charge pump 1204. The phase detector 1202 controls the charge pump 1204 to increase or decrease its output current using up and down signals, U 1203 and D 1205. To ensure that the charge pump 1204 maintains some nominal current output, the charge pump 1204 is internally biased. The internal biasing of the charge pump 1204 is dependent on bias signals, N_BP 1209 and N_BΝ 1211, generated from a bias generator 1208 (discussed below). The up and down signals 1203, 1205 adjust the current output of the charge pump 1204 with respect to the nominal current set by the bias signals 1209, 1211.

[0017] The charge pump 1204 adds or removes charge from a capacitor

1206, which in turn, changes a voltage potential at the input of the bias- generator 1208. The capacitor 1206 is connected between a power supply, V_DD> and a control signal, V_CTRL 1207. The bias-generator 1208 produces the bias signals 1209, 1211 in response to the control signal 1207, which, in turn, controls the delay of the voltage-controlled delay line 1210 and maintains a nominal current output from the charge pump 1204.

[0018] In Figure 4, the voltage-controlled delay line 1210 may be implemented using current starved elements. This means that the delays are controlled by modifying the amount of current available for charging and discharging capacitances. The linearity of a voltage controlled delay line's characteristics determines the stable range of frequencies over which the DLL 1200 can operate. The output signal 1217 of the voltage-controlled delay line 1210 represents a phase delayed copy of clock signal 1201 that is then used by other circuits.

[0019] Still referring to Figure 4, the negative feedback created by the output signal 1217 in the DLL 1200 adjusts the delay through the voltage-controlled delay line 1210. The phase detector 1202 integrates the phase error that results between the clock signal 1201 and the output signal 1217. The voltage- controlled delay line 1210 delays the output signal 1217 by a fixed amount of time such that a desired delay between the clock signal 1201 and the output signal 1217 is maintained. [0020] Accordingly, proper operation of the receiver circuit (1034 in Figure 3) depends on the DLL 1200 maintaining a constant phase delay between the clock signal 1201 and the output signal 1217.

Summary of Invention

[0021] According to one aspect of one or more embodiments of the present invention, an integrated circuit comprises: a clock path arranged to carry a clock signal; a power supply path arranged to receive power from a power supply; a locked loop circuit, operatively connected to the power supply path and the clock path, comprising: a detector arranged to detect at least one of a phase difference and a frequency difference between the clock signal and an output clock signal, a charge pump, responsive to the detector, arranged to output a current on a control signal path, and a capacitor, responsive to the current, arranged to store a voltage potential; a storage device arranged to store control information; and a leakage current offset circuit operatively connected to the capacitor and the storage device, where the leakage current offset circuit arranged to adjust the voltage potential dependent on the control information.

[0022] According to another aspect of one or more embodiments of the present invention, a method for post-fabrication treatment of a locked loop circuit comprises generating an output clock signal, comparing the output clock signal and input clock signal, generating a current dependent on the comparing, storing a voltage potential on a capacitor dependent on the current, selectively adjusting a leakage current of the capacitor using a leakage current offset circuit responsive to an adjustment circuit, and storing control information determined from the selectively adjusting.

[0023] According to another aspect of one or more embodiments of the present invention, an integrated circuit comprises means for generating a signal, means for comparing the signal and a clock signal, means for generating a current dependent on the means for comparing, means for storing a charge dependent on the means for generating, means for selectively adjusting a leakage current of the means for storing the charge, and means for storing control information dependent on the means for selectively adjusting.

[0024] Other aspects and advantages of the invention will be apparent from the following description and the appended claims.

Brief Description of Drawings

[0025] Figure 1 shows a typical computer system.

[0026] Figure 2 shows a block diagram of a typical locked loop circuit.

[0027] Figure 3 shows a typical computer system component.

[0028] Figure 4 shows a block diagram of a typical locked loop circuit.

[0029] Figure 5 shows a block diagram of a typical phase-frequency detector.

[0030] Figure 6 shows a block diagram of a typical charge pump.

[0031] Figure 7 shows a timing diagram for the phase-frequency detector shown in Figure 5.

[0032] Figure 8 shows a block diagram of a phase locked loop with an adjustable leakage current offset circuit and a storage device in accordance with an embodiment of the present invention.

[0033] Figure 9 shows a block diagram of a delay locked loop with an adjustable leakage current offset circuit and a storage device in accordance with an embodiment of the present invention.

[0034] Figure 10 shows an adjustment circuit in accordance with an embodiment of the present invention.

[0035] Figure 11 shows an storage device in accordance with an a embodiment of the present invention.

[0036] Figure 12 shows a timing diagram for the storage device shown in Figure 11.

[0037] Figure 13 shows a flow diagram in accordance with an embodiment of the present invention.

Detailed Description

[0038] The present invention relates to an adjustment and calibration system for post-fabrication adjustment of a locked loop circuit (e.g., a phase locked loop or a delay locked loop). In Figure 2, the PLL 200 determines the phase and frequency relationship between the system clock signal 201 and the chip clock signal 217 based on a voltage potential maintained by the capacitor 206. Similarly, in Figure 4, the DLL 1200 determines the amount of delay of the voltage-controlled delay line 1210 based on a voltage potential maintained by the capacitor 1206. With respect to both the PLL (200 in Figure 2) and DLL (1200 in Figure 4), charge may leak from the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4), which, in turn, changes the stored voltage potential on the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4). Accordingly, the frequency of a voltage-controlled oscillator (210 in Figure 2) in a PLL or the delay of a voltage-controlled delay line (1210 in Figure 4) in a DLL may drift. The adjustment and calibration system includes an adjustment circuit that can compensate for such a leakage current. Thus, the leakage current of the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) may be offset so that the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) maintains a constant voltage potential. The amount of leakage current offset is stored so that the post-fabrication adjustment of a locked loop circuit is maintained after calibration.

[0039] Figure 5 shows a block diagram of a typical phase-frequency detector

300. The phase-frequency detector 300 is representative of the phase- frequency detector shown in Figures 2 and 4. The phase-frequency detector 300 integrates the phase error that results between the clock A signal 221 and the clock B signal 223. The clock A signal 221 clocks a flip-flop 306 and the clock B signal 223 clocks a flip-flop 308.

[0040] When clock A signal 221 transitions from a low state to a high state, flip-flop 306 transfers the high state created by the power supply N_DD 351 on an input of the flip-flop 306 to the up signal 203. When the clock B signal 223 transitions from a low state to a high state, flip-flop 308 transfers the high state created by the power supply V_DD 351 on an input of the flip-flop 308 to the down signal 205. When both the up and down signals 203, 205 are at a high state, the AND gate 303 outputs a high state on signal line 307. The high state on signal line 307 resets both flip-flop 306 and flip-flop 308. The up and down signals 203, 205 transition to a low state when the flip-flop 306 and flip-flop 308 are reset, respectively.

[0041] Figure 6 shows a block diagram of a typical charge pump 400. The charge pump 400 is representative of the charge pumps shown in Figures 2 and 4. The charge pump 400 has two current sources 402, 408. The current source 402 is connected between the power supply N_DD 401 and the signal line 403. The current source 408 is connected between the power supply N_Ss 407 and the signal line 405.

[0042] In Figure 6, the up and down signals 203, 205 from the phase-frequency detector 300 shown in Figure 5 determine whether switches 404, 406 are closed, respectively. When the up signal 203 is at a high state, the switch 404 is closed. The switch 404 is connected between signal 403 and the control voltage 207. When closed, the switch 404 allows the current generated by the current source 402 to add charge to the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) using the control voltage 207.

[0043] When the down signal 205 is at a high state, the switch 406 is closed.

The switch 406 is connected between signal 405 and the control voltage (207 in Figure 2 and 1207 in Figure 4). When closed, the switch 406 allows the current generated by the current source 408 to remove charge from the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) using the control voltage (207 in Figure 2 and 1207 in Figure 4).

[0044] A short time period exists when both the up and down signals 203, 205 are at a high state. In Figure 5, when both the up and down signals 203, 205 transition to a high state, the AND gate 303 resets the flip-flops 306, 308 by generating a high state on the signal line 307. A finite time duration is needed for the AND gate 303 and the flip-flops 306, 308 to respond to this change in state. In Figure 6, both the switches 404, 406 are closed when both the up and down signals 203, 205 signals are high. During this time, a nominal amount of charge is added to the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4). Some or all of the current generated by the current source 402 is transferred to the Nss power supply 407 through the current source 408.

[0045] Figure 7 shows a timing diagram 500 for the phase-frequency detector

300 shown in Figure 5. The timing diagram 500 shows two clock cycles. The first clock cycle shows the clock B signal 223 lagging the clock A signal 221 (i.e., they are out of phase). The second cycle shows the clock B signal 223 properly aligned with the clock A signal 221.

[0046] In the first cycle, when the clock A signal 221 transitions from a low state to a high state, the up signal 203 transitions from a low state to a high state. When the clock B signal 223 transitions from a low State to a high state, the down signal 205 transitions from a low state to a high state. Because both the up and down signals 203, 205 are at a high state, the AND gate (303 shown in Figure 5) resets both flip-flops (306, 308 shown in Figure 5). The up and down signals 203, 205 output a low state when the flip-flops (306, 308 shown in Figure 5) are reset, respectively.

[0047] In the first cycle, the up signal 203 is at a high state for a longer duration than the down signal 205. Accordingly, the current source (402 shown in Figure 6) adds charge to the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4). If the down signal 205 was at a high state for a longer duration than the up signal 203, the current source (408 shown in Figure 6) would remove charge from the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4). The change in the voltage potential maintained by the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) affects the frequency of the voltage-controlled oscillator (210 shown in Figure 2) in a PLL or the delay of the voltage-controlled delay line (1210 shown in Figure 4) of a DLL.

[0048] In Figure 7, in the second cycle, both the clock A signal 221 and the clock B signal 223 transition from a low state to a high state at the same time. In other words, the clock A signal 201 and the clock B signal 223 are in phase. Accordingly, both the up and down signals 203, 205 transition from a low state to a high state at the same time. Also, both the flip-flops (306, 308 shown in Figure 5) are reset simultaneously. Because a finite time duration (i.e., t_MIN) is needed for the AND gate (303 shown in Figure 5) and the flip-flops (306, 308 shown in Figure 5) to respond to the change in state, both the up and down signals (203, 205) have a finite time duration for which they are high. A nominal amount of charge is added to the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) to maintain the present voltage potential on the control voltage (207 shown in Figure 2 and 1207 shown in Figure 4).

[0049] In Figure 7, the times during which the charge pump (400 shown in

Figure 6) may modify or maintain the charge on the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) are indicated. When the clock A signal 221 and the clock B signal 223 are aligned, the time duration that the charge pump (400 shown in Figure 6) is active is relatively small (i.e., t_MIN). During the time the charge pump (400 shown in Figure 4) is inactive (i.e., when both switches 404, 406 are open), the voltage potential on the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) may drift due to leakage currents inherent with devices used to form the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4). Furthermore, the time duration that the charge pump (400 shown in Figure 6) is inactive (i.e., when both switches 404, 406 are open) is increased during power reduction modes. As in the example above, the time duration between the charge pump (400 shown in Figure 6) activity is increased 16 times in a power reduction mode compared to normal operation. The voltage potential on the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) may drift a larger amount during the power reduction mode. A means to compensate for the drift and store the amount of compensation is needed.

[0050] Semiconductor capacitors are typically parallel plate capacitors formed by connecting the source and drain of a transistor together to create one terminal of the capacitor. The other terminal of the capacitor is formed by the gate connection of the transistor. Tunneling through the gate creates a path for leakage current. Leakage current causes the voltage potential originally stored on the capacitor to change. In a PLL, the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) helps maintain the amount of frequency produced by the voltage-controlled oscillator (210 shown in Figure 2) of a PLL or delay produced by the voltage-controlled delay line (1210 shown in Figure 4).

[0051] In Figures 2 and 4, the relatively long time durations between the charge pump updating the charge stored (i.e., voltage potential stored) on the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) may result in a drift in the expected amount of frequency of the PLL or delay of the DLL. Although a designer may intend for an integrated circuit to have a particular value for the leakage current of the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4), actual values for these parameters are typically unknown until the integrated circuit has been fabricated (i.e., in a post-fabrication stage).

[0052] For example, a designer may intend for the frequency drift of the PLL or delay drift of the DLL to be within in a particular range. The leakage current of the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) may be unintentionally affected by many factors in the fabrication process. Because the leakage current cannot be redesigned in the post-fabrication stage without considerable temporal and monetary expenditures, these fabrication factors may cause the locked loop circuit to have a different frequency or delay drift range than the range the locked loop circuit was designed. Consequently, the locked loop circuit may have poor performance. Accordingly, there is a need for a technique and design that facilitates increased post-fabrication control of leakage current in the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4) of a locked loop circuit. The amount of leakage current offset is stored so that the post-fabrication adjustment of the locked loop circuit is maintained after calibration.

[0053] Figure 8 shows an exemplary adjustable PLL 600 in accordance with an embodiment of the present invention. The phase-frequency detector 202, capacitor 206, bias-generator 208, and voltage-controlled oscillator 210 of the adjustable PLL 600 operate similar to those respective components described above with reference to Figure 2.

[0054] In Figure 8, a leakage current offset circuit 604 is connected between the control voltage 207 and a power supply N_ss. As the capacitor 206 leaks current, the voltage potential on the control voltage 207 has a tendency to drift toward the power supply N_DD. The leakage current offset circuit 604 is arranged to pull the voltage potential on the control voltage 207 toward a power supply N_Ss- For example, an n-channel transistor is used as the leakage current offset circuit 604.

[0055] One of ordinary skill in the art will appreciate that in other embodiments, the capacitor 206 may be connected between the control voltage 207 and the power supply N_ss. In this case, the leakage current offset circuit 604 is connected between the control voltage 207 and the power supply V_DD- A leakage current offset circuit 604 in this arrangement may be a p-channel transistor. [0056] Figure 9 shows an exemplary adjustable DLL 1600 in accordance with an embodiment of the present invention. The phase detector 1202, capacitor 1206, bias-generator 1208 and voltage-controlled delay line 1210 of the adjustable DLL 1600 operate similar to those respective components described above with reference to Figure 4.

[0057] In Figure 9, a leakage current offset circuit 1604 is connected between the control signal 1207 and a power supply N_ss. As the capacitor 1206 leaks current, the voltage potential on the control signal 1207 has a tendency to drift toward the power supply N_DD. The leakage current offset circuit 1604 is arranged to pull the voltage potential on the control signal 1207 toward a power supply Nss- For example, an n-channel transistor is used as the leakage current offset circuit 1604.

[0058] One of ordinary skill in the art will appreciate that in other embodiments, the capacitor 1206 may be connected between the control signal 1207 and the power supply N_Ss- In this case, the leakage current offset circuit 604 is connected between the control signal 1207 and the power supply V_DD- A leakage current offset circuit 1604 in this arrangement may be a p-channel transistor.

[0059] In Figures 8 and 9, an adjustment circuit 654 is used to adjust the leakage current offset circuit (604 in Figure 8 and 1604 in Figure 9) to compensate for the leakage current of the capacitor (e.g., 206 in Figure 8 and 1206 in Figure 9). A bias voltage potential, V_BIA_S 661, is used to control the amount of compensation applied to offset the leakage current. The bias voltage potential 661 may be adjusted to increase, decrease, turn off, or maintain the amount of leakage current compensation (i.e., leakage current offset) produced by the leakage current offset circuit 604.

[0060] In Figures 8 and 9, a test processor unit 652 controls the adjustment circuit 654 using multiple adjustment signals N 653. The values of the multiple adjustment signals N 653 are determined by the test processor unit 652. The test processor unit 652 may communicate through a host interface (not shown) using M communication lines 651. Those with ordinary skill in the art will appreciate that the host interface and M communication lines 651 may take a wide variety of forms. The communication may be defined by an industry standard.

[0061] The host interface (not shown) may be used to operatively connect to a separate computer system. For example, a tester 650 may communicate with the test processor unit 652. In some embodiments, the tester 650 may instruct the test processor unit 652 to adjust adjustment circuit 654 to modify a leakage current offset of the locked loop circuit. In some embodiments, the tester 650 may measure an operating characteristic of the adjustable locked loop circuit or a representative operating characteristic of an integrated circuit on which the adjustable locked loop circuit resides to determine the effect of the adjustment. A variety of different adjustments may be made in an effort to identify the adjustment settings that produce the desired operating characteristics of the adjustable locked loop circuit.

[0062] For example, the tester 650 may be used to adjust the adjustable locked loop circuit until the frequency drift in a voltage-controlled oscillator or delay drift of a voltage-controlled delay line is minimized. The tester 650 may also be used to adjust the adjustable locked loop circuit until the operating characteristics of the adjustable locked loop circuit reaches a desired performance level. The operating characteristics may include frequency drift, delay drift, maximum operating frequency, minimum operating frequency, minimum delay, lock time, etc.

[0063] A storage device 658 may be designed to store control information representative of the adjustment settings that produce the desired operating characteristics of the adjustable locked loop circuit. By using the tester 650, control information may be written into the storage device 658. The tester 650 may read or rewrite the control information in the storage device 658.

[0064] The storage device 658 may include multiple storage elements such that the control information may be represented by a binary word. For example, the control information stored in the storage device 658 may be a binary word that matches the values of the multiple adjustment signals N 653. Alternatively, the control information may be a binary encoded word. For example, if the multiple adjustment signals N 653 used eight adjustment signals, the control information might be represented with a three bit binary word. Alternatively, the control information may contain instructions, interpreted by the test processor unit 652, to control the multiple adjustment signals N 653.

[0065] In Figures 8 and 9, the tester 650 may be removed from the adjustable locked loop circuit. The test processor unit 652 may read the storage device 658 to obtain the control information and determine the amount of adjustment by the adjustment circuit 654. The adjustable locked loop circuit 600, after the test processor unit 652 reads the control information in the storage device 658 and adjusts the adjustment circuit 654, may have an operating characteristic similar to the operating characteristics obtained while connected to the tester 650. The test processor unit 652 reads the control information from storage device 658 using the L signal lines 663.

[0066] Those skilled in the art will appreciate that the adjustable locked loop circuit may be analog, digital, or a combination of both types of circuits.

[0067] Figure 10 shows an exemplary adjustment circuit 700 in accordance with an embodiment of the present invention. The adjustment circuit 700 includes multiple p-channel transistors 702, 706, 710 arranged in parallel with each other. The multiple p-channel transistors 702, 706, 710 connect between the power supply N_DD and a common node on which a bias voltage potential NBiAS 661 is supplied to the leakage current offset circuit (604 shown in Figure 8 and 1604 shown in Figure 9). The adjustment circuit 700 also includes multiple n-channel transistors 704, 708, 712 arranged in parallel with each other. The multiple n-channel transistors 704, 708, 712 connect between power supply Nss and the bias voltage potential 661.

[0068] Each transistor has an individual control signal that turns "on" or "off the respective p-channel transistors 702, 706, 710 and respective n-channel transistors 704, 708, 712. The p-channel transistors 702, 706, 710 have control signals EΝ_P₀ 701, EN_Pι 705, and EN_P_N 709 connected to their gates, respectively. The n-channel transistors 704, 708, 712 have control signals EN_N₀ 703, EN_N_! 707, and EN_N_N 711 connected to their gates, respectively. A "low" voltage potential on any of the EN_Pχ control signals 701, 705, 709, where "x" represents any index 0 through N, turns "on" the respective p-channel transistor 702, 706, 710. A "high" voltage potential on any of the EN_N control signals 703, 707, 711, where "x" represents any index 0 through N, turns "on" the respective n-channel transistor 704, 708, 712.

[0069] A p-channel transistor 702, 706, 710 that is "on" changes the bias voltage potential 661 toward power supply V_DD- An n-channel transistor 704, 708, 712 that is "on" changes the bias voltage potential 661 toward power supply Nss- By selecting which p-channel transistors 702, 706, 710 and/or n- channel transistors 704, 708, 712 are "on," a selected change in the bias voltage potential 661 may be achieved.

[0070] Those with ordinary skill in the art will appreciate that the p-channel transistors 702, 706, 710 and n-channel transistors 704, 708, 712) may be turned "on" individually or as a group. The p-channel transistors 702, 706, 710 and n-channel transistors 704, 708, 712 may be sized so that each transistor has a different effect compared to the other transistors. For example, a transistor's gate width may be varied to adjust the strength of each transistor. The gate widths of the p-channel transistors 702, 706, 710 and n-channel transistors 704, 708, 712 may be designed to provide a linear, exponential, or other function as more transistors are turned "on." In some embodiments, the p-channel transistors 702, 706, 710 and n-channel transistors 704, 708, 712 may be sized so that each transistor has a different resistance. For example, transistor gate lengths may be increased (i.e., long channel transistors) to increase the inherent resistance of each transistor. A larger inherent resistance may be advantageous if both a p-channel transistor and a n-channel transistor are "on" simultaneously. In one or more embodiments, the adjustment circuit 700 may include only one p-channel transistor (e.g., p-channel transistor 702) and one n- channel transistor (e.g., n-channel transistor 704) connected in series.

[0071] The adjustment circuit 700 in Figure 10 may be used as the adjustment circuit 654 shown in Figures 8 and 9. In Figures 8 and 9, the test processor unit 652 generates a binary control word that determines which n-channel transistors (704, 708, 712 shown in Figure 10) and p-channel transistors (702, 706, 710 shown in Figure 10) are "on" and which are "off in the adjustment circuit 654. Depending on the binary control word maintained by the test processor unit 652, multiple adjustment signals N 653 that represent EΝ_Ν_X signals (703, 707, 711 in Figure 10) and EN_P_X signals (701, 705, 709 in Figure 10) may turn "on" or turn "off the p-channel transistors (702, 706, 710 shown in Figure 10) and n-channel transistors (704, 708, 712 shown in Figure 10) in the adjustment circuit 654. The bias voltage potential 661 of the adjustment circuit 654 adjusts the leakage current offset circuit (604 in Figure 8 and 1604 in Figure 9).

[0072] Figure 11 shows an exemplary storage device 800 in accordance with an a embodiment of the present invention. The storage device 800 may be used for the storage device (658 shown in Figures 8 and 9). The storage device 800 includes electrically programmable fuses 804, 854 to store nonvolatile control information.

[0073] In Figure 11, multiple write signals such as write fuse 1 signal 801 through write fuse L signal 851 are used to program electrically programmable fuses 804, 854, respectively. A "high" voltage potential on the write fuse 1 signal 801 and write fuse L signal 851 causes n-channel transistors 802, 852 to turn "on," respectively. If n-channel transistors 802, 852 are "on" for a sufficient duration, the fuse 804 and fuse 854, respectively, create an "open" circuit. A precharge fuse signal 803 will pulse a "high" voltage potential on the gates of n-channel transistors 812, 862 to momentarily turn them "on." If n-channel transistors 812, 862 are "on," fuse out 1 signal 809 and fuse out L signal 859 will be pulled to a "low" voltage potential by n-channel transistors 812, 862. The "low" voltage potential on the fuse out 1 signal 809 and the fuse out L 859 will precharge the fuse out 1 signal 809 and the fuse out L signal 859 anticipation of a read operation.

[0074] In Figure 11, a "high" voltage potential on a read fuse signal 805 causes n-channel transistors 810, 860 to turn "on." If any of the fuses 804, 854 are intact (i.e., shorted), the fuse out 1 signal 809 and the fuse out L signal 859 are pulled to a "high" voltage potential. If any of the fuses 804, 854 are open, the fuse out 1 signal 809 and the fuse out L signal 859 remain at a "low" voltage potential. Sense amplifiers 806, 856 sense the voltage potential levels on the fuse out 1 signal 809 and the fuse out L signal 859, respectively, to amplify and maintain the voltage potential levels.

[0075] Figure 12 shows a timing diagram 900 related to the programming of the storage device (800 shown in Figure 11) in accordance with an embodiment of the present invention. In this example, the write fuse 1 signal 801 is pulsed to a "high" voltage potential to create an "open" on fuse 804. The write fuse L signal 851 remains at a "low" voltage potential to leave fuse 804 intact. Precharge fuse signal 803 signal pulses a "high" voltage potential to pull the fuse out 1 signal 809 and fuse out L signal 859 to a "low" voltage potential. The read fuse signal 805 pulses a "high" voltage potential to read the state of the fuses 804, 854. Because fuse 804 is "open," the fuse out 1 signal 809 remains at a "low" voltage potential. Because fuse 854 is intact or "shorted," the fuse outE signal 859 is pulled to a "high" voltage potential. [0076] Because the fuses 804, 854 have been programmed and read, the fuse out 1 signal 809 and the fuse out L signal 859 maintain the programmed control information. The state of the fuses 804, 854 may be read at any time by observing the voltage potential level on the fuse out 1 signal 809 and the fuse out L signal 859. Also, the state of the fuses 804, 854 may be read by repeating the precharge and read cycles. Using multiple fuses and related circuitry, a binary word may represent the stored control information.

[0077] One of ordinary skill in the art will appreciate that the electrically programmable fuses are but one method to store information. In other embodiments, the storage device (658 in Figures 8 and 9) may contain a wide variety of types of storage elements including, but not limited to, an electrically programmable fuse, an electrically programmable read only memory, an electrically erasable read only memory, a one time programmable memory, a flash memory, a laser programmable fuse, and a laser programmable anti-fuse.

[0078] Figure 13 shows a flow diagram in accordance with an embodiment of the present invention. At 982, an adjustment circuit value is selected. The selected adjustment value may be used to adjust adjustment circuit (654 shown in Figures 8 and 9). The adjustment circuit (654 shown in Figures 8 and 9) may create a bias voltage potential (661 shown in Figures 8 and 9) to adjust the leakage current offset circuit (604 shown in Figure 8 and 1604 in Figure 9). The adjustment of the amount of compensation of the leakage current modifies an operating characteristic of the adjustable locked loop circuit. Also, the performance of other circuits that rely on the adjustable locked loop circuit may be measured. At 984, the operating characteristics are measured.

[0079] At 986 a determination as to whether a desired operating characteristic(s) is obtained. The determination may be based on an operating characteristic(s) taken with the selected adjustment circuit value, or an interpolation or extrapolation from data obtained from selectively adjusting the adjustment circuit value. If the desired operating characteristic(s) has not been obtained, 982 and 984 are repeated until a desired operating characteristic(s) has been obtained. If the desired operating characteristic(s) has been obtained, the adjustment circuit value, or a representation of the value, is stored at 988. The desired adjustment circuit value or representation of the value is stored as control information in the storage device (658 in Figures 8 and 9). The storage device (658 in Figures 8 and 9) may contain control information that may be accessed and used to improve the performance of the adjustable PLL locked loop circuit after fabrication.

[0080] Advantages of the present invention may include one or more of the following. The adjustable locked loop circuit, having been fabricated, may demonstrate operating characteristics that may not have been apparent from simulation. In some embodiments, because the adjustment circuit (654 shown in Figures 8 and 9) may modify the operating characteristics of the locked loop circuit, the adjustable locked loop circuit may be calibrated.

[0081] In some embodiments, because the adjustable locked loop circuit may be fabricated with a means for compensating the leakage current of the capacitor (e.g., 206 in Figure 2 and 1206 in Figure 4), fewer design iterations and higher confidence in the adjustable locked loop circuit operating characteristics may be afforded.

[0082] In some embodiments, the tester (650 shown in Figures 8 and 9) and test processor unit (652 shown in Figures 8 and 9) may communicate so that the state of the adjustable locked loop circuit may be obtained, performance characteristics analyzed, and/or adjustments made to the adjustable locked loop circuit. By using the tester (650 shown in Figures 8 and 9), control information may be stored in a storage device (658 shown in Figures 8 and 9).

[0083] In some embodiments, the tester (650 shown in Figures 8 and 9) may take a relatively long time to determine the desired value and program the control information. Because the control information is programmed, the adjustable locked loop circuit and the integrated circuit on which it resides may quickly (for example, within a few nanoseconds) adjust the adjustable locked loop circuit to obtain proper operation.

[0084] In some embodiments, a limited number of adjustable locked loop circuits may need to be tested to determine the desired value for the control information for a larger number of adjustable locked loop circuits.

[0085] While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.

Claims

[cl] An integrated circuit, comprising: a clock path arranged to carry a clock signal; a power supply path arranged to receive power from a power supply; a locked loop circuit operatively connected to the power supply path and the clock path, comprising: a detector arranged to detect at least one of a phase difference and a frequency difference between the clock signal and an output clock signal, a charge pump, responsive to the detector, arranged to output a current on a control signal path, and a capacitor, responsive to the current, arranged to store a voltage potential; a storage device arranged to store control information; and a leakage current offset circuit operatively connected to the capacitor and the storage device, wherein the leakage current offset circuit arranged to adjust the voltage potential dependent on the control information.

[c2] The integrated circuit of claim 1, the locked loop circuit further comprising: an oscillator, operatively connected to the capacitor, arranged to generate the output clock signal.

[c3] The integrated circuit of claim 1, the locked loop circuit further comprising: a delay line, operatively connected to the capacitor, arranged to generate the output clock signal. [c4] The integrated circuit of claim 2, wherein the leakage current offset circuit comprises a transistor, and wherein the adjustment circuit is operatively connected to a gate of the transistor.

[c5] The integrated circuit of claim 1, further comprising: an adjustment circuit comprising: a first switch that controls current flow between a first voltage potential and an output of the adjustment circuit; and a second switch that controls current flow between a second voltage potential and the output of the adjustment circuit, wherein the output is operatively connected to the leakage current offset circuit.

[c6] The integrated circuit of claim 5, further comprising: a test processor unit operatively connected to the storage device and the adjustment circuit.

[c7] The integrated circuit of claim 6, further comprising: a tester arranged to communicate with the test processor unit and read at least a portion of the control information in the storage device.

[c8] The integrated circuit of claim 6, further comprising: a tester arranged to communicate with the test processor unit and write at least a portion of the control information in the storage device.

[c9] The integrated circuit of claim 1, wherein the storage device comprises a storage element selected from a group consisting of an electrically programmed fuse, an electrically programmed read only memory, an electrically erasable read only memory, a one time programmable memory, a flash memory, a laser programmable fuse, and a laser programmable anti-fuse. [clO] The integrated circuit of claim 1, wherein the confrol infonnation comprises at least one of a binary word and an instruction.

[ell] A method for post-fabrication treatment of a locked loop circuit, comprising: generating an output clock signal; comparing the output clock signal and input clock signal; generating a current dependent on the comparing; storing a voltage potential on a capacitor dependent on the current; selectively adjusting a leakage current of the capacitor using a leakage current offset circuit responsive to an adjustment circuit; and storing control information determined from the selectively adjusting.

[cl2] The method of claim 11 , further comprising: reading the confrol information using a test processor unit; and operatively controlling the selectively adjusting of the leakage current with the test processor unit.

[cl3] The method of claim 11 , further comprising: reading the control information using a tester; and controlling a test processor unit to adjust the leakage current using the adjustment circuit.

[cl4] The method of claim 11 , further comprising: writing the confrol information using a tester, wherein the control information represents an offset in the leakage current.

[cl5] An integrated circuit, comprising: means for generating a signal; means for comparing the signal and a clock signal; means for generating a current dependent on the means for comparing; means for storing a charge dependent on the means for generating; means for selectively adjusting a leakage current of the means for storing the charge; and means for storing control information dependent on the means for selectively adjusting.