WO2004015673A1

WO2004015673A1 - Back gate and bottom layer interconnect for active matrix displays

Info

Publication number: WO2004015673A1
Application number: PCT/US2003/025424
Authority: WO
Inventors: Thomas Shapton; David L. Keith; Bruce Odekirk
Original assignee: Iljin Diamond Co., Ltd.
Priority date: 2002-08-13
Filing date: 2003-08-12
Publication date: 2004-02-19
Also published as: TW200421228A; AU2003265436A1

Abstract

Active matrix displays include transistors having a top gate row line (208) and a bottom gate row line (212). The bottom gate row line is situated below the top gate row line and can be driven in parallel with the top gate row line (208). The bottom gate row line (212) can be formed as a patterned refractory conductor that is covered with a dielectric layer (216). A transistor active layer, gate oxide, and top row line are formed on top of the dielectric layer (216).

Description

BACK GATE AND BOTTOM LAYER INTERCONNECT FOR ACTIVE MATRIX DISPLAYS

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application

60/403,596, filed August 13, 2002, and U.S. Provisional Patent Application 60/405,365, filed August 22, 2002, that are incorporated herein by reference.

TECHNICAL FIELD The disclosure pertains to active matrix liquid crystal displays.

BACKGROUND

Active matrix displays are typically designed as arrays of pixels. Each pixel is associated with a capacitive storage element (a pixel capacitor) and a transistor that is used to gate image signal voltages onto the pixel capacitor. Signal voltages are typically written to the pixel capacitors row-by-row by placing signal voltages for each column of pixels on column conductors (column lines), and then selecting a row of pixels to receive the signal voltages by turning on all of the transistors in the row using a row select signal applied to a row select line. A commonly used pixel transistor design is a top gate MOS FET design illustrated schematically in FIGS. 1A-1B. Transistor bodies 102, typically formed in polysilicon, are situated on a display substrate 104, and are covered by a dielectric layer 106, typically an SiO₂ layer. A row select line 108, formed of the same material as the MOS FET gate (polysilicon) is positioned over the transistor bodies. Row select signals applied to the row select line 108 are used to turn such a transistor on or off so that a pixel capacitor or other capacitance associated with a selected pixel can be charged. Gate oxide and gate polysilicon layers are not shown in FIGS. 1A-1B.

The characteristics of the pixel transistor are important. The higher the current that can be produced in the on state, the more readily the pixel capacitor can be charged or discharged in the time available. The higher the drain leakage current in the off state, the greater the voltage loss during the time in which other rows are written. This voltage loss can result in display non-uniformity and an overall loss of contrast. Thus, a ratio of drive current to leakage current is an important pixel transistor specification. Unfortunately, most transistor designs that have reduced leakage current also have reduced drive current. In view of these and other limitations of prior art active matrix displays, improved displays and display methods are needed.

SUMMARY

Active matrix displays comprise an array of pixels and a pixel transistor associated with each pixel of the array. A first row line is configured to selectively activate a selected row of pixels, and a second row line is associated with the selected row. In some examples, the first row line is electrically connected to the second row line. According to representative examples, the second row line consists essentially of a metal silicide. h additional examples, the second row line is substantially opaque, and is situated opposite the first row line.

Active matrix substrates comprise an optically transmissive substrate and a conductor line situated on the optically transmissive substrate. An insulator layer is situated on the conductor line and an array of thin film transistors is situated on the insulator layer. A row line that is substantially opposite the conductor line is in communication with the thin film transistors. According to representative examples, the conductor line consists essentially of a metal silicide such as tungsten silicide. In other examples, the row line consists essentially of polysilicon.

Active matrix display panels comprise an array of pixel transistors and a patterned, conductive light-blocking layer electrically connected to at least one pixel transistor. In some examples, the patterned, conductive light-blocking layer is configured to form a plurality of row select lines or column select lines. In additional representative examples, the patterned, conductive light-blocking layer is configured to electrically connect to a plurality of pixel transistor sources or drains. In additional illustrative examples, a liquid crystal layer is provided that includes an array of pixel regions that are electrically switchable with the array of pixel transistors. The liquid crystal region includes at least one unswitchable region, and the patterned conductive light blocking layer is configured to reduce optical transmission associated with this region.

Display methods comprise selecting image values for at least one row of pixels, and transferring the selected image values by applying a row select signal to a row line and an opposing row line, wherein the opposing row line is formed of a conductive, light-blocking material. In additional examples, the conductive, light- blocking material is a metal silicide such as tungsten silicide.

Methods of forming electrical interconnects for an active matrix display comprise selecting a transparent substrate and forming a conductive light blocking layer on the transparent substrate. A pattern mask is provided that contains patterns for at least one electrical connection, and the conductive light-blocking layer is patterned with the pattern mask. In representative examples, the electrical connection patterns are associated with an array of transistors. In other examples, the electrical connections are associated with row select lines. In additional examples, an insulator layer is formed on the patterned conductive layer, and an array of pixel transistors is defined in one or more additional layers on the insulator layer. In other examples, row select lines are formed on the array of pixel transistors. In further representative examples, the electrical connections of the patterned conductive layer are associated with the row select lines. Methods of controlling a display pixel transistor comprise defining a first conductor in communication with a gate of the pixel transistor and defining a conductive light blocking conductor situated opposite the first conductor. A first electrical signal is applied to the first conductor and a second electrical signal is applied to the light blocking conductor. According to some examples, the first conductor and the light blocking conductor are electrically connected. In other examples, a dielectric layer is situated between the pixel transistors and the light blocking conductor, and a dielectric layer thickness is selected so that an electrical signal on the light blocking conductor substantially penetrates a pixel transistor channel. These and other features area described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic plan view of a portion of a display that includes conventional top gate MOS FETs. FIGS. IB is a sectional view of the display portion of FIG. 1 A.

FIG. 2A is a schematic plan view of a portion of a display that includes MOS FETs having bottom row lines.

FIGS. 2B is a sectional view of the display of FIG. 2 A.

FIG. 3 is a sectional view of a portion of an active matrix display assembly that includes a back conductor.

FIG.4 illustrates pixel transistor drain current as a function of gate-source voltage for several backgate voltages.

DETAILED DESCRIPTION

Pixel transistors in active matrix displays are typically fabricated in one or more layers formed, processed, and patterned on a display substrate such as quartz. Typically a transistor body that defines a FET source, channel, and drain is based on a single polysilicon layer, and a gate layer is situated on a dielectric layer (referred to as a gate oxide layer) that overlays the transistor body.

With reference to FIGS. 2A-2B, an active matrix display assembly 200 includes an array of thin film transistor bodies 202 and a display substrate 204. A bottom conductor row line ("back gate") 212 is formed on a surface of the substrate 202, and is covered or partially covered with a back gate dielectric layer 216. The back gate dielectric electrically insulates the bottom row line 212 and planarizes the assembly to receive additional layers. The transistor bodies 202 are situated on the back gate dielectric layer 216, and a dielectric layer 206 covers or partially covers the transistor bodies 202. The transistor bodies 202 are typically formed of polysilicon that is processed so that the transistor bodies 202 provide sources, drains, and channels for an array of FETs (i.e., pixel FETs) used to control voltages applied to display pixels (not shown). An additional insulator layer (a gate oxide layer) is typically formed over the transistor bodies 202, and a transistor gate is formed at locations corresponding to each of the transistor bodies 202. The gate oxide layer is typically formed of SiO₂ and the gate is formed of polysilicon. Such gates are referred to herein as "top gates." The gate oxide and gate polysilicon are not shown in FIGS. 2A-2B. Row lines 208 are in communication with the top gates and are situated over an insulator layer such as a gate oxide layer. The row lines 208 are configured to conduct row select signals to the top gates of the pixel transistors. When activated by the row select signal, the pixel transistors can be turned on to transfer image data to the pixels. Row lines and transistor gates (top gates) are typically defined in the same material, and are configured to pass over the transistor bodies as shown in FIGS. 2A-2B.

A section of a representative active matrix display panel is illustrated schematically in FIG. 3. The display includes a backplane conductor 302 and a liquid crystal layer 304. An indium tin oxide (ITO) layer 306, an associated ITO via 308, and interconnect metalizations (MET) 310, 312, 314 and associated vias 311, 313, 315 are provided to form metal interconnects. Dielectric layers 320, 322, 324 are typically made of TEOS, and a dielectric layer 326 is formed of BPSG. Polysilicon features (POLY) 330, 332 are provided adjacent an active layer 328 on which transistors are typically defined. A back conductor 340 is electrically connected to the metal interconnect 310. A first metal via 312 electrically connects to a gate and source/drain. The back conductor 340 is situated on a transparent substrate 342 such as quartz and is typically formed of an optically dense, electrical conductor such as tungsten silicide. The back conductor material can preferably withstand normal process temperatures.

With reference to FIG. 4, drain current I_<j is graphed as a function of gate source voltage (VGS) for a transistor having a top gate and an associated bottom gate. Bottom gate voltage ranges from +10 V to -10 V. VGS for a fixed drain current varies by over 1 V depending on back gate voltage.

The back conductor 340 can be patterned to serve various functions. As noted above, the back conductor can be patterned in association with one or more row lines in communication with pixel transistor gates, and serve as a back gate to improve pixel transistor characteristics. The back conductor can also be used as a back conductor interconnect for various display panel interconnections and to serve as a light blocking layer.

A representative layer stack and mask steps are listed in the following table for a display having a black matrix back conductor underneath a first polysilicon layer.

Bond pads

ITO

Via ITO to first metal interconnect

First metal interconnect

Via first metal to gate and source/drain

Source to drain implant gate

Via gate to black matrix/second metal interconnect

Capacitor implant

Active layer definition

Blackmatrix/second metal interconnect

Representative layer stack/mask steps

Forming the black matrix/back gate layer with a ref actory conductor layer such as tungsten silicide or other silicides permits active matrix processing to remain substantially unchanged. Because a refractory layer is largely unaltered by routine polysilicon process temperatures, no significant additional process development is needed. In some examples, back gates, back gate row lines, or other back gate patterns are associated with or correspond to top gates, top gate row lines, or other features defined on top of pixel transistors. Such top/bottom features can be referred to as "opposing" features. Such features can be generally similar and are situated on opposing sides of the pixel transistor body along an axis perpendicular to the substrate surface on which the active matrix is defined.

It will be apparent that the examples described above can be altered in arrangement and detail without departing from the principles of the disclosure. For example, such TFT arrays can be formed on other substrates, and different conductor materials can be used. Dielectric layer thickness can be selected so that a conductor row line (e.g., a back gate) is configured to increase an available on-state current. Typically such a contribution of the back gate can be enhanced by providing a relatively thin back gate cover layer. The TFT arrays can be provided with liquid crystal layers or other electro-optic layers, and generally include column lines in addition to the row lines and the back gate lines. The back gate conductor can also be patterned to form structures other than back gates. The disclosure is not to be taken as limiting, and we claim all that is encompassed by the appended claims.

Claims

We claim:

1. An active matrix display, comprising: an array of pixels; a pixel transistor associated with each pixel of the array; a row line configured to selectively activate a selected row of pixels; and a second row line electrically connected to the first row line and configured to activate the pixels of selected row.

2. The active matrix display of claim 1 , wherein the second row line is substantially opposite the first row line.

3. The active matrix display of claim 2, wherein the second row line consists essentially of a metal silicide.

4. The active matrix display of claim 2, wherein the second row line is substantially opaque.

5. An active matrix substrate, comprising: an optically transmissive substrate; a conductor line situated on the optically transmissive substrate; an insulator layer situated on the conductor layer; an array of thin film transistors situated on the insulator layer; and a row line in communication with the thin film transistors, wherein the row line is substantially opposite the conductor line.

6. The active matrix substrate of claim 5, wherein the conductor line consists essentially of a metal silicide.

7. The active matrix substrate of claim 5, wherein the conductor line is in electrical communication with the row line.

8. The active matrix substrate of claim 5, wherein the row line consists essentially of polysilicon.

9. An active matrix display panel, comprising: an array of pixel transistors; and a patterned conductive light blocking layer electrically connected to at least one pixel transistor.

10. The active matrix display of claim 9, wherein the patterned conductive light blocking layer is configured to form a plurality of row select lines.

11. The active matrix display of claim 9, wherein the patterned conductive light blocking layer is configured to form a plurality of column select lines.

12. The active matrix display of claim 9, wherein the patterned conductive light blocking layer is configured to electrically connect to a plurality of pixel transistor sources or drains.

13. The active matrix display of claim 9, further comprising a liquid crystal layer that includes an array of pixel regions that are electrically switchable with the array of pixel transistors and at least one unswitchable region, wherein the patterned conductive light blocking layer is configured to reduce optical transmission associated with the unswitchable region.

14. A display method, comprising: selecting image values for at least one row of pixels; and applying a first row select signal to a first row line and a second row select signal to an opposing row line, wherein the opposing row line is formed of a conductive, light-blocking material.

15. The method of claim 14, wherein the first row select signal and the second row select signal are the same.

16. The method of claim 14, wherein the conductive, light-blocking material is a metal silicide.

17. The method of claim 14, wherein the conductive, light-blocking material is a tungsten silicide.

18. A method of forming electrical interconnects for an active matrix display, comprising: selecting a transparent substrate; forming a conductive light blocking layer on the transparent substrate; providing a pattern mask that contains patterns for at least one electrical connection; and patterning the conductive light blocking layer with the pattern mask.

19. The method of claim 18, wherein the electrical connection patterns are associated with an array of transistors.

20. The method of claim 18, wherein the electrical connections are associated with row select lines.

21. The method of claim 18, further comprising: forming an insulator layer on the patterned conductive layer; and defining an array of pixel transistors on the patterned conductive layer.

22. The method of claim 21, further comprising forming row select lines on the array of pixel transistors.

23. The method of claim 22, wherein the electrical connections of the patterned conductive layer are associated with the row select lines.

24. A method of controlling a display pixel transistor, comprising: defining a first conductor in communication with a gate of the pixel transistor; and defining a conductive light blocking conductor situated opposite the first conductor and electrically connected to the first conductor.

25. The method of claim 24, further comprising situating a dielectric layer between the first conductor and the light blocking conductor, wherein a dielectric layer thickness is selected so that an electrical signal on the light blocking conductor substantially penetrates a pixel transistor gate.