WO2003077298A1 - Method of manufacturing nanowires and an electronic device - Google Patents

Method of manufacturing nanowires and an electronic device Download PDF

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Publication number
WO2003077298A1
WO2003077298A1 PCT/IB2003/000633 IB0300633W WO03077298A1 WO 2003077298 A1 WO2003077298 A1 WO 2003077298A1 IB 0300633 W IB0300633 W IB 0300633W WO 03077298 A1 WO03077298 A1 WO 03077298A1
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Prior art keywords
nanowires
substrate
etching
semiconductor
openings
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PCT/IB2003/000633
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French (fr)
Inventor
Johannes E. A. M. Van Den Meerakker
Rene J. G. Elfrink
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Koninklijke Philips Electronics N.V.
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Priority to AU2003206031A priority Critical patent/AU2003206031A1/en
Publication of WO2003077298A1 publication Critical patent/WO2003077298A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate

Definitions

  • the invention relates to a method of manufacturing nanowires, which method comprises the provision of a patterned etching mask having openings on a surface of a substrate made of a semiconductor material; and etching of the substrate so as to form the nanowires.
  • the invention also relates to a dispersion of nanowires.
  • the invention also relates to an electronic device comprising a semiconductor element provided with a first and a second electrode, which electrodes are interconnected by a semiconductor.
  • Nanowires are wires of a usually semiconducting material having a diameter of less than 200, preferably 100 nm. They are regarded as building blocks for further electronic and optoelectronic elements.
  • the nanowires have the advantage that dimensional restrictions given by the photolithographic patterning become less relevant.
  • the nanowires have other properties than units of the same material with larger dimensions because of quantization effects, such as a non-ohmic resistance.
  • a method as described in the opening paragraph is known from Yin et al., Adv. Mat. 12 (2000), 1426-1430.
  • a silicon-on-insulator (SOI) substrate was used as the semiconductor substrate, the silicon layer on the insulator having a thickness of 100 nm.
  • a photosensitive layer was provided and patterned thereon.
  • the pattern formed comprised lines with a width of 130 nm and a mutual spacing of 2 ⁇ .
  • the pattern was transferred to the semiconductor substrate by means of reactive ion etching in an atmosphere of O 2 , CHF 3 , and SF 6 at a rate of 80 nm/min.
  • the resulting lines of 100 nm thickness were taken from the insulator by lift-off in a solution of HF after oxidation. Nanowires with a cross-sectional area of approximately 55 by 40 nm were thus formed.
  • the first object is achieved in that the method comprises the following steps:
  • the etching mask has openings which have a substantially homogeneous pitch
  • the nanowires in the method according to the invention arise in a direction transverse to the surface.
  • the transverse instead of lateral etching direction renders possible the creation of a very large quantity of nanowires per unit surface area.
  • 2.10 9 nanowires were formed on a substrate with a diameter of 150 mm.
  • the nanowires may be removed from the subjacent layer inter alia by means of vibration, cutting, and pressure. Preferably, ultrasonic vibration is used. However, it is not absolutely necessary that the nanowires are removed from the substrate.
  • the pattern of the etching mask may be such that only in a limited area nanowires are; formed by etching, in a cavity in the substrate.
  • the non-etched parts of the substrate may there often be provided with doped region, layers or the like, to form transistors, interconnectstructures, other elements or only a spacer.
  • the resulting device incorporates then components in three dimensions.
  • the nanowires are herein made functional, in that the substrate comprises highly doped region and/or the end of the nanowires are provided with metallic contacts.
  • the nanowires may be used as emitters, f.i. in a field emission displays preferably, the cavities are filed with a suitable resulting material.
  • the dimensions of the nanowire itself need not be defined in the etching mask.
  • a lithography in which openings with a diameter on a micrometer scale are defined will suffice.
  • the pores grow into the substrate during anodic etching, during which they become gradually wider. Once the diameters of the pores start overlapping, the nanowires remain between the pores. No highly advanced photolithographic techniques are accordingly necessary for defining the wires in the etching mask.
  • the nanowires can be formed in a simple process which may also be carried out on an industrial scale and in which the nanowires can be optimized as desired.
  • the length of the wires may be adjusted by means of the etching time.
  • the properties of the wires may be adjusted by means of the material choice and the doping of the semiconductor substrate.
  • the current density is preferably set for a value between 0.9 and 1.0 times the peak current density i ps . Good results were obtained thereby in the case of a substrate made of Si.
  • the specific setting of the current density is dependent on a number of variables. It appears from the above definition that the peak current density i ps is proportional to the concentration of the hydrogen fluoride [HF] and proportional to exp ⁇ -c/T ⁇ , with c being a constant. Furthermore, the current density is dependent on the applied potential.
  • the specific setting can thus be achieved both by potentiostatic means and an adaptation of the HF concentration and/or the temperature, and by galvanostatic means and an adjustment of the potential. It is furthermore true that the location of the peak potential is dependent on a number of other factors such as the doping applied in the semiconductor substrate; the distance between mutually adjoining holes; the material of the semiconductor substrate; and the concentration of surfactants in the etching bath.
  • the anodic etching takes place in a direction substantially perpendicular to the surface of the substrate.
  • the distance between the surface of the substrate and the anode is limited thereby.
  • Said anode is present at a second surface which faces away from the first surface, or is in electrically conductive connection thereto.
  • a preliminary etching treatment for forming pointed notches at the surface of the substrate is carried out after the etching mask has been applied and before the actual anodic etching.
  • a strongly alkaline solution is preferably used for the preliminary etch, such as solutions of KOH, NaOH, and tetramethylammonium hydroxide (TMAH).
  • the pattern may be defined by soft- lithographic techniques such as microcontact printing.
  • notches may be provided, either chemically with a suitable etchant, or mechanically.
  • the provision of pointed notches prevents dislocations and other faults from influencing the growth of the pore.
  • the tip of the notch ensures that the growth of the pore can be well controlled.
  • the distance between two mutually adjoining notches is smaller than 10 ⁇ m. Good results were obtained in experiments with this embodiment. Greater distances involve the risk that the substrate is not etched away in accordance with the desired pattern, but is removed over the entire surface. This is the result when not only the pointed notches occur as sources for the etching, but a current starts running also in other locations in the substrate of semiconductor material. The distance is also dependent, however, on the degree of doping, and thus on the conductivity of the substrate.
  • the material of the semiconductor substrate may be inter alia GaAs, Si, InP, or some other III-V or II-VI type of semiconductor.
  • the doping may either be n-type or p-type.
  • n-type doping exposure takes place in particular on the second surface which faces away from the surface with the etching mask. This is not necessary if a base layer of a p-type is present at this second surface. If Si is used, it is preferred that the surface is present at the (100) crystal face. It is possible then to manufacture pyramid-shaped notches in the preliminary etch. The manufacture of these notches takes place, for example, in an etching solution of KOH. The pyramid shape arises because the etching substantially does not take place in the (111) direction.
  • the substrate may further be doped n-type in a first layer and p-type in a second layer, so as to obtain nanowires with internal p-n junctions.
  • the second object of the invention is achieved in a dispersion of the nanowires obtainable by the method according to the invention in a dispersing agent.
  • the dispersing agent is, for example, ethanol.
  • the dispersing agent is a volatile compound which can be readily evaporated when the dispersion is applied to a substrate.
  • the third object of the invention of providing an electronic device of the kind mentioned in the opening section is achieved in that nanowires obtained in accordance with one of the claims 1 to 6 are present as semiconductors.
  • Fig. 1 diagrammatically shows an arrangement with which the method can be carried out
  • Fig. 2 is a detailed diagram of a semiconductor substrate on which the method is carried out
  • Fig. 3 is a diagrammatic plan view of the pores with the nanowires
  • Fig. 4 shows the nanowires formed by the method
  • Fig. 5 is a diagrammatic cross-sectional view of an electronic device according to the invention.
  • Fig. 1 diagrammatically shows an arrangement 20 for carrying out the method according to the invention.
  • the arrangement 20 comprises an etching bath 25, in which a cathode 21 and an anode 22 interconnected by a current source 26 are present.
  • the cathode 21 is a Pt plate, with a surface area of 196 cm in this example.
  • the anode 22 is constructed as a Pt gauze in this example because this scatters and transmits light.
  • the arrangement further comprises an electrolytic cell 24 in which a semiconductor substrate 10 is placed.
  • a light source 23 is present, which source is switched on if a semiconductor substrate of Si with an n-type doping is used.
  • the light source 23 used is preferably a tungsten halogen lamp.
  • the etching bath 25 is a solution of ethanol (0-30 M), HF (1-10 M), and cetyltrimethylammonium chloride (CATC, 0-0.02 M) in water.
  • the etching bath 25 has a volume of 7.9 1.
  • the solution is pumped through a thermostat which keeps the temperature of the bath constant with an accuracy of 1 °C.
  • the temperature is set for the range between 0 and 60 °C.
  • the electrolytic cell 24 is bounded by the substrate 10, a chamber of polypropylene, and a plate of light- transmitting polycarbonate. A solution of 0.13 M K 2 SO 4 is present in the cell.
  • the potential between the anode 22 and the cathode 21 is typically of the order of 30 V, and the current density is of the order of 10 to 300 mA/cm 2 .
  • the anode 22 is connected to the substrate 10 viajhe electrical conduction through the solution of K 2 SO 4 .
  • Fig. 2 is a detailed diagrammatic picture of the substrate 10 in three stages of the method of manufacturing nanowires 104.
  • This substrate 10 has a surface 1 and, facing away therefrom and preferably substantially parallel thereto, a second surface 2.
  • a patterned etching mask is provided at the surface 1.
  • the substrate 10 is etched from this surface 1.
  • the semiconductor substrate 10 is present with its surface 1 in the etching bath 25 of water, ethanol, HF, and the surfactant cetyltrimethylammonium chloride (CTAC), and with its second surface 2 in the K 2 SO 4 solution of the electrolytic cell 24 (the etching bath and electrolytic cell are not shown in Fig. 2).
  • CTAC cetyltrimethylammonium chloride
  • the conductive potassium sulphate solution ensures an electrically conductive connection between the anode and the second surface 2 of the substrate 10.
  • the substrate 10 is p-type doped at the surface 1 in a concentration of approximately 10 atoms/cm , which corresponds to a resistivity of 10 to 30 ⁇ B is used as the dopant. Good results were also obtained in other experiments with higher resistivities of up to 1000 ⁇
  • the rear side 2 of the semiconductor substrate 10 is strongly doped with B (doping level 10 2 atoms/cm 3 or higher).
  • a conductive layer of, for example, Al may be provided.
  • Fig. 2 A shows the substrate 10 after notches 15 have been provided at the front 1.
  • the notches 15 are formed from the openings in a previously provided patterned etching mask.
  • This etching mask is manufactured as follows: a 140 nm thick layer of Si 3 N 4 and a photoresist are provided in that order on the substrate 10. This photoresist is locally exposed through a mask in which holes with a diameter of 1.5 ⁇ m are present.
  • the pitch 12 between the openings is 3.5 ⁇ m.
  • the pitch is defined as the distance between the centers of two mutually adjoining openings.
  • the photoresist is dissolved in the exposed locations, so that the Si 3 N 4 becomes exposed.
  • the Si N 4 is etched with a preferably concentrated solution of H 3 PO 4 .
  • the semiconductor substrate 10 is placed in an 8.8-mole KOH bath of 70 °C for 8 minutes. During this, the KOH bath etches away the semiconductor substrate 10 of Si along the fast (100) crystal direction, whereas the slow (111) crystal direction remains substantially unaffected. In this manner, more than a billion (10 9 ) pyramid-shaped pointed notches 15 of substantially identical shape are defined at the surface 1 of the semiconductor substrate 10. The pattern formed thereby is that of a hexagonal lattice.
  • Fig. 2B shows the substrate 10 after a period of anodic etching.
  • the temperature, the HF concentration, and the applied potential are adjusted such that the current density is greater than 90% of the peak current density i ps for the etching treatment. This is the case, for example, in a bath with a HF concentration of 3.0 M and a temperature of 30 °C at a current density of 130 ⁇ iA/cm . It was found that the etching takes place isotropically in a first phase. Then the etching continues anisotropically.
  • Fig. 2C shows the semiconductor substrate in a further stage.
  • the result is that nanowires 104 are obtained after the pores have overlapped.
  • the length of the nanowires 104 may be adjusted to a desired value of between 1 and 100 ⁇ m, and even longer. The adjustment takes place through a choice of the etching time. An etching time of approximately 20 minutes was necessary for obtaining nanowires 104 with a length of 100 ⁇ m at the above settings.
  • the nanowires 104 are obtained with diameters of 50 and 80 ⁇ m, and greater. The diameter may be reduced through thermal oxidation of the nanowires 104 at approximately 800 °C and etching away of the resulting SiO 2 in a solution of HF.
  • FIG. 3 is a diagrammatic plan view of the pores with the nanowires 104 formed between them. The pores are grown from the openings and not exclusively transversely to the surface of the substrate. The pores have also become wider to the extent that they overlap. The nanowires 104 then remain. Each pore is thus surrounded by six nanowires 104, and each nanowire 104 is surrounded by three pores. The result is that the number of nanowires is twice the number of pores, i.e. the number of openings in the etching mask.
  • Embodiment 2 The experiment is repeated a number of times. First of all, the pattern is changed. Openings 11 are defined with a diameter of 1.5 ⁇ m and a pitch 12 of 2.5 ⁇ m, and with a diameter of 2 ⁇ m and a pitch 12 of 5 ⁇ m. Instead of a p-type substrate with a resistivity of 10 to 30 ⁇ (doping level 10 15 atoms/cm 3 ), furthermore, an n-type substrate with the same doping level is used. The anodic etching process is now carried out under irradiation with the tungsten halogen lamp. Nanowires are obtained in all cases. When the pitch 12 is increased to 10 ⁇ m, however, with a diameter of the isolated regions 11 of 2 ⁇ m, the pores fail to grow far enough.
  • Table 1 shows the result of a further experiment. This was carried out at a constant temperature and HF concentration, while the current density was increased. The temperature was 22 °C.
  • the etching bath was a mixture of 500 ml H 2 O, 320 ml ethanol (14.9 M), 160 ml HF (4.67 M), and 12.7 ml CTAC. The notches had a diameter of 2.0 ⁇ m and their mutual distance was 5.0 ⁇ m.
  • the semiconductor substrate 10 was p-type doped at the front 1 with a doping concentration of approximately 10 atoms/cm .
  • Fig. 4 is a diagrammatic cross-sectional view of a semiconductor element 100, which is a thin-film transistor.
  • a source electrode 101 and a drain electrode 102 are provided on a substrate 110 of polyimide.
  • the electrodes 101, 102 comprise, for example, Au and are defined by lithographic means.
  • the electrodes 101, 102 are mutually separated by a channel 105 which comprises a dielectric material with preferably a low dielectric constant. Suitable materials are inter alia silicon dioxide, hydrogen- and methyl-silsesquioxane, porous silica, SiLK, and benzocyclobutene. The choice of material is also dependent on the substrate choice.
  • the surface 111 of the electrodes 101, 102 and the channel 105 is planarized, so that nanowires 104 are present on a substantially planar surface 111.
  • the nanowires 104 are deposited and aligned in that a droplet of a dispersion with the nanowires is provided on the surface 111, during which a voltage is applied.
  • the nanowires 104 are aligned by the applied AC voltage of more than 25 V and a frequency of 1 kHz.
  • a dielectric layer 106 separating the gate electrode 103 from the nanowires 104 is present on the nanowires 104.
  • alignment may take place in that a mold with channels is provided on the surface 111 and the entire assembly is placed in a bath containing the dispersion of nanowires. A current induced by a pressure difference sucks the nanowires into the channels of the mold. This will lead to an arrangement of aligned nanowires.
  • an electronic device preferably comprises a large quantity of semiconductor elements 100 which are interconnected in a desired pattern and form a circuit.
  • a large number of nanowires 104 may be present in a single semiconductor element 100, and that various materials may be chosen for the substrate 110, the electrodes 101, 102, 103, and the dielectric layers 105, 106, as is known to those skilled in the art of thin-film transistors.
  • a method of manufacturing nanowires is provided, according to which method the nanowires are prepared by etching a semiconductor substrate in a direction substantially perpendicular to the surface of the semiconductor substrate. The etching is preceded by the provision of a pattern of isolated domain at the surface of the semiconductor substrate. The resulting nanowires are suitable for use in semiconductor elements as semiconductor.
  • the nanowires may have a diameter of less than 100 nm, preferably less than 70 nm. The diameter can be reduced through an oxidation step after the etching.

Abstract

A method of manufacturing nanowires (104) is provided, according to which method the nanowires are prepared by etching a semiconductor substrate (10) in a direction substantially perpendicular to the surface of the semiconductor substrate (10). The etching is preceded by the provision of a pattern of isolated domains at the surface of semiconductor substrate (10). The resulting nanowires (104) are suitable for use in semiconductor devices.

Description

Method of manufacturing nanowires and an electronic device
The invention relates to a method of manufacturing nanowires, which method comprises the provision of a patterned etching mask having openings on a surface of a substrate made of a semiconductor material; and etching of the substrate so as to form the nanowires.
The invention also relates to a dispersion of nanowires.
The invention also relates to an electronic device comprising a semiconductor element provided with a first and a second electrode, which electrodes are interconnected by a semiconductor.
Nanowires are wires of a usually semiconducting material having a diameter of less than 200, preferably 100 nm. They are regarded as building blocks for further electronic and optoelectronic elements. The nanowires have the advantage that dimensional restrictions given by the photolithographic patterning become less relevant. In addition, the nanowires have other properties than units of the same material with larger dimensions because of quantization effects, such as a non-ohmic resistance.
A method as described in the opening paragraph is known from Yin et al., Adv. Mat. 12 (2000), 1426-1430. In the known method, a silicon-on-insulator (SOI) substrate was used as the semiconductor substrate, the silicon layer on the insulator having a thickness of 100 nm. A photosensitive layer was provided and patterned thereon. The pattern formed comprised lines with a width of 130 nm and a mutual spacing of 2 μ . The pattern was transferred to the semiconductor substrate by means of reactive ion etching in an atmosphere of O2, CHF3, and SF6 at a rate of 80 nm/min. The resulting lines of 100 nm thickness were taken from the insulator by lift-off in a solution of HF after oxidation. Nanowires with a cross-sectional area of approximately 55 by 40 nm were thus formed.
It is a disadvantage of the known method that the number of nanowires that can be formed from a semiconductor substrate is comparatively small, i.e. a few thousands. This number is small especially in comparison with the number of transistors that is defined in a semiconductor substrate nowadays and that is necessary for making a single integrated circuit operate. In other words: if an integrated circuit with nanowires is to be realized on an industrial scale, it will be necessary to manufacture nanowires in much greater numbers than is possible by the known method.
It is accordingly a first object of the invention to provide a method of the kind mentioned in the opening paragraph whereby a large number, for example more than 106, nanowires can be formed from a substrate of semiconductor material.
It is a second object of the invention to provide a dispersion of the nanowires that can be obtained by the method.
It is a third object of the invention to provide an electronic device of the kind mentioned in the opening section in which the nanowires formed by the method can be used. The first object is achieved in that the method comprises the following steps:
- the etching mask has openings which have a substantially homogeneous pitch; and
- anodic etching so as to form substantially parallel pores with a pitch corresponding to the pitch of the openings in the etching mask at a current density such that the diameter of the becomes at least as great as the pitch of the pores, whereby the nanowires are formed;
Whereas the nanowires are formed parallel to the surface and are defined by the etching mask in the prior art, the nanowires in the method according to the invention arise in a direction transverse to the surface. The transverse instead of lateral etching direction renders possible the creation of a very large quantity of nanowires per unit surface area. In typical experiments, 2.109 nanowires were formed on a substrate with a diameter of 150 mm. The nanowires may be removed from the subjacent layer inter alia by means of vibration, cutting, and pressure. Preferably, ultrasonic vibration is used. However, it is not absolutely necessary that the nanowires are removed from the substrate. The pattern of the etching mask may be such that only in a limited area nanowires are; formed by etching, in a cavity in the substrate. The non-etched parts of the substrate may there often be provided with doped region, layers or the like, to form transistors, interconnectstructures, other elements or only a spacer. The resulting device incorporates then components in three dimensions. The nanowires are herein made functional, in that the substrate comprises highly doped region and/or the end of the nanowires are provided with metallic contacts. Also the nanowires may be used as emitters, f.i. in a field emission displays preferably, the cavities are filed with a suitable resulting material.
It is a first advantage of the method according to the invention that a very large quantity of nanowires is obtained in a very simple manner, which wires all have approximately the same length. In the known method, the length is dependent on the pattern provided, and furthermore is somewhat dependent on the etching process during detaching.
It is a second advantage of the method according to the invention that a comparatively inexpensive substrate can be used, whereas a semiconductor substrate of the SOI type is necessary in the known method.
It is a third advantage of the method according to the invention that the dimensions of the nanowire itself need not be defined in the etching mask. In principle, a lithography in which openings with a diameter on a micrometer scale are defined will suffice. The pores grow into the substrate during anodic etching, during which they become gradually wider. Once the diameters of the pores start overlapping, the nanowires remain between the pores. No highly advanced photolithographic techniques are accordingly necessary for defining the wires in the etching mask.
It is a fourth advantage of the method according to the invention that the nanowires can be formed in a simple process which may also be carried out on an industrial scale and in which the nanowires can be optimized as desired. The length of the wires may be adjusted by means of the etching time. The properties of the wires may be adjusted by means of the material choice and the doping of the semiconductor substrate.
The use of anodic etching is known from the manufacture of pores with a mutual distance of a few micrometers. It was found that nanowires are formed instead of a number of pores when a current density is applied which is smaller than a so-termed peak current density ips, but greater than approximately half said density. This peak current density ips is a maximum in the current density which occurs at a given potential, the peak potential. The substrate of semiconductor material is uniformly etched when the current density is equal to or greater than ips. If the current density is set too low, the pores will become insufficiently wide, so that no separate wires are formed. The definition of the peak current density is known from J.E.A.M. van den Meerakker et al., Journal of the Electrochemical Society 147(2000), 2757-2761, the contents of which are included herein by reference. The current density is preferably set for a value between 0.9 and 1.0 times the peak current density ips. Good results were obtained thereby in the case of a substrate made of Si. The specific setting of the current density is dependent on a number of variables. It appears from the above definition that the peak current density ips is proportional to the concentration of the hydrogen fluoride [HF] and proportional to exp{-c/T}, with c being a constant. Furthermore, the current density is dependent on the applied potential. The specific setting can thus be achieved both by potentiostatic means and an adaptation of the HF concentration and/or the temperature, and by galvanostatic means and an adjustment of the potential. It is furthermore true that the location of the peak potential is dependent on a number of other factors such as the doping applied in the semiconductor substrate; the distance between mutually adjoining holes; the material of the semiconductor substrate; and the concentration of surfactants in the etching bath.
Preferably, the anodic etching takes place in a direction substantially perpendicular to the surface of the substrate. The distance between the surface of the substrate and the anode is limited thereby. Said anode is present at a second surface which faces away from the first surface, or is in electrically conductive connection thereto. Preferably, furthermore, a preliminary etching treatment for forming pointed notches at the surface of the substrate is carried out after the etching mask has been applied and before the actual anodic etching. In the case of a substrate of Si, a strongly alkaline solution is preferably used for the preliminary etch, such as solutions of KOH, NaOH, and tetramethylammonium hydroxide (TMAH). It is alternatively possible, however, to provide pointed notches in a different way. For example, the pattern may be defined by soft- lithographic techniques such as microcontact printing. After that or simultaneously, notches may be provided, either chemically with a suitable etchant, or mechanically. The provision of pointed notches prevents dislocations and other faults from influencing the growth of the pore. The tip of the notch ensures that the growth of the pore can be well controlled. In a further embodiment, the distance between two mutually adjoining notches is smaller than 10 μm. Good results were obtained in experiments with this embodiment. Greater distances involve the risk that the substrate is not etched away in accordance with the desired pattern, but is removed over the entire surface. This is the result when not only the pointed notches occur as sources for the etching, but a current starts running also in other locations in the substrate of semiconductor material. The distance is also dependent, however, on the degree of doping, and thus on the conductivity of the substrate.
The material of the semiconductor substrate may be inter alia GaAs, Si, InP, or some other III-V or II-VI type of semiconductor. In the case of Si, the doping may either be n-type or p-type. In the case of an n-type doping, exposure takes place in particular on the second surface which faces away from the surface with the etching mask. This is not necessary if a base layer of a p-type is present at this second surface. If Si is used, it is preferred that the surface is present at the (100) crystal face. It is possible then to manufacture pyramid-shaped notches in the preliminary etch. The manufacture of these notches takes place, for example, in an etching solution of KOH. The pyramid shape arises because the etching substantially does not take place in the (111) direction.
The substrate may further be doped n-type in a first layer and p-type in a second layer, so as to obtain nanowires with internal p-n junctions.
The second object of the invention is achieved in a dispersion of the nanowires obtainable by the method according to the invention in a dispersing agent. The dispersing agent is, for example, ethanol. Preferably, the dispersing agent is a volatile compound which can be readily evaporated when the dispersion is applied to a substrate. The third object of the invention of providing an electronic device of the kind mentioned in the opening section is achieved in that nanowires obtained in accordance with one of the claims 1 to 6 are present as semiconductors.
^ These and other aspects of the method according to the invention will be explained in more detail below with reference to the Figures, in which:
Fig. 1 diagrammatically shows an arrangement with which the method can be carried out;
Fig. 2 is a detailed diagram of a semiconductor substrate on which the method is carried out;
Fig. 3 is a diagrammatic plan view of the pores with the nanowires; Fig. 4 shows the nanowires formed by the method; and Fig. 5 is a diagrammatic cross-sectional view of an electronic device according to the invention.
Identical components have been given the same reference numerals in the Figures. The drawings are not true to scale and merely indicate examples. As will be obvious to those skilled in the art, alternative embodiments are conceivable within the scope of protection of the claims.
Embodiment 1
Fig. 1 diagrammatically shows an arrangement 20 for carrying out the method according to the invention. The arrangement 20 comprises an etching bath 25, in which a cathode 21 and an anode 22 interconnected by a current source 26 are present. The cathode 21 is a Pt plate, with a surface area of 196 cm in this example. The anode 22 is constructed as a Pt gauze in this example because this scatters and transmits light. The arrangement further comprises an electrolytic cell 24 in which a semiconductor substrate 10 is placed. A light source 23 is present, which source is switched on if a semiconductor substrate of Si with an n-type doping is used. The light source 23 used is preferably a tungsten halogen lamp. The etching bath 25 is a solution of ethanol (0-30 M), HF (1-10 M), and cetyltrimethylammonium chloride (CATC, 0-0.02 M) in water. The etching bath 25 has a volume of 7.9 1. The solution is pumped through a thermostat which keeps the temperature of the bath constant with an accuracy of 1 °C. The temperature is set for the range between 0 and 60 °C. The electrolytic cell 24 is bounded by the substrate 10, a chamber of polypropylene, and a plate of light- transmitting polycarbonate. A solution of 0.13 M K2SO4 is present in the cell. The potential between the anode 22 and the cathode 21 is typically of the order of 30 V, and the current density is of the order of 10 to 300 mA/cm2. The anode 22 is connected to the substrate 10 viajhe electrical conduction through the solution of K2SO4.
Fig. 2 is a detailed diagrammatic picture of the substrate 10 in three stages of the method of manufacturing nanowires 104. This substrate 10 has a surface 1 and, facing away therefrom and preferably substantially parallel thereto, a second surface 2. A patterned etching mask is provided at the surface 1. The substrate 10 is etched from this surface 1. For this purpose, the semiconductor substrate 10 is present with its surface 1 in the etching bath 25 of water, ethanol, HF, and the surfactant cetyltrimethylammonium chloride (CTAC), and with its second surface 2 in the K2SO4 solution of the electrolytic cell 24 (the etching bath and electrolytic cell are not shown in Fig. 2). The conductive potassium sulphate solution ensures an electrically conductive connection between the anode and the second surface 2 of the substrate 10. The substrate 10 is p-type doped at the surface 1 in a concentration of approximately 10 atoms/cm , which corresponds to a resistivity of 10 to 30 Ω B is used as the dopant. Good results were also obtained in other experiments with higher resistivities of up to 1000 Ω The rear side 2 of the semiconductor substrate 10 is strongly doped with B (doping level 102 atoms/cm3 or higher). To improve the conductance of the second surface 2 of the substrate 10 further, a conductive layer of, for example, Al may be provided.
Fig. 2 A shows the substrate 10 after notches 15 have been provided at the front 1. The notches 15 are formed from the openings in a previously provided patterned etching mask. This etching mask is manufactured as follows: a 140 nm thick layer of Si3N4 and a photoresist are provided in that order on the substrate 10. This photoresist is locally exposed through a mask in which holes with a diameter of 1.5 μm are present. The pitch 12 between the openings is 3.5 μm. The pitch is defined as the distance between the centers of two mutually adjoining openings. The photoresist is dissolved in the exposed locations, so that the Si3N4 becomes exposed. The Si N4 is etched with a preferably concentrated solution of H3PO4. Then the photoresist is removed in an oxygen plasma. The semiconductor substrate 10 is placed in an 8.8-mole KOH bath of 70 °C for 8 minutes. During this, the KOH bath etches away the semiconductor substrate 10 of Si along the fast (100) crystal direction, whereas the slow (111) crystal direction remains substantially unaffected. In this manner, more than a billion (109) pyramid-shaped pointed notches 15 of substantially identical shape are defined at the surface 1 of the semiconductor substrate 10. The pattern formed thereby is that of a hexagonal lattice.
Fig. 2B shows the substrate 10 after a period of anodic etching. The temperature, the HF concentration, and the applied potential are adjusted such that the current density is greater than 90% of the peak current density ips for the etching treatment. This is the case, for example, in a bath with a HF concentration of 3.0 M and a temperature of 30 °C at a current density of 130 πiA/cm . It was found that the etching takes place isotropically in a first phase. Then the etching continues anisotropically.
Fig. 2C shows the semiconductor substrate in a further stage. The result is that nanowires 104 are obtained after the pores have overlapped. The length of the nanowires 104 may be adjusted to a desired value of between 1 and 100 μm, and even longer. The adjustment takes place through a choice of the etching time. An etching time of approximately 20 minutes was necessary for obtaining nanowires 104 with a length of 100 μm at the above settings. The nanowires 104 are obtained with diameters of 50 and 80 μm, and greater. The diameter may be reduced through thermal oxidation of the nanowires 104 at approximately 800 °C and etching away of the resulting SiO2 in a solution of HF. A photograph of the nanowires 104 obtained from the substrate 10 is shown in Fig. 3. The photograph was made by Scanning Electron Microscopy (SEM) with a Philips XL40 FEG device with acceleration voltages of approximately 30 kV. The number of nanowires 104 obtained on a semiconductor substrate 10 is more than two billions (2.109). Fig. 3 is a diagrammatic plan view of the pores with the nanowires 104 formed between them. The pores are grown from the openings and not exclusively transversely to the surface of the substrate. The pores have also become wider to the extent that they overlap. The nanowires 104 then remain. Each pore is thus surrounded by six nanowires 104, and each nanowire 104 is surrounded by three pores. The result is that the number of nanowires is twice the number of pores, i.e. the number of openings in the etching mask.
Embodiment 2 The experiment is repeated a number of times. First of all, the pattern is changed. Openings 11 are defined with a diameter of 1.5 μm and a pitch 12 of 2.5 μm, and with a diameter of 2 μm and a pitch 12 of 5 μm. Instead of a p-type substrate with a resistivity of 10 to 30 Ω (doping level 1015 atoms/cm3), furthermore, an n-type substrate with the same doping level is used. The anodic etching process is now carried out under irradiation with the tungsten halogen lamp. Nanowires are obtained in all cases. When the pitch 12 is increased to 10 μm, however, with a diameter of the isolated regions 11 of 2 μm, the pores fail to grow far enough.
Table 1 shows the result of a further experiment. This was carried out at a constant temperature and HF concentration, while the current density was increased. The temperature was 22 °C. The etching bath was a mixture of 500 ml H2O, 320 ml ethanol (14.9 M), 160 ml HF (4.67 M), and 12.7 ml CTAC. The notches had a diameter of 2.0 μm and their mutual distance was 5.0 μm. The semiconductor substrate 10 was p-type doped at the front 1 with a doping concentration of approximately 10 atoms/cm .
Table 1 - Formation of nanowires as a function of current density
Figure imgf000009_0001
Embodiment 3
Fig. 4 is a diagrammatic cross-sectional view of a semiconductor element 100, which is a thin-film transistor. A source electrode 101 and a drain electrode 102 are provided on a substrate 110 of polyimide. The electrodes 101, 102 comprise, for example, Au and are defined by lithographic means. The electrodes 101, 102 are mutually separated by a channel 105 which comprises a dielectric material with preferably a low dielectric constant. Suitable materials are inter alia silicon dioxide, hydrogen- and methyl-silsesquioxane, porous silica, SiLK, and benzocyclobutene. The choice of material is also dependent on the substrate choice. The surface 111 of the electrodes 101, 102 and the channel 105 is planarized, so that nanowires 104 are present on a substantially planar surface 111. The nanowires 104 are deposited and aligned in that a droplet of a dispersion with the nanowires is provided on the surface 111, during which a voltage is applied. The nanowires 104 are aligned by the applied AC voltage of more than 25 V and a frequency of 1 kHz. A dielectric layer 106 separating the gate electrode 103 from the nanowires 104 is present on the nanowires 104. Alternatively, alignment may take place in that a mold with channels is provided on the surface 111 and the entire assembly is placed in a bath containing the dispersion of nanowires. A current induced by a pressure difference sucks the nanowires into the channels of the mold. This will lead to an arrangement of aligned nanowires.
As will be obvious to those skilled in the art, an electronic device preferably comprises a large quantity of semiconductor elements 100 which are interconnected in a desired pattern and form a circuit. It is further noted that a large number of nanowires 104 may be present in a single semiconductor element 100, and that various materials may be chosen for the substrate 110, the electrodes 101, 102, 103, and the dielectric layers 105, 106, as is known to those skilled in the art of thin-film transistors. In short, a method of manufacturing nanowires is provided, according to which method the nanowires are prepared by etching a semiconductor substrate in a direction substantially perpendicular to the surface of the semiconductor substrate. The etching is preceded by the provision of a pattern of isolated domain at the surface of the semiconductor substrate. The resulting nanowires are suitable for use in semiconductor elements as semiconductor. The nanowires may have a diameter of less than 100 nm, preferably less than 70 nm. The diameter can be reduced through an oxidation step after the etching.

Claims

CLAIMS:
1. A method of manufacturing nanowires from semiconductor material, comprising the steps of:
- providing a patterned etching mask with openings on a surface of a substrate of semiconductor material, which openings have a substantially homogeneous pitch; - placing the substrate with the etching mask in a liquid etchant for the semiconductor material; and anodic etching so as to form substantially parallel pores with a pitch corresponding to the pitch of the openings in the etching mask at a current density such that the diameter of the pores becomes at least as great as the pitch of the pores, whereby the nanowires are formed;
2. A method as claimed in claim 1 , characterized in that nanowires are removed from the substrate
3. A method as claimed in claim 1, characterized in that the anodic etching takes place in a direction substantially perpendicular to the surface of the substrate.
4. A method as claimed in claim 1, characterized in that a preliminary etching treatment for forming pointed notches at the surface of the substrate is carried out after the etching mask has been applied and before the actual anodic etching.
5. A method as claimed in claim 1, characterized in that the distance between two mutually adjoining openings is smaller than 10 μm.
6. A method as claimed in claim 1, characterized in that the semiconductor substrate is a substrate of Si whose surface is at the (100) crystal face, and in that the etchant is a solution of hydrogen fluoride.
7. A dispersion of nanowires in a dispersing agent, which nanowires are obtainable in accordance with one of the preceding claims 2-6.
8. An electronic device comprising a semiconductor element provided with a first and a second electrode which are intercormected via a semiconductor, characterized in that nanowires obtainable in accordance with any one of the claims 1 to 6 are present as the semiconductor.
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JP2006507133A (en) * 2002-11-18 2006-03-02 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Dispersion of nanowires of semiconductor materials
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EP2082425A4 (en) * 2006-10-05 2011-07-13 Hitachi Chemical Co Ltd Well-aligned, high aspect-ratio, high-density silicon nanowires and methods of making the same
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US7981772B2 (en) 2008-12-29 2011-07-19 International Business Machines Corporation Methods of fabricating nanostructures
IT201800003427A1 (en) * 2018-03-12 2019-09-12 Univ Degli Studi Cagliari Method to prepare the surface of a semiconductor for the fabrication of a porous semiconductor
EP3540762A1 (en) * 2018-03-12 2019-09-18 Università Degli Studi di Cagliari Method for the fabrication of a porous semiconductor with controlled pores distribution

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