WO2003075484A1

WO2003075484A1 - Power control device and method for controlling the transmission power of a transmitter in a mobile communication network

Info

Publication number: WO2003075484A1
Application number: PCT/EP2002/002517
Authority: WO
Inventors: Bill William Shurvinton; David Spink
Original assignee: Nokia Corporation
Priority date: 2002-03-07
Filing date: 2002-03-07
Publication date: 2003-09-12
Also published as: AU2002238570A1

Abstract

The invention relates to a power control device and method for controlling the transmission power of a transmitter of a mobile communication network in which burst signals are output to the transmitter. The burst signals include a fixed training sequence. The device and method are arranged to control the output power of a power amplifier of the transmitter using a power control loop. The device and method are adapted to detect the output power of the power amplifier only when the latter outputs the training sequence, and to control the power based on the detected output power.

Description

TITLE

POWER CONTROL DEVICE AND METHOD FOR CONTROLLING THE

TRANSMISSION POWER OF A TRANSMITTER IN A

MOBILE COMMUNICATION NETWORK

DESCRIPTION

FIELD AND BACKGROUND OF THE INVENTION

The invention relates to a power control device and method for controlling the transmission power of a transmitter of or in a mobile communication network in which burst signals are applied to the transmitter. The burst signals include a fixed training sequence.

More generally, the invention relates to Power Control, in particular Digital Power Control of a transmitter such as a Transceiver (TRX) or a BTS Transmitter. More specifically, the invention aims at providing a power control function applicable to a device, system, and method requiring power control.

In existing GSM compatible basestations, Power Control is implemented by a combination of two methods: closed loop, when the transmitter is on, and open loop when the transmitter is off. The closed loop mode is a real time control in which the output power is sampled and compared to a reference signal, and the gain is corrected. The closed loop part of the power control operation is also used to control the ramp shape between timeslots so that the power versus time mask is met.

The open loop part of the power control function is used in the off period between timeslots as the linear range of the output detector limits the closed loop operation.

In the standard GSM system, with a constant RF envelope, power control can be easily carried out utilizing an integrator as a loop filter. If there is any ripple on the envelope, the integrator, depending upon the loop bandwidth, attempts to recover the variation on the envelope by altering the attenuation on the RF path. However, the analog (closed loop) power control schemes as used with GMSK (Gaussian

Minimum Shift Keying) , have difficulty with EDGE (Enhanced Data for GSM Evolution) 8PSK modulation, as the signal has no longer a constant envelope.

The analog power control has been enhanced for EDGE by adding a replica of the modulation envelope onto the power control voltage and comparing it to the detected voltage. Switching the loop bandwidth during the burst enables this scheme to meet the ramping requirements of GSM, make the power control scheme less sensitive to delay and minimise amplitude error.

As mentioned above, the analog scheme requires a combination of closed loop and open loop control as the linear range of the detector is not sufficient for the Tx Off state (Tx = transmitter) . Such as solution is difficult to implement and often causes distortion of the signal due to switching transients caused by the switching of the loop bandwidth. Transients may also occur when switching between closed loop and open loop operation as the- detector range is not sufficient to detect the whole envelope. Additionally, as the power ramping is controlled by the closed loop, overshoot of the ramp often occurs, giving type approval difficulties. SUMMARY OF THE INVENTION

The invention provides a device and/or method with enhanced possibility of effective and yet simple power control.

The present invention provides a device and/or method as defined in the independent claims or any of the dependent claims.

Generally, the invention relates to a power control device and method for controlling the transmission power of a transmitter in a mobile communication network in which burst signals are applied to the transmitter, the burst signals including a fixed training sequence. The device and method are arranged to control the output power of a power amplifier of the transmitter using a power control loop. The device and method are adapted to detect the output power of the power amplifier only when the latter outputs the training sequence, and to control the power based on the detected output power.

In accordance with a preferred implementation of the invention, the training sequence (also known as midamble) is used to measure power.

Digital ramping is used with the baseband functions. The power control is working open loop at all times. Therefore, the problems related to EDGE envelope variations are removed.

The digital Power Control loop according to a preferred implementation of the invention as described above and below removes the above mentioned problems.

The power control system uses the training sequence to set the power control and may be employed with any appropriate type of modulation, e.g. Edge or GMSK modulation. This feature, preferably as part of a system using digital ramping techniques, allows a simple and low cost power control system to be implemented.

The Digital Power Control scheme according to the invention is different from the existing Analog scheme. The power is controlled in open loop mode, i.e. no power corrections are made during the measured timeslot. The output power is set on the basis of information measured in the previous timeslot.

The Digital power control method also has some advantages in that can it be utilised when implementing a power control method for multicarrier transmitter.

The digital power control method operates in an open loop basis, using the midample of the burst for power measurement. Compared to the analog power control used e.g. for 8-PSK modulated signal, the controlling circuit is open, thus there is no realtime feedback circuit to the controller. The method and device according to the invention does not suffer from the problems of the analog ones.

Monitoring the known midamble will give an exact information on the output power, provided that, as usual, the measuring circuit (integrator, integration time, zeroing) works properly and does not produce any error.

As the system is open loop, in that no adjustments are performed during the measured burst, there is a reduction in the dynamic range requirements of the lineariser. As power ramping is performed in the digital domain, over- or undershooting of the ramping waveform does not occur. Further, the same power control system can be used with any modulation scheme, provided that it has a known midamble. Further, the number of parts required to implement the Tx lineup is reduced, reducing costs.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 illustrates a first embodiment of the invention which comprises a basic control loop,

Fig. 2 shows the structures of normal bursts for EDGE and GMSK,

Fig. 3 illustrates a further embodiment of the present invention including a single control loop,

Fig. 4 shows the detector dynamic range in an embodiment of the present invention,

Fig. 5 illustrates a further embodiment of the present invention implemented for a smart antenna case, and

Fig. 6 shows another embodiment of the present invention illustrating the places for power control in a smart antenna structure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE

INVENTION

The described Digital Power Control scheme in accordance with the invention is for instance applicable in a GSM transceiver. The power control method and devices are designed and applicable for Smart Antenna applications or non Smart Antenna applications. Generally, a smart antenna system combines multiple antenna elements with a signal-processing capability to optimize its radiation and/or reception pattern automatically in response to the signal environment.

The purpose of the power control system is to control the output power of the transmitter in several steps, e.g. sixteen steps of 2 dB. Power control is also responsible for meeting the power versus time requirements and switching transient requirements specified in the Digital Cellular Telecommunications System (Phase 2+) for GSM (Global System for Mobile Communications) .

According to a preferred implementation of the invention, the output of the Power Amplifier is detected during the training sequence, averaged using an integrator, and then digitised with an ADC (Analog to Digital Converter) . This digitised signal is fed to the power control algorithm which can be implemented as hardware, e.g. an ASIC, or in software, e.g. residing in an embedded processor. The algorithm compares the measured output to the desired signal level, and forms an error signal which steps the RF attenuator to the correct level.

Fig. 1 shows an embodiment of the invention employing such a structure and functioning.

The power control device of Fig. 1 includes an attenuator 1 to which the RF signal to be applied to an antenna (not shown) is supplied. The attenuator 1 is controllable as regards its gain, and applies its output, e.g. the power- controlled RF signal, to a power amplifier (PA) 2 having its output connected to a line 3 which leads to the antenna. For power detection, a detector circuit 4, such as a diode detector circuit is coupled to the PA output (line 3) via an appropriate coupling means such as a directional coupler. The analog output signal of detector circuit 4 is supplied to an analog-digital converter (ADC) 5 either directly or preferably via an integrating or averaging means. The output of the ADC 5 is applied to a baseband module 6 and represents the measured power level.

The baseband module 6 includes an error correction device such as the shown summing means 7 which receives the output signal of ADC e.g. at its inverting input, and a reference value representing the desired power level, e.g at its non- inverting input. The resulting error signal output from summing means 7 is applied to the control input of attenuator 1 for controlling its gain appropriately.

There are four main fundamental features (implementable either solely or in arbitrary combination) within the digital power control design according to the shown embodiments which are :

- Baseband Ramping within the control means;

- Open Loop Static Control (e.g. Power Levels 0 to 6);

- Dynamic Control set within the control means (e.g. Power Levels 7 to 15) ;

- Estimation of output Power is based upon the digitised Training Sequence of the output signal.

These features are explained in more detail in the following.

The Baseband Ramping is achieved in an appropriate element such as in the transceiver, e.g. in an ASIC chip.

The output of the modulator is digitally multiplied by a programmable smooth ramp profile, which brings up the power gradually to avoid switching transients. This ramped digital signal is then used as the input to a DAC (Digital to Analog Converter) - the output of which can be up-converted and amplified to the correct level. The output signal of this DAC may represent the desired value "Ref." applied to summing means 7 as shown in Fig. 1.

The power ramp is generated in a DDS (Direct Digital Synthesis) structure and is synchronized to the falling edge of the Power Control Scheme clock, e.g. PWC (Pulse Width

Control) clock. The power ramp goes down between timeslots in all cases. The Power control unit gets its timing, slope and power level information preferably from a power control table e.g. within the ASIC.

As regards Open Loop Static Power Level Control, the control of the static power levels, Power Levels 0 to 6, may e.g. be effected by a single attenuator, e.g. a 30dB, 2dB step digital Attenuator, at RF (Radio Frequency) . The attenuator receives its information from the ASIC. This attenuator is also used to take out unit to unit variations in components and the effects of temperature variations.

The Dynamic Power Level Control is effected in the power control means, preferably using a basic structure as shown in Fig. 1. Preferably, a digital multiplier, before the modulator output, sets the output power for dynamic levels PL7 to PL15 _.(PL = Power Level) .

As regards Training Sequence Detection, rather than trying to detect the whole envelope of the timeslot, the invention preferably detects only the midamble training sequence. The training sequence is a fixed bit sequence which compensates for the effects of multipath fading and allows synchronisation. The output of the detector is then preferably averaged using an integrator and then converted to a digital signal of e.g. 12 bit.

Fig. 2 shows the structure, in the time domain, of a normal burst of data for both EDGE and GSM. The position of the training sequence (midamble) within each burst is highlighted.

The bursts for EDGE or GMSK are standardised and include tails 8 at the beginning and end, a midamble (training sequence) 10 in the midst of the burst signals, and information sections 9 between the training sequence 10 and the tails 8. Fig. 2 indicates the bit lengths of the individual sections of the bursts, as well as the total bit lengths of the bursts.

This approach has two main advantages. Firstly the position of the training sequence and its duration within the burst are fixed and secondly a diode detector circuit is able to detect the output power for all output power levels.

The embodiment preferably comprises only a single power control loop.

A simplified version of the power control algorithm is suitable for inclusion in the power control means, e.g. ASIC. As before, the power control compares the required output power with the measured power, and appropriately steps the attenuator and digital multiplier within the power control chip, e.g. ASIC.

Fig. 3 shows the main components of a single control loop.

The power control shown in Fig. 3 includes a power control means 11 which is connected to a baseband module (baseband board BBB) 12 which may be similar to baseband module 6 of Fig. 1 and which applies, at its output DL, appropriate signals to the power control means 11. The power control means 11 includes a transmitter chip 13 which may be an ASIC or an embedded processor. A static power control means 14 such as a controllable amplifier or attenuator is connected to the RF output of chip 13. The output of static power control means 14 is connected to the input of power amplifier 15 which outputs the signals to be transmitted to an output 16 connected to one or more antennas (not shown) .

The power control means 11 comprises a directional coupler 17 for sensing the output power of power amplifier 15, an attenuator means 18, a detector means 19, an integrator 21, an ADC (Analog to Digital Converter) 22, a power detection section 23, and an algorithm section 24. The power detection section 23 comprises a static control part issuing a control signal to static power control means 14 for controlling the actual static power control level, as well as a power detection section issuing a control signal which is applied, via line 20, to the control input of detector means 19.

The power detection section 23 generates the control signal on line 20 with a timing so as to operate the detection section 19 only when the power amplifier outputs the midamble (training sequence) 10 shown in Fig. 2.

Therefore, the detector means 19 is controlled using a time- window for activating the detection section only during training sequence, and for stopping the detection function of detector means during the other times of the time slot signal (tails 8 and information sectors 9 as shown in Fig. 2) . As the bit difference, and therefore the time difference, between start of a burst (starting with the front tail 8) and the begin of the training sequence 10 is fixed for every burst, the control section 23 can easily generate the control signal on line 20 by providing a time delay between start of a burst and start of the control signal sufficient so as to open the detection function of detector means 19 only when the first bits of the midamble are occurring at the input of the detector means 19. Likewise, the time window for detecting the PA output signal is closed at or before the occurrence of the last bits of the midamble 10, the total time duration of the midamble being known to the system beforehand in accordance with the standardised burst form.

In the following, the Power Detector and Integrator Circuit is described in more detail. The Power detector and Integrator circuit essentially consists of three main parts, a directional coupler 17, the analogue detector circuit 19 and the Analog to Digital Conversion circuit 22. The highest possible coupling factor is used to minimise through loss and reduce the power dissipation in the attenuator 18 connected to the coupled output arm. The coupler 17 must also drive the detector means 19 with sufficient power so as to maintain adequate sensitivity at the lowest power level, i.e. Power Level 15.

The output from the coupled port of the directional coupler 17 drives the detector means 19, e.g. detector diode matching circuit, via the attenuator 18 of at least βdB which is used to improve the detector match and set the required power level at the input to the detector 19. The matching circuit is tuned to achieve high sensitivity at low power levels over the GSM 900 band.

Following the detector diode matching circuit is the integrator 21 which may include a temperature compensation circuit. The purpose of the integrator 21 is to average out the amplitude variations inherent in the EDGE signal and hence to reduce the error in the sampled power measurement.

The output of the integrator 21 feeds into the ADC 22 which converts the detected analog voltage into a digital output which may be a word having an appropriate number of bits. In the case of this single loop example, this digital word is fed directly into the power control chip 13, 23, where it is compared to a reference.

With regard to Detector Dynamic Range, the power detector circuit is implemented to operate monotonically over at least the range of 36 dB, from 3dB above to 33dB below the nominal full power output.

The power detector circuit preferably provides an absolute accuracy of ±0.5dB over the power range 0 to 17dB below nominal PA GMSK full power output (PA = Power Amplifier) . In addition it preferably provides an absolute accuracy of ± l.OdB over the power range from 17dB to 33dB below nominal full power output.

The breakdown of the 36dB detector range requirement is represented graphically in Fig. 4 (dynamic range 25) and is as follows: -

3dB for PA overdrive under fault conditions (no power accuracy requirement) ;

3dB difference in mean power level between EDGE and GMSK modulation; - 14dB for the 7 static power steps ( i.e. 8 power levels); 16dB for the 8 dynamic power steps (i.e. 9 power levels).

In the following, details of the algorithm stored in algorithm section 24 are described. The algorithm maintains a table of gain values on various channels. The table index will be sent by the baseband board 12 to the power control means. The algorithm is told the static power level (i.e. the maximum transmit power of the basestation due to geographical constraints) in an initialisation message and is told the desired output power in each downlink burst message. The algorithm calculates the dynamic power level, i.e. the amount by which the base station is backed-off from the static power, which is used to digitally scale the modulator output.

The gain value stored in the table is preferably provided as a ramp or staircase with small increments, e.g. in l/8th dB increments, in the range from 0 to e.g. 31.875 dB. This gain value is used to drive a step attenuator in the transmit chain, with a step size of either 0.5dB, ldB or 2dB. The remainder when the gain table setting is divided by the step attenuator resolutions is used to digitally scale the modulator output.

The output power is measured during the training sequence 10, preferably using either an integrator to average the power or by taking multiple readings, and the gain table setting is updated based on the difference between the wanted and measured power.

If the difference is less than some pre-determined value adB, the value is left unchanged. If greater than adB but less than 2dB, the table is moved by one step (i.e. l/8th dB) in the appropriate direction. If 2dB or more, the table is stepped by 16 (2dB) , to accelerate convergence during warm- up. If the power level is below some programmable cut-off, the table is only stepped by one unit if the difference is 2dB or more, to account for the detector being less accurate at low power levels.

The mapping from channel number to table index will be done by the baseband software. A simple but effective mapping would be to assign three channels to each table entry, but a better mapping could be determined if the number and distribution of channels is known.

The static attenuation, i.e. the control of the static power levels, Power Levels 0 to 6, is effected by attenuator 14, e.g. a single 30dB, 2dB step digital attenuator, at RF. The attenuator 14 receives its information from the power control chip 13, e.g. ASIC. This attenuator 14 is also used to take out unit to unit variations in components and the effects of temperature .

Fig. 5 shows a further embodiment of the invention which includes multiple TRX's configured in a smart antenna implementation. Here the transmit section of the transceiver is split into three sections: TRX(s) 28, the interconnect matrix 27 and Power Amplifier module (s) 26. The detected output power information is then detected in the same manner as in the above described example but then passed from power report elements via line 30 to Baseband Boards 29 where it is used to adjust the power settings.

The method by which the detected data is passed back to the baseband module may be application specific.

There are for example up to eight antennas in the Smart Antenna case, so there will be up to eight power control loops. The C/I (Carrier to Interference ratio) can be improved by running the outer antennas at a lower power level, which reduces the sidelobe power. The power adjustment on the antenna array, called a beam taper, will be introduced by backing off the vector modulators in the control loops for the outer antennas. The vector modulators are also responsible for phasing the antennas and hence steering the beam.

The Smart Antenna system will require antenna calibration bursts to be sent, in the GSM idle slots. It is sufficient to use just these bursts to calibrate the power control loop, as long as a suitably smart power control algorithm is used. The simple measure-and-correct algorithm used in the non-smart case described above would possibly lead to unsatisfying results in some cases. Most gain variations in the transmit paths are going to be due to temperature changes in the PAs and couplers, so will be roughly independent of frequency. There are gain effects that depend strongly on frequency, such as temperature changes at the SAW (Surface Acoustic Wave) filter, but these will happen over a much longer timescale than PA temperature changes.

This leads to an algorithm which measures the error on one channel, corrects that channel, and then applies a proportion of that correction to all channels assuming that a large proportion of that error was frequency-independent. The process of exactly correcting an error will require a division operation, which is easiest done in a microprocessor or DSP, rather than implementing, as an alternative, the algorithm directly in hardware.

Gain control is preferably performed as a part of gain/phase calibration. The power control algorithm in the Smart Antenna situation is difficult to separate from the phase/gain calibration that is also occurring. The antenna calibration hardware will produce a set of phases and relative gains for each antenna path through a particular TRX. The power- measuring circuits in the PA's for power control will produce absolute powers for each PA output. There is a need to reconcile the absolute and relative power measurements, especially if they conflict. The power control operations will involve stepping attenuators in the different transmit chains, and this will alter the phase through that path, requiring another phase calibration.

Power/gain control can be done in four places in the transmit path, in the Smart Antenna option. These places are highlighted by arrows in Fig. 6.

The dynamic power is input, via line 33, to a digital multiplier 32 in a power control chip 31, e.g. ASIC. This gives fine, linear control of the output power of all antenna paths. Using this approach degrades the noise floor, so it can only be used for dynamic power setting plus other small increments .

A common step attenuator 34 gives coarse control over all paths, and will probably be used only for setting the static power level. A splitter 35 distributes the output signal of attenuator 34 to several antenna paths which each include a coarse path attenuator 36, a vector modulatbr 37, an attenuator 38 for feedback power control, a power amplifier 39, and an antenna 40.

The coarse path attenuators 36 give a good range, e.g. 30dB, of attenuation, but in coarse steps of e.g. 2dB, that will affect the phase of the signal. System must be calibrated after stepping this attenuator 36.

The vector modulators 37 can be assumed to be fine-step power controlling devices, which means that the device must have been characterised accurately. This table should allow phase and gain to be set independently of each other.

The optional autonomous attenuators 38 driven by temperature- sensing equipment in the power amplifiers 39 will only affect phase to a small degree, but this may be significant.

In the following, the algorithm is described. The algorithm maintains a table of gains, in the range 0 to 30dB with a high precision for each TRX path and each channel setting in use. These gains are approximately equal to the amount of attenuation which has to be provided in the coarse path attenuator 36 and vector modulator 37, holding the common step attenuator 34 at the correct setting for this static power level, so that the maximum input to the digital multiplier (4095) will provide the correct static power level at the PA output. An approximation is preferably provided because the coarse path attenuator 36 will not have exactly 2dB steps.

The inputs to the algorithm are the static power level, the dynamic level of this burst (i.e. the amount in dBs that it is backed-off from the maximum allowed power for this BTS) , and the tapering of the antenna.

The common attenuator 34 is preferably set to the static power level. It is possible to account for gain drifts in the whole antenna array here, but this may be unnecessarily complicated.

The digital multiplier 32 is preferably set to 4095x10^° where d = 0, -2, -4,... is the dynamic power level in dB. The beam taper or profile should be added to the vector modulator settings. The taper cannot be done by changing the coarse path attenuators 36, because the taper can change from one timeslot to another, but the phase must remain constant for every timeslot between calibrations. The taper needs to be changeable to allow packet services to be broadcast to many • recipients, while targeting traffic channels to a single user. Although the invention has been described above with reference to specific embodiments, the scope of the invention also covers any alterations, additions, modifications, and omissions of the disclosed features.

Claims

1. Power control device for controlling the transmission power of a transmitter in a mobile communication network, the device being adapted to output burst signals to the transmitter which burst signals include a fixed training sequence, comprising a power amplifier and a power control loop for controlling the output power of the power amplifier, wherein the device is adapted to detect the output power of the power amplifier only when outputting the training sequence and to control the power based on the detected output power.

2. Device according to claim 1, wherein the power control loop contains a detector means for detecting the output of the power amplifier, and a control means is provided for controlling the detector means so as to detect the output of the power amplifier only during the time of output of the training sequence.

3. Device according to claim 2, wherein the power control loop includes an integrator or averaging means for integrating or averaging the detected output of the power amplifier.

4. Device according to claim 2 or 3, wherein the power control loop contains an attenuating means for attenuating the output of the power amplifier before application to the detector means.

5. Device according to claim 2, 3, or 4, wherein the detector means is a diode detector means.

6. Device according to any one of the preceding claims, comprising an open loop static power control for controlling the output power of the power amplifier.

7. Device according to claim 6, wherein the open loop static power control comprises a controllable attenuator means arranged upstream of the input side of the power amplifier, the controllable attenuator means being controlled by a control means of the device.

8. Device according to any one of the preceding claims, comprising a baseband module which is adapted to provide digital power ramping.

9. Device according to any one of the preceding claims, which is adapted to set the output power on the basis of information measured in a previous timeslot and no power corrections are made during a measured timeslot.

10. Device according to any one of the preceding claims, for application in a smart antenna structure comprising several antennas, including a power amplifier in each antenna path, a common attenuator, and a splitter arranged between the common attenuator and the antenna pathes, each power amplifier including a power control loop.

11. Device according to claim 10, comprising an interconnect matrix arranged at a position between the splitter and the power amplifiers.

12. Power control method for controlling the transmission power of a transmitter in a mobile communication network, wherein burst signals are output to the transmitter which burst signals include a fixed training sequence, and wherein the output power of a power amplifier is controlled using a power control loop which detects the output power of the power amplifier, the output power of the power amplifier being detected only when outputting the training sequence, and the power is controlled based on the detected output power.

13. Method according to claim 12, wherein the power control loop contains a detector means for detecting the output of the power amplifier, and wherein a control means controls the detector means so as to detect the output of the power amplifier only during the time of output of the training sequence.

14. Method according to claim 13, wherein the detected output of the power amplifier is integrated or averaged.

15. Method according to claim 13 or 14, wherein the output of the power amplifier is attenuated before application to the detector means.

16. Method according to claim 13, 14, or 15, wherein the detector means is a diode detector means.

17. Method according to any one of the preceding method claims, providing an open loop static power control for controlling the output power of the power amplifier.

18. Method according to claim 17, wherein the open loop static power control comprises a controllable attenuator means arranged upstream of the input side of the power amplifier, the controllable attenuator means being controlled by a control means.

19. Method according to any one of the preceding method claims, wherein a baseband module provides digital power ramping .

20. Method according to any one of the preceding method claims, which is adapted to set the output power on the basis of information measured in a previous timeslot and no power corrections are made during a measured timeslot.

21. Method according to any one of the preceding method claims, for application in a smart antenna structure comprising several antennas, including a power amplifier in each antenna path, a common attenuator, and a splitter arranged between the common attenuator and the antenna pathes, each power amplifier including a power control loop.

22. Method according to claim 21, comprising an interconnect matrix arranged at a position between the splitter and the power amplifiers.