WO2003050870A1 - Diffusion barrier - Google Patents

Diffusion barrier Download PDF

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Publication number
WO2003050870A1
WO2003050870A1 PCT/GB2002/005521 GB0205521W WO03050870A1 WO 2003050870 A1 WO2003050870 A1 WO 2003050870A1 GB 0205521 W GB0205521 W GB 0205521W WO 03050870 A1 WO03050870 A1 WO 03050870A1
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WIPO (PCT)
Prior art keywords
layer
barrier
nitrogen
dielectric
hydrogen
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PCT/GB2002/005521
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French (fr)
Inventor
Knut Beekmann
Kathrine Giles
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Trikon Technologies Limited
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Publication date
Priority claimed from GBGB0129567.4A external-priority patent/GB0129567D0/en
Application filed by Trikon Technologies Limited filed Critical Trikon Technologies Limited
Priority to DE10297447T priority Critical patent/DE10297447T5/en
Priority to AU2002347353A priority patent/AU2002347353A1/en
Publication of WO2003050870A1 publication Critical patent/WO2003050870A1/en

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/32—Carbides
    • C23C16/325—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/36—Carbonitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Diffusion Barrier This invention relates to a metal diffusion barrier and in particular, but not exclusively, to barriers which limit the diffusion of copper into an insulating layer. It is well known, in the manufacture of semi-conductors and similar devices, that if a metal, such as copper, has a direct interface with an insulating material such as silicon dioxide, then, particularly when the metal atoms are energetic under heating or when current is passed, those metal atoms diffuse into the insulating layer and can set up a conducting short circuit between wiring lines and the like. The likelihood of such occurrences increases as the dimensions of the architecture of the devices decreases.
  • EP-0725440 also suggests the possibility of silicon carbides being used as diffusion barriers or having the silicon carbides as the insulating layer themselves.
  • the specification is however very short on description and is confused about the dielectric constants involved. However, in its plainest statement, it would appear that the dielectric constant of the silicon carbide is nearer 5 than 3.5.
  • the present invention consists in a copper diffusion barrier including a layer of silicon carbide type material, the layer having a thickness of 100 nanometers or less, a dielectric constant of 3.5 or less and containing nitrogen and hydrogen.
  • the invention consists in a metal diffusion barrier comprising a layer of silicon carbide type material which has been exposed to ionised hydrogen, e.g. a hydrogen containing plasma, subsequent to deposition.
  • ionised hydrogen e.g. a hydrogen containing plasma
  • the material contains nitrogen and it is particularly preferred that the material has a dielectric constant of 3.5 or less.
  • the period of exposure is determined by the thickness of the layer.
  • the period may be calculated at about 40 seconds per hundred nanometers of layer thickness.
  • the treatment requires a sufficiency of ionised hydrogen at the surface of the layer and has been successfully carried out at 1KW of RF applied to both a 230mm and 360mm diameter electrode opposed a 200mm wafer - being plasma densities of 2.4 Watt/cm 2 and 1 Watt/cm 2 approximately.
  • the layer is preferably deposited by chemical vapour deposition (CVD) and most preferably by plasma enhanced CVD (PECVD) and the precursors for the CVD preferably are or include tetramethylsilane and nitrogen.
  • CVD chemical vapour deposition
  • PECVD plasma enhanced CVD
  • the precursors for the CVD preferably are or include tetramethylsilane and nitrogen.
  • other organo-silanes or mixtures thereof may be utilised and the nitrogen may be present in a nitrogen containing gas.
  • the CVD may take place at a temperature less than about 60°C.
  • the invention may further include a dielectric assembly comprising a dielectric layer and a barrier layer, according to any one of the preceding claims, deposited on or under the dielectric layer.
  • the dielectric constant of both layers may be 3.5 or less.
  • the etch selectivity of the barrier layer may be at least 3:1 , and preferably at least 4.5:1 , to the dielectric layer, which may be silicon dioxide and, in particular maybe a porous silicon dioxide.
  • the dielectric layer which may be silicon dioxide and, in particular maybe a porous silicon dioxide.
  • a convenient material is Trikon Technologies Limited's Orion material which has a dielectric constant of approximately 2.2.
  • the low dielectric constant of the silicon carbide type material itself may enable a barrier layer to be dispensed with at least in certain circumstances.
  • the resultant exposed surface can be hydrogen plasma treated, as proposed above, to form an effective barrier layer at the surface of the formation.
  • hydrogen treatment may be introduced for the initial part of the deposition either by passing hydrogen into the chamber or by providing a short interruption in the supply of precursors to allow hydrogen treatment to take place.
  • the invention also consists in a method of forming a metal diffusion barrier including depositing the barrier by CVD from an organic silane containing precursor and nitrogen and hydrogen plasma treating the layer subsequent to or during deposition.
  • the silane precursor is tetramethylsilane, but any suitable organo-silane or mixture thereof can be used.
  • the nitrogen flow rate is significantly higher than the silane flow rate and a nitrogen flow rate of at least ten times that of the silane flow rate is preferred.
  • the CVD may take place at less than 60°C.
  • the barrier layer may be exposed to the ionised hydrogen, e.g. from a plasma, for a period determined by the thickness of the layer and that period may be calculated at about 40 seconds per 100 nanometer of layer thickness.
  • Figure 1 is an FTIR (Fourier Transform Infra Red) trace of a nitrogen containing silicon carbide etch stop layer;
  • Figure 2 is an FTIR trace of the material of Figure 1 after hydrogen plasma treatment
  • Figure 3 is an FTIR trace of a prior art silicon carbide deposited using trimethylsilane at a higher deposition temperature
  • Figure 4 is an SIMS (Secondary Ion Mass Spectroscopy) which illustrates the secondary ion count on either side of a silicon carbide copper interface for various anneal temperatures.
  • a nitrogen-containing hydrogenated silicon carbide like material was deposited using the process of Table 1.
  • 4MS stands for tetramethylsilane.
  • the process is characterised as "low temperature”, by which is meant that it takes place at less than about 60°C.
  • the substrate is 200 mm dia and the temperature is that of the wafer platen. Pressure is in torr/millitorr, gas flow is standard cubic centimetres per minute and the power is 13.56 MhzRF applied to a 230 mm dia electrode opposing the wafer platen.
  • the traces in Figure 2 and Figure 3 illustrate the difference between the current film (Figure 2) after hydrogen plasma treatment and the prior art silicon carbide of Figure 3.
  • the composition of the material seems primarily to be Si- N( ⁇ 832cm- 1 ), Si-C( ⁇ 800cm “1 ), Si-CH 2 -Si( ⁇ 1040cm “1 ), Si-CH 3 ( ⁇ 1260cm “1 ), Si- H( ⁇ 2100cm “1 ), C-H( ⁇ 2900cm “1 ).
  • the presence of Si-N is also firmly evidenced by XPS (X-ray Photo-electron Spectroscopy) depth profile data, which reveals the presence of nitrogen at up to about 9% of the peaks detected in this particular film. Hydrogen, not detected by XPS, is expected to constitute 40 atomic % or more of the material.
  • Figures 1 and 2 evidence the change in the film caused by the ionised hydrogen process which is at least partly chemical and at these power levels is not rate- limited by power applied. It is presumed that activated hydrogen reacts with the layer in a manner that is not wholly as a result of ion impact with its surface.

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Abstract

This invention relates to a metal diffusion barrier of insulating material and in particular, but not exclusively, to barriers which limit the diffusion of copper into an insulating layer. The insulating layer may be of a silicon carbide type material which has been exposed to ionised hydrogen subsequent to deposition. Preferably the material contains nitrogen and it is particularly preferred that the material has a dielectric constant of 3.5 or less.

Description

Diffusion Barrier This invention relates to a metal diffusion barrier and in particular, but not exclusively, to barriers which limit the diffusion of copper into an insulating layer. It is well known, in the manufacture of semi-conductors and similar devices, that if a metal, such as copper, has a direct interface with an insulating material such as silicon dioxide, then, particularly when the metal atoms are energetic under heating or when current is passed, those metal atoms diffuse into the insulating layer and can set up a conducting short circuit between wiring lines and the like. The likelihood of such occurrences increases as the dimensions of the architecture of the devices decreases.
It has been known for some time that the way to overcome this problem is to deposit a barrier layer between the metal and the insulating layer. However, many of the usual candidates, such as silicon nitride, significantly increase the capacitance created by the insulating layer as a whole which is undesirable. WO00/19498 proposes the use of a SiC material as a barrier layer, but the materials suggested all have a dielectric constant of over 4 and indeed 4.2 seems to be the best value reported for the barrier layer.
EP-0725440 also suggests the possibility of silicon carbides being used as diffusion barriers or having the silicon carbides as the insulating layer themselves. The specification is however very short on description and is confused about the dielectric constants involved. However, in its plainest statement, it would appear that the dielectric constant of the silicon carbide is nearer 5 than 3.5.
From one aspect the present invention consists in a copper diffusion barrier including a layer of silicon carbide type material, the layer having a thickness of 100 nanometers or less, a dielectric constant of 3.5 or less and containing nitrogen and hydrogen.
From a further aspect the invention consists in a metal diffusion barrier comprising a layer of silicon carbide type material which has been exposed to ionised hydrogen, e.g. a hydrogen containing plasma, subsequent to deposition. Preferably the material contains nitrogen and it is particularly preferred that the material has a dielectric constant of 3.5 or less.
Where the layer is exposed to the plasma, it is preferred that the period of exposure is determined by the thickness of the layer. The period may be calculated at about 40 seconds per hundred nanometers of layer thickness. The treatment requires a sufficiency of ionised hydrogen at the surface of the layer and has been successfully carried out at 1KW of RF applied to both a 230mm and 360mm diameter electrode opposed a 200mm wafer - being plasma densities of 2.4 Watt/cm2 and 1 Watt/cm2 approximately.
The layer is preferably deposited by chemical vapour deposition (CVD) and most preferably by plasma enhanced CVD (PECVD) and the precursors for the CVD preferably are or include tetramethylsilane and nitrogen. However, other organo-silanes or mixtures thereof may be utilised and the nitrogen may be present in a nitrogen containing gas. The CVD may take place at a temperature less than about 60°C. The invention may further include a dielectric assembly comprising a dielectric layer and a barrier layer, according to any one of the preceding claims, deposited on or under the dielectric layer. The dielectric constant of both layers may be 3.5 or less.
The etch selectivity of the barrier layer may be at least 3:1 , and preferably at least 4.5:1 , to the dielectric layer, which may be silicon dioxide and, in particular maybe a porous silicon dioxide. A convenient material is Trikon Technologies Limited's Orion material which has a dielectric constant of approximately 2.2.
Alternatively, in many arrangements, the low dielectric constant of the silicon carbide type material itself may enable a barrier layer to be dispensed with at least in certain circumstances. Thus if a recess or other formation is etched into the silicon carbide, the resultant exposed surface can be hydrogen plasma treated, as proposed above, to form an effective barrier layer at the surface of the formation. Similarly, where a metal layer or wire lies beneath the dielectric layer, hydrogen treatment may be introduced for the initial part of the deposition either by passing hydrogen into the chamber or by providing a short interruption in the supply of precursors to allow hydrogen treatment to take place.
The invention also consists in a method of forming a metal diffusion barrier including depositing the barrier by CVD from an organic silane containing precursor and nitrogen and hydrogen plasma treating the layer subsequent to or during deposition.
Preferably the silane precursor is tetramethylsilane, but any suitable organo-silane or mixture thereof can be used.
For the formation of barrier layers, it is particularly preferred that the nitrogen flow rate is significantly higher than the silane flow rate and a nitrogen flow rate of at least ten times that of the silane flow rate is preferred. The CVD may take place at less than 60°C.
The barrier layer may be exposed to the ionised hydrogen, e.g. from a plasma, for a period determined by the thickness of the layer and that period may be calculated at about 40 seconds per 100 nanometer of layer thickness.
Although the invention has been defined above, it is to be understood that it includes any inventive combination of the features set out above and in the following description.
The invention may be performed in various ways and specific embodiments will now be described with reference to the accompany drawings, in which:
Figure 1 is an FTIR (Fourier Transform Infra Red) trace of a nitrogen containing silicon carbide etch stop layer;
Figure 2 is an FTIR trace of the material of Figure 1 after hydrogen plasma treatment;
Figure 3 is an FTIR trace of a prior art silicon carbide deposited using trimethylsilane at a higher deposition temperature; and
Figure 4 is an SIMS (Secondary Ion Mass Spectroscopy) which illustrates the secondary ion count on either side of a silicon carbide copper interface for various anneal temperatures.
A nitrogen-containing hydrogenated silicon carbide like material was deposited using the process of Table 1. In this table 4MS stands for tetramethylsilane. The process is characterised as "low temperature", by which is meant that it takes place at less than about 60°C.
Figure imgf000005_0001
Table 1.
It will be noted that the flow rate for the nitrogen is significantly higher than the 4MS flow rate and this approach is somewhat different to previous proposals relating to nitrogen-containing silicon carbide materials, which have previously been developed to achieve a low dielectric constant. In the experiment the as deposited material was further processed or "set" by the plasma process of Table 2. Hydrogen plasma processing of dielectric layers has previously been proposed in order to reduce the dielectric constant of those materials and it has been discovered that this reduction in k value is because the material is rendered at least partially porous. It is therefore somewhat surprising that hydrogen plasma treatment should be beneficial in improving the materials resistance to diffusion.
Experimentation has shown that if the plasma treatment is carried out for the kind of periods utilised in creating low dielectric constant dielectric layers, then a significant crust of carbon depleted material is formed on the deposited layer of the material of the present invention, which is undesirable from the point of view of its barrier properties and dielectric constant. Therefore for the material of the experiment at least, shorter periods of around 40 seconds per hundred nanometers thickness of material have proved to be appropriate and it is believed that periods of as low as 20 seconds per hundred nanometers thickness of material will improve the barrier qualities of the material.
Figure imgf000006_0001
Table 2.
In both tables, the substrate is 200 mm dia and the temperature is that of the wafer platen. Pressure is in torr/millitorr, gas flow is standard cubic centimetres per minute and the power is 13.56 MhzRF applied to a 230 mm dia electrode opposing the wafer platen. The traces in Figure 2 and Figure 3 illustrate the difference between the current film (Figure 2) after hydrogen plasma treatment and the prior art silicon carbide of Figure 3.
From Figure 2 the composition of the material seems primarily to be Si- N(~832cm-1), Si-C(~800cm"1), Si-CH2-Si(~1040cm"1), Si-CH3 (~1260cm"1), Si- H(~2100cm"1), C-H(~2900cm"1). The presence of Si-N is also firmly evidenced by XPS (X-ray Photo-electron Spectroscopy) depth profile data, which reveals the presence of nitrogen at up to about 9% of the peaks detected in this particular film. Hydrogen, not detected by XPS, is expected to constitute 40 atomic % or more of the material.
In Figure 4 a layer of the film was deposited on a layer of copper and the secondary ion count was monitored both sides of the interface, which is indicated by a vertical line on the diagram. The diffusion of silicon ions into the copper and copper ions into the silicon is duly plotted as shown by the legend for no anneal, 400°C anneal and 500°C anneal. It will be noted that there is effectively no difference in the level of copper diffusion across the boundary at temperatures up to 500°C and this accordingly shows that the applicants have developed a low dielectric materials which constitutes a good diffusion barrier to copper. Experiments to date have been limited to copper diffusion. These characteristics are also indicative of, more generally, alkali metal ion and moisture barrier properties. The hydrogen treatment has been carried out with an R.F. powered electrode at
1 KW in both a 300m (360mm) diameter) and 200mm (230mm diameter) process module upon a cluster tool suitable for semiconductor wafer processing. Figures 1 and 2 evidence the change in the film caused by the ionised hydrogen process which is at least partly chemical and at these power levels is not rate- limited by power applied. It is presumed that activated hydrogen reacts with the layer in a manner that is not wholly as a result of ion impact with its surface.

Claims

Claims 1. A copper diffusion barrier including a layer of silicon carbide type material, the layer having a thickness of 100 nanometers or less, a dielectric constant of 3.5 or less and containing nitrogen and hydrogen.
2. A metal diffusion barrier comprising a layer of silicon carbide type material which has been exposed to a hydrogen containing plasma subsequent to or during deposition.
3. A barrier as claimed in claim 2 wherein the material contains nitrogen.
4. A barrier as claimed in claim 2 or claim 3 wherein the material has a dielectric constant of 3.5 or less.
5. A barrier layer as claimed in any one of claims 2 to 4 wherein the layer has been exposed to ionised hydrogen for a period determined by its thickness.
6. A barrier layer as claimed in claim 5 wherein the period is calculated at about 40 seconds per 100 nanometers of layer thickness.
7. A barrier layer as claimed in any one of claims 1 to 6 wherein the layer is deposited by Chemical Vapour Deposition (CVD).
8. A barrier layer as claimed in claim 7 wherein the precursors of the CVD are tetramethylsilane and nitrogen.
9. A barrier layer as claimed in claim 8 wherein the CVD takes place at temperatures less than about 60°C.
10. A dielectric assembly comprising a dielectric layer and a barrier layer according to any one of the preceding claims deposited on or under the first dielectric layer.
1 1. An assembly as claimed in claim 10 wherein the dielectric constant of both layers is 3.5 or less.
12. An assembly as claimed in claim 10 or claim 11 wherein the etch selectively of the barrier layer is at least 3:1 to the dielectric layer.
13. A dielectric layer comprising a nitrogen-containing silicon carbide material wherein a surface or surface zone of the layer has been treated to form an integral barrier layer. 5
14. A dielectric layer wherein the surface has been treated with ionised hydrogen to form a barrier layer.
15. A method of forming a metal diffusion barrier including depositing the barrier by CVD from an organic silane containing precursor and nitrogen and hydrogen plasma treating the layer subsequent to or during deposition. 0
16. A method as claimed in claim 15 wherein the silane precursor is tetramethylsilane.
17. A method as claimed in claim 15 or claim 16 wherein the nitrogen flow rate is at least ten times the silane flow rate.
18. A method as claimed in any one of claims 15 to 17 wherein the CVD 5 takes places at less than 60°C.
19. A method as claimed in any one of claims 15 to 18 wherein the barrier layer is exposed to the ionised gas for a period determined by the thickness of the layer.
20. A method as claimed in any one of claims 15 to 19 wherein the period is o calculated at about 40 seconds per hundred nanometer of layer thickness.
PCT/GB2002/005521 2001-12-11 2002-12-06 Diffusion barrier WO2003050870A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1523034A3 (en) * 2003-10-09 2006-01-11 Asm Japan K.K. Method of manufacturing silicon carbide film

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0725440A2 (en) * 1995-02-02 1996-08-07 Dow Corning Corporation Silicon carbide metal diffusion barrier layer
WO2000019498A1 (en) * 1998-10-01 2000-04-06 Applied Materials, Inc. In situ deposition of low k si carbide barrier layer, etch stop, and anti-reflective coating for damascene applications
US6201291B1 (en) * 1997-12-10 2001-03-13 U.S. Philips Corporation Semiconductor device and method of manufacturing such a device
US20010030369A1 (en) * 2000-01-19 2001-10-18 Macneil John Methods and apparatus for forming a film on s substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0725440A2 (en) * 1995-02-02 1996-08-07 Dow Corning Corporation Silicon carbide metal diffusion barrier layer
US6201291B1 (en) * 1997-12-10 2001-03-13 U.S. Philips Corporation Semiconductor device and method of manufacturing such a device
WO2000019498A1 (en) * 1998-10-01 2000-04-06 Applied Materials, Inc. In situ deposition of low k si carbide barrier layer, etch stop, and anti-reflective coating for damascene applications
US20010030369A1 (en) * 2000-01-19 2001-10-18 Macneil John Methods and apparatus for forming a film on s substrate

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ISHIMARU T ET AL: "Development of low-k copper barrier films deposited by PE-CVD using HMDSO, N/sub 2/O and NH/sub 3/", PROCEEDINGS OF THE IEEE 2001 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (CAT. NO.01EX461), PROCEEDINGS OF THE IEEE 2001 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, BURLINGAME, CA, USA, 4-6 JUNE 2001, 2001, Piscataway, NJ, USA, IEEE, USA, pages 36 - 38, XP002233091, ISBN: 0-7803-6678-6 *
KUO-LUNG FANG ET AL: "Electrical reliability of low dielectric constant diffusion barrier (a-SiC:H) for copper interconnect", PROCEEDINGS OF THE IEEE 2001 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (CAT. NO.01EX461), PROCEEDINGS OF THE IEEE 2001 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, BURLINGAME, CA, USA, 4-6 JUNE 2001, 2001, Piscataway, NJ, USA, IEEE, USA, pages 250 - 252, XP002233092, ISBN: 0-7803-6678-6 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1523034A3 (en) * 2003-10-09 2006-01-11 Asm Japan K.K. Method of manufacturing silicon carbide film

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