WO2003036523A1 - Simulation method, simulation program, and display method - Google Patents

Simulation method, simulation program, and display method Download PDF

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Publication number
WO2003036523A1
WO2003036523A1 PCT/JP2001/009321 JP0109321W WO03036523A1 WO 2003036523 A1 WO2003036523 A1 WO 2003036523A1 JP 0109321 W JP0109321 W JP 0109321W WO 03036523 A1 WO03036523 A1 WO 03036523A1
Authority
WO
WIPO (PCT)
Prior art keywords
simulation
processing
nodes
circuit
result
Prior art date
Application number
PCT/JP2001/009321
Other languages
French (fr)
Japanese (ja)
Inventor
Junji Sato
Peter Lee
Goichi Yokomizo
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to JP2003538942A priority Critical patent/JP3905885B2/en
Priority to PCT/JP2001/009321 priority patent/WO2003036523A1/en
Publication of WO2003036523A1 publication Critical patent/WO2003036523A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

A simulation method comprising the step of a first processing for carrying out a first simulation using circuit nodes (N1-N14) of an upper-level side layer of hierarchical circuit data as result output nodes and a second processing for carrying out a second simulation under the initial condition equivalent to that of the first simulation of circuit nodes (N15-N17) of the lower-level side layer by using the simulation result stored after the first processing as input/output information on a circuit area including the circuit nodes of the lower-level side layer. The result output nodes where the simulation result is stored are limited to the upper-level side layer, and therefore the amount of data to be stored about the simulation can be reduced. The circuit nodes other than the stored result output nodes can be reproduced by the second processing by using the data on the result of the first processing.
PCT/JP2001/009321 2001-10-24 2001-10-24 Simulation method, simulation program, and display method WO2003036523A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003538942A JP3905885B2 (en) 2001-10-24 2001-10-24 Simulation method, simulation program, and display processing method
PCT/JP2001/009321 WO2003036523A1 (en) 2001-10-24 2001-10-24 Simulation method, simulation program, and display method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2001/009321 WO2003036523A1 (en) 2001-10-24 2001-10-24 Simulation method, simulation program, and display method

Publications (1)

Publication Number Publication Date
WO2003036523A1 true WO2003036523A1 (en) 2003-05-01

Family

ID=11737861

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2001/009321 WO2003036523A1 (en) 2001-10-24 2001-10-24 Simulation method, simulation program, and display method

Country Status (2)

Country Link
JP (1) JP3905885B2 (en)
WO (1) WO2003036523A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007041839A (en) * 2005-08-03 2007-02-15 Renesas Technology Corp Simulation method
JP2007213274A (en) * 2006-02-09 2007-08-23 Renesas Technology Corp Simulation method and simulation program
JP2007528553A (en) * 2004-03-09 2007-10-11 セヤン ヤン DYNAMIC VERIFICATION FOR IMPROVING VERIFICATION PERFORMANCE AND VERIFICATION EFFICIENCY-A verification method based on a basic method and a verification methodology using the same
JP2015215736A (en) * 2014-05-09 2015-12-03 トヨタ自動車株式会社 Simulation device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0561933A (en) * 1991-09-04 1993-03-12 Hokuriku Nippon Denki Software Kk Logical inspecting device
JPH09160960A (en) * 1995-12-14 1997-06-20 Kawasaki Steel Corp Method and device for displaying logical simulation result for semiconductor integrated circuit
JPH09265489A (en) * 1996-03-29 1997-10-07 Fujitsu Ltd Simulation processing method
JPH10254914A (en) * 1997-03-07 1998-09-25 Mitsubishi Electric Corp Logic simulated result analyzer
JPH10293772A (en) * 1997-04-18 1998-11-04 Hitachi Ltd Logic simulation device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0561933A (en) * 1991-09-04 1993-03-12 Hokuriku Nippon Denki Software Kk Logical inspecting device
JPH09160960A (en) * 1995-12-14 1997-06-20 Kawasaki Steel Corp Method and device for displaying logical simulation result for semiconductor integrated circuit
JPH09265489A (en) * 1996-03-29 1997-10-07 Fujitsu Ltd Simulation processing method
JPH10254914A (en) * 1997-03-07 1998-09-25 Mitsubishi Electric Corp Logic simulated result analyzer
JPH10293772A (en) * 1997-04-18 1998-11-04 Hitachi Ltd Logic simulation device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007528553A (en) * 2004-03-09 2007-10-11 セヤン ヤン DYNAMIC VERIFICATION FOR IMPROVING VERIFICATION PERFORMANCE AND VERIFICATION EFFICIENCY-A verification method based on a basic method and a verification methodology using the same
JP2007041839A (en) * 2005-08-03 2007-02-15 Renesas Technology Corp Simulation method
JP4554464B2 (en) * 2005-08-03 2010-09-29 ルネサスエレクトロニクス株式会社 Simulation device
JP2007213274A (en) * 2006-02-09 2007-08-23 Renesas Technology Corp Simulation method and simulation program
US7721234B2 (en) 2006-02-09 2010-05-18 Renesas Technology Corp. Simulation method and simulation program
JP2015215736A (en) * 2014-05-09 2015-12-03 トヨタ自動車株式会社 Simulation device

Also Published As

Publication number Publication date
JP3905885B2 (en) 2007-04-18
JPWO2003036523A1 (en) 2005-02-17

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