WO2003017453A1 - Pfc apparatus for a converter operating in the borderline conduction mode - Google Patents
Pfc apparatus for a converter operating in the borderline conduction mode Download PDFInfo
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- WO2003017453A1 WO2003017453A1 PCT/IL2001/000776 IL0100776W WO03017453A1 WO 2003017453 A1 WO2003017453 A1 WO 2003017453A1 IL 0100776 W IL0100776 W IL 0100776W WO 03017453 A1 WO03017453 A1 WO 03017453A1
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- current
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- converter
- inductor
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the present invention relates to the field of switching power converters. More particularly, the present invention relates to a method and apparatus for regulating the harmonics content of the current drawn from the power line by electrical equipment and loads by utilizing Borderline Conduction Mode (BCD) of operation without sampling the input voltage.
- BCD Borderline Conduction Mode
- the present invention also relates to the electronic circuit design, physical construction and layout of such an apparatus.
- APFC Active Power Factor Correction
- the input voltage is rectified by diode bridge D x and fed into a Boost converter that comprises an input inductor L in , a switch S l 5 a high frequency rectifier (D 2 ), an output filter capacitor (C 0 ) and a load (R L ).
- a power switch (S 2 ) is driven by a high frequency control signal of duty cycle D 0N , so as to force the input current (i im ) to follow the shape of the rectified input voltage (V ivR ), in which case the power converter becomes essentially a resistive load to the power line; i.e., the Power Factor (PF) will be a unity.
- APFC converters The need for APFC converters is driven by the worldwide concern for the quality of the power line supplies. Injection of high harmonics into the power line and poor Power Factor (PF) in general, is known to cause many problems. Among these problems are the lower efficiency of power transmission, possible interference to other units connected to the power line, and distortion of the line voltage shape. In the light of the practical importance of APFC converters, many countries have adopted, or are in the process of adopting, voluntary and mandatory standards. These standards set limits to the permissible current line harmonics injected by any given equipment that is powered by an alternating current (AC) electrical power source, so as to maintain a high power-quality. Another advantage of an APFC converter is the increase in the power level than can be drawn from a given power line.
- AC alternating current
- the effective (i.e., rms) current will be higher than the magnitude of the first harmonics of the current, the latter being the only component that contributes real power to the load. Additionally, protection elements such as fuses and circuit breakers respond to the rms current. Consequently, the rms current limits the maximum power that can be drawn from the line. In Power Factor Correction equipment, the rms current equals the magnitude of the first harmonic of the current (since the higher harmonics are absent) and hence, the power drawn from the line essentially reaches its maximum theoretical value. It is thus evident that the need for APFC circuits is widespread and that economical realization of such circuits is of prime importance.
- Common APFC converters usually operate in one of three modes (with respect to the current passing through the main inductor Lin):
- CCM Continuous Conduction Mode
- DCM Discontinuous Conduction Mode
- Borderline Conduction Mode in which the inductor current rises immediately after it drops to zero.
- T ON is the time during which the power switch
- T 0FF is the time during which the inductor (current) is in
- the most efficient mode of operation is CCM, since the rms current of the power switch SI is the lowest.
- reverse recovery of the main diode D 2 poses extra losses and EMI generation.
- implementing an APFC converter in CCM mode requires that L in is of high inductance value, making it bulky and costly.
- the DCM is the least desirable since the inductor rms current is the highest, which increases the power switch losses and makes the main inductor large in size, because the physical size of an inductor is proportional to the rms current that is expected to pass through it. A good compromise is, therefore, the BCM mode of operation.
- Implementing the BCM mode allows reduction of the inductor size, as well as the power switch losses.
- the voltage across the power switch will, by itself, drop to zero just after the inductor current reverses its direction due to the reverse current of the main diode.
- ZNS zero voltage switching
- Fig. 5 represents a conventional realization of a BCM converter according to the prior art.
- the controller CO ⁇ T receives the shape of the rectified power line voltage ( V ac rej - ) obtained via the voltage divider R a , R b from
- V ivR which is used as the reference for the desired shape of the input current.
- the controller receives the voltage V se across R se , which is identical to the input current when the power switch Q l is conducting, and generates gate pulses D 0N to the power switch Q x , so as to force the inductor current to follow the reference voltage shape.
- the current level is adjusted for any given load R ⁇ by monitoring the output voltage V od via the voltage divider Rj , R 2 , and multiplying the reference signal V ac re by the deviation from the desired output voltage level, so as to adjust the effective reference signal to the load.
- BCM operation is achieved by turning on the power switch Q ⁇ (i.e.
- auxiliary winding L 2 that is coupled to the main inductor L in .
- the auxiliary winding L 2 produces a positive voltage V tr whenever the inductor current reaches zero.
- the same L 2 winding can also be used, together withD 3 , R tr a.nd C b , to generate the auxiliary power supply + V CC required for the controller.
- a major drawback of the prior art BCM converter is the need to sense the converter's input voltage, namely the line voltage after rectification. Due to the switching effects, the input voltage V ivR is normally noisy and is susceptible to interference that may distort the reference signal and hence the controlled input current. Furthermore, the extra contact required for sensing the input current increases the number of pins of a modular device, if built according to conventional BCM schemes.
- US Patent No. 5,742,151 discloses a PFC converter that provides unity PF by sensing only a current in the PFC circuit and a DC supply voltage.
- the feature of sensing the input voltage is not used.
- conventional methods that do not sample the input voltage cannot operate in the BCM, but only in CCM and, with some inferior performance, in DCM.
- the reason for this is the fundamental difference between CCM, DCM and BCM.
- the switching frequency is constant, whereas in BCM, the switching frequency has to adaptively change over the line voltage cycle.
- the reason for the need to change the switching frequency in BCM is that at the end of each T OFF the inductor current must reach zero.
- US Patent No. 5,047,912 discloses a modular four terminal solution to the realization of APFC converters.
- the control scheme applies a signal differentiator to generate a reference signal to the feedback loop.
- differentiators are extremely sensitive to noise that may corrupt the output signal. This is of particular concern in the environment of a switching circuit such as a Pulse Width Modulation (PWM) Boost converter, which is characterized by high frequency noise injection.
- PWM Pulse Width Modulation
- Boost Pulse Width Modulation
- Another drawback of the solution of said patent is that the reference feedback signal is derived from the line voltage. Since this signal normally includes noise, the derived reference signal may be highly corrupted by signals that distort the shape of the desired controlled line current.
- APFC converters can be built in either of the following ways:
- a typical prior art subcircuit is included: the input rectifier D x , inductor L in , power switch (such as a power MOSFET) Q , a high frequency main diode D 2 , an output capacitor C 0 , an IC APF Controller with some auxiliary passive components, current sensing resistor R s and an output voltage divider Rj and R 2 .
- This physical embodiment has many disadvantages. High cost and low reliability are normally associated with a design that includes a large component count.
- the rather massive wiring required to realize the APFC converter makes it highly susceptible to Electro Magnetic Interference (EMI) and 'ground' noises. Consequently, this embodiment is highly undesirable, as it has many economic and engineering drawbacks;
- EMI Electro Magnetic Interference
- Another possible embodiment of the APFC converter is to implement it as one block that includes all major components.
- the complete APFC converter is packaged as a single unit that includes all the required circuitry.
- This embodiment has the advantage of providing a solution to the problem mentioned in relation to Fig. 6.
- a problem of heat removal arises in this case.
- the cost of such a solution is normally high. This is of special importance considering the fact that the APFC converter is an add-on to the equipment - it is not required for its basic operation, but only to comply with line interface standards.
- Another disadvantage of this approach is the fact that it is compatible with IC technology and hence cannot benefit from the relatively low production cost of microelectronics.
- a further drawback of the one-block construction is the fact that all heat dissipating components, such as the main switch, diodes and inductor, are in close proximity to each other and hence the problem of heat removal could limit the ability of such a module to handle high power levels. Also, close proximity components that generate considerable EMI necessitates the inclusion of heavy shielding and filtering that increase complexity and cost and lower the efficiency.
- APFC controllers that operate in DCM mode, but which do not require sensing the input voltage. It would be further highly desirable that the same circuit be able to operate both in BCM mode and, by employing slight hardware or software changes, in CCM mode. Moreover, it would be highly advantageous to have APFC controllers of modular construction that are also compatible with current microelectronics technologies.
- PF Power Factor
- APFC Active Power Factor Correction
- the present invention is directed to a power factor correction apparatus, for a switching power supply fed by an array of rectifying diodes and consisting of at least an input inductor, a contact of which is connected in series with a contact of the array, and of a power switch connected between the other contact of the array and the other contact of the input inductor, that comprises: a) circuitry for identifying, in each cycle determined by the switching frequency of the power supply, whenever the instantaneous value of the current through the inductor reaches a minimal value; b) circuitry for switching the power switch to its conducting state in response to the minimal current through the inductor; c) circuitry for reflecting the current flowing through the inductor by a measurable or simulated parameter; and d) circuitry for providing indication, in each cycle, by using the parameter, the indication being related to the timing until the peak value of the current, that corresponds to a specific load, has been essentially reached, or to the time from the moment that the current reaches the minimal value until the timing, and for switching the power
- the apparatus further comprises: a) circuitry for sampling the output voltage; b) circuitry for generating a signal which reflects the deviation of the output voltage from a predetermined voltage value; and c) circuitry for modifying the value of one or more of the parameters in response to the signal, and for adjusting the timing at which the power switch is switched to its non-conducting state, thereby allowing the inductor current to reach a different peak value, for compensating the deviation, while keeping the portion, in each cycle, of the time period during which the power switch is in its non-conducting state.
- the minimal value may be essentially zero, especially when the apparatus operates near border-line mode.
- the deviation in the output voltage may result from changes in the load or in the power line voltage.
- the circuitry for reflecting the current flowing through the inductor comprises: a) a capacitor that is charged discharged by a combination of a constant current source being inactive during the time periods when the power switch is in its conducting state and a dependent current source for discharging the capacitor with a current that is proportional to the input inductor current, such that the voltage over the capacitor inversely reflects the value of/changes in, the current flowing through the input inductor; b) a first comparator, connected to the capacitor, for switching the power switch to its non-conducting state and for activating the constant current source whenever the voltage across the capacitor reaches a predetermined reference voltage; and c) a second comparator that samples the current flowing through the input inductor, for switching the power switch to its conducting state and for disactivating the constant current source whenever the current flowing through the input inductor reaches an essentially zero value.
- the apparatus may comprise: a) a timing circuitry for continuously sampling the output voltage of the converter and the input current passing through the converter, and for generating a cyclic intermediate signal, having in each cycle a portion of positive slope and a portion of negative slope, the positive slope having a duration being equal to the time required for the input current to decline from its maximum value, during the cycle, to a zero value, and the negative slope having a duration being equal to the time it takes the intermediate signal to decline from its maximum value to a reference value; b) a first controllable current source, for adjusting the rising rate of the positive slope portion of the intermediate signal; c) a second controllable current source, coupled to the timing circuitry, for adjusting the rate of decline of the negative portion of the intermediate signal and the rising rate of the positive slope portion of the intermediate signal, the second controllable current source having a magnitude that is smaller than the magnitude of the first controllable current source; d) a first controllable switch, coupled to the output of the controlled converter, for controlling the input
- the timing circuitry comprises: a) a first means for comparing a voltage being a representative of the output voltage of the converter with a voltage reference; b) a second means for sensing whenever the input current reaches a zero value; and c) means for multiplying the output of the first means by a voltage being a representative of the input current, for adjusting the second controllable current source.
- the driving circuit may comprise a flip-flop, coupled to the timing circuit, that generates switching signal from the intermediate signal, for switching the first controllable switch.
- the first controllable current source may be controlled by a voltage being a representative of the output voltage of the converter that is controlled.
- the second controllable current source may be controlled by a voltage being a representative of the output voltage of the converter being controlled.
- the timing circuitry may comprise a capacitor, coupled to the second switch, to the second controllable current source and to one input of an amplifier, the capacitor being charged whenever the second switch is closed and discharged whenever the second switch is open, the voltage of the capacitor being the intermediate signal and compared to a reference voltage coupled to a second input of the amplifier of which output is coupled to the flip-flop.
- the timing circuitry may comprise: a) an 'Absolute-value' module (ABS), the input of which is coupled to the first and second current sources whenever the second switch is closed, and to the second current source whenever the second switch is open; b) a Voltage-Controlled-Oscillator (VCO) module, coupled to the output of the ABS module, having an output clock signal of which frequency being dependent on the value of the magnitude of the current being delivered from the output of the ABS module to the input of the VCO module; and c) an 'up-down' counter, coupled to the NCO module and to the flip-flop, the counter counts 'up' whenever the second switch is closed and 'down' whenever the second switch is open, the 'up' and 'down' counting rates are a function of the NCO frequency being a representative of the absolute value of the magnitude of the current passing through the input of the ABS module.
- ABS 'Absolute-value' module
- VCO Voltage-Controlled-Oscillator
- the timing circuitry may further comprise a first oscillator having a constant frequency, for allowing to initialize/excite the operation of the converter and/or to resume normal operation, the first oscillator being inoperative in normal operation of the converter and a second oscillator having a constant frequency, for allowing to operate the converter at constant frequency, the frequency being adjusted so as to maintain the input current of the converter above zero.
- the first oscillator and the second oscillator may be the same oscillator, that further comprises means for programming and/or for configuring and/or for switching the oscillator.
- the first current source adjusts a rate of decline of the intermediate signal and the second current source adjusts a rate of rise of the intermediate signal, the second controllable current source being greater in magnitude in comparison with the first controllable current source.
- the zero value input current of the converter may be sensed by means of an analog comparator, by digital means or by a second inductor, being inductively coupled to the first inductor, the first inductor induces voltage on the second inductor.
- control circuit comprises: a) a first means for digitizing the output voltage of the converter; b) a second means for digitizing the input current of the converter; and c) means for processing the data gathered from the first and second digitizing means, for generating the switching signal for the first controllable switch.
- the control circuit components may be contained in a module that comprises five external contacts or in an integrated circuit (IC).
- the input current sensing resistor and/or the output diode and/or the power switch may be contained in, or being external to, a module that comprises five external contacts and/or to an integrated circuit (IC).
- Fig. 1 illustrates a PWM Boost converter (prior art);
- Fig. 2 illustrates exemplary Inductor current in Continuous Conduction Mode (CCM) for the converter illustrated in Fig. 1;
- Fig. 3 illustrates exemplary Inductor current in Discontinuous Conduction Mode (DCM) for the converter illustrated in Fig. 1;
- Fig. 4 illustrates exemplary Inductor current in Borderline Conduction Mode (BCM) for the converter illustrated in Fig. 1;
- Fig 5 illustrates a BCM APFC converter (prior art);
- Fig 6 illustrates a typical construction of an APFC converter (prior art);
- Fig. 7 illustrates one block embodiment of a APFC controller (prior art).
- Fig. 8 illustrates an APFC controller with no sensing of input voltage (prior art);
- Fig. 9 illustrates a general layout and functioning of the BCM APFC controller, according to a preferred embodiment of the invention;
- Fig. 10 illustrates exemplary control waveforms for the exemplary controller illustrated in Fig. 9;
- Fig. 11 illustrates the general layout and functioning of one possible embodiment in which 'k' is a variable, according to one embodiment of the invention.
- Fig. 12 illustrates the general layout and functioning of another possible embodiment in which the 2 j is a variable, according to one embodiment of the invention.
- Fig. 13 illustrates exemplary realization of a circuit in which I is a variable in accordance with the general layout illustrated in Fig. 12;
- Fig. 14 illustrates exemplary realization of a circuit in which 'k' is a variable in accordance with the general layout illustrated in Fig. 11;
- Fig.15 illustrates a general layout and functioning, showing 'End of T Q PP ' 'pick-up' from inductor voltage, according to another embodiment of the invention;
- Fig. 16 illustrates a general layout and functioning, showing 'End of TOFF ' 'pick-up' from power transistor voltage, according to still another embodiment of the invention
- Fig. 17 illustrates a first general layout and functioning according to which the CCM APFC is implemented without sensing the input voltage, according to still another embodiment of the invention
- Fig. 18 illustrates a second general layout and functioning according to which the CCM APFC is implemented without sensing the input voltage, according to still another embodiment of the invention
- Fig. 19 illustrates a general functioning and layout of a digital APFC controller, according to one embodiment of the invention
- Fig. 20 illustrates a general functioning and layout of a 'microprocessor-based' APFC controller, according to another embodiment of the invention
- Fig. 21 illustrates a general functioning and layout of a 'counter -based' APFC controller, according to still another embodiment of the invention.
- Fig. 22 illustrates a practical example of a 'five-pin' electronic module for implementing APFC circuit in BCM mode, according to a preferred embodiment of the invention
- Fig. 23 illustrates a simulated boost inductor (Lin) current and capacitor (Cc) voltage for the exemplary boost converter illustrated in Fig. 9;
- Fig. 24 illustrates a simulated input voltage, input current and average input current for the exemplary boost converter illustrated in Fig. 9, and in accordance with the controlling signal depicted in Fig. 23;
- Fig. 25 illustrates a 'five-pin' modular implementation of an APFC system, the module of which detailed circuitry is depicted in Fig. 22, according to one embodiment of the invention; and Fig. 26 illustrates microelectronics unit implementation, according to another embodiment of the invention.
- the present invention relates to a method for realizing an APFC converter that forces the system to remain in the Borderline Conduction Mode (BCM) without sampling the voltage at the input of the converter.
- BCM Borderline Conduction Mode
- the novel control methods can also be utilized for APFC operating in CCM mode.
- Two current sources are utilized for charging a capacitor for a first duration being equal to "T 0FF " , and for discharging the same capacitor for a second duration being equal to "T 0N ".
- the capacitor may be either in a state of 'charging' or in a state of 'discharging'.
- T OFF depends only on the time it takes the inductor current to reach zero. On the other hand, the longer the duration "T 0FF " is, the higher the voltage level of the capacitor, resulting in longer
- forcing the converter to remain in the BCM mode is achieved by allowing the inductor current to reach zero, and by forcing the inductor current to increase immediately after it reaches zero.
- a comparator senses the inductor zero current and forces the output of a 'flip-flop' to be in its 'High' state.
- a power switch coupled to said flip-flop, is closed to allow the Inductor current to increase, thereby allowing energy to accumulate in the Inductor.
- the controller includes: (1) a timing circuit that continuously samples/senses the output voltage of the converter being controlled, and also the input current passing through the converter.
- the timing circuit generates a cyclic intermediate signal, which has in each cycle a portion of positive slope and a portion of negative slope.
- the rate of the positive slope depends on the magnitudes and flow direction of two controllable current sources, and the duration of the positive slope portion equals to the time it takes the converter's input current to decline from its maximum value (i.e. in a specific cycle), to a zero value.
- the negative slope duration equals to the time it takes the intermediate signal to decline from its maximum value to a reference value, and the rate of the negative slope depends on one controllable current source, (2) A first controllable current source (i.e.
- a second controllable current source (i.e. I 2 ), the magnitude of which is smaller than the first current I ⁇ , is constantly coupled to the timing such a way that its current and the current of the first current source flow in opposite directions into the timing circuit whenever the positive slope portion of the intermediate signal should be generated. In this way, the second current source I 2 also affects the adjustment of the rate of rise of the negative portion of the intermediate signal.
- the negative slope rate is determined only by the second current source I 2 , (4) a first controllable switch, which is coupled to the output of the controlled converter, for controlling the input current of said converter, (5) a second controllable switch for intermittently connecting and disconnecting the first current source / j , for causing the intermediate signal to rise and decline, and (6) a drive circuit, which is coupled to the timing circuitry.
- the drive circuit generates a switching signal from the intermediate signal for switching the first controllable switch, thereby controlling the input current of the converter.
- the timing function performed by the timing circuit is implemented by a capacitor being charged and discharged in accordance with the current passing through it; namely a positive current (i.e., I and I 2 ) whenever a positive slope portion of the intermediate signal is to be generated, and a negative current (-I 2 ) whenever a negative slope portion of the intermediate signal is to be generated. Therefore, the voltage of the capacitor forms the intermediate signal, from which a switching signal is generated by a flip-flop, for driving the first switch.
- the timing function performed by the timing circuit is implemented by a digital counter.
- This implementation utilizes two current sources in exactly the same way as described regarding the capacitor, except that in this implementation the 'charging' phase is replaced by "counting-up” by the counter, and the 'discharging' phase is replaced by a "counting-down" counter.
- the control circuit comprises Analog-to-Digital (AD) modules to digitize samplings of the output voltage and input current of the converter, and a microprocessor that manipulates the digitized values for generating switching signals for the first switch.
- AD Analog-to-Digital
- a novel feature of the invention disclosed herein is that an APFC converter operates in BDM mode without sampling the input voltage of the converter. This makes the converter less sensitive to noise and facilitates a modular construction of the electronics in either monolithic (i.e., an electronic microchip), hybrid or discrete implementation. These features reduce the cost of APFC converters built in accordance with this invention and improve their performance.
- Another feature of the present invention is the application of control methods that reduce the number of interconnections and wiring, and combining the switch and associated control circuitry into one module. This allows the construction of a complete APFC converter from five basic and independent elements: the input rectifier, inductor, switch module, output diode and output capacitor.
- the diode within the main switch assembly, the number of components for a complete system is reduced to four. Since the number of interconnections is minimal the power flow is simple, resulting in minimum interference to other parts of the equipment. At the same time, the streamlined construction minimizes the susceptibility of the circuit to switching noises and hence improve the stability and reliability of the circuit.
- This construction is compatible with microelectronics technology.
- the switch and control module, with or without the output diode can be produced by conventional Silicon based IC technology, making this sub-assembly a relatively low cost component.
- the invention also provides a cost-effective solution to the problem of efficiently generating a local supply voltage needed to power the internal circuitry of the switch module.
- the present invention provides a method for optimizing the design of APFC converters in the sense that the APFC can be assembled from basic building blocks that are easy to mount, have high reliability, potentially lower cost and are highly compatible with common heat removal methods, such as heat sinks and fan cooling.
- control strategy and constructional method according to this invention thereby overcome the drawbacks of existing design and control methods, which include many interconnected components, signal differentiating or a costly single module with poor heat management capabilities.
- An important new feature of the invention is the ability to operate the system in either BCM or CCM.
- the prior art APFC is realized using a Boost converter and associated circuitry.
- Some of the components (such as L in and C Q ) are of relatively large size and are not compatible with microelectronics technology.
- Other elements such as the power switch (S i ), the controller and the rectifier diode (D 2 ), axe made of Silicon and can be produced on a single IC chip.
- the embodiment of Fig. 2 includes many individual components and back and forth interconnection that precludes the streamlining of the APFC converter.
- the rectified input voltage V ivR should be sensed and hence, a wire has to be connected between the feed point and the controller.
- a sense line should be connected between the output port (i.e. V 0 ) and the controller (normally after voltage division by R j and R 2 ).
- FIG. 8 An improvement in construction of APFC converters can be obtained by applying a modified control strategy that does not require sensing the input voltage. Such an arrangement is depicted in Fig. 8.
- the operation of this control scheme is as follows: In Fig. 8, voltage (V ⁇ ) is a pulsating voltage having maximum amplitude VQ and duration of T OFF when Q is not conducting. Consequently, the average voltage at point 'a' (V a ) will be:
- T s is the PWM switching period
- V ivR The input voltage fed into the Boost converter (V ivR ), is assumed to be of
- V ivR is the instantaneous low frequency component of V ivR .
- N is a constant and i ina is the low frequency component of the input current (i ina ), then:
- the value of the input resistance and hence the input current can thus be controlled by varying ⁇ .
- V 0 should be maintained constant even if the load (R ⁇ ) varies.
- the output voltage can be maintained constant by closing a feedback loop on the value of ⁇ .
- Fig. 8 schematically illustrates changing the duty cycle of PWM signal that is delivered to the power switch Q x .
- V Rs the voltage that is proportional to the input current
- V e the voltage that is proportional to the output current
- V e the voltage that is proportional to the input current
- V e the voltage that is proportional to the input current
- V e the voltage that is proportional to the input current
- V e the voltage that is proportional to the input current
- V e the output of an error amplifier
- the output signal of the amplifier is proportional to the deviation of the output voltage V 0 from a reference voltage V rej - .
- the product, which is proportional to i ina by a given factor ⁇ is fed to a PWM modulator that controls the value of D 0FF according to (7).
- the PWM modulator is driven by an oscillator having a constant frequency (not shown). Consequently, this conventional method cannot be utilized for operation in BCM mode.
- the duration T 0FF (Fig. 4) is the time it takes the inductor current to drop to zero. Therefore, this period cannot be controlled or modified by the control circuit.
- D 0FF as defined by (3) can still be programmed according to Eq. (7) by adjusting D 0N .
- Fig. 9 schematically illustrates the general functioning and layout of one embodiment of the present invention.
- the solution includes two current sources that feed a capacitor C c (96): an independent current source 91 that produces the current I and a dependent current source 92 that produces a current that is proportional to i ina (i.e. k * i jna ).
- the dependent current source 92 is controlled by the voltage across the sense resistor R s through which i ina is passing.
- the current source 91 is connected to the capacitor via a switch SW (93) that is conducting during the period T 0FF .
- the signal Doff for the duration T 0FF as well as the complementary signal D 0N , axe produced by a flip-flop FF (94) whose state corresponds to D 0N while Q corresponds to Doff.
- the FF (94) is set and reset by two comparators. Comparator Compl produces a reset signal whenever the capacitor voltage (V c ) drops below a reference voltage (V re f ).
- the FF (94) is set when the input current drops to zero.
- An independent oscillator OSC (95) is utilized to initiate and/or trigger the circuit at start-up or in a case of deadlock (i.e., resuming normal operation).
- the OSC is inactive during normal operation, since its frequency is constant and lower than the frequency of the signal at the output of the flip-flop (94), of which signal resets the OSC (95).
- the capacitor C c is charged from level re yj by a current (I - k * i in ⁇ ) and discharged by k * i in ⁇ to return to V rejX .
- the relationship between the voltage across C c (V c ) and the inductor current (i ina ) is depicted in Fig. 10. Duration T 0N is triggered whenever the inductor current drops to zero, while duration T 0FF is triggered whenever the voltage of C c drops to the level of Nrefl.
- the peak voltage of C c (V Cpk ) can be calculated from duration T 0FF and duration T ON :
- Equation (16) implies that either controlling k or I j can adjust the input resistance (Re).
- Fig. 11 illustrates a solution for controlling the variable 'k '. This is accomplished by applying an error amplifier AMPl that produces a signal that is proportional to the deviation of the output voltage (as measured via the divider Rl, R2) from a reference voltage V re f 3 .
- the amplified error signal is fed to one input of an analog multiplier M (97), while VRs, being proportional to i ina , is fed to another input of said analog multiplier M, thereby allowing to control the coefficient 'k' of the dependent current source (92), which is varied so as to keep the output voltage (V 0 ) constant.
- V 0 being a regulated voltage
- the voltage on L in is essentially kept constant, resulting in L in current declining from its peak value to a zero value at a rate which is essentially constant, independent of the load value.
- T 0FF (Fig. 10) changes accordingly, and so does T 0N (i.e. due to corresponding changes in V c p . (Fig. 10).
- D 0FF is kept constant for any value of load current. Only the switching frequency is changed in accordance with the load changes. For example, if the load's current is increased, V 0 tends to decrease.
- AMP1 together with Multiplier
- the current source I can be controlled.
- Fig. 12 illustrates a possible solution for controlling Re by controlling I ⁇ .
- the controllable current source that produces 7 j is realized by a dependent current source 121 (transconductance amplifier).
- the magnitude of I thus, varies whenever the output voltage deviates from the desired value ( re 4 ), thereby balancing the input and output power.
- l changes in accord with changes in £ (these changes being reflected in od ) so as to change the frequency of the control signal (i.e. the signal at the flip-flop output
- controlling '£' can be implemented by a circuit, such as shown in Fig. 13. Multiplying is accomplished by the two-quadrant multiplier, built around Q 3 , ⁇ 2 , Q s .
- the current mirror Q & , Q 9 generates the constant current, and the switching function is built around the pair Q 6 , Q 7 .
- the variable ' J j ' can be controlled, for example, in the way illustrated in Fig. 14.
- error amplifier AMP2 controls the current mirror that generates I ⁇
- k * i tna is constant by the current source built around AMP3 and Q 10 .
- Fig. 15 depicts the option of detecting the zero level by an extra winding L 2 on the main inductor L in .
- An additional method of detection is shown in Fig.
- the example described hereinabove relates to operating an APFC converter in BCM mode. According to the invention, essentially the same apparatus can be exploited as a basis for a CCM-based converter - also without sensing/sampling the input voltage.
- OSC constant frequency oscillator
- Fig. 18 illustrates an alternative embodiment to the control scheme for CCM mode of operation.
- the current k * i ina charges the capacitor C c (96) while the current ⁇ /j -k * i ina ⁇ discharges it.
- the operation of this circuit is analogous to the circuit illustrated in Fig. 17, except that in Fig. 18, the charging and discharging currents are reversed. Since Eq. (14) still holds in this case, CCM APFC operation is assured.
- essentially the same electronic circuit elements are utilized for either operating the converter in CCM mode or in BCM mode. Switching between these two modes is implemented by a minor hardware change and/or by proper software and/or by configuring the oscillator OSC according to the desired mode of operation.
- slope compensation could be formed by adding, for example, a triangular waveform to the voltage V re f[ in Fig. 17.
- the implementation of APFC converter requires using a capacitor C c that is intermittently charged and discharged in each switching cycle.
- the size of this capacitor is a function of the charging current magnitude and the available dynamic range, i.e., the voltage range that can be handled in a given system.
- the required value of the capacitor may be too large for implementation on an IC, thus becoming a drawback whenever a microelectronics solution is desired.
- Another practical problem that may deteriorate the performance of an APFC system is the typical inherent interference of a switch mode system due to spikes. The spikes may cause false triggering of the comparators used in the analog implementation described above.
- the two above-mentioned problems are overcome by performing some modifications in the aforementioned embodiments.
- the capacitor which is intermittently charged and discharged, functions for evaluating the time period (i.e., T 0N , Fig. 10), after which the Inductor is forced to deliver its stored energy to the load/output. Therefore, the 'timing' function can be performed in a more straightforward method, i.e., by using a counter.
- the capacitor is replaced by a programmable counter that can be realized by either hardware or software.
- the analog comparators are replaced by digital circuitry.
- Fig. 19 schematically illustrates layout of a power factor correction circuit that utilizes a digital controller.
- the Digital Controller (191) receives signals that are proportional to the input current (i ina ) and output voltage
- V 0 V 0
- Q x the required gate signals for the switch Q x .
- the process utilized by the digital controller emulates the charge and discharge comparison scheme relating to the analog embodiments.
- implementing the Digital Controller is carried out in the ways depicted in Figs. 20 and 21.
- Fig. 20 schematically illustrates the implementation of a digital controller.
- digitizing is carried out by an Analog-to-Digital converter (A/D) 200b (for sampling the output voltage NO) and 200d (for sampling the input current i ina ), and the process is implemented as a program code in the microcontroller ( ⁇ C) 200c.
- A/D Analog-to-Digital converter
- ⁇ C microcontroller
- an electronic "chip” or module 200 is produced such that it contains some, or all of, the elements 200a to 200e.
- Digital implementation such as depicted in Fig. 20 is advantageous, since several critical problems, such as overloading, shortening or disconnecting the output are solved by implementing flexible mathematical manipulations by the microprocessor 200c. An analog implementation would have required additional circuitry to solve these problems. Other mathematical manipulations, such as digital filtering, are also easy to carry out with the microprocessor 200c.
- Fig. 21 schematically illustrates another implementation of a digital controller.
- the capacitor C c (for example, in Fig. 11) is replaced by an 'up-down' counter 211 the count rate of which is controlled by a Voltage Controlled Oscillator (VCO) 212, which in turn is connected to the charging and discharging currents after passing the absolute-value stage (ABS) 213.
- VCO Voltage Controlled Oscillator
- ABS absolute-value stage
- the counter counts up, while 'Q' is at 'Low' state and L in delivers energy to the output of the controlled converter (i.e. load).
- the output 'Q' of the flip-flop switches to 'Low' state, thereby opening switch Q x and forcing said L in to deliver energy stored in it to the output/load.
- the counter counts 'up' to generate a new controlling cycle.
- the ABS module depicted in Fig. 21 is required, since the VCO module (212) operates with positive signal at its input. However, distinguishing a positive going current (i.e. I ⁇ -k*i ina , Fig.21) from a negative going current (i.e. k * i ina ) is carried out by changing the state of the counter, i.e., from 'up' ('+' sign) counting to 'down' ('-' sign) counting, and vice versa. For example, whenever output Q of the flip-flop is at 'High' state, switch 93 is closed, thereby causing a total positive current to flow through the ABS module (213), in which case the counter counts up.
- a positive going current i.e. I ⁇ -k*i ina
- Fig.21 distinguishing a positive going current (i.e. I ⁇ -k*i ina , Fig.21) from a negative going current (i.e. k * i ina
- the 'counter-based' controller depicted in Fig. 21 is implemented by discrete modules (such as 91, 92, 94, 211 to 215), or by affiliating these modules functions into one electronic integrated chip (IC) or module (210).
- IC electronic integrated chip
- Fig. 22 illustrates an example for implementing an APFC converter according to a preferred embodiment of the invention.
- This circuit follows the concept of controlling variable 'k' (see Fig. 11).
- the input current is sensed by Rill, filtered out by R113, C104 and translated to the collector of Q106.
- the pair Q103, Q104 and Q106 form a two quadrant multiplier such that the current at the collector of Q104 is controlled by the error signal formed by subtracting from a voltage proportional to the out Vo, the reference voltage at the junction of R103, R104.
- the collector current of Q104 is controlled by the deviation of V 0 from desired level.
- the current source I ⁇ is implemented by the current mirror pair Q101, 102.
- the current ii forced by Q102 is switched by Q105 such that during D 0N I is shorted to ground and it does not charge C c .
- C c is thus charged and discharged according to the programming rule (12, 13).
- the triggers for the FF are obtained by comparators COMPl and COMP2 that detect when C c discharge reaches V re y ⁇ and by COMP2 that detects when the input current drops to zero.
- the FF is formed by two NAND gated N3, N4 while the oscillator is built around N6. The rest of the circuit: gate drivers M102, M103, etc., follow the standard design practice.
- a 'five-pin' module 220 there is illustrated an option of including the control circuit components in a 'five-pin' module 220, in accordance with the present invention.
- a module is advantageous, since it simplifies and shortens the design phase of APFC systems.
- a module 220 As depicted in Fig. 22.
- some components may be left outside this module.
- input current 'sense' resistor Rill (Fig. 22) and/or main diode D112 and/or main transistor (i.e., power switch) M101 may be left outside module 220.
- the auxiliary power supply for powering module 220 may be external or internal.
- Fig. 23 illustrates a simulated boost inductor (L in ) current and capacitor
- the current of the inductor starts to decrease from point 4b until it reaches zero value (i.e., at point 5), and another cycle is generated (i.e., a 'SET' signal is generated at 6a, etc.).
- the frequency of the control signal illustrated in Fig. 23 is about 50 kHz.
- the control circuitry dynamically changes the control frequency in order to meet the circuit conditions, such as the size of the inductor and the load at the output of the converter. Consequently, the control frequency may deviate within a large range; e.g., 50-100 kHz.
- Fig. 24 illustrates a simulated input voltage, input current and average input current for the exemplary boost converter illustrated in Fig. 9, and in accordance with the controlling signal depicted in Fig. 23.
- the average input current follows the input voltage in time and amplitude proportionality; i.e., the input voltage and current are maintained in phase relative to each other, thereby providing unity power factor.
- the essence of the present invention is implementing a BCM without sensing the converter's input voltage, which is advantageous, since it allows generating a 'cleaner' control signal (i.e., with far fewer spikes and distortions), which reflects in an average input current that is nearly free of interference and distortions, as can be seen in Fig. 24.
- Fig. 25 illustrates, in accordance with the present invention, a typical modular APFC system, wherein the control circuitry is contained in a 'five-pin' module 250, such as that depicted in Fig. 22 (220).
- a modular implementation such as that depicted in Fig. 25, reduces the size and price of the APFC systems.
- Fig. 26 illustrates implementing an APFC controller by microelectronics.
- an integrated circuit (IC) 260 performs the control function of the APFC system.
- the IC implementation is also advantageous in reducing the size and price of APFC systems.
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Abstract
Description
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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GB0405656A GB2395577B (en) | 2001-08-16 | 2001-08-16 | PFC apparatus for a converter operating in the borderline conduction mode |
PCT/IL2001/000776 WO2003017453A1 (en) | 2001-08-16 | 2001-08-16 | Pfc apparatus for a converter operating in the borderline conduction mode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/IL2001/000776 WO2003017453A1 (en) | 2001-08-16 | 2001-08-16 | Pfc apparatus for a converter operating in the borderline conduction mode |
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WO2003017453A1 true WO2003017453A1 (en) | 2003-02-27 |
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PCT/IL2001/000776 WO2003017453A1 (en) | 2001-08-16 | 2001-08-16 | Pfc apparatus for a converter operating in the borderline conduction mode |
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GB (1) | GB2395577B (en) |
WO (1) | WO2003017453A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007121945A2 (en) * | 2006-04-21 | 2007-11-01 | Tridonicatco Gmbh & Co.Kg | Boost power factor correction circuit (boost pfc) |
WO2007121944A2 (en) * | 2006-04-21 | 2007-11-01 | Tridonicatco Gmbh & Co. Kg | Boost power factor correction circuit (boost pfc) |
CN102946186A (en) * | 2012-11-06 | 2013-02-27 | 西安开容电子技术有限责任公司 | Active harmonic suppressing mechanism |
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US5991172A (en) * | 1996-06-21 | 1999-11-23 | Delta Electronics, Inc. | AC/DC flyback converter with improved power factor and reduced switching loss |
US6043633A (en) * | 1998-06-05 | 2000-03-28 | Systel Development & Industries | Power factor correction method and apparatus |
EP1049239A1 (en) * | 1997-12-09 | 2000-11-02 | Motorola, Inc. | Power factor correction controller circuit |
US6259614B1 (en) * | 1999-07-12 | 2001-07-10 | International Rectifier Corporation | Power factor correction control circuit |
-
2001
- 2001-08-16 WO PCT/IL2001/000776 patent/WO2003017453A1/en active Application Filing
- 2001-08-16 GB GB0405656A patent/GB2395577B/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US5991172A (en) * | 1996-06-21 | 1999-11-23 | Delta Electronics, Inc. | AC/DC flyback converter with improved power factor and reduced switching loss |
EP1049239A1 (en) * | 1997-12-09 | 2000-11-02 | Motorola, Inc. | Power factor correction controller circuit |
US6043633A (en) * | 1998-06-05 | 2000-03-28 | Systel Development & Industries | Power factor correction method and apparatus |
US6259614B1 (en) * | 1999-07-12 | 2001-07-10 | International Rectifier Corporation | Power factor correction control circuit |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007121945A2 (en) * | 2006-04-21 | 2007-11-01 | Tridonicatco Gmbh & Co.Kg | Boost power factor correction circuit (boost pfc) |
WO2007121944A2 (en) * | 2006-04-21 | 2007-11-01 | Tridonicatco Gmbh & Co. Kg | Boost power factor correction circuit (boost pfc) |
WO2007121945A3 (en) * | 2006-04-21 | 2008-05-22 | Tridonicatco Gmbh & Co Kg | Boost power factor correction circuit (boost pfc) |
WO2007121944A3 (en) * | 2006-04-21 | 2008-06-12 | Tridonicatco Gmbh & Co Kg | Boost power factor correction circuit (boost pfc) |
CN101427450B (en) * | 2006-04-21 | 2013-03-20 | 赤多尼科阿特可两合股份有限公司 | Boost power factor correction circuit (boost PFC) |
CN102946186A (en) * | 2012-11-06 | 2013-02-27 | 西安开容电子技术有限责任公司 | Active harmonic suppressing mechanism |
Also Published As
Publication number | Publication date |
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GB2395577B (en) | 2005-07-27 |
GB2395577A (en) | 2004-05-26 |
GB0405656D0 (en) | 2004-04-21 |
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