WO2003010826A3 - Verfahren zur herstellung eines vertikaltransistors in einem graben - Google Patents

Verfahren zur herstellung eines vertikaltransistors in einem graben Download PDF

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Publication number
WO2003010826A3
WO2003010826A3 PCT/EP2002/007593 EP0207593W WO03010826A3 WO 2003010826 A3 WO2003010826 A3 WO 2003010826A3 EP 0207593 W EP0207593 W EP 0207593W WO 03010826 A3 WO03010826 A3 WO 03010826A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
lateral wall
semiconductor substrate
trench
grow
Prior art date
Application number
PCT/EP2002/007593
Other languages
English (en)
French (fr)
Other versions
WO2003010826A2 (de
Inventor
Albert Birner
Joern Luetzen
Original Assignee
Infineon Technologies Ag
Albert Birner
Joern Luetzen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Albert Birner, Joern Luetzen filed Critical Infineon Technologies Ag
Priority to US10/484,562 priority Critical patent/US7208370B2/en
Priority to JP2003516105A priority patent/JP4056974B2/ja
Priority to EP02754852A priority patent/EP1410441A2/de
Priority to KR1020047001162A priority patent/KR100581773B1/ko
Publication of WO2003010826A2 publication Critical patent/WO2003010826A2/de
Publication of WO2003010826A3 publication Critical patent/WO2003010826A3/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)

Abstract

Zur Herstellung eines Vertikaltransistors wird ein Graben (4) bereitgestellt, dessen Seitenwand (6) von einem einkristallinen Halbleitersubstrat (2) und dessen Boden (8) von einem polykristallinen Halbleitersubstrat (10) gebildet wird. Zwischen der Seitenwand (6) und dem Boden (8) ist ein Übergangsbereich (12) aus einem isolierenden Material angeordnet. Selektiv zum Material des Übergangsbereichs (12) wird eine Halbleiterschicht abgeschieden, so daß auf der Seitenwand (6) eine epitaktische Halbleiterschicht (24) und auf dem Boden (8) eine Halbleiterschicht (26) aufwächst, zwischen denen ein Zwischenraum verbleibt. Die abgeschiedenen Halbleiterschichten (24, 26) werden mit einem dünnen, einen Stromfluß nur teilweise begrenzenden Dielektrikum (28) bedeckt und der Zwischenraum mit einem leitfähigen Material (30) gefüllt. Bei einer nachfolgenden Wärmebehandlung diffundieren Dotierstoffe aus dem leitfähigen Material (30) in die epitaktische Halbleiterschicht (26) und bilden dort ein Dotierungsgebiet (44). Das dünne Dielektrikum (28) begrenzt einerseits die Diffusion der Dotierstoffe in das Halbleitersubstrat (2) und andererseits verhindert es die Ausbreitung von Kristallgitterfehlern in die epitaktische Halbleiterschicht (26).
PCT/EP2002/007593 2001-07-26 2002-07-08 Verfahren zur herstellung eines vertikaltransistors in einem graben WO2003010826A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US10/484,562 US7208370B2 (en) 2001-07-26 2002-07-08 Method for fabricating a vertical transistor in a trench, and vertical transistor
JP2003516105A JP4056974B2 (ja) 2001-07-26 2002-07-08 トレンチに垂直トランジスタを製造する方法、および垂直トランジスタ
EP02754852A EP1410441A2 (de) 2001-07-26 2002-07-08 Verfahren zur herstellung eines vertikaltransistors in einem graben
KR1020047001162A KR100581773B1 (ko) 2001-07-26 2002-07-08 트렌치 내에 수직 트랜지스터를 제조하는 방법, 수직 트랜지스터 및 이를 포함하는 반도체 제품

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10136333.8 2001-07-26
DE10136333A DE10136333A1 (de) 2001-07-26 2001-07-26 Verfahren zur Herstellung eines Vertikaltransistors in einem Graben sowie Vertikaltransistor

Publications (2)

Publication Number Publication Date
WO2003010826A2 WO2003010826A2 (de) 2003-02-06
WO2003010826A3 true WO2003010826A3 (de) 2003-09-25

Family

ID=7693112

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/007593 WO2003010826A2 (de) 2001-07-26 2002-07-08 Verfahren zur herstellung eines vertikaltransistors in einem graben

Country Status (7)

Country Link
US (1) US7208370B2 (de)
EP (1) EP1410441A2 (de)
JP (1) JP4056974B2 (de)
KR (1) KR100581773B1 (de)
DE (1) DE10136333A1 (de)
TW (1) TW579578B (de)
WO (1) WO2003010826A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10233916C1 (de) * 2002-07-25 2003-08-21 Infineon Technologies Ag Verfahren zur Herstellung eines vertikalen Transistors sowie Halbleiterspeicherzelle mit einem Grabenkondensator und einem zugehörigen vertikalen Auswahltransistor
DE10328634B3 (de) * 2003-06-26 2004-10-21 Infineon Technologies Ag Verfahren zur Herstellung eines Buried-Strap-Kontakts für einen Speicherkondensator
US7485910B2 (en) * 2005-04-08 2009-02-03 International Business Machines Corporation Simplified vertical array device DRAM/eDRAM integration: method and structure
WO2007100803A1 (en) * 2006-02-23 2007-09-07 Vishay-Siliconix Process for forming a short channel trench mosfet and device
US7521332B2 (en) * 2007-03-23 2009-04-21 Alpha & Omega Semiconductor, Ltd Resistance-based etch depth determination for SGT technology
US8021563B2 (en) * 2007-03-23 2011-09-20 Alpha & Omega Semiconductor, Ltd Etch depth determination for SGT technology
US7872297B2 (en) * 2007-04-17 2011-01-18 Snu R&Db Foundation Flash memory device and fabricating method thereof comprising a body recess region
TWI413191B (zh) * 2008-01-02 2013-10-21 Nanya Technology Corp 記憶元件、記憶元件陣列及其製造方法
KR101040445B1 (ko) * 2008-09-03 2011-06-09 이동현 보빈 지지축에 간섭되지 않는 구조의 염색용 보빈 커버
KR101040397B1 (ko) * 2008-09-11 2011-06-09 이동현 걸림턱을 갖는 고정바가 조립되는 염색용 보빈
US7915672B2 (en) * 2008-11-14 2011-03-29 Semiconductor Components Industries, L.L.C. Semiconductor device having trench shield electrode structure
WO2015097798A1 (ja) * 2013-12-25 2015-07-02 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 柱状半導体装置の製造方法
CN112582260B (zh) * 2020-12-04 2023-08-22 杭州芯迈半导体技术有限公司 沟槽型mosfet及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365097A (en) * 1992-10-05 1994-11-15 International Business Machines Corporation Vertical epitaxial SOI transistor, memory cell and fabrication methods
EP0971414A1 (de) * 1998-06-15 2000-01-12 Siemens Aktiengesellschaft Grabenkondensator mit Isolationskragen und vergrabenen Kontakt und entsprechendes Herstellungsverfahren
US6144054A (en) * 1998-12-04 2000-11-07 International Business Machines Corporation DRAM cell having an annular signal transfer region
US6262448B1 (en) * 1999-04-30 2001-07-17 Infineon Technologies North America Corp. Memory cell having trench capacitor and vertical, dual-gated transistor
DE10113187C1 (de) * 2001-03-19 2002-08-29 Infineon Technologies Ag Verfahren zur Herstellung eines Grabenkondensators einer Speicherzelle eines Halbleiterspeichers
WO2002073657A2 (de) * 2001-03-09 2002-09-19 Infineon Technologies Ag Halbleiterspeicherzelle mit grabenkondensator und verfahren zu ihrer herstellung

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093614A (en) 1998-03-04 2000-07-25 Siemens Aktiengesellschaft Memory cell structure and fabrication
DE10011889A1 (de) * 2000-03-07 2001-09-20 Infineon Technologies Ag Speicherzelle mit Graben und Verfahren zu ihrer Herstellung

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365097A (en) * 1992-10-05 1994-11-15 International Business Machines Corporation Vertical epitaxial SOI transistor, memory cell and fabrication methods
EP0971414A1 (de) * 1998-06-15 2000-01-12 Siemens Aktiengesellschaft Grabenkondensator mit Isolationskragen und vergrabenen Kontakt und entsprechendes Herstellungsverfahren
US6144054A (en) * 1998-12-04 2000-11-07 International Business Machines Corporation DRAM cell having an annular signal transfer region
US6262448B1 (en) * 1999-04-30 2001-07-17 Infineon Technologies North America Corp. Memory cell having trench capacitor and vertical, dual-gated transistor
WO2002073657A2 (de) * 2001-03-09 2002-09-19 Infineon Technologies Ag Halbleiterspeicherzelle mit grabenkondensator und verfahren zu ihrer herstellung
DE10113187C1 (de) * 2001-03-19 2002-08-29 Infineon Technologies Ag Verfahren zur Herstellung eines Grabenkondensators einer Speicherzelle eines Halbleiterspeichers

Also Published As

Publication number Publication date
KR20040017837A (ko) 2004-02-27
WO2003010826A2 (de) 2003-02-06
JP4056974B2 (ja) 2008-03-05
TW579578B (en) 2004-03-11
DE10136333A1 (de) 2003-03-06
JP2004536466A (ja) 2004-12-02
US20040256665A1 (en) 2004-12-23
US7208370B2 (en) 2007-04-24
EP1410441A2 (de) 2004-04-21
KR100581773B1 (ko) 2006-05-23

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