WO2002099871A3 - Kunststoffgehäuse mit mehreren halbleiterchips und einer umverdrahtungsplatte sowie ein verfahren zur herstellung des kunststoffgehäuses in einer spritzgussform - Google Patents
Kunststoffgehäuse mit mehreren halbleiterchips und einer umverdrahtungsplatte sowie ein verfahren zur herstellung des kunststoffgehäuses in einer spritzgussform Download PDFInfo
- Publication number
- WO2002099871A3 WO2002099871A3 PCT/DE2002/002044 DE0202044W WO02099871A3 WO 2002099871 A3 WO2002099871 A3 WO 2002099871A3 DE 0202044 W DE0202044 W DE 0202044W WO 02099871 A3 WO02099871 A3 WO 02099871A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- plastic housing
- semiconductor chips
- injection
- producing
- modification plate
- Prior art date
Links
- 238000012986 modification Methods 0.000 title abstract 4
- 230000004048 modification Effects 0.000 title abstract 4
- 239000004065 semiconductor Substances 0.000 title abstract 4
- 238000001746 injection moulding Methods 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01052—Tellurium [Te]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01061—Promethium [Pm]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003502880A JP2004528729A (ja) | 2001-06-05 | 2002-06-05 | 複数の半導体チップ、および配線ボードを有する樹脂パッケージ、ならびにこの樹脂パッケージを射出成形用金型によって製作する方法 |
KR10-2003-7015897A KR20040012896A (ko) | 2001-06-05 | 2002-06-05 | 플라스틱 패키지, 배선 보드, 주입 몰드, 전자 구성 요소,플라스틱 패키지 생성 방법 |
EP02740387A EP1393364A2 (de) | 2001-06-05 | 2002-06-05 | Kunststoffgehäuse mit mehreren halbleiterchips und einer umverdrahtungsplatte sowie ein verfahren zur herstellung des kunststoffgehäuses in einer spritzgussform |
US10/478,682 US20040175866A1 (en) | 2001-06-05 | 2002-06-05 | Plastic housing comprising several semiconductor chips and a wiring modification plate, and method for producing the plastic housing in an injection-molding mold |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10127009A DE10127009A1 (de) | 2001-06-05 | 2001-06-05 | Kunststoffgehäuse mit mehreren Halbleiterchips und einer Umverdrahtungsplatte sowie ein Verfahren zur Herstellung des Kunststoffgehäuses in einer Spritzgußform |
DE10127009.7 | 2001-06-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002099871A2 WO2002099871A2 (de) | 2002-12-12 |
WO2002099871A3 true WO2002099871A3 (de) | 2003-03-06 |
Family
ID=7687076
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2002/002044 WO2002099871A2 (de) | 2001-06-05 | 2002-06-05 | Kunststoffgehäuse mit mehreren halbleiterchips und einer umverdrahtungsplatte sowie ein verfahren zur herstellung des kunststoffgehäuses in einer spritzgussform |
Country Status (7)
Country | Link |
---|---|
US (1) | US20040175866A1 (de) |
EP (1) | EP1393364A2 (de) |
JP (1) | JP2004528729A (de) |
KR (1) | KR20040012896A (de) |
DE (1) | DE10127009A1 (de) |
TW (1) | TW558813B (de) |
WO (1) | WO2002099871A2 (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW567594B (en) | 2001-01-15 | 2003-12-21 | Chuen Khiang Wang | Method of packaging microchip devices, the interposer used therefor and the microchip device packaged thereby |
WO2004001838A1 (en) | 2002-06-19 | 2003-12-31 | Chuen Khiang Wang | Packaging of a microchip device-i |
JP4376781B2 (ja) * | 2002-06-19 | 2009-12-02 | ユナイテッド テスト アンド アセンブリ センター (エス) ピーティーイー リミテッド | マイクロチップパッケージ |
DE10320579A1 (de) * | 2003-05-07 | 2004-08-26 | Infineon Technologies Ag | Halbleiterwafer, Nutzen und elektronisches Bauteil mit gestapelten Halbleiterchips, sowie Verfahren zur Herstellung derselben |
JP4243177B2 (ja) * | 2003-12-22 | 2009-03-25 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US7235423B1 (en) * | 2004-11-05 | 2007-06-26 | Super Talent Electronics, Inc. | Molded memory card production using carrier strip |
US20060223227A1 (en) * | 2005-04-04 | 2006-10-05 | Tessera, Inc. | Molding method for foldover package |
US20080175748A1 (en) * | 2005-08-12 | 2008-07-24 | John Pereira | Solder Composition |
US20070292708A1 (en) * | 2005-08-12 | 2007-12-20 | John Pereira | Solder composition |
DE102005046737B4 (de) | 2005-09-29 | 2009-07-02 | Infineon Technologies Ag | Nutzen zur Herstellung eines elektronischen Bauteils, Bauteil mit Chip-Durchkontakten und Verfahren |
DE102008032330A1 (de) | 2008-07-09 | 2010-01-14 | Akro Plastic Gmbh | Verfahren zur Herstellung von montagefertigen, kunststoffumspritzten Elektronikbauteilen bzw. Elektronikbaugruppen |
US20100081237A1 (en) * | 2008-09-30 | 2010-04-01 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd. | Integrated Circuit Assemblies and Methods for Encapsulating a Semiconductor Device |
KR101012461B1 (ko) * | 2010-07-13 | 2011-02-08 | 이원철 | 본체 코팅층의 수명감지부가 구비된 조리기기 |
CN102315200A (zh) * | 2011-09-02 | 2012-01-11 | 华为终端有限公司 | 一种芯片封装结构、封装方法及电子设备 |
KR20140009799A (ko) | 2012-07-13 | 2014-01-23 | 에스케이하이닉스 주식회사 | 전자 소자의 패키지 및 제조 방법 |
KR101688079B1 (ko) * | 2015-07-13 | 2016-12-20 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 이의 제조 방법 |
PL3168874T3 (pl) | 2015-11-11 | 2021-07-12 | Lipac Co., Ltd. | Obudowa chipów półprzewodnikowych z interfejsem optycznym |
DE102016124270A1 (de) * | 2016-12-13 | 2018-06-14 | Infineon Technologies Ag | Halbleiter-package und verfahren zum fertigen eines halbleiter-package |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997001865A1 (en) * | 1995-06-28 | 1997-01-16 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
US6143581A (en) * | 1999-02-22 | 2000-11-07 | Micron Technology, Inc. | Asymmetric transfer molding method and an asymmetric encapsulation made therefrom |
US6201299B1 (en) * | 1999-06-23 | 2001-03-13 | Advanced Semiconductor Engineering, Inc. | Substrate structure of BGA semiconductor package |
US6210992B1 (en) * | 1999-08-31 | 2001-04-03 | Micron Technology, Inc. | Controlling packaging encapsulant leakage |
US6294825B1 (en) * | 1999-02-22 | 2001-09-25 | Micron Technology, Inc. | Asymmetrical mold of multiple-part matrixes |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4868349A (en) * | 1988-05-09 | 1989-09-19 | National Semiconductor Corporation | Plastic molded pin-grid-array power package |
US5275546A (en) * | 1991-12-30 | 1994-01-04 | Fierkens Richard H J | Plastic encapsulation apparatus for an integrated circuit lead frame and method therefor |
KR100386061B1 (ko) * | 1995-10-24 | 2003-08-21 | 오끼 덴끼 고오교 가부시끼가이샤 | 크랙을방지하기위한개량된구조를가지는반도체장치및리이드프레임 |
US6667560B2 (en) * | 1996-05-29 | 2003-12-23 | Texas Instruments Incorporated | Board on chip ball grid array |
DE19736210A1 (de) * | 1996-11-12 | 1998-05-14 | Siemens Ag | Preßform sowie Verfahren zum Herstellen eines Kunststoffverbundkörpers |
US6001672A (en) * | 1997-02-25 | 1999-12-14 | Micron Technology, Inc. | Method for transfer molding encapsulation of a semiconductor die with attached heat sink |
US6048755A (en) * | 1998-11-12 | 2000-04-11 | Micron Technology, Inc. | Method for fabricating BGA package using substrate with patterned solder mask open in die attach area |
DE19954888C2 (de) * | 1999-11-15 | 2002-01-10 | Infineon Technologies Ag | Verpackung für einen Halbleiterchip |
US20030082845A1 (en) * | 2000-01-14 | 2003-05-01 | Amkor Technology, Inc. | Package for multiple integrated circuits and method of making |
DE10014380A1 (de) * | 2000-03-23 | 2001-10-04 | Infineon Technologies Ag | Vorrichtung zum Verpacken von elektronischen Bauteilen |
JP4018375B2 (ja) * | 2000-11-30 | 2007-12-05 | 株式会社東芝 | 半導体装置 |
US6635209B2 (en) * | 2000-12-15 | 2003-10-21 | Siliconware Precision Industries Co., Ltd. | Method of encapsulating a substrate-based package assembly without causing mold flash |
JP2002208656A (ja) * | 2001-01-11 | 2002-07-26 | Mitsubishi Electric Corp | 半導体装置 |
US20020173074A1 (en) * | 2001-05-16 | 2002-11-21 | Walsin Advanced Electronics Ltd | Method for underfilling bonding gap between flip-chip and circuit substrate |
US6528408B2 (en) * | 2001-05-21 | 2003-03-04 | Micron Technology, Inc. | Method for bumped die and wire bonded board-on-chip package |
US6668449B2 (en) * | 2001-06-25 | 2003-12-30 | Micron Technology, Inc. | Method of making a semiconductor device having an opening in a solder mask |
US6458626B1 (en) * | 2001-08-03 | 2002-10-01 | Siliconware Precision Industries Co., Ltd. | Fabricating method for semiconductor package |
JP3790705B2 (ja) * | 2001-12-27 | 2006-06-28 | 新光電気工業株式会社 | 配線基板およびこれを用いた半導体装置の製造方法 |
KR100480909B1 (ko) * | 2001-12-29 | 2005-04-07 | 주식회사 하이닉스반도체 | 적층 칩 패키지의 제조 방법 |
US6857865B2 (en) * | 2002-06-20 | 2005-02-22 | Ultratera Corporation | Mold structure for package fabrication |
-
2001
- 2001-06-05 DE DE10127009A patent/DE10127009A1/de not_active Withdrawn
-
2002
- 2002-06-05 WO PCT/DE2002/002044 patent/WO2002099871A2/de not_active Application Discontinuation
- 2002-06-05 EP EP02740387A patent/EP1393364A2/de not_active Withdrawn
- 2002-06-05 JP JP2003502880A patent/JP2004528729A/ja active Pending
- 2002-06-05 TW TW091112124A patent/TW558813B/zh active
- 2002-06-05 KR KR10-2003-7015897A patent/KR20040012896A/ko not_active Application Discontinuation
- 2002-06-05 US US10/478,682 patent/US20040175866A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997001865A1 (en) * | 1995-06-28 | 1997-01-16 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
US6143581A (en) * | 1999-02-22 | 2000-11-07 | Micron Technology, Inc. | Asymmetric transfer molding method and an asymmetric encapsulation made therefrom |
US6294825B1 (en) * | 1999-02-22 | 2001-09-25 | Micron Technology, Inc. | Asymmetrical mold of multiple-part matrixes |
US6201299B1 (en) * | 1999-06-23 | 2001-03-13 | Advanced Semiconductor Engineering, Inc. | Substrate structure of BGA semiconductor package |
US6210992B1 (en) * | 1999-08-31 | 2001-04-03 | Micron Technology, Inc. | Controlling packaging encapsulant leakage |
Also Published As
Publication number | Publication date |
---|---|
JP2004528729A (ja) | 2004-09-16 |
EP1393364A2 (de) | 2004-03-03 |
US20040175866A1 (en) | 2004-09-09 |
KR20040012896A (ko) | 2004-02-11 |
WO2002099871A2 (de) | 2002-12-12 |
DE10127009A1 (de) | 2002-12-12 |
TW558813B (en) | 2003-10-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2002099871A3 (de) | Kunststoffgehäuse mit mehreren halbleiterchips und einer umverdrahtungsplatte sowie ein verfahren zur herstellung des kunststoffgehäuses in einer spritzgussform | |
WO2003067657A3 (de) | Halbleiterbauteil mit sensor- bzw. aktoroberfläche und verfahren zu seiner herstellung | |
WO2002001634A3 (de) | Systemträger für halbleiterchips und elektronische bauteile sowie herstellungsverfahren für einen systemträger und für elektronische bauteile | |
TWI299748B (en) | Adhesive composition, its manufacturing method, and adhesive film, substrate for carrying a semiconductor device and semiconductor device using such adhesive composition | |
DE10345302A1 (de) | Elektronisches Gerät sowie Verfahren zu seiner Herstellung | |
CA2328626A1 (en) | Method for overmolding sink marks for an automotive component | |
WO2004027882A3 (de) | Leadframe-basiertes gehäuse, oberflächenmontierbares optoelektronisches bauelement und verfahren zur herstellung | |
TW200420404A (en) | Method of resin encapsulation, apparatus for resin encapsulation, method of manufacturing semiconductor device, semiconductor device and resin material | |
EP1460688A3 (de) | Harzvergossene elektronische Anordnung und Verfahren zu Ihrer Herstellung | |
WO2004061898A3 (en) | Yield improvement | |
WO2007010315A3 (en) | Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component | |
WO2003015165A3 (de) | Elektronisches bauteil mit einem kunststoffgehäuse und verfahren zu seiner herstellung | |
WO2003024865A3 (de) | Verfahren zur herstellung von mikro-elektromechanischen bauelementen | |
AU2003283035A1 (en) | Polarized lens formed by an injection/coining injection molding process | |
EP0929097A3 (de) | Verfahren zum Zusammenbau einer Halbleiteranordnung und Halbleiteranordnung durch dieses Verfahren hergestellt | |
DE10294862T1 (de) | Kompressionsspritzgussvorrichtung, Kompressionsspritzgussverfahren, Kompressionsspritzgegossene Erzeugnisse, die durch selbiges Verfahren herstellbar sind, und thermoplastische Harzerzeugnisse | |
SG70600A1 (en) | Semiconductor element-mounting board manufacturing method for the board semiconductor device and manufacturing method for the device | |
TW200618344A (en) | Optical semiconductor device, optical connector and electronic equipment | |
WO2004032257A3 (de) | Folie mit organischen halbleitern | |
EP1119037A3 (de) | Halbleiter und Verfahren zur Herstellung | |
EP1447845A3 (de) | Gehäuse für elektronische Bauteile und Herstellungsverfahren dafür | |
AU2002351666A8 (en) | Molecular electronic component used to construct nanoelectronic circuits, molecular electronic component, electronic circuit and method for producing the same | |
WO2002013270A3 (de) | Halbleiterbauelement und verfahren zur identifizierung eines halbleiterbauelementes | |
MY150899A (en) | Electronic control unit and process of producing the same | |
EP1740027A3 (de) | Hertellungsverfahren einer umgossenen elektronischen Baugruppe |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP KR SG US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
AK | Designated states |
Kind code of ref document: A3 Designated state(s): JP KR SG US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2002740387 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020037015897 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10478682 Country of ref document: US Ref document number: 2003502880 Country of ref document: JP |
|
WWP | Wipo information: published in national office |
Ref document number: 2002740387 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 2002740387 Country of ref document: EP |