WO2002097776A2

WO2002097776A2 - An interface lamina

Info

Publication number: WO2002097776A2
Application number: PCT/US2002/016821
Authority: WO
Inventors: Ingemar V. Rodriguez; William P. Bischoff
Original assignee: Itw Inc.
Priority date: 2001-05-25
Filing date: 2002-05-24
Publication date: 2002-12-05
Also published as: AU2002310172A1; AU2002310172A8; EP1573705A2; WO2002097776A3; EP1573705A3; WO2002097776A9

Abstract

An emission layer 3 of an FED device has emitters which are caused to emit electrons or not according to whether or not a voltage on a gate 12, that is to say on a gate line 20 and thus at a gate aperture 121 surrounding the point 13 of the emitter generates an electric field at the point which is sufficiently high for electrons to be emitted from the point. For the voltages of the emitters and the gates of the pixel are controlled. Emitter lines 18 are arranged at the front face 19 of the substrate 4 parallel to one edge of the display and gate lines 20 are arranged at the front face 21 of the emission layer 3, orthogonal to the emitter lines. The front face is covered by an interface lamina 1011, 101 forming part of the emission layer 130. The lamina 1011, 101 is a single thickness of fired photo imageable glass.

Description

AN INTERFACE LAMINA

The present invention relates to an interface lamina in particular but not exclusively for an emission layer of a field emission device.

In International Patent Application No PCT/US98/20813, as its claims stand in the European Regional Phase No 98949752.4, (the "Eariier Application") there is described and claimed:

A field effect emission device for a visual display comprising: • a multilayer substrate having a front substrate layer and at least one additional substrate layer and

♦ an emission layer on one face of the substrate, the emission layer having:

• a multiplicity of emitters and gates, arranged as an array of emission pixels and • conductive connections in the emission layer to the emitters and the gates;

• the substrate having:

• conductive vias provided through the front layer thereof to at least some of the said conductive connections in the emission layer for electrical connection to their emitters and gates, the front layer vias being in the body of the emitters and the gates,

• conductive vias provided through the or each additional substrate layer,

• electrical interconnection tracks provided at the interface(s) between the or each adjacent pair of substrate layers for electrical interconnection of the vias of the pair(s) of adjacent layers, • the arrangement of the vias and the interconnection tracks being such that the position of a via in the front substrate layer is off-set from that of a via in a back one of the additional substrate layer(s) to which it is electrically connected,

• electrical connections being provided on an outer face of a back one of the additional substrate Iayer(s) opposite from the front substrate layer.

This device has its front substrate layer and its emission layer. Difficulties can arise at the interface between these layers. It is desirable to provide the emitters of the emission layer in groups at each pixel on conductive, emitter lines. Further it is desirable to provide resistive material between the emitter lines and the emitters. These two factors combine to displace the emitters forwards from the front substrate layer. Again it is desirable to provide the gates at gate apertures in gate lines which extend from pixel to pixel orthogonally of the emitter lines and at the same time avoid non-linearity in the gate lines transverse to the planes of the front substrate layer and the emission layer. Thus these factors conflict.

The object of the present invention is to provide a field effect emission device having an improved emission layer.

According to the invention there is provided a field emission device comprising:

• a substrate having at least a front substrate layer, • an emission layer on a front face of the substrate, the emission layer having:

• a multiplicity of emitters and gates, arranged as an array of emission pixels,

• a dielectric lamina separating the emitters and the gates and

• conductive connections in the emission layer to the emitters and the gates, the conductive connections including:

* emitter lines disposed between the front substrate layer and the dielectric lamina,

* gate lines on the front side of the dielectric lamina and

* gate vias through the dielectric lamina to the gate lines, • the front substrate layer having:

• conductive vias provided therethrough to at least some of the said conductive connections in the emission layer for electrical connection to their emitters and gates, these front layer vias being predominantly in the body of the emitters and the gates, • the emission layer including:

• an interface lamina between the front substrate layer and the dielectric lamina of the emission layer, the interface lamina being of insulating material and having: • conductive vias for connecting gate ones of the conductive vias in the front substrate layer to the gate vias in the dielectric lamina.

Whilst it can be envisaged that the emitter lines may be provided on top of the interface lamina, it is prefeπred that they are incorporated in it and that emitter connection regions for connecting emitter ones of the conductive vias in the front substrate layer to the emitters are provided in the interface lamina. This has the advantage of enabling the front face of the interface lamina to be ground and polished flat or otherwise planarised.

It is also envisaged that the interface lamina and the dielectric lamina may be separated by another lamina, itself having connection vias.

Preferably the interface lamina is of so-called "photo imageable vitreous material". Normally this will be of glass, that is to say a particular glass material which is laid down in a binder that can be photographically exposed and chemically developed, selectively etched (for forming its vias and connection regions) and subsequently fired to coherent form. It is envisaged that other vitreous photo imageable material may be suitable. In particular, a material based on a ceramic/glass mixture or indeed based on ceramic. The presently preferred material is KQ 125 material from the Heraeus Amersil Inc., 3473 Satellite Boulevard, Duluth, GA 30096- 5821 , www.heraeus-amersil.cooi. It is envisaged that with adjustment to its viscosity, this material can be spun onto the substrate. However, it is preferably screen printed thereon prior to development and ground/polished to a uniform thickness after firing. The polishing ability is enhanced by the glass being non- crystalline. Other particular materials are expected to be found suitable. Their choice will be influenced by compatibility of thermal expansion with the substrate, ability to be fired at elevated temperature, typically between 750°C and 920°C and ability to retain its shape on successive firing of additional thicknesses, for instance. Preferably the firing temperature should be lower than that of the firing temperature of the substrate. It should be noted that although this interface material is referred to herein as a glass, the interface lamina comprised of the material and indeed the material itself may be thought of as a glaze. We prefer not to use this term. Alternative methods of deposit of the interface lamina are use of photo- imageable glass tape or apertured (e.g. punched) glass tape, either tape being applied by lamination to the substrate.

The interface lamina can be of single thickness, i.e. a single application, or of double thickness. Where it is of double thickness, the first thickness is fired prior to the second being laid down by screen printing . It is envisaged that at least two more thicknesses may be laid down in particular applications.

Where the interface lamina is of single thickness, the emitter lines are laid down on the front face of the substrate prior to application of the lamina. This can be by screen printing onto the front face of the substrate prior to firing of the substrate, as in the Earlier Application; alternatively, as is now preferred, the emitter lines can be laid down, as by screen printing, after firing of the substrate and immediately prior to. the screen printing of the interface lamina. Where it is of double thickness, the emitter lines can be laid down between the two thicknesses, with the first thickness having been patterned with vias to the emitter vias in the substrate and these having been filled. These emitters vias and the gate vias in the first thickness are formed together.

In either case, i.e. one or two thicknesses, apertures are opened in the thickness over the emitter lines to form the emitter connection regions. These may be continuously along the emitter lines. However, they are preferably provided as discrete regions, at least one for each colour within each pixel or at least one for each pixel. The regions may be filled with conductive material for deposition of the emitters thereon. However, as is well known in the field emission art, it is desirable ^' to interpose resistive material between the emitter lines and the deposited emitters. This can be provided by laying down resistive vitreous material in the region openings, as by screen printing. This material is then fired at the same time as the material in which the opening for it was etched. It also is polished subsequent to firing. This polishing is simultaneous with the polishing of the rest of the interface lamina. It has the advantage of providing a smooth and planar surface on which the emitters and indeed the other features of the emission layer can be deposited. Where the lamina is of double thickness, there is the additional advantage of the emitter lines being laid down on the polished surface of the first thickness. In the absence of the interface lamina, the surface of the emitter lines can be disturbed by ceramic grains pulled from the front face of substrate during polishing, because the grains can be larger or comparable in size to the emitter lines. The latter can be of the order of 0.2microns.

Further, the conductive vias to the gate vias in the dielectric lamina can also be formed by etching and filling with conductive material, which will usually be different from the resistive material, but conceivably could be the same. Where the materials are different, two stages of filling, as by screen printing, will be employed.

The resistive pads and the lamina vias can be of metal oxide glass.

It is anticipated that substrates with interface layers may be supplied as items of commerce in their own right, to be incorporated in field, emission devices and possibly even other electrical devices by third parties.

Thus according to another aspect of the invention, there is provided an electrical component to have an electrical device incoφorated thereon, the electrical component comprising:

• a substrate having at least a front substrate layer, having:

• conductive vias provided therein for electrical connection therethrough to the electrical device to be incorporated thereon, these front layer vias being distributed across the front substrate layer,

• an interface lamina deposited on the front substrate layer, the interface lamina being of insulating material and having:

• conductive vias for connecting at least some of the conductive vias in the front substrate layer to connections of the electrical device; and preferably • additional connection regions for connecting others of the conductive vias in the front substrate layer to other connections of the electrical device. To help understanding of the invention, a specific embodiment thereof will now be described by way of example and with reference to the accompanying drawings, in which:

Figure 1 is a scrap cross-sectional view through a. field emission device according to the invention;

Figure 2 is a diagrammatic view on large scale of two emission pixels of the field emission device of Figure 1, part only of a front substrate layer being shown;

Figure 3 is a similar view of a single emission pixel and a gate via interconnection in variant of the arrangement of Figure 2; Figure 4 is another similar view, showing a preferred double thickness interface lamina and

Figure 5 is a diagrammatic plan view on a small scale of several emission pixels of the emission layer having the interface lamina of Figure 4.

Referring to Figures, 1 and 2, there js shown_^a scrap cross-section through an

FED display 1, having a cathode 2 with an, emission, layer 3 on the front face of a ceramic substrate 4. Opposite the cathode is an anode 5 with a phosphor layer 6. In use, electrons are emitted from the emission layer, accelerated across the gap to the anode and cause the phosphor layer to emit photons, which can be viewed: Each layer is divided into addressable pixels, at least as regards connection to drivers mentioned below, whereby individual phosphor pixels can be illuminated by individual emission pixels to cause an image to be displayed.

The emission layer and the phosphor layers are divided into pixels, opposite each other. Within each emission pixel, a plurality of pointed emitters 11 are provided directed at the anode, a diagrammatic few emitters only being shown. They are caused to emit electrons or not according to whether or not a voltage on a gate 12, that is to say on a gate line 20 and thus at a gate aperture 121 surrounding the point 13 of the emitter generates an electric field at the point which is sufficiently high for electrons to be emitted from the point. For the voltages of the emitters and the gates of the pixel are controlled. For this they are connected to drivers 7 on the back of the substrate 4. In accordance with the Earlier Application, connections are routed through the substrate, via a series of vias 14 and interconnects 15, the vias passing through the individual layers of the substrate and the interconnects being arranged along the interface between the layers. The arrangement is such that the pitch and arrangement of the pins 16 on the drivers is matched to the disposition of the pixels and their gates and emitters, with fan-out from the pixel pitch and crossing of interconnects as appropriate. In particular, emitter lines 18 are arranged at the front face 19 of the substrate 4 parallel to one edge of the display and gate lines 20 are arranged at the front face 21 of the emission layer 3, orthogonal to the emitter lines.

Referring now in particular to Figure 3, two via interconnect routes are shown through a substrate 140 to a typical front face via 114_e from an interconnect 115_C for an emitter line 118 and another 114_ε from an interconnect 115_g for a gate line 120. In accordance with the present invention, the front face is covered by an interface lamina 101 forming part of the emission layer 130. (It should be noted that as drawn, Figure 2 also shows an interface lamina 1011.) The lamina 101 is a single thickness of fired photo imageable glass._..The, emitter line is a screen printed deposit, which was laid down on and pressed into.the front face.to become flush with it prior to the firing o the substrate. After firing of the substrate, it is polished, i.e. planarised.

The interface lamina 101 is screen printed on and dried. It is exposed with light through a mask - not shown -the light cross-linking its polymeric binder and fixing the glass particles in the areas where the lamina is to be present and chemically developed, which allows the lower molecular weight, un-τeacted polymer and glass (which has been masked) to be dissolved and washed away where the lamina is to be apertured, particularly at a gate via 102 and an emitter connection region 103. The interface lamina (including the substrate) is fired and if desired polished and planarised. The gate vias and emitter connection regions are filled with conductive material by screen printing to form the via per se and a base 1031 on which the emitters are to be deposited (such a base 31 is also shown in Figure 2).

Typically, the interface lamina will be 0.002" thick and the vias will be 0.001" in diameter. Subsequently the dielectric lamina 104 is laid down and the gate line 120 is laid next, extending into a via aperture 105 formed in the dielectric lamina, again by a photographic and etching process. Gate apertures 1121 are opened and cavities etched in the oxide below them. The emitter tips 106 are deposited in a manner believed to be known to the man skilled in the field emission art.

In a preferred embodiment shown in Figure 4, the substrate 204 has both the emitter vias 214_e and the gate vias 214_g extending flush to the polished front face 219 of the substrate. The interface lamina 201 is laid down as two separate thicknesses 2011,2012 individually screen printed on, exposed, developed, washed, fired and polished.

In the first thickness 2011 , via apertures are formed and filled with conductive material to provide vias 2141_c, 2141_e corresponding to and electrically contacting the emitter and gate vias 214_€j 214_g. After polishing of the first thickness, emitter lines 218 are screen printed onto the first thickness over the respective emitter vias 2141_c in the first thickness. The second thickness 2012 is screen printed on and apertures for gate vias 2142,, and an emitter connection_' regions 203 are formed. The former have additional screen printings of conductive material made into them. The emitter regions have resistive material 2031 screen printed in to provide resistive bases for emitter tips 206 to be formed on them after firing of the second thickness and its polishing. The tips are formed after laying down of a dielectric lamina 2104 and gate lines 220 in like manner to those 104,120.

Referring now to Figure 5, individual, emission pixel outlines are shown by heavy lines P. It will be noted that each pixel has one gate line 220 and emitter lines 218 orthogonal to the gate line, the emitter lines being 218G, 218B, 218R for emission sub-pixels G,B,R corresponding to green, blue and red phosphor sub-pixels (not shown). The emitter lines are closely spaced, typically at 0.001" within each pixel and 0.002" between pixels for a individual line widths of 0.003". This allows a 0.002" gap 230 for the gate vias 2141 2₈ to pass between the green emitter line 180G of one pixel and the red emitter line 218R of the next. It will readily be appreciated that whereas this is feasible if the gate via is of 0.001" diameter, as the invention permits, and has a closely controlled position, it would not be feasible with a conventional substrate ceramic via size of O.004".

More space is available for the emitter vias 2141c, not least because these do not have to pass between the gate lines which are provided at a higher level in the emission layer. Nevertheless, it can be noted that the gate lines can be 0.008" wide, leaving a 0.005" gap 231 therebetween. It can be noted also that the emission sub- pixels are rectangular with an appreciable aspect ratio, 3:8 in this embodiment.

The resistive emitter connection regions 203 have the same aspect ratio, being co-extensive with the sub-pixels areas of intersection of the gate fines and the emitter lines. Equally, it should be noted that the resistive regions are individually discrete, being separated by the inter-gate-line gap 2 1 along the length of the emitter lines and along the gate lines by the inter-e itter-line gaps 230 between the pixels and 232 between the sub-pixels.

Provision of the interface lamina has advantages in enabling the tips to be laid down on a flat surface at the emitter connection regions, as mentioned above. It also has the advantage at least in the two thickness embodiment of enabling deposition of discrete resistive bases at these regions for the emitter tips, one base being provided for each pixel. Further, there are dimensional advantages as follows.

The front layer of the substrate can be of ceramic material, conveniently low temperature co-fired ceramic (LTCC), such as available from W.C. Heraeus GmbH, Hanau, Germany, www.heraeus.com and Dupont Photopolymer & Electronic

Materials, Research Triangle Park, NC, USA, www.dupont.com. LTCC generally comprises a glass ceramic composite, which enables the material to be fired at its comparatively low temperature in the region of 850°C. The actual grade of material chosen will be such as to fire at a higher temperature than that of interface lamina, which is fired subsequently, or at least the material should not deform at the firing temperature of the interface lamina. The front layer has its apertures punched in prior to lamination. Alternatively, it can be a thicker ceramic material which is fired prior to forming of the via apertures. They arc then cut by laser drilling. Such vias are smaller and are more costly to cut than punched vias. Whichever way the vias are cut, they are then filled and the substrate is subsequently laminated and fired again. These techniques form no part of the present invention and will not therefore be described in greater detail.

However, where the via apertures are punched, the smallest via size readily obtainable is approximately 0.004" in diameter at the front face. In the context of an FED display having some hundred lines to the inch, i.e. inter-line spacing of 0.010", this via diameter potentially restricts the size of the emission pixels, i.e. the size of the emitter connection regions at least wherever a gate via is required between two pixels.

The vias in the vitreous interface lamina can be made smaller than 0.004". Typically 0.001" is achievable, with a thin lamina, of the order of 25 microns. This benefits the size of the emitter regions in two ways. Firstly, the inter-pixel spacing at adjacent regions can be reduced,' bearing in mind that, it is comprised of the gate via diameter together with a margin for insulation on both sides of the via. Further where the emitter lines are laid direct oh the front 'face b the substrate, they are still restricted by the diameter of the vias' in the substrate. However, lifting the emitter lines by placing them on top of me first thickness of the interface lamina removes this limitation and allows the emitter lines to be sized and positioned in accordance with the smaller interlace lamina vias. This is of particular significance where the display is a colour display, with each pixel having three emitter regions, one for each of red, blue and green.

The invention is not intended to be restricted to the details of the above described embodiment For instance, the metallic material of the emitter lines can be screen printed as a continuous sheet and then etched to form the lines, as opposed to being screen printed in lines. Further, the emitter lines can be sputter deposited as a continuous sheet, which is subsequently patterned into lines. Again, instead of LTCC, high temperature co-fired ceramic (HTCC) can be used for the substrate. This material has less glass and requires a higher temperature in the region of 1100°C for its firing. However, it is stronger and less brittle than LTCC, with the latter'$ higher glass content. Where the substrate is comprised of a thick pre-fired layer and thinner tape layers added as laminates, the former which is likely to provide the front layer can be of HTCC and the latter of LTCC. Alternatively other co-fired glass/ceramic substrates can be envisaged.

Furthermore, in preparation for the laying down of the interface lamina, the front face of the substrate can be chemically mechanically polished. This process can also be applied to the fired interface lamina.

Claims

CLAIMS: .

1. A field emission device comprising:

• a substrate having at least a front substrate layer,

• an emission layer on a front face of the substrate; the emission layer having: • a multiplicity of emitters and gates, arranged as an array of emission pixels,

• a dielectric lamina separating the emitters and the gates and

♦ conductive connections in the emission layer to the emitters and the gates, the conductive connections including: • emitter lines disposed between the front substrate layer and the dielectric lamina,

• gate lines on the front side of the dielectric lamina and

• gate vias through the dielectric lamina to the gate lines,

• the front substrate layer having: • conductive vias provided therethrough to at least some of the said conductive connections in the emission layer for electrical connection to their emitters and gates, these front layer vias being predominantly in the body of the emitters and the gates,

• the emission layer including: • an interface lamina between the front substrate layer and the dielectric lamina of the emission layer, the interface lamina being of insulating material and having:

• conductive vias for connecting gate ones of the conductive vias in the front substrate layer to the gate vias in the dielectric lamina.

2. A field emission device as claimed in claim 1 , wherein the emitter lines are provided on top of the interface lamina.

3. A field emission device as claimed in claim 1 , wherein the emitter lines are iπcoφorated in the interface lamina and that emitter connection regions for connecting emitter ones of the conductive vias in the front substrate layer to the emitters are provided in the interface lamina.

4. A field emission device as claimed in claim 1, claim 2 or claim 3, including a further lamina, itself having connection vias, the further lamina separating the interface lamina and the dielectric lamina.

5. A field emission device as claimed in any preceding claim, wherein the interface lamina is of photo-imageable vitreous material.

6. A field emission device as claimed in claim 5, wherein the interface lamina is of ceramic material.

7. A field emission device as claimed in claim 5, wherein the interface lamina is of glass material.

8. A field emission device as claimed in claim 5, wherein the interface lamina is of ceramic/glass mixture material.

9. A field emission device as claimed in claim 7 or claim 8, wherein the glass is non- crystalline.

10. A field emission device as claimed in any one of claims 5 to 9, wherein the photo- imageable vitreous material was applied by spinning onto the substrate.

11. A field emission device as claimed in any one of claims 5 to 9, wherein the photo- imageable vitreous material was applied by screen printing.

12. A field emission device as claimed in claim 10 or claim 11, wherein the photo- imageable vitreous material was ground or polished to uniform thickness after firing.

13. A field emission device as claimed in claim 12, wherein photo-imageable vitreous material has a firing temperature lower than that of the substrate.

14. A field emission device as claimed in any one of claims 5 to 9, wherein the photo- imageable vitreous material was applied as photo-imageable glass tape, applied by lamination to the substrate.

15. A field emission device as claimed in any one of claims 5 to 9, wherein the photo- imageable vitreous material was applied as apertured glass tape, applied by lamination to the substrate.

16. A field emission device as claimed in any preceding claim, wherein the interface lamina of single thickness.

17. A field emission device as claimed in anyone of claims 1 to 15, wherein the interface lamina is of two or more thicknesses.

18. A field emission device as claimed in any preceding claim, wherein the emitter lines are laid down on the front face of the substrate prior to application of the lamina.

19. A field emission device as claimed in claim 17, whereΪD the emitter lines can be laid down between the two thicknesses.

20. A field emission device as claimed in claim 18 or claim 19, including apertures in single thickness or the upper of the two or more thicknesses, the apertures being filled with conductive vitreous material upon which emitters are deposited.

21. A field emission device as claimed in claim 18 or claim 19, including apertures in single thickness or the upper of the two or more thicknesses, the apertures being filled with resistive vitreous material upon which emitters are deposited.

22. A field emission device as claimed in any preceding claim, wherein the interface lamina includes gate vias of conductive vitreous material.

23. An electrical component to have an electrical device incoφorated thereon, the electrical component comprising:

• a substrate having at least a front substrate layer, having:

• conductive vias provided therein for electrical connection therethrough to the electrical device to be incoφorated thereon, these front layer vias being distributed across the front substrate layer, ' • an interface lamina deposited on the front substrate layer, the interface lamina being of insulating material and haying:

• conductive vias for connecting at least some of the conductive vias in the front substrate layer to connections of the electrical device; and preferably

• additional connection regions for connecting others of the conductive vias in the front substrate layer to other connections of the electrical device.

24. A electrical component as claimed in claim 23, wherein the interface lamina is of photo-imageable vitreous material.

25. A electrical component as claimed in claim 24, wherein the interface lamina is of ceramic material.

26. A electrical component as claimed in claim 24, wherein the interface lamina is of glass material.

27. A electrical component as claimed in claim 24, wherein the interface lamina is of ceramic/glass mixture material.

28. A electrical component as claimed in claim 26 or claim 27, wherein the glass is non-crystalline.

29. A electrical component as claimed in any one of claims 24 to 28, wherein the photo-imageable vitreous material was applied by spinning onto the substrate.

30. A electrical component as claimed in any one of claims 24 to 28, wherein the photo-imageable vitreous material was applied by screen printing.

31. A electrical component as claimed in claim 29 or claim 30, wherein the photo- imageable vitreous material was ground or polished to uniform thickness after firing.

32. A electrical component as claimed in claim 31 , wherein photo-imageable vitreous material has a firing temperature lower than that of the substrate.

33. A electrical component as claimed in any one of claims 24 to 28, wherein the photo-imageable vitreous material was applied as photo-imageable glass tape, applied by lamination to the substrate.

34. A electrical component as claimed in any one of claims 24 to 28, wherein the photo-imageable vitreous material was applied as apertured glass tape, applied by lamination to the substrate.

35. A electrical component as claimed in any preceding claim, wherein the interface lamina of single thickness.

36. A electrical component as claimed in any one of claims 1 to 15, wherein the interface lamina is of two or more thicknesses.

37. A electrical component as claimed in any one of claims 24 to 36, wherein the emitter lines are laid down on the front face of the substrate prior to application of the lamina.

38. A electrical component as claimed in claim 37, wherein the emitter lines can be laid down between the two thicknesses.

39. A electrical component as claimed in claim 38 or claim 39, including apertures in single thickness or the upper of the two or more thicknesses, the apertures being filled with conductive vitreous material upon which emitters are deposited.

40. A electrical component as claimed in claim 38 or claim 39, including apertures in single thickness or the upper of the two or more thicknesses, the apertures being filled with resistive vitreous material upon which emitters are deposited.

41. A electrical component as claimed in any one of claims 24 to 40, wherein the interface lamina includes gate vias of conductive vitreous material.

42. A method of manufacturing the field emission device of claim 1 or the electrical component of claim 24, the method including the steps of:

• depositing the interface lamina on the front substrate layer;

• opening vias in the interface lamina; and • filling the vias with conductive material.

43. A method as claimed in claim 42, wherein the step of depositing the interface lamina and the step of opening the vias are performed simultaneously.

44. A method as claimed in claim 42, wherein the step of depositing the interface lamina and the step of opening the vias are performed one after the other.

45. A method as claimed in claim 42, wherein the interface lamina is of photo- imageable vitreous material and the deposition step comprises spinning of the material onto the substrate and subsequent firing thereof.

46. A method as claimed in claim 42, wherein the interface lamina is of photo- imageable vitreous material and the deposition step comprises screen printing of the material onto the substrate and subsequent firing thereof.

47. A method as claimed in claim 42, wherein the interface lamina is of photo- imageable vitreous material and the deposition step comprises application of it as photo-imageable glass tape by lamination to the substrate and subsequent firing thereof.

48. A method as claimed in claim 42, wherein the interface lamina is of photo- imagcablc vitreous material and the deposition step comprises application of it as apertured glass tape by lamination to the substrate and subsequent firing thereof.

49. A method as claimed in any one of claims 45 to 48, wherein the deposition step includes grinding or poUshing of the photo-imageable vitreous material to uniform thickness after firing.

50. A method as claimed in any one of claims 42 to 49, wherein emitter lines are laid down on the front face of the substrate prior to deposition of the interface lamina.

51. A method as claimed in claim 50, wherein the emitter lines are laid down by screen printing onto the front face of the substrate prior to firing of the substrate.

52. A method as claimed in claim 50, wherein the emitter lines are laid down by screen printing onto the front face of the substrate after firing of the substrate.

53. A method as claimed in any one of claims 42 to 49, wherein the interface layer is deposited as at least two thicknesses and the first thickness is fired prior to the second being laid down by screen printing.

54. A method as claimed in claim 53, including the steps prior to deposition of the second thickness of:

• opening and filling emitter and gate vias in the first thickness and • laying down of emitter lines over the emitter vias.

55. A method as claimed in any one of claims 50 to 54, including the step of opening apertures in the thickness over the emitter lines to form the emitter connection regions.

56. A method as claimed in claim 55, including the additional steps of:

• filling the apertures with conductive or resistive vitreous material;

• firing this material; and

• polishing it and the interface lamina material simultaneously.