WO2002095879A1 - A high frequency, low cost package for semiconductor devices - Google Patents

A high frequency, low cost package for semiconductor devices Download PDF

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Publication number
WO2002095879A1
WO2002095879A1 PCT/US2001/016136 US0116136W WO02095879A1 WO 2002095879 A1 WO2002095879 A1 WO 2002095879A1 US 0116136 W US0116136 W US 0116136W WO 02095879 A1 WO02095879 A1 WO 02095879A1
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WO
WIPO (PCT)
Prior art keywords
package
component
substrate
dielectric
micromachined
Prior art date
Application number
PCT/US2001/016136
Other languages
French (fr)
Inventor
Phillip Joseph Koh
Original Assignee
Sophia Wireless, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sophia Wireless, Inc. filed Critical Sophia Wireless, Inc.
Priority to PCT/US2001/016136 priority Critical patent/WO2002095879A1/en
Publication of WO2002095879A1 publication Critical patent/WO2002095879A1/en

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Definitions

  • the present invention relates inter alia to a micromachined package useful, for example, for high frequency circuits and also to a method for directly interconnecting packaged circuits.
  • MMIC mobile broadband integrated circuit
  • MMIC's into high frequency communication systems and devices has increased the need for a low cost packaging system that can be mass produced.
  • Conventional packaging techniques are inadequate for high frequency devices, such as the MMIC, because the package fails to adequately transmit the signal thus resulting in a loss with every transmission.
  • I standard package can not carry the high frequency signal. These losses and the erratic signal behavior occur as a result of the internal structure of the package and the signal transitioning from one package down to the circuit board and back up into another package.
  • a solution is also needed to solve other assembly problems. For example, assembling a module having multiple chips using either the traditionally packaged chip or bare die assembly requires extensive time and numerous prototype iterations before a final design is produced. Forming modules using conventionally packaged chips mandates numerous hours of design and tedious wire bonding that often results in mistakes, thus requiring the module to be either scrapped or reassembled. The long time needed to produce a module greatly increases the manufacturing cost.
  • the present invention solves the above disclosed and other problems by introducing a low cost packaging technology for high frequency devices wherein individual packages can be directly attached to one another and then surface mounted as a unit to form a module of multiple integrated circuits on multiple chips.
  • one or more chips with integrated circuits can be mounted on a substrate of high resistivity material with metal conductors patterned on the substrate.
  • a means is provided for coupling the desired wave signals from one side of the substrate to the other side through the substrate.
  • the package has the capability to be interconnected with other packages.
  • the package may be shaped as either a plug or a socket or the package may have both the plug and socket capability. The packages are then directly attachable to one another.
  • Direct package-to-package attachment provides significant performance advantages over circuit-board-based interconnections.
  • the interconnection therefore solves the signal loss problem experienced using traditional packaging techniques by preventing the signal from repeatedly passing up and back between the packages and circuit board.
  • the technology ofthe invention greatly simplifies the RF design since the transmission line maintains essentially a constant cross-section until immediately before reaching the MMIC.
  • the interconnection packaging technology of this invention offers immense commercial capabilities since the interconnection of packages enables various modules of multiple packages to be assembled quickly.
  • integrated circuits can be packaged in packages ofthe invention and multiple packaged circuits can be quickly and easily joined together to form selected circuit combinations, such as amplifiers easily connected with modulators and the like.
  • the electrical characteristics of the packages being very similar assures not only low losses between packages but repeatability of circuit characteristics among the supply of packaged circuits.
  • the prepackaged chips are standardized, thereby guaranteeing precise circuit characteristics.
  • a designer can create a module by selecting the appropriate prepackaged chips and directly coupling the packages to one another (i.e.: a plug and play concept). This ability allows modules to be created in a rapid and precise environment, thereby eliminating the traditional prototype to final design procedure.
  • a package having interconnection capabilities uses a plug-and-socket approach.
  • Two substrates made, for example, from silicon or ceramic or other suitable material for micromachining, are fabricated to include at least one of a male (plug) and female (socket) formation.
  • the plug may be trapezoidal in cross section while the socket may have a dovetail-jointlike aperture.
  • the plug is accepted by the socket thereby directly attaching one IC package to another.
  • the two packages would be locked together when the plug portion is fitted to the socket portion.
  • the plug/socket combination is not limited to the trapezoidal/dovetail cross section or even to the male/female type connector arrangement.
  • the package's direct attachment configuration may comprise a cross type layout wherein two or more connectors, for example, four plugs/sockets are provided with one plug or socket extending from a respective edge of the package.
  • two or more connectors for example, four plugs/sockets are provided with one plug or socket extending from a respective edge of the package.
  • two packages of the invention are held together by a flexible spring formed integral with the package substrate.
  • the spring applies a compressive force when the two packages are mated, thus bringing the respective contact portions in electrical contact.
  • the spring may create a frictional force keeping the components coupled together.
  • the spring edges may be tapered to ease insertion into a spring seat on an adjoining package, consequently providing a positive lock when the packages are fully joined together.
  • MMIC's are directly coupled via a double plug configuration.
  • the double plug configuration utilizes one plug for providing coarse alignment, which may be termed a guide plug, while the second plug carries the signal and may be termed a signal plug.
  • the signal plug provides the spring binding force.
  • the guide plug restricts the signal plug's range of travel so that the movement of the signal plug in the socket does not exceed the maximum excursion ofthe spring, regardless of the position and direction in which the packages are brought together.
  • a package is fabricated to provide full encapsulation of a semiconductor chip.
  • the semiconductor chip is sealed within a cavity formed between two or more patterned substrates.
  • the semiconductor chip is mounted between two or more patterned substrates, and a window may also be formed in at least one of the substrates so that the chip can be viewed through the aperture.
  • MMICs or other integrated circuits are mounted on a package substrate prior to bonding step whereby a second package substrate is bonded to the first package substrate carrying the MMIC. The first substrate is then bonded to the second substrate thereby simultaneously sealing the MMIC between the substrates. This forms a prepackaged semiconductor device that can be mass-produced and coupled to other devices to form a module.
  • the integrated circuit is not mounted before wafer bonding.
  • the IC packages are not completely sealed. Instead, the package has a window etched above the site where the IC will be mounted.
  • two substrates may be bound together and with a window forming empty package.
  • Many packages may be formed simultaneously on wafers such as a silicon wafer. On a first wafer is formed multiple first substrates at respective die positions in the wafer. On a second wafer may be formed multiple second substrates at respective positions. The wafer can be aligned and bonded to each other, thereafter the bonded wafers can be diced apart. In one embodiment, ICs can be mounted between the two substrates before the wafers are diced apart. In another embodiment no ICs are mounted before the dicing operation and after the dicing the individual packages formed by each die can be sold as an empty package. A user could then mount an IC such as an MMIC through a window located on the package. The user could then wire bond the connections and seal the packages with a cap, such as a metal cap.
  • a cap such as a metal cap.
  • Objects, features and advantages of this invention are to provide a low cost mass producible package and packaging system that can be used with high frequency devices.
  • An aspect of the packaging system of the present invention is to enable the packages and the chips mounted therein to be interconnected via a direct attachment to one another thereby reducing loss.
  • the present invention also eliminates the multiple prototype cycle inherent in traditional module design by providing a technology wherein a module may be immediately created by assembling prepackaged ICs with interconnecting capabilities.
  • FIG. 1 is a plan view of a first embodiment of a micromachined package according to the invention having a double socket interconnection configuration.
  • FIG. la is a plan view of a second embodiment of a micromachined package according to the invention having a double plug interconnection configuration
  • FIG. lb is an underneath perspective ofthe second embodiment having the double plug configuration depicted in FIG. la wherein the electrical conductors for carrying including high frequency signals are shown;
  • FIG. 2 is a plan view of an alternative embodiment of a micromachined package of the invention having a single plug interconnection configuration
  • FIG. 2a is a plan view of an alternative embodiment of a micromachined package of the invention having a single socket interconnection configuration
  • FIG. 2b is another plan view of the single plug configuration depicted in 2a showing electrical signal conductors;
  • FIG. 3 and 3 a are a cross sectional view of the plug and socket type connectors with transmission line metal for propagating a wave signal including millimeter wave signals;
  • FIG. 4 is a cross sectional across the double plug inserted into the double socket view of the interconnection system of the present invention wherein the plug is fully inserted into the socket;
  • FIGS. 5, 5a, and 5b are cross-sectional views down the centerline ofthe package shown in Fig. 2.;
  • FIG. 6 is an alternative embodiment of a micromachined package having a plug located at a longitudinal end and a socket located at the other longitudinal end;
  • FIG. 7 is an alternative embodiment of a micromachined package having a quad plug interconnection configuration
  • FIG 8 is an alternative embodiment of a micromachined package having a plug located at each end ofthe silicon package
  • FIG. 9 is a sectional view of a package of the present invention wherein the chip is mounted in the substrate aperture;
  • FIG. 10 is a sectional view of the chip mounted in a package and wire bonded to the CPW line on the silicon substrate;
  • FIG. 11 is a perspective view of an assembled micromachined package fully encapsulating an MMIC
  • FIG. 12 is a view of an alternate embodiment employing a nub for direct attachment purposes
  • FIG. 13 is an exemplary view of the present invention's direct attachment technique
  • FIG. 14 is an exemplary view of the present invention's direct attachment technique using four packages to form a module
  • FIG. 15 is an exemplary view of a module formed by the present invention's direct attachment technique mounted on a circuit board.
  • FIG. 16 is an exemplary view of a module formed using the direct attachment technique ofthe present invention wherein each circuit is fully encapsulated by the package.
  • FIG. 1 FIG. 1a and lb
  • FIGS. 1, 1a and lb will be jointly described, thus it is important to note that FIG. la and FIG. lb are the same double plug silicon package however, FIG. la illustrates an external view of the double plug silicon package while FIG. lb depicts an internal (or bottom) view ofthe double plug silicon package.
  • the packages may be formed of a material that can be micromachined.
  • Micromachining is any process with the ability to selectively add or remove dielectrics and conductors to form a desired three-dimensional shape, including such processes as: etching through a photolithography-defined mask layer or punching, drilling, or routing small holes in layers which may be subsequently bonded or co-fired together.
  • Numerous types of material may be micromachined.
  • An example of such a material is silicon, ceramics, such as LTCC, and printed circuit board material, such as a glass/epoxy-based, PTFE-based, or ceramic/organic circuit board material.
  • the invention is not limited to silicon as the substrate material, the following description is provided using silicon as an example of the package material and particularly ofthe substrate material forming the package.
  • FIG. 1 depicts a plan view of a double socket type silicon package (1) having both a guide socket (4) and an original socket (6).
  • FIG. la and FIG. lb illustrate a double plug silicon package (2) having both a guide plug (8) and a signal plug (10).
  • the double plug silicon package (2) of FIG. la is fitted into the matching sockets of the double socket type silicon package (1) of FIG. 1, thereby allowing direct attachment of two devices, such as high frequency devices in a manner that enables efficient signal transmission for high frequency semiconductor devices.
  • the double socket type silicon package (1) and the double plug silicon package (2) are fabricated using two high-resistivity silicon wafers for each package. The fabrication process will be fully described below.
  • the double socket type silicon package (1) contains a circuit aperture (14) for housing an integrated circuit, preferably an MMIC.
  • the double plug silicon package (2) also contains a circuit aperture (14).
  • Any type of circuit, including passive or active circuits, can be packaged using the silicon-based packaging technology of the present invention.
  • Other devices, such as optical fibers may be housed using the silicon-based package having a male or female component, thereby allowing optical fibers to be directly coupled to one another.
  • a further component that may be housed in one or both packages of the present invention includes an optical semiconductor component such as, a laser diode, an optical modulator or an optical receiver.
  • Both silicon packages (1) and (2) further contain a center conductor line (12b) separated by a non-metallized channel from a ground conductor (12a) on either side that run along the flat mating surfaces ofthe signal plug (10) and socket (6).
  • the electrical conductors (12) for the double plug silicon package (2) are illustrated in FIG. lb.
  • Several transmission-line/waveguides variations are possible.
  • an electrical connection can be made utilizing the coplanar waveguide- stripline (CPW-stripline) technique. This technique, as depicted in FIG. 1 and FIG. lb, employs a center conductor (12b) surrounded by two planar ground conductors (12a).
  • CPW-stripline coplanar waveguide- stripline
  • the conductors may be electroplated gold metal areas, separated by unmetallized channels which expose the high- resistivity substrate. Once the signal plug (10) is inserted into the socket (6) and a tight fit is formed (as will be fully explained below), the conductors (12) all make contact. Electrically, each pair of overlaid conductors (12) act as one.
  • the CPW-stripline transmission line runs inside each silicon package (1) and (2), where a connection is made to the MMIC located in the circuit aperture (14). This is accomplished by forming a cavity in the upper wafer to provide clearance.
  • the transmission line makes a transition from TEM-mode CPW-stripline (which is fully surrounded by silicon) to quasi-TEM mode CPW (with silicon below and air above the plane of the conductors) (16).
  • This transition is achieved by tapering the center conductor (12b) to achieve equal impedance and then a wire or ribbon bond makes the connection to the MMIC.
  • This bond couples a signal input or signal output pad of the MMIC to the center conductor (12b) ofthe transmission line.
  • the signal does not travel up or down between packages and through a printed circuit board. This greatly simplifies the RF design, since the transmission line maintains constant cross-section until immediately before reaching the MMIC.
  • the silicon packages illustrate an embodiment of the direct attachment method of the present invention.
  • a double plug and socket configuration is used to join the two silicon packages together.
  • a double plug silicon package (2) has a guide plug (8) that provides coarse alignment when signal plug (10) is inserted into signal socket (6) ofthe silicon package (1), wherein signal plug (10) carries the signal via the electrical conductors (12).
  • a flexible silicon spring (18) is used to apply compressive force when the signal plug (10) is inserted into the socket (6). The spring beam (18) generates a frictional force on the signal plug (10) to secure the two packages together.
  • the edges of signal plug (10) and the spring beam (18) can be tapered to allow easy insertion and a positive lock when signal plug (10) is fully inserted into signal socket (6).
  • the guide plug (8) as depicted in FIGS. 1-lb, restricts the range of travel of signal plug (10) so that the movement ofthe signal plug (10) in the signal socket (6) does not exceed the maximum excursion ofthe silicon spring beam (18), regardless ofthe position and direction in which the two packages are brought together.
  • FIGS. 2, 2a and 2b another aspect of the present invention using a single plug and socket configuration to directly attach two silicon packages that house semiconductor devices is illustrated.
  • FIG 2 and FIG. 2a depict the external surface of a single plug silicon package (20) and single socket silicon package (30) that can be interconnected by inserting signal plug (10) into socket (6).
  • the single plug silicon package (20) has a circuit window (22), usually enclosed by a metal cap, wherein a circuit (24) is housed.
  • Such a circuit window may be used independent ofthe plug/socket arrangement of the packages and thus such an optional window may be also used in the embodiment of Figs. 1-15
  • the circuit window (22) enables circuits to be placed in the silicon package after the silicon package is fabricated. Thus, empty silicon packages can be sold such that the buyer can choose which circuit to place within the package.
  • FIG. 2a depicts a silicon package with a circuit window (22) ready to accept any circuit.
  • the circuit (24) is fully encapsulated by the silicon substrates, thus a circuit window (22) is not provided.
  • FIG. 2b depicts a bottom portion view of single plug silicon package (20), wherein the electrical conductors (12) and non-metalized channels (54) form the transmission line (12), and circuit (24) is located within the circuit aperture (14).
  • the signal plug (10) of the single silicon package (20) is inserted into the socket (6) of package (30). Once fully inserted, the electrical conductors of silicon package (30) and silicon package (20) make contact thereby enabling a signal to pass between the two circuits housed in individual silicon packages that are directly attached.
  • the signal plug (10) and socket (6) are held together as a result of inversely slanted edges.
  • FIG. 3 illustrates the signal plug (10) as trapezoidal in cross section while socket (6) is formed as a dovetail-joint-like aperture that accepts the signal plug (10).
  • the angled edges of the socket (40) create a dovetail-joint like aperture that welcomes the slanted edges of the plug (38) to ensure a tight fit between the two silicon packages.
  • the angles of the slanted edges (38)(40) with respect to vertical is the same on both the signal plug (10) and socket (6).
  • the three electrical lines / conductors (12) may be gold, but any other metal may be substituted.
  • the two gaps between the three conductors are bare silicon (54) of the substrate.
  • the edges of the plug and socket may be formed in a vertical formation.
  • a force-applying lever or a spring-like mechanism may be bonded to the top of either the plug package or socket package such that the lever or spring located on a first package applies a force that affixes the first package to a second package.
  • FIG. 4 a cross sectional view, across a double plug inserted into a double socket is illustrated.
  • a silicon package (44) having a signal plug (10) and a guide plug (8), is fully inserted into the silicon package (46) having two sockets (4)(6).
  • Electrical contact is made upon full insertion of the plug into the socket when the overlapped metal of the plug and socket form the center conductor (12b) and ground planes (12a) of the CPW-stripline transmission line.
  • the guide plug (8) may provide DC and IF connections via several gold lines on the bottom of the guide plug (8) and several gold lines on the surface ofthe guide socket (4).
  • the conductors (12) come into contact thus providing DC and IF connections.
  • the silicon piece (53) on the double socket silicon package separates the two sockets (4) and (6).
  • FIGS. 5-5b provide another cross sectional view of a silicon package having a plug being inserted into a silicon package having a socket.
  • the silicon package further comprises a circuit aperture (14) for housing the integrated circuit (24) which is wire bonded (43) to the electrical metal conductors (16) ofthe CPW line.
  • the electrical conductors (12) run the length of both silicon packages.
  • the signal plug (10) is inserted into the socket (6), as depicted in FIGS. 5a and 5b, the electrical conductors (12) overlap and touch, allowing the signal to flow from one package to the other.
  • FIG. 5 further illustrates an embodiment of the present invention wherein the circuit is not fully encapsulated within the silicon package. This allows the circuit to be placed within the package at any given time after the silicon package is fabricated. Once a circuit is placed in the package, a lid (47) is placed over the circuit aperture (14) to protect the circuit (24). In an alternate embodiment of the present invention, the circuit is fully encapsulated within the silicon package.
  • FIGS. 6-8 depict additional aspects of the present invention, wherein a silicon package is fabricated having multiple plug and socket components. These additional aspects illustrate preferred configurations for directly attaching silicon packages that house high frequency devices together, however, any and all configurations, utilizing a connector attachment structure fall within the ambit of this invention.
  • FIG. 6 illustrates a silicon package having a socket located at one edge of the silicon package and a plug located at the opposite edge ofthe silicon package.
  • the plug and socket may be located at any point along the edges of the silicon package and is therefore not limited to the edges ofthe package shown.
  • a silicon package having four plugs is illustrated. One plug is located at each side of the silicon package. Any package shape having a connector formation of the present invention may be utilized.
  • a silicon package having a plug located at each end of the silicon package is illustrated.
  • the silicon package may comprise two sockets located at each end of the silicon package.
  • the plugs/sockets may be located at any point along the silicon package. Furthermore, it is possible to have multiple chips within a package, and depending on the function, they may require any number of plug or socket components.
  • the fabrication of the packages may be performed using standard micromachining techniques.
  • An embodiment of the fabrication process for a double-plug silicon package wherein one guide plug provides coarse alignment while the other plug carries the RF signal, is fully described below.
  • the silicon package fabrication process begins with two high- resistivity silicon wafers, approximately 20 mils thick, double side polished, hereinafter referred to as wafer 1 and wafer 2.
  • the wafers are cleaned using an industry standard RCA cleaning process.
  • a wet oxidation is performed using a conventional wetox process thereby heating the wafers to 1200C for four hours in a wet oxygen atmosphere.
  • Thermal oxides approximately 1.2 microns thick are grown on both wafers.
  • a coating of photoresist is applied to the backside of the wafer by spin coating and is then hard baked.
  • a coating of photoresist is also applied to the front side of the wafer. The wafers are then patterned with the appropriate masks on both the top and bottom side.
  • the pattern is transferred into the silicon oxide layer by wet etching. Upon completion of the wet etch, the photoresist is stripped using a standard stripper. This oxide forms a mask that protects some areas of the silicon, while areas with no oxide are exposed.
  • via holes are required which make electrical connection from one side of the wafer to the other.
  • small holes are etched from the top of wafer 1 through to the bottom side.
  • the aperture in the top side oxide may be square and the length of each side of the aperture is roughly twice the wafer thickness.
  • the wafers are deep silicon etched before metal plating.
  • the silicon etching is performed last.
  • the wafer is subsequently cleaned and a thin film of metal is applied as a seed layer for electroplating.
  • the thin film is deposited by vacuum or sputtering and comprises approximately lOOnm of Chrome followed by approximately lOOnm of gold.
  • the standard photoresist cycle is performed again using a photomask for metal patterning.
  • Photoresist is applied and patterned to form the openings where metal will be electroplated. For wafers with via holes, a conformal coating of photoresist is required. This requires the use of an optimized coating process typically using thicker photoresist, slower spin speeds, and low baking temperatures.
  • the photoresist is patterned in a contact aligner.
  • This pattern will consist of the CPW lines used to carry the RF signal down the plug into the receptacle. Also, the pattern will remove resist inside the via holes and from around the perimeter of the via hole; after plating, this will form a pad on the top and a pad on the bottom which are electrically connected.
  • Gold metal is electroplated onto the wafer (for example 4 micron thickness), and then the resist is removed. The wafer is re-patterned for electroplating of the bonding metal. This pattern places bonding metal in any areas where the two wafers come into contact, except under the cantilevered silicon spring beam, which should not be attached to wafer 1 since it must be free to bend.
  • the bonding metal is any metal which bonds under heat treatment. Examples are Tin/Lead eutectic or Tin/Gold eutectic.
  • the photoresist is stripped, and the electroplating base is removed by wet etching or sputter etching.
  • the wafer is now ready for deep silicon etching.
  • the wafer is immersed in a reflux tub of TMAH that causes the silicon to be removed from areas not protected by metal or silicon oxide.
  • the wafers are removed once the etched features have proceeded all the way through the wafer. Additionally, etching may be added as needed to round the corners and other features to the exact design and shape.
  • Wafer 2 is bonded onto the top of Wafer 1 using an aligner- bonder. They are clamped together so that all features align correctly, and then they are bonded by a heat cycle. For example, with Sn Pb bonding metal, a 15 minute cycle to 220 C in a forming gas atmosphere is typically sufficient. After bonding, the stack of wafers is cut into individual packages with a dicing saw. The cuts are aligned to the package to properly define the edges ofthe package.
  • the above photomasks are modified somewhat to improve the definition of the features.
  • convex corners of the mask opening quickly get rounded in the silicon etch.
  • a standard technique is to add extensions to the corner, so that after etching it will be less rounded.
  • the proper size of this extension for a particular etching system is determined by etching test wafers with a range of extension sizes.
  • the mask patterns for the socket and plug silicon etches are modified to incorporate the convex-corner protection extensions.
  • FIG. 9 a cavity/circuit aperture formed within the silicon substrate to mount a chip is illustrated.
  • the cavity/circuit aperture (14) depth approximately equal to the chip thickness, the top surface of the chip (24) after mounting is made level with the silicon surface (68). This allows a shorter wire bond, as depicted in FIG 10, to be used to connect the chip (24) input/output pads to the CPW line (12) on the silicon substrate (68).
  • the circuit aperture (14) is formed by inserting additional etching steps at the beginning ofthe fabrication sequence described above.
  • the wafers are initially cleaned, and a thermal oxide grown.
  • the oxide is then patterned with rectangular openings for the cavities.
  • the wafer is etched in anisotropic etchant such as EDA-P to the desired depth, for example 4 mils for many MMICs.
  • the wafer is then re-cleaned and a new thermal oxide layer is grown which seals the cavity.
  • the fabrication procedure continues as described above, except that all subsequent photoresist layers are applied using a spin recipe or coater, which gives good coverage ofthe etched features.
  • chips are mounted on the silicon wafers before the bonding step.
  • many chips are mounted on a wafer and another wafer is bonded to the first wafer, thereby simultaneously forming several sealed packages.
  • FIG. 11 illustrates one example ofthe packaging technology of the present invention wherein an MMIC is fully encased in the silicon package.
  • ICs are not mounted before wafer bonding. Instead, the IC packages are not completely sealed, but have a window etched into the silicon wafer above the site where the IC is to be mounted. The wafers are bonded together, forming empty silicon packages.
  • the packages are diced apart, and sold as empty packages. Users then mount an IC, through the window in the top of the package, wire bond the connections, and finally seal the package with a metal cap.
  • This cap is a typical package cap including, stamped metal sealed with solder preforms.
  • nub located on both the silicon spring beam and the guide plug to provide a more positive locking action is illustrated.
  • the side of the plug (8) which touches the silicon spring beam (18) is slightly narrower at the tip, and moving along the plug (8) from the tip, it widens slightly, then narrows slightly.
  • a nub/recess (62) arrangement as shown in Fig. 12 may be used.
  • the silicon spring beam (18) may also have a tapered shape, so that when the plug (8) is inserted, the silicon spring beam (18) will flex outward, then will move back towards its original position once the nub (38) on the plug (8) and silicon beam (18) pass each other. This provides a binding force that tends to pull the plugs (8) (10) into the sockets (4)(6).
  • the spring beam (18) may be located at any point on the package wherein the beam is capable of applying an attaching force (compressional and/or frictional).
  • the nubs (38) are formed by a variety of methods. A protrusion on the photomask pattern will form such a nub, however, the etching will tend to reduce or remove this nub. Experimentation is used to find the appropriate shape for the modification to the photomask pattern.
  • Another aspect ofthe present invention uses edges as shown in
  • Fig. 12 that are angled (60) relative to the ⁇ 111> crystal plane to form the nubs (38).
  • an edge (60) which is 10 degrees from the ⁇ 111> plane will tend to propagate as the etch progresses, so that the angled edge (60) moves in the ⁇ 111> plane at a rate of approximately five times the vertical etch rate.
  • FIGS. 13-16 a module created using the direct attachment technique of the present invention is illustrated.
  • FIGS. 13 and 13 illustrate four silicon packages with varying direct attachment components. Specifically, Package A (70) has a plug and socket configuration whereas Package C (90) and D (100) have a single plug configuration. A double socket configuration is illustrated by Package B (80).
  • a receiver can be constructed by interconnecting the following packages: Package A (70) contains a Low Noise Amplifier (LNA) MMIC chip, Package B (80) contains a mixer MMIC chip, Package C (90) contains an oscillator MMIC, and Package D (100) contains a MMIC with a printed circuit antenna (Package D (100) has no lid, so the antenna is open to the outside).
  • LNA Low Noise Amplifier
  • Package B 80
  • Package C contains an oscillator MMIC
  • Package D (100) contains a MMIC with a printed circuit antenna (Package D (100) has no lid, so the antenna is open to the outside).
  • Packages A (70), B (80), and C (90) have several via holes (not shown) passing through wafer 1 connecting pads on top of wafer 1 to pads on the bottom. These via holes may be for DC power and IF connections. Wire bonds are made from the DC and IF pads on the MMICs to the pads on top of wafer 1, and they are connected through via holes to pads on the bottom ofthe package.
  • Package A has a socket on one side for input and a plug on the opposite side for output. It has two pads on the bottom: one for DC power, and another for ground.
  • Package B has a socket on one side for RF input, and another socket on the opposite side for LO input. It has pads on the bottom for DC power and ground, and a pad for IF output. The IF output pad has a ground pad on either side.
  • Package C (90) has a plug for RF output, and pads on the bottom for DC power and ground.
  • Package D (100) has a plug for RF output. Referring to FIGS. 15 and 16, a module assembled using the direct attachment technique of the present invention is illustrated.
  • the plug of Package D (100) is inserted into the socket of Package A (70). Then, the plug of package A (70) is inserted into the socket for the input on package B (80). The plug of package C (90) is inserted into the socket for a local oscillator (LO) input on package B (80).
  • LO local oscillator
  • the four packages are connected and form a module (105).
  • the module (105) is then surface-mounted onto a circuit board (110), as depicted in FIG. 15, which provides connections to the pads on the bottom of the packages.
  • the circuit board (110) provides power to the packages, and circuitry to perform IF amplification and processing.

Abstract

A package may be shaped as either a plug or a socket. The plug (10) is trapezoidal in cross section and the socket (6) has dovetail aperture. The plug is inserted into the socket directly attaching one package to another.

Description

A HIGH FREQUENCY, LOW COST PACKAGE FOR SEMICONDUCTOR DEVICES
BACKGROUND OF THE INVENTION
1. Field of the Invention
[001] The present invention relates inter alia to a micromachined package useful, for example, for high frequency circuits and also to a method for directly interconnecting packaged circuits.
2. Description of Related Art
[002] The integration of Monolithic Microwave Integrated Circuits
(MMIC's) into high frequency communication systems and devices has increased the need for a low cost packaging system that can be mass produced. Conventional packaging techniques are inadequate for high frequency devices, such as the MMIC, because the package fails to adequately transmit the signal thus resulting in a loss with every transmission.
[003] Traditionally, integrated circuits (IC) formed on a semiconductor chip are packaged by enclosing the chip within a plastic or ceramic casing and attaching wire bonds between the pads of the chip and the package leads which can be soldered to a circuit board. This technique is acceptable for low frequency devices. When applied to high frequency devices however, the millimeter components corresponding to the high frequency components of the signal exhibit odd behavior because the
I standard package can not carry the high frequency signal. These losses and the erratic signal behavior occur as a result of the internal structure of the package and the signal transitioning from one package down to the circuit board and back up into another package. In addition to the need for a low cost packaging with low signal loss, a solution is also needed to solve other assembly problems. For example, assembling a module having multiple chips using either the traditionally packaged chip or bare die assembly requires extensive time and numerous prototype iterations before a final design is produced. Forming modules using conventionally packaged chips mandates numerous hours of design and tedious wire bonding that often results in mistakes, thus requiring the module to be either scrapped or reassembled. The long time needed to produce a module greatly increases the manufacturing cost. Accordingly, there is an immense need to eliminate multiple prototype iterations and the long time needed to produce packaged integrated circuits useful in high frequency applications, by creating a low cost package and packaging method, with interconnection capabilities between packaged integrated circuits, thus enabling a module to be assembled with precision in a short period of time.
SUMMARY OF THE INVENTION [005] The present invention solves the above disclosed and other problems by introducing a low cost packaging technology for high frequency devices wherein individual packages can be directly attached to one another and then surface mounted as a unit to form a module of multiple integrated circuits on multiple chips. As will be described in detail below, one or more chips with integrated circuits can be mounted on a substrate of high resistivity material with metal conductors patterned on the substrate. A means is provided for coupling the desired wave signals from one side of the substrate to the other side through the substrate. [006] Additionally, the package has the capability to be interconnected with other packages. The package may be shaped as either a plug or a socket or the package may have both the plug and socket capability. The packages are then directly attachable to one another. [007] Direct package-to-package attachment provides significant performance advantages over circuit-board-based interconnections. By directly attaching the packages to one another, the signal is directly transmitted between packages. The interconnection therefore solves the signal loss problem experienced using traditional packaging techniques by preventing the signal from repeatedly passing up and back between the packages and circuit board. The technology ofthe invention greatly simplifies the RF design since the transmission line maintains essentially a constant cross-section until immediately before reaching the MMIC. The interconnection packaging technology of this invention offers immense commercial capabilities since the interconnection of packages enables various modules of multiple packages to be assembled quickly. Thus, integrated circuits can be packaged in packages ofthe invention and multiple packaged circuits can be quickly and easily joined together to form selected circuit combinations, such as amplifiers easily connected with modulators and the like. The electrical characteristics of the packages being very similar assures not only low losses between packages but repeatability of circuit characteristics among the supply of packaged circuits. Thus, the prepackaged chips are standardized, thereby guaranteeing precise circuit characteristics. Using plural prepackaged chips ofthe invention, a designer can create a module by selecting the appropriate prepackaged chips and directly coupling the packages to one another (i.e.: a plug and play concept). This ability allows modules to be created in a rapid and precise environment, thereby eliminating the traditional prototype to final design procedure. [009] In one aspect of the invention, a package having interconnection capabilities uses a plug-and-socket approach. Two substrates made, for example, from silicon or ceramic or other suitable material for micromachining, are fabricated to include at least one of a male (plug) and female (socket) formation. The plug may be trapezoidal in cross section while the socket may have a dovetail-jointlike aperture. The plug is accepted by the socket thereby directly attaching one IC package to another. The two packages would be locked together when the plug portion is fitted to the socket portion. Of course the plug/socket combination is not limited to the trapezoidal/dovetail cross section or even to the male/female type connector arrangement. The invention envisions any type of direct, stable intersection between packages using connector portions integral with the respective substrates of interconnected packages. These connector portions further include respective contact portions for electrical signal flow.
[0010] In another aspect of the present invention, the package's direct attachment configuration may comprise a cross type layout wherein two or more connectors, for example, four plugs/sockets are provided with one plug or socket extending from a respective edge of the package. Such a configuration allows multiple packages to be coupled to a single package of the invention. Any module configuration that enables two or more packages to be coupled together are within the scope of this invention.
[0011] In yet another aspect of the present invention, two packages of the invention are held together by a flexible spring formed integral with the package substrate. The spring applies a compressive force when the two packages are mated, thus bringing the respective contact portions in electrical contact. The spring may create a frictional force keeping the components coupled together. The spring edges may be tapered to ease insertion into a spring seat on an adjoining package, consequently providing a positive lock when the packages are fully joined together.
[0012] In still another aspect of the present invention, two packaged
MMIC's are directly coupled via a double plug configuration. The double plug configuration utilizes one plug for providing coarse alignment, which may be termed a guide plug, while the second plug carries the signal and may be termed a signal plug. The signal plug provides the spring binding force. In this configuration, the guide plug restricts the signal plug's range of travel so that the movement of the signal plug in the socket does not exceed the maximum excursion ofthe spring, regardless of the position and direction in which the packages are brought together.
[0013] In still another aspect of the present invention, a package is fabricated to provide full encapsulation of a semiconductor chip. The semiconductor chip is sealed within a cavity formed between two or more patterned substrates. Alternatively, the semiconductor chip is mounted between two or more patterned substrates, and a window may also be formed in at least one of the substrates so that the chip can be viewed through the aperture.
[0014] In another aspect of the present invention, MMICs or other integrated circuits are mounted on a package substrate prior to bonding step whereby a second package substrate is bonded to the first package substrate carrying the MMIC. The first substrate is then bonded to the second substrate thereby simultaneously sealing the MMIC between the substrates. This forms a prepackaged semiconductor device that can be mass-produced and coupled to other devices to form a module.
[0015] In another aspect ofthe present invention, the integrated circuit is not mounted before wafer bonding. The IC packages are not completely sealed. Instead, the package has a window etched above the site where the IC will be mounted. In one aspect, two substrates may be bound together and with a window forming empty package.
[0016] Many packages may be formed simultaneously on wafers such as a silicon wafer. On a first wafer is formed multiple first substrates at respective die positions in the wafer. On a second wafer may be formed multiple second substrates at respective positions. The wafer can be aligned and bonded to each other, thereafter the bonded wafers can be diced apart. In one embodiment, ICs can be mounted between the two substrates before the wafers are diced apart. In another embodiment no ICs are mounted before the dicing operation and after the dicing the individual packages formed by each die can be sold as an empty package. A user could then mount an IC such as an MMIC through a window located on the package. The user could then wire bond the connections and seal the packages with a cap, such as a metal cap.
[0017] Objects, features and advantages of this invention are to provide a low cost mass producible package and packaging system that can be used with high frequency devices. An aspect of the packaging system of the present invention is to enable the packages and the chips mounted therein to be interconnected via a direct attachment to one another thereby reducing loss. The present invention also eliminates the multiple prototype cycle inherent in traditional module design by providing a technology wherein a module may be immediately created by assembling prepackaged ICs with interconnecting capabilities.
[0018] Further objects, features and advantages of the invention will become apparent from a consideration of the following description and the appended claims when taken in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The above aspects of the present invention will become more apparent by describing in detail embodiments thereof with reference to the attached drawings, in which:
FIG. 1 is a plan view of a first embodiment of a micromachined package according to the invention having a double socket interconnection configuration.;
FIG. la is a plan view of a second embodiment of a micromachined package according to the invention having a double plug interconnection configuration;
FIG. lb is an underneath perspective ofthe second embodiment having the double plug configuration depicted in FIG. la wherein the electrical conductors for carrying including high frequency signals are shown;
FIG. 2 is a plan view of an alternative embodiment of a micromachined package of the invention having a single plug interconnection configuration;
FIG. 2a is a plan view of an alternative embodiment of a micromachined package of the invention having a single socket interconnection configuration;
FIG. 2b is another plan view of the single plug configuration depicted in 2a showing electrical signal conductors; FIG. 3 and 3 a are a cross sectional view of the plug and socket type connectors with transmission line metal for propagating a wave signal including millimeter wave signals;
FIG. 4 is a cross sectional across the double plug inserted into the double socket view of the interconnection system of the present invention wherein the plug is fully inserted into the socket;
FIGS. 5, 5a, and 5b are cross-sectional views down the centerline ofthe package shown in Fig. 2.;
FIG. 6 is an alternative embodiment of a micromachined package having a plug located at a longitudinal end and a socket located at the other longitudinal end;
FIG. 7 is an alternative embodiment of a micromachined package having a quad plug interconnection configuration;
FIG 8 is an alternative embodiment of a micromachined package having a plug located at each end ofthe silicon package;
FIG. 9 is a sectional view of a package of the present invention wherein the chip is mounted in the substrate aperture;
FIG. 10 is a sectional view of the chip mounted in a package and wire bonded to the CPW line on the silicon substrate;
FIG. 11 is a perspective view of an assembled micromachined package fully encapsulating an MMIC; FIG. 12 is a view of an alternate embodiment employing a nub for direct attachment purposes;
FIG. 13 is an exemplary view of the present invention's direct attachment technique;
FIG. 14 is an exemplary view of the present invention's direct attachment technique using four packages to form a module;
FIG. 15 is an exemplary view of a module formed by the present invention's direct attachment technique mounted on a circuit board; and
FIG. 16 is an exemplary view of a module formed using the direct attachment technique ofthe present invention wherein each circuit is fully encapsulated by the package.
DETAILED DESCRIPTION OF THE INVENTION [0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The present invention is not restricted to the following embodiments, and many variations are possible within the spirit and scope ofthe present invention. The embodiments of the present invention are provided to more completely explain the present invention to one skilled in the art. [0021] Referring to FIG. 1, FIG. la and FIG. lb, an embodiment for directly attaching at least two packages housing semiconductor devices together using a plug-and-socket approach is illustrated. FIGS. 1, 1a and lb will be jointly described, thus it is important to note that FIG. la and FIG. lb are the same double plug silicon package however, FIG. la illustrates an external view of the double plug silicon package while FIG. lb depicts an internal (or bottom) view ofthe double plug silicon package.
[0022] The packages may be formed of a material that can be micromachined. Micromachining is any process with the ability to selectively add or remove dielectrics and conductors to form a desired three-dimensional shape, including such processes as: etching through a photolithography-defined mask layer or punching, drilling, or routing small holes in layers which may be subsequently bonded or co-fired together. Numerous types of material may be micromachined. An example of such a material is silicon, ceramics, such as LTCC, and printed circuit board material, such as a glass/epoxy-based, PTFE-based, or ceramic/organic circuit board material. Although the invention is not limited to silicon as the substrate material, the following description is provided using silicon as an example of the package material and particularly ofthe substrate material forming the package.
[0023] In this technique, two silicon structures are fabricated, each having a male and/or female component. Specifically, FIG. 1 depicts a plan view of a double socket type silicon package (1) having both a guide socket (4) and an original socket (6). FIG. la and FIG. lb, on the other hand, illustrate a double plug silicon package (2) having both a guide plug (8) and a signal plug (10). Generally, the double plug silicon package (2) of FIG. la is fitted into the matching sockets of the double socket type silicon package (1) of FIG. 1, thereby allowing direct attachment of two devices, such as high frequency devices in a manner that enables efficient signal transmission for high frequency semiconductor devices.
[0024] The double socket type silicon package (1) and the double plug silicon package (2) are fabricated using two high-resistivity silicon wafers for each package. The fabrication process will be fully described below. As can be seen in FIG. 1, the double socket type silicon package (1) contains a circuit aperture (14) for housing an integrated circuit, preferably an MMIC. The double plug silicon package (2) also contains a circuit aperture (14). Any type of circuit, including passive or active circuits, can be packaged using the silicon-based packaging technology of the present invention. Other devices, such as optical fibers, may be housed using the silicon-based package having a male or female component, thereby allowing optical fibers to be directly coupled to one another. A further component that may be housed in one or both packages of the present invention includes an optical semiconductor component such as, a laser diode, an optical modulator or an optical receiver.
[0025] Both silicon packages (1) and (2) further contain a center conductor line (12b) separated by a non-metallized channel from a ground conductor (12a) on either side that run along the flat mating surfaces ofthe signal plug (10) and socket (6). The electrical conductors (12) for the double plug silicon package (2) are illustrated in FIG. lb. Several transmission-line/waveguides variations are possible. For example, an electrical connection can be made utilizing the coplanar waveguide- stripline (CPW-stripline) technique. This technique, as depicted in FIG. 1 and FIG. lb, employs a center conductor (12b) surrounded by two planar ground conductors (12a). The conductors may be electroplated gold metal areas, separated by unmetallized channels which expose the high- resistivity substrate. Once the signal plug (10) is inserted into the socket (6) and a tight fit is formed (as will be fully explained below), the conductors (12) all make contact. Electrically, each pair of overlaid conductors (12) act as one. The CPW-stripline transmission line runs inside each silicon package (1) and (2), where a connection is made to the MMIC located in the circuit aperture (14). This is accomplished by forming a cavity in the upper wafer to provide clearance. At this point, the transmission line makes a transition from TEM-mode CPW-stripline (which is fully surrounded by silicon) to quasi-TEM mode CPW (with silicon below and air above the plane of the conductors) (16). This transition is achieved by tapering the center conductor (12b) to achieve equal impedance and then a wire or ribbon bond makes the connection to the MMIC. This bond couples a signal input or signal output pad of the MMIC to the center conductor (12b) ofthe transmission line. ] Unlike conventional surface mount attachment technology, in the present invention, the signal does not travel up or down between packages and through a printed circuit board. This greatly simplifies the RF design, since the transmission line maintains constant cross-section until immediately before reaching the MMIC. Such a design has inherently extremely wide bandwidth and low dispersion. 028] Referring to the FIG. 1, FIG. la and FIG. lb, the silicon packages illustrate an embodiment of the direct attachment method of the present invention. Specifically, a double plug and socket configuration is used to join the two silicon packages together. A double plug silicon package (2) has a guide plug (8) that provides coarse alignment when signal plug (10) is inserted into signal socket (6) ofthe silicon package (1), wherein signal plug (10) carries the signal via the electrical conductors (12). A flexible silicon spring (18) is used to apply compressive force when the signal plug (10) is inserted into the socket (6). The spring beam (18) generates a frictional force on the signal plug (10) to secure the two packages together. Additionally, the edges of signal plug (10) and the spring beam (18) can be tapered to allow easy insertion and a positive lock when signal plug (10) is fully inserted into signal socket (6). [0029] The guide plug (8), as depicted in FIGS. 1-lb, restricts the range of travel of signal plug (10) so that the movement ofthe signal plug (10) in the signal socket (6) does not exceed the maximum excursion ofthe silicon spring beam (18), regardless ofthe position and direction in which the two packages are brought together.
[0030] Once signal plug (10) of silicon package (2) is inserted into socket (6) of silicon package (1), there is a tight fit, with only very small air gaps remaining between the silicon of the two packages. Once in a fully inserted position, the plug (8)(10) and socket (4)(6) overlap in a precise way so that the electrical conductors (12) overlap and touch, allowing the signal to flow from one package to the other. The two packages are then handled as a unit, and are mounted on a circuit board or within a separate housing to form a module. DC power and low frequency control signals may be connected by conventional surface mount connections to a circuit board or by wire bonds.
[0031] Referring to FIGS. 2, 2a and 2b, another aspect of the present invention using a single plug and socket configuration to directly attach two silicon packages that house semiconductor devices is illustrated. FIG 2 and FIG. 2a depict the external surface of a single plug silicon package (20) and single socket silicon package (30) that can be interconnected by inserting signal plug (10) into socket (6). [0032] As shown in FIG. 2, the single plug silicon package (20) has a circuit window (22), usually enclosed by a metal cap, wherein a circuit (24) is housed.
[0033] Such a circuit window may be used independent ofthe plug/socket arrangement of the packages and thus such an optional window may be also used in the embodiment of Figs. 1-15 The circuit window (22) enables circuits to be placed in the silicon package after the silicon package is fabricated. Thus, empty silicon packages can be sold such that the buyer can choose which circuit to place within the package. FIG. 2a depicts a silicon package with a circuit window (22) ready to accept any circuit. In another embodiment of the present invention (not shown), the circuit (24) is fully encapsulated by the silicon substrates, thus a circuit window (22) is not provided.
[0034] FIG. 2b depicts a bottom portion view of single plug silicon package (20), wherein the electrical conductors (12) and non-metalized channels (54) form the transmission line (12), and circuit (24) is located within the circuit aperture (14). As described above, the signal plug (10) of the single silicon package (20) is inserted into the socket (6) of package (30). Once fully inserted, the electrical conductors of silicon package (30) and silicon package (20) make contact thereby enabling a signal to pass between the two circuits housed in individual silicon packages that are directly attached. [0035] In another aspect of the present invention depicted in FIG. 3, the signal plug (10) and socket (6) are held together as a result of inversely slanted edges. FIG. 3 illustrates the signal plug (10) as trapezoidal in cross section while socket (6) is formed as a dovetail-joint-like aperture that accepts the signal plug (10). The angled edges of the socket (40) create a dovetail-joint like aperture that welcomes the slanted edges of the plug (38) to ensure a tight fit between the two silicon packages. The angles of the slanted edges (38)(40) with respect to vertical is the same on both the signal plug (10) and socket (6). The three electrical lines / conductors (12) may be gold, but any other metal may be substituted. The two gaps between the three conductors are bare silicon (54) of the substrate. It is important to note that, when utilizing some substrate materials such as certain ceramics and printed circuit board material, the edges of the plug and socket may be formed in a vertical formation. To hold the packages together, a force-applying lever or a spring-like mechanism may be bonded to the top of either the plug package or socket package such that the lever or spring located on a first package applies a force that affixes the first package to a second package.
[0036] Referring to FIG 4, a cross sectional view, across a double plug inserted into a double socket is illustrated. In FIG. 4, a silicon package (44), having a signal plug (10) and a guide plug (8), is fully inserted into the silicon package (46) having two sockets (4)(6). [0037] Electrical contact is made upon full insertion of the plug into the socket when the overlapped metal of the plug and socket form the center conductor (12b) and ground planes (12a) of the CPW-stripline transmission line. Furthermore, the guide plug (8) may provide DC and IF connections via several gold lines on the bottom of the guide plug (8) and several gold lines on the surface ofthe guide socket (4). Upon insertion of the plug (8) into the socket (4), the conductors (12) come into contact thus providing DC and IF connections.
[0038] The silicon piece (53) on the double socket silicon package separates the two sockets (4) and (6). The angled edges of (53), as seen in FIG. 4, illustrates the dove-tail sockets (4) (6) that keep the two silicon packages connected to one another when the signal plug (10), having slanted edges, is inserted into the socket (6).
[0039] FIGS. 5-5b provide another cross sectional view of a silicon package having a plug being inserted into a silicon package having a socket. The silicon package further comprises a circuit aperture (14) for housing the integrated circuit (24) which is wire bonded (43) to the electrical metal conductors (16) ofthe CPW line.
[0040] As illustrated in FIG. 5, the electrical conductors (12) run the length of both silicon packages. When the signal plug (10) is inserted into the socket (6), as depicted in FIGS. 5a and 5b, the electrical conductors (12) overlap and touch, allowing the signal to flow from one package to the other. FIG. 5 further illustrates an embodiment of the present invention wherein the circuit is not fully encapsulated within the silicon package. This allows the circuit to be placed within the package at any given time after the silicon package is fabricated. Once a circuit is placed in the package, a lid (47) is placed over the circuit aperture (14) to protect the circuit (24). In an alternate embodiment of the present invention, the circuit is fully encapsulated within the silicon package.
[0041] FIGS. 6-8 depict additional aspects of the present invention, wherein a silicon package is fabricated having multiple plug and socket components. These additional aspects illustrate preferred configurations for directly attaching silicon packages that house high frequency devices together, however, any and all configurations, utilizing a connector attachment structure fall within the ambit of this invention.
[0042] Specifically, FIG. 6 illustrates a silicon package having a socket located at one edge of the silicon package and a plug located at the opposite edge ofthe silicon package. The plug and socket may be located at any point along the edges of the silicon package and is therefore not limited to the edges ofthe package shown.
[0043] Referring to FIG. 7, a silicon package having four plugs is illustrated. One plug is located at each side of the silicon package. Any package shape having a connector formation of the present invention may be utilized. [0044] Referring to FIG. 8, a silicon package having a plug located at each end of the silicon package is illustrated. The silicon package may comprise two sockets located at each end of the silicon package. As disclosed above, the plugs/sockets may be located at any point along the silicon package. Furthermore, it is possible to have multiple chips within a package, and depending on the function, they may require any number of plug or socket components.
[0045] The fabrication of the packages may be performed using standard micromachining techniques. An embodiment of the fabrication process for a double-plug silicon package wherein one guide plug provides coarse alignment while the other plug carries the RF signal, is fully described below.
[0046] The silicon package fabrication process begins with two high- resistivity silicon wafers, approximately 20 mils thick, double side polished, hereinafter referred to as wafer 1 and wafer 2. The wafers are cleaned using an industry standard RCA cleaning process. A wet oxidation is performed using a conventional wetox process thereby heating the wafers to 1200C for four hours in a wet oxygen atmosphere. Thermal oxides approximately 1.2 microns thick are grown on both wafers.
[0047] Next, a standard double-side photolithography cycle is performed.
A coating of photoresist is applied to the backside of the wafer by spin coating and is then hard baked. A coating of photoresist is also applied to the front side of the wafer. The wafers are then patterned with the appropriate masks on both the top and bottom side.
[0048] Following the photoresist cycle, the pattern is transferred into the silicon oxide layer by wet etching. Upon completion of the wet etch, the photoresist is stripped using a standard stripper. This oxide forms a mask that protects some areas of the silicon, while areas with no oxide are exposed.
[0049] For certain types of packages, via holes are required which make electrical connection from one side of the wafer to the other. In these packages, small holes are etched from the top of wafer 1 through to the bottom side. For these holes, the aperture in the top side oxide may be square and the length of each side of the aperture is roughly twice the wafer thickness. For packages with via holes, the wafers are deep silicon etched before metal plating. For packages without via holes, the silicon etching is performed last.
[0050] The wafer is subsequently cleaned and a thin film of metal is applied as a seed layer for electroplating. The thin film is deposited by vacuum or sputtering and comprises approximately lOOnm of Chrome followed by approximately lOOnm of gold. Upon completion, the standard photoresist cycle is performed again using a photomask for metal patterning. [0051] Photoresist is applied and patterned to form the openings where metal will be electroplated. For wafers with via holes, a conformal coating of photoresist is required. This requires the use of an optimized coating process typically using thicker photoresist, slower spin speeds, and low baking temperatures. The photoresist is patterned in a contact aligner.
[0052] This pattern will consist of the CPW lines used to carry the RF signal down the plug into the receptacle. Also, the pattern will remove resist inside the via holes and from around the perimeter of the via hole; after plating, this will form a pad on the top and a pad on the bottom which are electrically connected. Gold metal is electroplated onto the wafer (for example 4 micron thickness), and then the resist is removed. The wafer is re-patterned for electroplating of the bonding metal. This pattern places bonding metal in any areas where the two wafers come into contact, except under the cantilevered silicon spring beam, which should not be attached to wafer 1 since it must be free to bend. The bonding metal is any metal which bonds under heat treatment. Examples are Tin/Lead eutectic or Tin/Gold eutectic. The photoresist is stripped, and the electroplating base is removed by wet etching or sputter etching.
[0053] For packages which have no via holes and have not yet been etched, the wafer is now ready for deep silicon etching. The wafer is immersed in a reflux tub of TMAH that causes the silicon to be removed from areas not protected by metal or silicon oxide. The wafers are removed once the etched features have proceeded all the way through the wafer. Additionally, etching may be added as needed to round the corners and other features to the exact design and shape.
[0054] Wafer 2 is bonded onto the top of Wafer 1 using an aligner- bonder. They are clamped together so that all features align correctly, and then they are bonded by a heat cycle. For example, with Sn Pb bonding metal, a 15 minute cycle to 220 C in a forming gas atmosphere is typically sufficient. After bonding, the stack of wafers is cut into individual packages with a dicing saw. The cuts are aligned to the package to properly define the edges ofthe package.
[0055] In an alternate embodiment of the invention, the above photomasks are modified somewhat to improve the definition of the features. Typically, convex corners of the mask opening quickly get rounded in the silicon etch. Thus, a standard technique is to add extensions to the corner, so that after etching it will be less rounded. The proper size of this extension for a particular etching system is determined by etching test wafers with a range of extension sizes. The mask patterns for the socket and plug silicon etches are modified to incorporate the convex-corner protection extensions.
[0056] Referring to FIG. 9, a cavity/circuit aperture formed within the silicon substrate to mount a chip is illustrated. By making the cavity/circuit aperture (14) depth approximately equal to the chip thickness, the top surface of the chip (24) after mounting is made level with the silicon surface (68). This allows a shorter wire bond, as depicted in FIG 10, to be used to connect the chip (24) input/output pads to the CPW line (12) on the silicon substrate (68).
[0057] The circuit aperture (14) is formed by inserting additional etching steps at the beginning ofthe fabrication sequence described above. The wafers are initially cleaned, and a thermal oxide grown. The oxide is then patterned with rectangular openings for the cavities. The wafer is etched in anisotropic etchant such as EDA-P to the desired depth, for example 4 mils for many MMICs. The wafer is then re-cleaned and a new thermal oxide layer is grown which seals the cavity. Upon completion of the circuit aperture/cavity, the fabrication procedure continues as described above, except that all subsequent photoresist layers are applied using a spin recipe or coater, which gives good coverage ofthe etched features.
[0058] In an alternative embodiment of the invention, chips are mounted on the silicon wafers before the bonding step. Thus, many chips are mounted on a wafer and another wafer is bonded to the first wafer, thereby simultaneously forming several sealed packages. This creates prepackaged ICs that can be directly attached to other ICs to form a module instantaneously. FIG. 11 illustrates one example ofthe packaging technology of the present invention wherein an MMIC is fully encased in the silicon package. [0059] In an alternative embodiment, ICs are not mounted before wafer bonding. Instead, the IC packages are not completely sealed, but have a window etched into the silicon wafer above the site where the IC is to be mounted. The wafers are bonded together, forming empty silicon packages. The packages are diced apart, and sold as empty packages. Users then mount an IC, through the window in the top of the package, wire bond the connections, and finally seal the package with a metal cap. This cap is a typical package cap including, stamped metal sealed with solder preforms.
[0060] Referring to FIG. 12, a nub located on both the silicon spring beam and the guide plug to provide a more positive locking action is illustrated. In this embodiment, small bumps or "nubs" (38) on both the silicon spring beam (18) and plug (8) to provide a more positive locking action when the signal plug (10) is inserted into the socket (6). The side of the plug (8) which touches the silicon spring beam (18) is slightly narrower at the tip, and moving along the plug (8) from the tip, it widens slightly, then narrows slightly. A nub/recess (62) arrangement as shown in Fig. 12 may be used.
[0061] The silicon spring beam (18) may also have a tapered shape, so that when the plug (8) is inserted, the silicon spring beam (18) will flex outward, then will move back towards its original position once the nub (38) on the plug (8) and silicon beam (18) pass each other. This provides a binding force that tends to pull the plugs (8) (10) into the sockets (4)(6). The spring beam (18) may be located at any point on the package wherein the beam is capable of applying an attaching force (compressional and/or frictional).
[0062] The nubs (38) are formed by a variety of methods. A protrusion on the photomask pattern will form such a nub, however, the etching will tend to reduce or remove this nub. Experimentation is used to find the appropriate shape for the modification to the photomask pattern.
[0063] Another aspect ofthe present invention uses edges as shown in
Fig. 12 that are angled (60) relative to the <111> crystal plane to form the nubs (38). For example, an edge (60) which is 10 degrees from the <111> plane will tend to propagate as the etch progresses, so that the angled edge (60) moves in the <111> plane at a rate of approximately five times the vertical etch rate.
[0064] In a design for 20 mil thick wafers, a propagation of approximately 112 mils is typically expected. The photomask is then adjusted so that the angled edges (60) will be in the desired position when the etching is completed. That is, the angled edges (60) are offset by 112 mils from their desired final location.
[0065] Referring to FIGS. 13-16, a module created using the direct attachment technique of the present invention is illustrated. FIGS. 13 and 13 illustrate four silicon packages with varying direct attachment components. Specifically, Package A (70) has a plug and socket configuration whereas Package C (90) and D (100) have a single plug configuration. A double socket configuration is illustrated by Package B (80).
[0066] By inserting the plug of one package into the socket of another package, an RF connection is formed between the packages. For example, a receiver can be constructed by interconnecting the following packages: Package A (70) contains a Low Noise Amplifier (LNA) MMIC chip, Package B (80) contains a mixer MMIC chip, Package C (90) contains an oscillator MMIC, and Package D (100) contains a MMIC with a printed circuit antenna (Package D (100) has no lid, so the antenna is open to the outside).
[0067] Packages A (70), B (80), and C (90) have several via holes (not shown) passing through wafer 1 connecting pads on top of wafer 1 to pads on the bottom. These via holes may be for DC power and IF connections. Wire bonds are made from the DC and IF pads on the MMICs to the pads on top of wafer 1, and they are connected through via holes to pads on the bottom ofthe package.
[0068] Package A (70) has a socket on one side for input and a plug on the opposite side for output. It has two pads on the bottom: one for DC power, and another for ground. Package B (80) has a socket on one side for RF input, and another socket on the opposite side for LO input. It has pads on the bottom for DC power and ground, and a pad for IF output. The IF output pad has a ground pad on either side. Package C (90) has a plug for RF output, and pads on the bottom for DC power and ground. Package D (100) has a plug for RF output. Referring to FIGS. 15 and 16, a module assembled using the direct attachment technique of the present invention is illustrated. To assemble the system, the plug of Package D (100) is inserted into the socket of Package A (70). Then, the plug of package A (70) is inserted into the socket for the input on package B (80). The plug of package C (90) is inserted into the socket for a local oscillator (LO) input on package B (80). Thus, the four packages are connected and form a module (105). The module (105) is then surface-mounted onto a circuit board (110), as depicted in FIG. 15, which provides connections to the pads on the bottom of the packages. The circuit board (110) provides power to the packages, and circuitry to perform IF amplification and processing.

Claims

What is claimed is:
1. An interconnectable module usable with high frequency devices comprising: a first package of a dielectric material for housing a component, said first package having at least one female connection component; and a second package of dielectric material for housing a component, said second package having at least one male connection component; wherein the male connection component of the second package is operably configured to connect to the female connection component of the first package thereby coupling the first package to the second package thus providing an efficient way to transmit signals for high frequency devices.
2. The interconnectable module of Claim 1Λ wherein the interconnected modules are surface mounted onto a circuit board.
3. The interconnectable module of Claim 1Λ wherein conductors are patterned on the first package and on the second package, whereby an electrical connection is made between the patterned conductors when the first and second package are coupled together.
4. The interconnectable module of Claim 1Λ wherein the male connection component of said second package is trapezoidal in shape and the female connection component of said first package is shaped as a dovetail like aperture, the trapezoidal shape of said male component and the dove-tail like aperture shape of said female component enable the first package to be coupled to the second package.
5. The interconnectable module of Claim 1, wherein a spring, located on an edge of one of the first package and second package applies a compressive force to the other of the first package and second package when the first package and second package are coupled together.
6. The interconnectable module of Claim 1, wherein the male connection component of said second package has at least one vertical edge and the female connection component of said first package has at least one vertical edge, wherein the vertical edge of said first package enables said first package to be coupled to said second package.
7. The interconnectable module of Claim 1, wherein the first package has a first and second female connection components and the second package has a first and second male connection components, the first male connection component having conductors for carrying an electrical connection whereas the second male connection component provides alignment when the male connection components slides into the female connection components.
8. The interconnectable module of Claim 1, wherein the first and second packages are made of silicon and the component housed in the silicon package is an integrated circuit.
9. The interconnectable module of Claim 8, wherein the integrated circuit is a monolithic microwave integrated circuit.
10. The interconnectable module of Claim 1, wherein the component housed in the first and second package of dielectric material is an optical fiber.
11. The interconnectable module of Claim 1, wherein the component housed in the first and second package of dielectric material is an optical semiconductor.
12. The interconnectable module of Claim 8, wherein the integrated circuit housed in the silicon is fully encapsulated in the silicon package.
13. The interconnectable module of Claim 1, wherein the dielectric material is silicon.
14. The interconnectable module of Claim 1, wherein the dielectric material is at least one of a glass/epoxy-based, a PTFE-based, a ceramic/organic material and a material commonly used in circuit boards
15. The interconnectable module of Claim 1, wherein the dielectric material is a ceramic.
16. The interconnectable module of Claim 1, wherein an aperture, operably configured to accept the component, is included on the first and second package of dielectric material.
17. The interconnectable module of Claim 1, wherein the first package further includes at least one male connection component thus enabling multiple packages to be coupled to the first package.
18. The interconnectable module of Claim 17, wherein the first package houses at least one integrated circuit for each female and male connection component.
19. The interconnectable module of Claim 1, wherein the second package further includes at least one female connection component thus enabling multiple packages to be coupled to the second package.
20. The interconnectable module of Claim 19, wherein the second package houses at least one integrated circuit for each female and male connection component.
21. The interconnectable module of Claim 1, wherein the first package of dielectric material has at least one hermaphrodite connection component.
22. The interconnectable module of Claim 1, wherein the first and second package of dielectric material each have at least one hermaphrodite connection component.
23. A micromachined p ackage comprising : a first micromachined substrate for housing a component; and a second micromachined substrate bonded to said first micromachined substrate wherein the second micromachined substrate has an integral connector.
24. The micromachined package of Claim 23Λ wherein the integral connector is a female connection component.
25. The micromachined package of Claim 23, wherein the integral connector is a male connection component.
26. The micromachined package of Claim 23, wherein the component is an integrated circuit and the integrated circuit is fully encapsulated by said second micromachined substrate.
27. The micromachined package of Claim 26, wherein the integrated circuit is a monolithic microwave integrated circuit (MMIC).
28. The micromachined package of Claim 23, wherein the component housed in said first micromachined substrate is an optical fiber.
29. The micromachined package of Claim 24, wherein the female component is dovetail in shape.
30. The micromachined package of Claim 25 , wherein the male component is trapezoidal in shape.
31. The micromachined package of Claim 23, wherein the integral connector is a hermaphrodite component.
32. The micromachined package of Claim 23, wherein the material ofthe micromachined substrates is a high resistivity material.
33. The micromachined package of Claim 32, wherein the high resistivity material is silicon.
34. The micromachined package of Claim 32, wherein the high resistivity material is ceramic.
35. The micromachined package of Claim 23, wherein said first and second micromachined substrate further includes conductors patterned on at least one side ofthe first micromachined substrate.
36. The micromachined package of Claim 23, wherein second micromachined substrate has at least one female connection component and at least one male connection component.
37. The micromachined package of Claim 36, wherein the first micromachined substrate houses an integrated circuit for each female and male connection component on the second micromachined substrate.
38. The micromachined package of Claim 23, further including a spring, the spring located on at least one of the first substrate and the second substrate.
39. The micromachined package of Claim 23, wherein the second micromachined substrate has a first male component having conductors that carry an electrical signal and a second male component that provides alignment.
40. The micromachined package of Claim 39, wherein the second micromachined substrate has a first female component for accepting the first male component carrying the electrical signal and a second female component for accepting the second male component that provides alignment.
41. The micromachined package of Claim 23, wherein the integral connector of the second substrate includes four male connection components, the second micromachined substrate includes four sides and wherein one of said four male connection components extends from said each ofthe four sides ofthe second substrate.
42. The micromachined package of Claim 23, wherein the integral connector of the second substrate is four female connection components, the second micromachined substrate includes four sides and wherein one of said four female connection components is located on each of the four sides of the substrate.
43. The micromachined package of Claim 23, wherein the integral connector ofthe second substrate is at least two male connection components.
44. The micromachined package of Claim 23, wherein the integral connector of the second substrate includes at least two female connection components.
45. The micromachined package of Claim 23 , wherein the integral connector ofthe second substrate includes at least one male connection component and at least one female connection component.
46 A method for interlocking packages comprising the steps of: housing a component in a first package having at least one female connection member, housing a component in a second package having at least one male connection member, and coupling the second package to the first package by coupling the male connection member to the female connection member thereby creating a functional module for high frequency devices.
47. The method for interlocking packages of Claim 46, wherein the component housed in the first and second package is an integrated circuit.
48. The method for interlocking packages of Claim 47, wherein the integrated circuit is a monolithic microwave integrated circuit.
49. The method for interlocking packages of Claim 46, wherein the component housed in the first and second package is an optical fiber.
50. The method for interlocking packages of Claim 46, wherein the component housed in the first and second package is an optical semiconductor component.
51. The method of interlocking packages of Claim 46, wherein conductors are located on at least one side of said first and second package wherein an electrical connection is made when said conductors of said second package contact said conductors of said first package when said male connection member of said second package is coupled to said female connection member of said first package.
52. The method of interlocking packages of Claim 46, wherein the first and second package are formed from silicon.
53. The method of interlocking packages of Claim 46, wherein the first and second package are formed from ceramic.
54. A package having interconnecting capabilities comprising: a substrate shaped in a plug formation, said plug having a trapezoidal cross section wherein the edges of said trapezoidal cross section are slanted in an inward direction so that the top surface ofthe plug is broader than a central surface ofthe plug; a substrate shaped in a socket formation, the socket having a dovetail aperture wherein the edges of said dovetail aperture are slanted in an inward direction; wherein the plug is accepted by the socket thereby locking the two substrates together when the edges of the plug are fitted to the inversely slanted edges ofthe socket.
55. The package having interconnecting capabilities of Claim 54, wherein the substrates having a plug and socket formation are made of silicon.
56. The package having interconnecting capabilities of Claim 54, wherein the substrate shaped in a plug formation houses an integrated circuit.
57. The package having interconnecting capabilities of Claim 54, wherein the substrate shaped in a socket formation house an integrated circuit.
58. The package having interconnecting capabilities of Claim 54, wherein the substrate shaped in a plug formation houses an optic fiber.
59. The package having interconnecting capabilities of Claim 54, wherein the substrate shaped in a socket formation houses an optic fiber.
60. The package having interconnecting capabilities of Claim 54, wherein the substrate shaped in a plug formation houses an optic semiconductor component.
61. The package having interconnecting capabilities of Claim 54, wherein the substrate shaped in a socket formation houses an optic semiconductor component.
62 The package having interconnecting capabilities of Claim 54, wherein conductors are patterned on both the plug and socket shaped substrates, whereby an electrical connection is made between the conductors of the plug and socket shaped substrates when the plug is accepted by the socket.
63. The package having interconnecting capabilities of Claim 62, wherein the conductors are gold.
64. The package having interconnecting capabilities of Claim 54, wherein the substrate having a plug formation further includes a first plug for carrying an electrical signal and a second plug for providing guide alignment.
65. The package having interconnecting capabilities of Claim 54, wherein the substrate having a socket formation further includes a first socket for accepting the first plug and a second socket for accepting the second plug that provides guide alignment.
66. The package having interconnecting capabilities of Claim 54, wherein the subsfrate having a socket formation further includes a spring, the spring applies a frictional force when the substrate having a plug formation is accepted by the subsfrate having a socket formation, and thereby assists the coupling ofthe two substrates.
67. The package having interconnecting capabilities of Claim 54, wherein the substrate having a plug formation further includes a spring, the spring applies a frictional force when the substrate having a socket formation is accepts by the substrate having a plug formation, and thereby assists the coupling ofthe two substrates.
68. A dielectric package comprising: a first dielectric substrate for housing a component; and a second dielectric substrate bonded to said first dielectric substrate wherein the second dielectric substrate has an integral connector.
69. The dielectric package of Claim 68Λ wherein the integral connector is a female connection component.
70. The dielectric package of Claim 68, wherein the integral connector is a male connection component.
71. The dielectric package of Claim 68, wherein the component is an integrated circuit and the integrated circuit is fully encapsulated by said second dielectric substrate.
72. The dielectric package of Claim 71, wherein the integrated circuit is a monolithic microwave integrated circuit (MMIC).
73. The dielectric package of Claim 68, wherein the component housed in said first dielectric substrate is an optical fiber.
74. The dielectric package of Claim 69, wherein the female component is dovetail in shape.
75. The dielectric package of Claim 70, wherein the male component is trapezoidal in shape.
76. The dielectric package of Claim 69, wherein the female component has vertically shaped edges.
77. The dielectric package of Claim 70, wherein the male component has vertically shaped edges.
78. The dielectric package of Claim 68, wherein the integral connector is a hermaphrodite component.
79. The dielectric package of Claim 68, wherein the material of the dielectric substrates is a high resistivity material.
80. The dielectric package of Claim 79, wherein the high resistivity material is silicon.
81. The dielectric package of Claim 79, wherein the high resistivity material is ceramic.
82. The dielectric package of Claim 68, wherein said first and second dielectric substrate further includes conductors patterned on at least one side ofthe first dielectric substrate.
83. The dielectric package of Claim 68, wherein second dielectric substrate has at least one female connection component and at least one male connection component.
84. The dielectric package of Claim 73, wherein the first dielectric substrate houses an integrated circuit for each female and male connection component on the second dielectric substrate.
85. The dielectric package of Claim 68, further including a spring, the spring located on at least one ofthe first substrate and the second substrate.
86. The dielectric package of Claim 68, wherein the second dielectric substrate has a first male component having conductors that carry an electrical signal and a second male component that provides alignment.
87. The dielectric package of Claim 86, wherein the second dielectric substrate has a first female component for accepting the first male component carrying the electrical signal and a second female component for accepting the second male component that provides alignment.
88. The dielectric package of Claim 68, wherein the integral connector of the second subsfrate includes four male connection components, the second dielectric substrate includes four sides and wherein one of said four male connection components extends from said each of the four sides of the second subsfrate.
89. The dielectric package of Claim 68, wherein the integral connector of the second substrate is four female connection components, the second dielectric subsfrate includes four sides and wherein one of said four female connection components is located on each of the four sides of the substrate.
90. The dielectric package of Claim 68, wherein the integral connector ofthe second substrate is at least two male com ection components.
91. The dielectric package of Claim 68, wherein the integral connector of the second subsfrate includes at least two female connection components.
92. The dielectric package of Claim 68, wherein the integral connector ofthe second substrate includes at least one male connection component and at least one female connection component.
93. A method of making an interconnectable package comprising: providing a first wafer having a plurality of bottom die; providing a second wafer having a plurality of top die patterning at least one transmission line on at least one side of said bottom die of said first wafer etching at least one integral connector and at least one transmission line on said top die of said second wafer; coupling a component to each of said plurality of bottom die of said first wafer; forming a wafer stack by bonding said second wafer to said first wafer such that said top die of said second wafer is aligned with said bottom die of said first wafer; and dicing said wafer stack into a plurality of individual packets wherein each of said plurality of packets contains a top die having said integral connector bonded to said bottom die having a component.
94. The method of making an interconnectable package of claim 93 further comprising: etching an aperture in said top die of said second wafer such that said component may be placed through said aperture and coupled to said bottom die of said second wafer after the bonding and dicing of said first and second wafer.
95. The method of making an interconnectable package of claim 94 wherein a cap is bonded over said aperture after said component is placed though said aperture.
96. The method of making an interconnectable package of claim 93, wherein the component is an integrated circuit.
97 The method of making an interconnectable package of claim 96, wherein the integrated circuit is an millimeter microwave integrated circuit.
98. The method of making an interconnectable package of claim 93, wherein the component is an optical fiber.
99. The method of making an interconnectable package of claim 93, wherein the component is an optical semiconductor.
100. The method of making an interconnectable package of claim 93, wherein the integral connector etched on said top die of said second wafer is shaped as a male connection component.
101. The method of making an interconnectable package of claim 93, wherein the integral connected etched on said top die of said second wafer is shaped as a female connection component.
102. The method of making an interconnectable package of claim 93, wherein the integral connected etched on said top die of said second wafer is shaped as a hermaphrodite connection component.
103. The method of making an interconnectable package of claim 93, wherein the integral connected etched on said top die of said second wafer is shaped as a female connection component.
104. A method of making a dielectric package for housing a component and having an integral connection member comprising: providing a first die having at least one conductor patterned on the die; providing a second die having at least one conductor pattered on said second die; bonding said second die to said first die such that the conductor on said first die is aligned with said conductor on said second die.
105. The method of making a dielectric package for housing a component and having an integral connection member of claim 104, wherein the first die is formed having a female shape.
106. The method of making a dielectric package for housing a component and having an integral connection member of claim 104, wherein the second die is formed having a male shape.
107. The method of making as dielectric package for housing a component and having an integral connection member of claim 106, further comprising: coupling a component to said first die prior to bonding the second die to said first die.
108. The method of making as dielectric package for housing a component and having an integral connection member of claim 104, further comprising: etching an aperture into said second die.
109. The method of making as dielectric package for housing a component and having an integral connection member of claim 108, wherein a component is placed through said aperture on said second die and coupled to said first die after the second die is bonded to the first die.
110. The method of making as dielectric package for housing a component and having an integral connection member of claim 104, wherein the component is an integrated circuit.
111. The method of making a dielectric package for housing a component and having an integral connection member of claim 110, wherein the integrated circuit is a millimeter microwave integrated circuit.
112. The method of making a dielectric package for housing a component and having an integral connection member of claim 104, wherein the component is an optical fiber.
113. The method of making a dielectric p ackage for housing a component and having an integral connection member of claim 104, wherein the component is an optical semiconductor.
PCT/US2001/016136 2001-05-18 2001-05-18 A high frequency, low cost package for semiconductor devices WO2002095879A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2001/016136 WO2002095879A1 (en) 2001-05-18 2001-05-18 A high frequency, low cost package for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4080026A (en) * 1976-10-28 1978-03-21 Richard Gianni Multi-level socket for an integrated circuit
JPH05152468A (en) * 1991-11-26 1993-06-18 Mitsubishi Electric Corp Ic socket
US5376825A (en) * 1990-10-22 1994-12-27 Seiko Epson Corporation Integrated circuit package for flexible computer system alternative architectures
US5825082A (en) * 1993-08-13 1998-10-20 Kabushiki Kaisha Toshiba Semiconductor device in which a first resin-encapsulated package is mounted on a second resin-encapsulated package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4080026A (en) * 1976-10-28 1978-03-21 Richard Gianni Multi-level socket for an integrated circuit
US5376825A (en) * 1990-10-22 1994-12-27 Seiko Epson Corporation Integrated circuit package for flexible computer system alternative architectures
JPH05152468A (en) * 1991-11-26 1993-06-18 Mitsubishi Electric Corp Ic socket
US5825082A (en) * 1993-08-13 1998-10-20 Kabushiki Kaisha Toshiba Semiconductor device in which a first resin-encapsulated package is mounted on a second resin-encapsulated package

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