WO2002054228A1

WO2002054228A1 - Register renaming

Info

Publication number: WO2002054228A1
Application number: PCT/GB2001/004795
Authority: WO
Inventors: Nigel Paul Smart; Michael David May; Hendrik Lambertus Muller
Original assignee: University Of Bristol
Priority date: 2000-12-06
Filing date: 2001-10-30
Publication date: 2002-07-11

Abstract

A random register renaming unit for renaming the virtual registers associated with fetched instructions that use an instruction set to corresponding physical register that are executed on a processor. The source registers specified in each fetched instruction are used as indexes into a translation look-up table that allocates a physical register to each source register. For the destination register specified in each fetched instruction, a random selection unit allocates an available physical register to the destination register and updates the translation look-up table accordingly. By renaming the registers specified by each fetched instruction the non-deterministic level of the processor is increased. This level may be increased even more where the issue unit that executes the renamed register instructions does so in a random order.

Description

REGISTER RENAMING

This invention relates to register renaming in a processor, and particularly to a method of renaming registers, a method of executing instructions in a processor and to a register renaming unit.

The era of digital communications has brought about many technological advancements which make our lives easier, but at the same time pose a new set of problems that need attention. A particular area of concern is data security where businesses and customers alike have their own security requirements of the services which they supply or receive. Computer hackers are seen by business as potential hazards for attracting new e-commerce customers, unless customers can be assured that their transactions will be secure. Many encryption schemes have been suggested in an attempt to overcome 'eavesdropping' on private or personal digital communications such as confidential email messages or receiving television broadcasts which have not been paid for, i.e. pay-TV.

Modern cryptography is about ensuring the integrity, confidentiality and authenticity of digital communications. Secret keys are used to encrypt and decrypt the data and it is essential that these keys remain secure. Whereas in the past secret keys were stored in centralised secure vaults, today's network-aware devices have embedded keys making the hardware an attractive target for hackers. A great deal of research has gone into algorithm design and hackers are more prone to concentrate their efforts on the hardware in which the cryptographic unit is housed.

One such attack is performed by taking physical measurements of the cryptographic unit as described by P.Kocher et al in the two articles entitled "Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS and other systems" and "Differential Power Analysis", both in the Advances in Cryptology journal, CRYPTO '96 pages 104-113 (1996) and CRYPTO '99 pages 388-397 (1999) respectively. By taking measurements of power consumption, computing time or EMF radiations over a large number of encryption operations and using known statistical techniques, it is possible to discover the identity of the secret keys. Kocher goes on to describe three main techniques: i) timing attacks, ii) Simple Power Analysis (SPA) and iii) Differential Power Analysis (DPA).

DPA provides the most powerful attack using very cheap resources. Many people have started to examine this problem and S. Chad et al provides a worrying analysis regarding the weakness of AES (Advanced Encryption Standard) algorithms on Smart cards, see the article entitled "A Cautionary Note Regarding the Evaluation of AES Candidates on Smart-Cards" in the Second Advanced Encryption Standard Conference, Rome, March 1999.

L. Goubin et al proposes three general strategies to combat Differential Power Analysis attacks in his article entitled "DES and Differential Power Analysis, The Duplication Method" in Cryptographic Hardware and Embedded Systems pages 158-172, 1999. These are:

i) Make algorithmic changes to the cryptographic primitives under consideration.

ii) Replace critical assembler instructions with ones whose signature is hard to analyse, or re-engineer the crucial circuitry that performs arithmetic operations or memory transfers.

iii) Introduce random timing shifts so as to decorrelate the output traces on individual runs.

The first approach has been attempted before. For example, Goubin et al suggests splitting the operands into two and duplicating the workload. This however means at least doubling the required computer resources. Similarly, Chad proposes masking the internal bits by splitting them up and processing the bit shares in a certain way so that once recombined the correct result is obtained.

Kocher et al have attempted the second approach by balancing the Hamming weights of the operands, physical shielding or adding noise circuitry, as discussed for example in "Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS and other systems".

The present invention seeks to improve tamper resistance according to the third approach, that is, by decorrelating the timing of power traces on successive program executions.

Kocher et al also describe two ways of producing the required temporal misalignment by introducing: i) introducing random clock signals, and ii) introducing randomness into the execution order. Kocher et al, in "Differential Power Analysis" mention that randomising execution order can help defeat DPA, but can lead to other problems if not done carefully. One randomising approach uses the idea of randomised multi-threading at an instruction level using a set of essentially "shadow" registers. This allows auxiliary threads to execute random encryptions, hence hoping to mask the correct encryption operation. The disadvantage is that additional computational tasks are again required and this requires a more complex processor architecture having separate banks of registers, one for each thread.

In particular, Chad et al in an article entitled "Towards Sound Approaches to Counteract Power-Analysis Attack" in Advances in Cryptology, CRYPTO '99, pages 398-4'12, shows that for a randomised execution sequence to be effective the randomisation needs to be done extensively. However, no mechanism is disclosed in Chad to enable extensive randomised execution. For example, if only the XOR instruction in each DES (Data Encryption Standard) round is randomised then DPA is still possible by taking around 8 times as much data.

DES (Data Encryption Standard) is the most widely used encryption algorithm and is known as a "block cipher", which operates on plaintext blocks of a given size (64-bits) and returns ciphertext blocks of the same size. DES operates on the 64-bit blocks using key sizes of 56- bits. The keys are actually stored as being 64 bits long, but every 8th bit in the key is not used (i.e. bits numbered 7, 15, 23, 31, 39, 47, 55, and 63). Hence for randomised execution order to work it needs to be done in a highly aggressive manner which would preclude the type of local randomisation implied by the descriptions above. In addition this cannot be achieved in software since a software randomiser would work at too high a level of abstraction. The randomised multi-threading idea is close to a solution but suffers from increased CPU time and requires a more complex processor with separate banks of registers, one for each thread.

Our earlier British Application No. 0029735.8 (PWF Ref. 102286) describes a technique which allows extensive randomised execution of instructions to be performed at run time so that successive program executions are uncorrelated.

According to the invention defined in that application there is provided a method of issuing instructions to an execution unit in a processor, the method comprising: identifying in an ordered sequence of instructions a set of instructions for which the order of execution is not critical; and selecting instructions in said set for successive execution on a random basis each time the ordered sequence of instructions is executed.

The identification of a set of instructions for which the order of execution is not critical relies on establishing instructions which do not have dependencies on other instructions in the sequence. There are two types of data dependencies between instructions. One is a dependency that a result value produced by one instruction is needed by a later instruction. Another dependency is when a result value is loaded into a register which is going to be overwritten by an instruction but where the result value is still needed by an earlier instruction.

The first mentioned dependency is a real dependency in that the computation of the later instruction cannot proceed until the previous result value has been computed. The second dependency is however a resource constraint. The computation could proceed if a different register was available to hold the result value. It is one aim of the invention to reduce the number of dependencies of the second type in a processor so as to maximise the possibility of issuing instructions in a random sequence to increase non-determinism.

A further object of the invention is to increase non-determinism in a processor regardless of whether or not instructions are issued in a random sequence.

According to one aspect of the present invention there is provided a method of allocating registers in a processor wherein an instruction set to be executed on the processor defines a set of virtual register identifiers and the processor includes a set of physical registers, the method comprising: reading virtual register identifiers specified in an instruction; and identifying physical registers associated respectively with said virtual register identifiers, said physical registers being used for execution of the instruction, wherein at least one of said physical registers is selected at random from the set of physical registers during said identifying step.

According to another aspect of the present invention there is provided a register renaming unit for use in a processor, the register renaming unit comprising: a register mapper which maintains a mapping between a set of virtual register identifiers and a set of physical registers, wherein virtual register identifiers are specified in instructions to be executed by a processor and physical registers are provided in the processor for holding values relating to by execution of the instruction; means for allocating selected physical registers from said second set to be used for the virtual register identifiers specified in an instruction; a random selection unit for selecting at least one of said physical registers at random from the set of physical registers; and means for updating the register mapper after random selection of said physical register.

According to a further aspect of the present invention there is provided a method of executing instructions in a processor, the method comprising: issuing successive instructions from an ordered sequence of instructions, wherein said instructions specify virtual register identifiers identifying registers from a first set of virtual registers; for each instruction, reading said virtual register identifiers and allocating corresponding physical registers from a second set of physical registers provided in the processor for execution of the instruction; wherein at least one of said physical registers is allocated at random from said second set; and executing said instruction using the physical registers which have been allocated to the virtual registers specified in the instruction.

The present invention will now be described by way of an example with reference to the accompanying drawings, in which:-

Figure 1 shows a block diagram of a generic CPU architecture;

Figure 2 shows a non-deterministic processor executing two instructions compared to other processors;

Figure 3 is an example of a random register renaming unit;

Figure 4 is a flow chart explaining operation of the random register renaming unit;

Figure 5 shows an embodiment of the random issue unit;

Figure 6 shows a flow chart explaining how instructions are issued at random;

Figure 7 shows an example of two input random selection unit;

Figures 8A and 8B show a generic model and a 16 input random selection unit; and

Figure 9 shows a flow chart describing a method for choosing which random instruction in the issue buffer to execute.

Figure 1 is a block diagram illustrating the standard functional units that make up a pipelined computer system. A program memory 2 contains program instructions, which are addressable at different memory locations. An ADDRESS bus 6 and a DATA bus 4 transfer information to and from the various elements that make up the processor 8. The system contains an instruction fetch unit 16 having a program counter 12 that stores the address of the next instruction to be fetched. For sequential execution of instructions the program counter will normally be incremented by a single addressing unit. However, if a branch instruction is encountered, the program flow is broken and the program counter 12 needs to be loaded with the address of a target instruction (that is, the first instruction of the branch sequence). The instructions are fetched from the program memory and stored in an instruction issue buffer 14. It is worth noting that the program counter referred to herein is used to control instruction fetches from memory. There may also be an execution counter which is used by the execution unit 18 to specify which instruction is currently being executed. Next, the instructions are decoded and supplied to relevant execution units. In this example, only one execution unit 18 or pipeline is shown, however the present invention is intended to be used in conjunction with modern processors which may have several execution units allowing parallel execution paths. Encryption algorithms need a substantial level of computational power and modern processor architectures such as superscalar, VLIW (Very Long Instruction Word) and SIMD (Single Instruction Multiple Data) are ideally suited to the present invention. Finally, the results of the operations are written back by a result write stage 22 into temporary registers of a register file 20, which is used to load and store data in and out of main memory.

The present invention is concerned mainly with the register renaming unit denoted by the reference numeral 100. Also, the present description deals with a modified issue buffer 14 which will be described in more detail later. The issue buffer generates an instruction fetch signal 13 to control which instructions are supplied from the fetch unit 10. Furthermore, part of the decode circuitry may be used to decode the instruction dependencies. This will also be described in more detail at a later stage. The processor of the described embodiment is a non-deterministic processor. Non-deterministic processing as described herein means that for successive runs of the program, although the result will be the same, the order of execution of the instructions will be random. This reduces the impact of a DPA-type attack in that the power traces resulting from successive program runs will be different.

Figure 2 serves to highlight the differences between a non-deterministic processor and other known processors when executing a simple program consisting of the following two lines of code:

>4DD a, b XOR c, d

The execution flow on the left of Figure 2 represents a standard processor having a single execution pipeline where the two instructions are executed sequentially, i.e. the ADD instruction is executed in cycle 1 followed by the XOR instruction in cycle 2. The middle execution flow represents a modern Pentium processor having a plurality of execution paths, which execute independent instructions in parallel. The execution flow on the right of Figure 2 represents a non-deterministic processor having a single pipeline.

The important point to note is that the non-deterministic processor allows the instructions to be executed in any order provided that it has been established that the instructions are independent. So in the first cycle either the ADD or the XOR instruction can be carried out and in the second cycle the other instruction will be executed. In contrast, the standard processor executes instructions sequentially and although there is a little "out of order" execution to help with branch prediction, this occurs on a small scale. In any event, in such a processor each time a program is run containing a certain sequence of instructions, the execution sequence will be identical. Although the Pentium processor has a plurality of execution units (A) and (B), which execute the independent instructions in parallel the processor is still deterministic in that the ADD and the XOR instructions are executed concurrently in pipes (A) and (B). A slightly more complex code sequence comprising eight instructions is shown in Table 1.

Table 1

It is apparent from the code listing above that the sequential execution of these eight instructions I0, 11 ... 17 is merely one way that the code sequence may be correctly executed. There are in fact 80 different code sequences, i.e. instruction orderings, for executing these eight instructions which will all give the right answer. For example, the LOAD instruction I0 reads the value of register R1 holding a memory address and the value stored at this address is written into the register R8. It can be seen that the LOAD instructions I0, 11 , 13 and 14 are all independent instructions, and an equally valid execution sequence could be, for example, 11 , I0, 13, 14, 15, 12, 16, 17 in that none of them are dependent on the results of execution of another. However, an incorrect result occurs if the ADD instruction 12 is executed before the LOAD instruction 11. That is, the purpose of 11 is to LOAD a value addressed by register R2 into register R9. The intention of the code sequence is to add the loaded value from R8 to the value in R9. Therefore, if the ADD instruction 12 is carried out before 11 , the old value of R9 will be added to R8 yielding an incorrect value for the resulting summation R10. We say that there is a dependency between the ADD instruction 12 and the LOAD instruction 11.

The non-deterministic processor described herein makes use of the fact that in many code sequences a number of instructions are independent and thus can, in theory, be executed in any order. This is exploited by executing the instructions in a random order at run time. This causes the access patterns to memory for either data or instructions to be uncorrelated for successive program executions, and thus causes the power trace to be different each time.

However, conversely, there are many code sequences in which there are data dependencies between instructions. This is particularly the case where registers are used to hold computed values. Where register resources are constrained, it can frequently be the case that execution of an instruction must be held up, not because its values are not available to carry out the computation defined by the instruction, but because there is no free register into which to write the result. This is because the register is already in use, and, often, it may be in use for several cycles of execution, effectively holding a live value which is not required until later in the code sequence. Clearly this is a wasted resource.

The technique described in the following allows the register resource to be fully utilised, whilst also increasing the non-deterministic nature of the processor. It has the added benefit that certain data dependencies between instructions are removed, thereby allowing greater flexibility for issuing instructions in a random order.

Reference numeral 100 in Figure 1 denotes a register renaming unit which is located in the fetch stage 10 of the processor. The detailed construction of the register renaming unit 100 is shown in Figure 3. The register renaming unit 100 allows registers to be named during execution of a program. A virtual register set is defined, which are the registers specified by a particular instruction set. These are referred to herein as R1 , R2 etc. Exemplary code sequences therefore use this denotation to denote virtual registers. Registers in the register file 20, that is the so-called physical registers are specified herein using Reg1 , Reg2 etc. It is these physical registers which are the ones actually used by the processor for execution of instructions. To implement the present invention, the number of physical registers should be greater than the number of virtual registers.

The register renaming unit 100 comprises a translation look-up table 102 which maintains a mapping from virtual to physical registers. In essence, the translation look-up table 102 contains an index for every virtual register specified in the instruction set. One such fetched instruction is labelled 212 in Figure 3, supplied along an instruction fetch path 214. Using this index it is possible to locate a physical register associated with the specified virtual register.

Physical registers can be pre-allocated to virtual registers, or can be allocated (or reallocated) on the fly as discussed more particularly in the following in relation to destination registers. A random selection unit 106 selects physical registers at random using a random number generator 108 as described more fully in the following.

Operation of the random register renaming unit 100 will now be described with reference to Figure 3 and also with reference to the flow diagram of Figure 4. The random register renaming unit 100 is operative in relation to each instruction 212 which is fetched by the fetch unit 12. These instructions define virtual registers R1, R2 etc. One such instruction is labelled as 212 in Figure 3. The instruction 212 has an opcode field OPC, first source operand field VSRO, a second source operand field VSR1 and a destination field VDR. The virtual source operand fields VSRO, VSR1 (of course taking the form of virtual registers identifiers R1 , R2, etc) are supplied as indexes into the register translation lookup table 102. The mappings for the source operands are predetermined and are set into the look up table. The physical registers associated with these virtual registers and obtained from the translation look-up table 102, are then supplied as Reg1 , Reg2 into physical source operand fields PSR1 , PSR2 of a renamed instruction 210. The destination operand field VDR of the fetched instruction 212 specifies a destination virtual register, that is one in which a result is to be loaded. The register translation look-up table 102 will use the VDR (Virtual Destination Register) as an index into the table 102, and in this explanation it is assumed that the indexed table entry initially contains the number of physical register 3. A physical register for holding the destination result is selected randomly from the set of physical registers marked as 'free'. This selection is performed by the random selection unit 106 and will now be described.

The set of free' registers is determined using an issue window matrix 200 whose purpose is to keep track of the physical registers being used by the instructions.

Assume there are 2^V virtual registers (registers used in the instruction set) and 2^P physical registers (registers used in the processor) where P and V are integers and P is larger than V. The issue window matrix 200 has I rows where each row of the matrix corresponds to an instruction, and 2^P columns, where each column corresponds to a physical register (i.e. Reg1 ,Reg2, etc). A matrix of size Ix2^p maintains for each instruction in the issue window which physical registers that instruction uses. A one in element (i, p) in the matrix indicates that physical register p will be used by instruction i. A zero in element (i, p) indicates that register p will not be used by instruction i. Alternatively, if a physical register is being used by a particular instruction then a flag bit corresponding to the relevant matrix element is set to one whereas if the physical register is not being used then the flag bit is a zero.

Figure 3 also illustrates a set of physical register usage flags (PRUF) labelled as row 201. These can be implemented as an extra row associated with the issue window matrix (as illustrated) or separately. These flags represent which physical register may be used by future instructions. A "1" in column (p) indicates that register p may be used by future instructions. A "0" in column (p) indicates that register p cannot be used by future instructions.

Therefore, after the virtual operands of a fetched instruction have been renamed to corresponding physical registers using the random register renaming unit 100, then the flag bits associated with each of the physical registers used by the renamed instruction 210 will be set 202 in the issue window matrix 200. In other words, an instruction with renamed physical registers is stored in location 202 of the issue window 200 such that the bits in row 202 that are set to one correspond to the instruction's physical source and destination registers.

The physical register usage flags 201 are updated by clearing the bit associated with the old mapping of the destination register along path 221 , and by setting the bit associated with the new mapping of the destination register.

An OR gate performs a logical OR operation across all the flag bits of a particular column of the issue window matrix 200. Each column corresponds to a physical register such that if the OR'ed result for a column is zero then this indicates that the relevant physical register is not being used by any instructions. Thus, for each of the 2^P OR gates 206, the result is checked such that if a one is output then the physical register is being used by at least one instruction, whereas if the result is a zero this indicates that the corresponding physical register is free and is available for selection by the random selection unit 106.

The random selection unit 106 uses the random number generator 108 to randomly select one of the set of physical registers marked as being free. Two processes then occur:

i) the translation look-up table 102 is updated to include an identification along path 220 of the newly mapped randomly selected physical register as corresponding to the virtual destination register identified in the instruction;

ii) the destination virtual register as specified in the fetched instruction is renamed by supplying the identifier along path 222 to specify the randomly selected physical register.

Once an instruction has been completed, the flag bits of all the physical registers of the row corresponding to the completed instruction in the issue window table are marked as free 204 (i.e. set to zero). Alternatively, a preferred solution would be to reset (i.e. set to zero) the flag bits corresponding to the source registers when the source registers have been read by the execution unit 18, and to reset the destination register when the result value has been written.

Therefore, the operands of the fetched instruction that originally identified virtual register have been renamed to specify physical register identifiers 210. The instruction 210 with renamed registers is then sent via path 208 to the issue buffer 14. It should be understood that the non-deterministic nature of the processor can be increased if the instructions in the issue buffer can be executed at random using a random issue unit as described in more detail later with reference to Figure 5. Alternatively, these instructions can be executed normally using a conventional processor architecture where the issue unit does not execute instructions in a random order.

In the flow diagram of Figure 4, step S100 denotes the initial mapping step. Step S102 denote the maintenance of the used bits where the row of matrix 200 associated with a completed instruction is cleared and the flag bits of the matrix 200 are set for the physical source and destination registers used. This includes setting the flag bits in row 201 relating to the use of feature instructions. Step S104 denotes the final updating of the register translation look-up table 102.

Assume that there is the following code sequence having the two assignment statements A=B and C=D:

LOAD B, R0

STORE R0,A

LOAD D, R0

STORE R0, C

By replacing all occurrences of R0 from the second LOAD instruction by R1 , it is possible to remove the data dependency that exists between the use of R0 in the first STORE instruction and the writing into R0 by the second LOAD instruction. The following code sequence illustrates one of the advantages of random register renaming, where the example now has been extended to four assignment statements, A=B, C=D, E=F and G=H and where only two registers are to be to be used. The random register renaming operation can be done on the fly, while performing the assignment operations. However, in the context of a limited set of available registers, there is only limited renaming which can be performed at compile-time. The following sequence represents the best register renaming which would be possible in the absence of the random register renaming technique herein described:

LOAD B, R0

STORE R0,A

LOAD D, R1

STORE R1,C

LOAD F, R0

STORE R0, E

LOAD H, R1

STORE R1,G

There are 70 different ways of executing this code sequence. This can be increased to 2520 ways if four registers were available and there were no dependencies between the assignment statements.

Therefore, by employing random register renaming at run-time a renaming unit will check for dependencies and rename registers at random, so that for the example given above the code sequence can be renamed in any of the ways shown below.

LOAD B, R0 LOAD B, R0 LOAD B, R0 LOAD B, R0

STORE R0, A STORE R0, A STORE R0, A STORE RO,

A LOAD D,R0 LOAD D, R1 LOAD D, RO LOAD D, R1

STORE RO, C STORE R1.C STORE RO, C STORE R1, C

LOAD R,R0 LOAD F, RO LOAD F, R1 LOAD F, R1

STORE RO, E STORE RO, E STORE R1,E STORE R1,E

LOAD H, RO LOAD H, RO LOAD H, RO LOAD H, R1

STORE RO, G STORE RO, G STORE RO, G STORE R1,G

Therefore, by increasing the number of registers available to be used for renaming and using the technique of randomly allocating these registers the number of ways of executing a code sequence increases, and corresponds to an overall increase in the level of non-determinism exhibited by the processor.

Random register renaming has another advantage. Power dissipation of overwriting a register from one value with another depends on both data values (that is the number of bits which need to be flipped). If it is not predetermined how registers are allocated, then the power dissipation between write-backs into the register file is not deterministic.

Thus, the random register renaming technique described herein can be used by itself to improve non-determinism in a processor. Alternatively, it can be used in conjunction with the random issue of instructions so that the two effects together provide a synergistic result in increasing tamper-resistance. The random issue of instructions is now described in the following. It will be appreciated that the instruction which is supplied to the random issue unit discussed below is the renamed instruction 210 of Figure 3.

Figure 5 shows an example of the implementation of a random issue unit. The random issue unit comprises an instruction table 32 with an associated dependency matrix table 30. Instructions are prefetched into the instruction table 32 using conventional instruction fetch circuitry. The dependency matrix table has slots and columns, where the slots represent bit-masks associated with each instruction in the instruction table 32. The bit-masks or dependency bits are an indication as to whether an instruction has a dependency on another instruction. Broadly speaking there are two types of dependencies that need to be considered for an instruction:

1) Use dependencies - which are the dependencies of the source registers that an instruction uses to read data from.

2) Defined dependencies - which are the dependencies of the destination registers that an instruction defines to write data to.

In Figure 5, a particular instruction will be decoded and the mask bits will be set accordingly in the Used Registers table 34 and Defined Registers table 36. The Used and Defined Register tables 34, 36 shown in Figure 5 each comprise a number of rows and columns. Each row corresponds to a register (or operand) and each column corresponds to a particular slot (or instruction) in the instruction issue table 32. Each register comprises a plurality of slots corresponding to the number of instructions in the instruction table 32 and is the so-called bit-mask for a register. The bit-mask for a register is a binary stream where a "1" indicates which instruction has a dependency on that register. As an example, consider the Used and Defined Register tables 34, 36 of Figure 5 where each table has five rows corresponding to registers Reg1 to Reg5, i.e. Reg1 corresponds to the top row and Reg5 to the bottom row. At run-time the processor performs a logical OR operation 38 of the bit mask of the Used Registers table 34 and the Defined Registers table 36 thereby creating a new bit-mask stored in a free slot of the dependency matrix 30.

A test can be performed by OR-ing with OR gates 40 each of the dependency bits of a slot of the dependency matrix. If all the dependency bits of a slot associated with a particular instruction are set to zero, then the instruction can be executed and a FIRE signal 42 is generated to the Random Selection Unit 44. Given the result of the OR for each row of the table, a number of zeros (indicating instructions to be executed) and a number of ones (indicating instructions that are blocked) are obtained. The random selection unit 44 selects one of the slots which is indicated at value zero, at random, and causes that instruction to be executed next. In the described embodiment, the dependency bits are overwritten with new values when the dependencies of the next instruction are loaded into the matrix.

All the instructions that have no dependencies are thus identified by fire signals 42 to the random selection unit 44. For purposes of clarity we will assume a single execution pipeline where for each execution cycle the random selection unit selects by selection signal 46 only one of the fired instructions. However it should be appreciated that for example, in a superscalar architecture having parallel execution pipelines, a number of instructions could be issued in parallel under the control of the Random Selection Unit 44. The selection signal 46 of the Random Selection Unit 44 points to an instruction to be executed, while at the same time issues a feedback signal 48 to "free-up" future instructions that may have been dependent on the instruction currently being executed.

The random issue unit supplies an instruction to be executed from the instruction table 32 along instruction supply path 50 and loads an instruction into the instruction table 32 along instruction load path 52 at the same time. Figure 6 is a flow chart indicating how the instructions in the instruction issue buffer 14 are issued for execution and loaded concurrently. The load operations are represented by the left branch flow (C), while the issue operations are represented by the right branch flow (D).

The left branch flow (C) of figure 6 relates to an instruction load operation starting at step S1 where the next instruction, specified by the program counter 12, is loaded into the instruction table 32 of the issue buffer 14. The load operations will firstly be described in general terms, and then more specifically in relation to one example. Each instruction defines two source operands 54 and a destination operand 56. These will nearly always be defined as registers although that is not necessary. Direct addresses or immediates are possible. The source and destination operands 54,56 are simultaneously decoded. At S2, the decoded information is translated into bit-masks that are set in the Used Registers and Defined Registers tables 34,36. These bit-masks are OR-ed by OR gate 38 (Figure 5) to create dependency bits indicating on which instructions the loaded instruction depends. At S3, the empty slot E associated with the loaded instruction is then selected for replacement by setting the InValid flag 58 to zero. The dependency bits are loaded into the selected slot E of the dependency matrix. At S4, the bit-masks in column E of the Registers Used and Registers Defined tables 34,36 are set to "1" along path 62 for the corresponding rows of these tables to ensure that future instructions that use those registers are going to wait for the instruction to finish.

A specific example of the load operation will now be described.

The Used and Defined Register tables 34, 36 are set-up during the instruction fetch or LOAD sequence, as already indicated. The fetched instruction is decoded and the bit-masks associated with each of the registers specified in the instruction are checked for dependencies with other instructions. For example, assume the instruction: ADD Reg2, Reg3, Reg4 is fetched. The bit masks associated with the registers Reg2 and Reg3 in the Used Registers table 34 (i.e. the source registers) are sent to OR gate 38. Also, the bit mask associated with register Reg4 in the Defined Registers Table (i.e. the destination register) is sent to the OR gate 38. Assuming there are N instructions in the instruction table 32, therefore each bit mask has N slots where each slot corresponds to a particular instruction.

The OR gate 38 receives the bit-masks and performs a bit-wise logical OR operation for each slot simultaneously. For example, assume the following bit- masks exist:

The resulting set of dependency bit (or dependency mask) is shown as

0010000 0, which is then sent from the OR gate 38 to a horizontal slot in the dependency matrix 30 that is associated with the corresponding instruction of the instruction table 32. During the execution stage (which is discussed more fully below with reference to the right branch of figure 6), the first step includes simultaneously performing a second OR operation 40 across all the dependency bits for each slot of the dependency matrix 30 to determine which instructions have no dependencies. For the example, a "1" set in the third bit of the dependency mask for the instruction in question means that the OR'ed result will be a "1". Therefore this instruction still has dependencies stage and cannot be fired at the random selection unit 44.

Returning to the load operation (i.e. left branch of Figure 6), the final step is to set the appropriate bit masks associated with the currently loaded instruction. The appropriate bit-masks being the registers that cannot be used by future instructions until the current instruction has been issued. Thus, for the example instruction (i.e. ADD Reg2, Reg3, Reg4), register Reg4 in the Used Registers table 34 for the present instruction column in set to "1" to inform all future instructions that Reg4 cannot be used as a source register (i.e. read from), because the present instruction uses this as a destination register (i.e. write to). Similarly, registers Reg2 and Reg3 are source registers for the present instruction and thus these registers are set to "1" in the Defined Registers table 36 to indicate that these registers cannot be written to until the present instruction has completed. The right branch flow (D) of Figure 6 relates to random instruction issue starting at S1 where the dependency bits associated with each instruction are checked using an OR operation via OR gate 40. Then all of the independent instructions are flagged as ready for issue and appropriate fire signals are sent to the Random Selection Unit. At step S2, the Random Selection Unit 44 selects one of the instructions 46 for example the instruction X, which is issued along instruction supply path 50 to the relevant execution unit. At S3, column X is then cleared (i.e. bits are set to zero) from the dependency matrix 30 as well as from the Registers Used and Registers Defined tables 34, 36. Also, the InValid flag is set (i.e. to 1). Thus, the dependency column for the instructions currently being executed is erased, indicating that any instruction waiting for this instruction can now be executed. According to step S4, a pointer E is initialised for the next iteration. E is a pointer that points to an empty slot which is available in the issue table. After every instruction has been loaded, E must point to another free slot. One could, for example, use the instruction previously executed to initialise E. In that way, the pointer E would follow the executed instructions around the table.

Figure 7 represents a two input example of how a random selection unit 44 may be implemented. The truth table for the random selector is shown below:

Table 2

Figure 7 shows two inputs 70 and 72 for the random selection unit 44. It should be apparent from figure 5 that each input I_. or \-_ will either be a '0' or a '1'. More generally, a '0' will appear if all of the dependency bits of the relevant slot are '0'. Thus, a '0' indicates an independent instruction, which can be selected by the Random Selection Unit 44. An inspection of truth table 2 reveals that if one of the inputs is a '1', then the output 46 of the random selector will always take the logical value of the other input. Input is shown coupled to an AND gate 76 through an inverting element 75. The AND gate 76 accepts two other inputs, i.e. a random signal R 80 and an enable signal E 78. The output of the AND gate is OR-ed 74 with input l₀ to produce the selected output 46 of the random selection unit 44.

The random signal R does not have to be truly random. It could be typically generated using a pseudo-random generator that is reseeded regularly with some entropy. The enable signal 78 allows random issue to be disabled, i.e. non- determinism can be turned off, for example to allow a programmer to debug code by stepping through the instructions.

Figures 8A and 8B show a slightly more complex example of a random selection unit having 16 inputs. As shown a 16 input random issue unit can be provided by adapting the simple two input structure shown in Figure 7 and connecting it in a cascaded structure. Figure 8A shows a generalised stage of one of the random selection units. The inputs run from l₀ to 1₂ ^κ+1-1. The generalised stage can be applied to the 16 input random selector shown by Figure 8B.

Sixteen inputs means the selector has inputs l₀ to l₁₅ and from the generalised case we can say:

2^K+1-1=15 2^K+1 = 16

Therefore, k = 3

Therefore in the final stage (i.e. R-box3), the 16 inputs are divided in half with the even inputs I0. 12... 114 being input to a first multiplexer 82 and the odd inputs 11 , 13, ...115 being input to a second multiplexer 84. Each multiplexer selects 1 output from 2^k inputs (i.e. 8:1 in the final stage) and each multiplexer accepts control signals from the lower stages A_. ... Aκ-ι (i.e. A_, A-i, A₂ in the final stage). This is confirmed by diagram on the right, which shows the selected signals from the lower stages being feedback into the higher stages. Then the relevant stage behaves as the two input model shown in Figure 7.

Figure 9 is a flow chart illustrating a method to choose which instruction in the instruction buffer to execute. At S11 , the issue buffer is assigned the symbol B. At S12, the number of instructions remaining in the issue buffer 14 is examined and if the buffer contains only one instruction then step S13a issues this instruction to the relevant execution unit and the program sequence is completed i.e. EXIT. If however, there is more than one instruction in the buffer, step S13b involves dividing the buffer into two sets of roughly equal size and assigning the symbols L and R respectively. Then at S14, the instructions within the L buffer are examined to see if any independent instructions can be issued. If not, step S15b sets the active issue buffer B to look at buffer R and the process is repeated from step S12. If however, buffer L does contain instructions that are ready for issue, then at step S15a, the R buffer is examined to see if it contains any instructions ready for issue. If not, step S16b sets the active buffer B to be buffer L and the process is repeated from step S12. If both L and R contain instructions that are ready for issue, the flow proceeds to step S16a where a random bit is generated. If the random bit is '1 ' then the process moves to step S16b where the L buffer is selected or if the bit is a '0' then the process moves to step S15b where the R buffer is selected. In both cases, the process will be repeated until there is only one instruction in one of the buffers in which case step S13a is invoked and the program sequence is completed. Although the specific example outlined in the invention is directed at cryptography, it should be understood that this invention may be equally applied to any situation where it is desired to keep the environmental impact of the processor non-deterministic, for example reducing resonances in small computing devices. Furthermore, it should be appreciated that the random selection unit described herein is only an example of a possible implementation. The present invention may include any features disclosed herein either implicitly or explicitly or any generalisation thereof, irrespective of whether it relates to the presently claimed invention. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims

CLAIMS:

1. A method of allocating registers in a processor wherein an instruction set to be executed on the processor defines a set of virtual register identifiers and the processor includes a set of physical registers, the method comprising:

reading virtual register identifiers specified in an instruction; and

identifying physical registers associated respectively with said virtual register identifiers, said physical registers being used for execution of the instruction,

wherein at least one of said physical registers is selected at random from the set of physical registers during said identifying step.

2. A method according to claim 1 , wherein each virtual register identifier specified in an instruction is used as an index into a translation look-up table having a mapping that associates physical registers with respective virtual register identifiers.

3. A method according to claim 1 or 2, wherein each instruction comprises virtual register identifiers for at least one source operand and a destination operand.

4. A method according to claim 1 , wherein the at least one of said physical registers selected at random is allocated to the destination operand of said instruction.

5. A method according to claim 4, comprising the step of maintaining a record of the physical registers of said physical register set which are free wherefrom the random selection may be made.

6. A method according to claim 5, wherein the record is maintained in a matrix comprising a plurality of rows and columns where each row forms an instruction slot corresponding to an instruction and each column corresponds to a physical register, wherein flag bits are set at each row and column intersection where a physical register is specified in a certain instruction.

7. A method according to claims 5 and 6, which comprises the step of determining which physical registers are free by performing a logical OR operation across the flag bits for all the columns and checking if the result is set, thereby indicating that at least one of the instructions is using said physical register such that it is not free.

8. A register renaming unit for use in a processor, the register renaming unit comprising:

a register mapper which maintains a mapping between a set of virtual register identifiers and a set of physical registers, wherein virtual register identifiers are specified in instructions to be executed by a processor and physical registers are provided in the processor for holding values relating to by execution of the instruction;

means for allocating selected physical registers from said second set to be used for the virtual register identifiers specified in an instruction;

a random selection unit for selecting at least one of said physical registers at random from the set of physical registers; and

means for updating the register mapper after random selection of said physical register.

9. A register renaming unit according to claim 8, wherein the register mapper is a translation look-up table.

10. A register renaming unit according to claim 8, wherein the means for allocating selected physical registers comprises an issue window matrix having a plurality of rows and columns where each row forms an instruction slot corresponding to an instruction and each column corresponds to a physical register, wherein flag bits are set at each row and column intersection where a physical register is specified in a certain instruction, whereby physical registers which are not free to be selected are identifiable.

11. A register renaming unit according to claim 10, comprising means for clearing the flag bits corresponding to a particular row of the issue window matrix when the instruction corresponding to that row has been executed such that the physical registers are subsequently identifiable as free to be selected.

12. A method of executing instructions in a processor, the method comprising: issuing successive instructions from an ordered sequence of instructions, wherein said instructions specify virtual register identifiers identifying registers from a first set of virtual registers;

for each instruction, reading said virtual register identifiers and allocating corresponding physical registers from a second set of physical registers provided in the processor for execution of the instruction;

wherein at least one of said physical registers is allocated at random from said second set; and

executing said instruction using the physical registers which have been allocated to the virtual registers specified in the instruction.

13. A method according to claim 12, wherein the renamed instruction to be executed identifying the physical registers is held in an instruction issue unit prior to execution.

14. A method according to claim 13, wherein the instruction issue unit is arranged to issue renamed instructions for execution in a random order.