WO2002050700A3 - Processor architecture - Google Patents

Processor architecture Download PDF

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Publication number
WO2002050700A3
WO2002050700A3 PCT/GB2001/004685 GB0104685W WO0250700A3 WO 2002050700 A3 WO2002050700 A3 WO 2002050700A3 GB 0104685 W GB0104685 W GB 0104685W WO 0250700 A3 WO0250700 A3 WO 0250700A3
Authority
WO
WIPO (PCT)
Prior art keywords
processing element
signal line
value
port
logic state
Prior art date
Application number
PCT/GB2001/004685
Other languages
French (fr)
Other versions
WO2002050700A2 (en
Inventor
Anthony Peter John Claydon
Original Assignee
Picochip Designs Ltd
Anthony Peter John Claydon
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Picochip Designs Ltd, Anthony Peter John Claydon filed Critical Picochip Designs Ltd
Priority to JP2002551728A priority Critical patent/JP4241045B2/en
Priority to AU2001295768A priority patent/AU2001295768A1/en
Priority to US10/450,615 priority patent/US8386752B2/en
Priority to EP01976500A priority patent/EP1377911A2/en
Publication of WO2002050700A2 publication Critical patent/WO2002050700A2/en
Publication of WO2002050700A3 publication Critical patent/WO2002050700A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Bus Control (AREA)
  • Power Sources (AREA)
  • Information Transfer Systems (AREA)

Abstract

There is described a processor architecture having a plurality of processing elements, each element having at least one input port and at least one output port, each port having at least a data bus and a valid data signal line; and a bus structure which contains a plurality of switches which are arranged so as to allow an output port of any first processing element to be connected to the input port of any second processing element for a time interval, in which each processing element is enabled to set a value on the valid data signal line of its output port to a first logic state when the associated data bus contains a transfer value, and to a second logic state when the data bus does not contain a transfer value, and in which each processing element is further enabled to enter a waiting state for a predetermined time interval when the value on the valid data signal line of the associated input port is in the second logic state. This reduces the power consumption of the device.
PCT/GB2001/004685 2000-12-19 2001-10-19 Processor architecture WO2002050700A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2002551728A JP4241045B2 (en) 2000-12-19 2001-10-19 Processor architecture
AU2001295768A AU2001295768A1 (en) 2000-12-19 2001-10-19 Processor architecture
US10/450,615 US8386752B2 (en) 2000-12-19 2001-10-19 Processor architecture
EP01976500A EP1377911A2 (en) 2000-12-19 2001-10-19 Processor architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0030994.8 2000-12-19
GB0030994A GB2370381B (en) 2000-12-19 2000-12-19 Processor architecture

Publications (2)

Publication Number Publication Date
WO2002050700A2 WO2002050700A2 (en) 2002-06-27
WO2002050700A3 true WO2002050700A3 (en) 2003-11-06

Family

ID=9905411

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2001/004685 WO2002050700A2 (en) 2000-12-19 2001-10-19 Processor architecture

Country Status (7)

Country Link
US (1) US8386752B2 (en)
EP (1) EP1377911A2 (en)
JP (2) JP4241045B2 (en)
CN (1) CN1316402C (en)
AU (1) AU2001295768A1 (en)
GB (1) GB2370381B (en)
WO (1) WO2002050700A2 (en)

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US8862076B2 (en) 2009-06-05 2014-10-14 Intel Corporation Method and device in a communication network
US8892154B2 (en) 2009-06-05 2014-11-18 Intel Corporation Method and device in a communication network
US8904148B2 (en) 2000-12-19 2014-12-02 Intel Corporation Processor architecture with switch matrices for transferring data along buses
US9107136B2 (en) 2010-08-16 2015-08-11 Intel Corporation Femtocell access control

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US10445234B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features
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US10445451B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features
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US10515049B1 (en) 2017-07-01 2019-12-24 Intel Corporation Memory circuits and methods for distributed memory hazard detection and error recovery
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Cited By (5)

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Publication number Priority date Publication date Assignee Title
US8904148B2 (en) 2000-12-19 2014-12-02 Intel Corporation Processor architecture with switch matrices for transferring data along buses
US8849340B2 (en) 2009-05-07 2014-09-30 Intel Corporation Methods and devices for reducing interference in an uplink
US8862076B2 (en) 2009-06-05 2014-10-14 Intel Corporation Method and device in a communication network
US8892154B2 (en) 2009-06-05 2014-11-18 Intel Corporation Method and device in a communication network
US9107136B2 (en) 2010-08-16 2015-08-11 Intel Corporation Femtocell access control

Also Published As

Publication number Publication date
AU2001295768A1 (en) 2002-07-01
JP2004525440A (en) 2004-08-19
US20050076187A1 (en) 2005-04-07
EP1377911A2 (en) 2004-01-07
CN1316402C (en) 2007-05-16
GB2370381B (en) 2003-12-24
GB0030994D0 (en) 2001-01-31
JP4241045B2 (en) 2009-03-18
CN1518705A (en) 2004-08-04
WO2002050700A2 (en) 2002-06-27
JP2009054154A (en) 2009-03-12
US8386752B2 (en) 2013-02-26
GB2370381A (en) 2002-06-26

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