WO2002046885A2 - Handling conditional processing in a single instruction multiple datapath processor architecture - Google Patents
Handling conditional processing in a single instruction multiple datapath processor architecture Download PDFInfo
- Publication number
- WO2002046885A2 WO2002046885A2 PCT/US2001/050992 US0150992W WO0246885A2 WO 2002046885 A2 WO2002046885 A2 WO 2002046885A2 US 0150992 W US0150992 W US 0150992W WO 0246885 A2 WO0246885 A2 WO 0246885A2
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- WO
- WIPO (PCT)
- Prior art keywords
- state
- datapath
- processing
- conditional
- value
- Prior art date
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- 238000012545 processing Methods 0.000 title claims abstract description 186
- 238000000034 method Methods 0.000 claims description 26
- 230000008859 change Effects 0.000 claims description 12
- 230000008569 process Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Definitions
- TECHNICAL FIELD This invention relates to handling conditional processing in a single instruction multiple datapath (SIMD) processor architecture.
- SIMD single instruction multiple datapath
- SIMD processor is a parallel processor array architecture wherein multiple datapaths are controlled by a single instruction. Each datapath handles one data item at a given time. In a simple example, in a SIMD processor having four datapaths, each data item in a four data item array would be processed in a respective one of the four datapaths.
- multiple datapaths may be enabled prior to encountering a conditional processing block, such as an if-then-else- processing block.
- the processor enable (PE) states of each of the datapaths i.e., whether they are enabled or disabled, must be saved in case any of the datapath PE states is changed during execution of the conditional processing block. Further, upon exiting the conditional processing block, the PE states of the datapaths must be restored to the states that existed prior to entry of the conditional processing block.
- One approach to handling the datapath PE states during conditional processing operations is to maintain the PE state of each datapath in a register stack. As the PE state of the datapath is changed during the conditional processing, the previous PE state is pushed onto the register stack. Upon completion of the conditional processing block, the datapath's PE state is restored to that which the datapath had prior to executing the conditional processing block, by popping that previous PE state off the register stack. If the conditional processing block contains multiple conditional operations (e.g., nested if-then-else-operations), the stack must contain multiple registers to save the datapath PE states during (and restore the datapath PE states after) the various conditional operations. It may be difficult for software to manage the stack during nested conditional operations, because of limitations in the number of parallel registers available for use in the stack.
- One general aspect of this invention features maintaining a PE state of a datapath during conditional processing, by saving a current PE state of the datapath as an indication thereof before the conditional processing, and manipulating the indication during the conditional processing to reflect changes in the PE state of the datapath that may occur during the conditional processing.
- the invention features an instruction set and an SIMD processor for carrying out these steps. Preferred embodiments may include one or more of the following features.
- the saved PE state of the datapath is restored based at least in part on the indication.
- the saving, manipulating, and restoring steps are performed for each one of a plurality of datapaths in a SIMD processor that performs the conditional processing.
- the conditional processing includes an if- processing statement.
- the saving step includes storing the indication as a value representing the current PE state of the datapath.
- the manipulating includes changing the value based on the PE state of the datapath during the conditional processing. The value is incremented if the PE state of the datapath is disabled during the saving. The value is not changed from an initial value if the PE state of the datapath is enabled during the conditional processing.
- the saved PE state of the datapath is restored based at least in part on the value.
- the restoring comprises assigning the datapath to a disabled PE state if the value exceeds a threshold, and otherwise assigning the datapath to an enabled PE state.
- the value is changed (e.g., decremented) if the value exceeds the threshold.
- the conditional processing block may comprise a plurality of the if-processing statements. In this case, the saving, manipulating, and restoring steps are performed for each of the if-processing statements.
- the conditional processing block can also include an else-processing statement.
- the manipulating step further comprises changing (e.g., inverting) or not changing the value prior to performing the else-processing statement based on whether processing of the if-processing statement changed the PE state of the datapath.
- the manipulating includes changing the value to indicate the enabled state. If the saved PE state of the datapath was an enabled state and the processing of the if-processing statement did not change the PE state, the manipulating includes changing the value to indicate the disabled state. If the saved PE state of the datapath was a disabled state, the processing of the if-processing statement will not change the PE state, and thus the manipulating includes maintaining the value to indicate the disabled state.
- the invention features instructions that combine one or more of the PE state saving and manipulating steps with a branch operation.
- the invention enables the datapath PE state to be accurately tracked (and correctly restored) with minimal hardware overhead, even when the conditional processing block includes many nested conditional operations.
- PE state is tracked for each datapath with a single register, thereby eliminating the need for a stack that is multiple registers deep to maintain the PE state.
- datapath PE state is saved, manipulated, and restored rapidly at the start of, during, and upon exiting, the conditional processing block. Combining one or more of the PE state saving and inverting steps with a branch operation greatly reduces software overhead and increases processing speed.
- FIG. 1 is a block diagram of a single instruction multiple datapath (SIMD) processor.
- FIG. 2 is a flow diagram of a process for maintaining a PE state of a datapath in a SIMD processor during conditional processing.
- SIMD single instruction multiple datapath
- FIG. 3 shows a table of program code utilizing SANE_PE, RESTORE_PE and FLIP_PE instructions.
- a single instruction multiple datapath (SIMD) processor 10 includes an instruction cache 12, control logic 14, a serial datapath 16, and a number of parallel datapaths labeled 18a, 18b, 18c, 18, ... 18n.
- the parallel datapaths 18 write to a memory 20.
- Each of the datapaths 18 has an associated processor enable (PE) bit 22 that represents the PE state of that datapath.
- PE processor enable
- parallel datapath 18a is associated with a PE bit 22a
- parallel datapath 18b is associated with a PE bit 22b, and so forth.
- PE bit 22a For example, if PE bit 22a is enabled, data items may be written by parallel datapath 18a; if PE bit 22b is enabled, data items may be written by parallel datapath 18b. If PE bit 22n is enabled, data items may be written by parallel datapath 18n. When a PE bit is disabled, its associated parallel datapath is disabled and data items may not be written by that parallel datapath.
- control logic 14 fetches an instruction from the instruction cache 12.
- the instruction is fed to the serial datapath 16 that provides the instruction to the datapaths 18.
- serial datapath 16 that provides the instruction to the datapaths 18.
- Each of the datapaths 18 is read together and written together unless the processor enable bit is disabled for a particular datapath.
- conditional processing block within the program code (e.g., a processing block that includes one or more if-then-else processing statements)
- the current PE state of each of the datapaths must be accounted for, so that if any of the PE states of the datapaths are altered during execution of the conditional processing block, the PE states can be restored upon the completion of the conditional processing block.
- a conditional processing block contains multiple conditional processing operations, some of which may be executed during (i.e., nested within) the processing of other conditional processing operations.
- the PE state of each datapath must be saved prior to entering each nested conditional operation, and the saved PE state must be restored upon completing the conditional operation.
- conditional processing operation is an if-then- else-processing operation.
- an interesting phenomenon occurs. Specifically, once the PE state of a datapath is disabled, the PE state of that datapath never again becomes enabled during operations that comprise that if-then-else processing block.
- the present invention tracks the PE state of each datapath by providing and manipulating a PE state indication that exploits this phenomenon.
- a datapath when a datapath enters a conditional processing block, its PE state indication is set to a value that indicates the current PE state of datapath (enabled or disabled, as evidenced by the datapath's PE bit), and that value is stored (e.g., in a parallel register associated with the datapath). The current PE state is thereby saved as an indirect indication thereof.
- the value is updated, as necessary, based on the datapath's PE state during the conditional processing.
- the value is used to restore the datapath's PE state to the PE state that the datapath had prior to entering the if-then-else processing block.
- FIG. 2 illustrates a process 50 of maintaining the state of a datapath in SIMD processor 10 during an exemplary if-then-else conditional processing block.
- the datapath's PE state indication (which is held in one of the datapath's parallel registers R, Fig.
- a threshold value of -1 is used for purposes discussed below. If the datapath's PE state is disabled when the if-processing block is encountered (i.e., at the time that the PE state is saved) (54), the value is incremented (56). Otherwise, the value is not changed (as shown by line 58). During the if-processing, the datapath's PE state may or may not be modified, depending on the results of the if-processing (59). If the conditional processing block includes an else-processing block (60), the process determines whether to invert the datapath's PE state prior to performing the else-processing (62); when else-processing is not included in the conditional processing block, step 62 is skipped (64).
- process 50 inverts the PE state of the datapath from the saved PE state (i.e., the PE state of the datapath prior to executing the if-then-else-processing block) if the PE state of the datapath was enabled prior to executing the if-then-else-processing block. If, however, the PE state was disabled prior to encountering the if-then-else processing block, it will remain disabled, and thus process 50 does not change it.
- the saved PE state i.e., the PE state of the datapath prior to executing the if-then-else-processing block
- process 50 Upon completing the else-processing block (or the if-processing block if the conditional processing block does not include an "else" statement), process 50 restores the saved PE state (i.e., the current PE state of the datapath prior to the datapath encountering the conditional processing block).
- Process 50 enables the PE state if the value of the indication is less than zero (66); otherwise, the datapath's PE state is disabled.
- the value of the indication is decremented if the value is greater than or equal to zero (68), that is, if the value exceeds the -1 threshold.
- the conditional processing block may include other conditional processing statements. For example, it may include additional if-then-else-processing statements or if-processing statements arranged in nested relationship. If so, the various steps of process 50 are performed for the conditional processing statements to which they apply.
- three instructions are provided that are inserted in the assembly code produced by a compiler during compilation of a program to be executed in SIMD processor 10. The three instructions are:
- SANE_PE RESTORE_PE
- FLIP_PE FLIP_PE
- P refers to a parallel register in SIMD processor 10 in which the datapath's PE state indication is stored.
- the compiler inserts the SANE_PE (P) instruction (which implements steps 54-58 of process 50) prior to the start of an if-processing block (e.g., immediately prior to the "if processing statement), and inserts the RESTORE_PE (P) instruction (which performs steps 66 and 68) at the end of the if-processing block.
- the compiler inserts the FLIP_PE (P) instruction (which implements steps 60-64) at the start of the else-processing block (e.g., immediately prior to the "else" processing statement), and inserts the RESTORE_PE (P) instruction at the end of the else-processing block.
- the RESTORE_PE (P) instruction performs two functions. If the value of the PE state indication is greater than -1 (i.e., if the saved PE state of the datapath is the disabled state), the RESTORE_PE (P) instruction assigns the datapath to the disabled PE state; otherwise, the datapath is enabled. The RESTORE_PE(P) instruction also decrements the PE state indication value stored in register P if the value is greater than or equal to zero. Otherwise, the RESTORE_PE (P) instruction does not change the stored value of the PE state indication. In this manner, the value of the indication is not decremented below -1.
- the SAVE_PE (P) instruction is always paired with a RESTORE_PE (P) instruction.
- a datapath that is in the enabled PE state prior to encountering the if-processing block is restored to the enabled PE state at the conclusion of the if- processing block, regardless of whether (or how) the PE state may have been changed during the execution of the if-processing block.
- the SANE_PE (P) instruction causes the state indication value to be incremented from
- the RESTORE_PE (P) instruction causes the value to be decremented back to -1. Because the value was greater than zero, however, the datapath is assigned the disabled PE state upon exiting the if-processing block.
- the FLIP_PE (P) instruction is used for the "else" part of an if-then-else processing block.
- the operation of the FLLP PE (P) instruction is based on the current PE state of the datapath and the saved PE state of the datapath. Simply put, if the execution of the "if statement disabled the datapath (i.e., changed the associated PE bit from 1 to 0), the FLIP_PE (P) instruction will re-enable the datapath (i.e., change PE back to 1).
- a table 100 is presented showing an example utilizing the SANE_PE, RESTORE_PE, and FLIP_PE instructions in a conditional processing block 101 involving two if-processing operations 102 and 104, and one else-processing operation 106.
- if-processing operation 104 is nested within if- processing operation 102 and else-processing operation 106.
- the table includes a stub of program code 108 and the resulting assembly code 110 generated by a SIMD compiler (not shown).
- the table 100 illustrates the assembly code 110 and register manipulation for a SIMD processor 10 having four datapaths DPO, DPI, DP2, and DP3.
- PI and P2 are parallel registers that respectively store data used during execution of the conditional processing block.
- P3 is the register that stores the PE state indication values
- PE is the register (22, Fig. 1) that stores the PE bits of the individual datapaths.
- datapaths DPO, DPI and DP2 are enabled, while datapath DP3 is disabled. This is shown in line 111.
- the compiler inserts a SANE_PE (P3) instruction 112 before the first if-processing block 102, a SANE_PE (P3) instruction 114 before the second (nested) if-processing block 104, a RESTOREJPE (P3) instruction 116 upon exiting the second if-processing block 104, a FLIP_PE (P3) instruction 118 at the start of the else-processing block 106, and a RESTORE_PE (P3) instruction 120 at the end of the else-processing block 106.
- the data values stored in register PI are initially 1, 0, -1, and -1, respectively.
- register P2 is initially unused.
- Line 111 indicates the initial PE states of the datapaths, as described above.
- Line 127 illustrates the operation of SANE_PE (P3) instruction 112. Because DP0-DP2 are currently enabled, the values for those datapaths stored in P3 (line 126) are not incremented from their initial value of -1. But because DP3 is disabled, SANE_PE (P3) instruction 112 causes the value in P3 for DP3 to be incremented to 0.
- Line 128 shows the operation of if-statement 102.
- the PE state of the datapath is enabled if PI is greater than or equal to 0 and the datapath is currently in the enable state.
- PI is greater than or equal to 0 and PE is enabled (line 111), so PE is enabled for both datapaths.
- PI is not greater than or equal to zero, so PE is disabled.
- P2 is set to 1 in DPO and DPI. Because DP2 and DP3 are disabled, the contents of P2 for those datapaths are not changed.
- Line 132 shows the operation of SANE_PE (P3) instruction 114 for if- processing block 104. Because the current PE state of DPO and DPI (shown by line 128) is enabled, instruction 114 does not increment the value in register P3 for those datapaths. However, instruction 114 increments the value in register P3 for DP2 and DP3, because those datapaths are disabled.
- Line 134 shows the operation of if-statement 104. DPO remains enabled, but DPI becomes disabled. DP2 and DP3 remain disabled.
- Line 140 shows the effect of FLIP_PE (P3) instruction 118 on the PE states of the PE bits. Note that else-statement 106 is paired with if-statement 102. Thus, it is the PE states of the datapaths as saved by SAVE_P3 (PE) instruction 112 (shown in line 127) that are relevant. Because the saved PE states of DPO and DPI were enabled, and because DPO an DPI are currently enabled (as shown by line 138), FLIP_PE (P3) instruction 118 disables these datapaths. As a result, PE is changed to 0 for DPO and DPI (line 140).
- PE SAVE_P3
- the PE bit is set according to the contents of register Pa and if equal to zero, a branch is taken to destination X. For example, if all PE bits are set to zero, the datapaths branch around (i.e. skip) the remainder of the conditional processing block, because none of the datapaths are enabled to perform any further work on the conditional processing block.
- the FLIP instruction may be combined with a branch, for example, in the following instruction: if (FLIP_PE (Pb)) go to X This instruction will invert the PE bits in the manner discussed above, and will branch to destination X if none of them are set. In this way, the datapaths are routed around a subsequent "else" processing block if they are all in the disabled PE state.
- Either or both branches may be made a function of whether the program code is deterministic. That is, if either branch is taken, by definition work is skipped and the program runs faster. If the programmer wants the program to always run in the same amount of time, regardless of whether the branch conditions apply (e.g., if the program code must meet real-time deadlines), he or she will set a deterministic bit (DET) in the processor's register set. Neither branch is taken if the DET is set, even if all datapaths' PE states are disabled.
- DET deterministic bit
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE0001348167T DE01988453T1 (en) | 2000-11-28 | 2001-11-09 | DEVELOPING CONDITIONAL PROCESSING IN A PROCESSOR ARCHITECTURE WITH A COMMAND AND SEVERAL DATA WAYS |
EP01988453A EP1348167A2 (en) | 2000-11-28 | 2001-11-09 | Handling conditional processing in a single instruction multiple datapath processor architecture |
AU2002241759A AU2002241759A1 (en) | 2000-11-28 | 2001-11-09 | Handling conditional processing in a single instruction multiple datapath processor architecture |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US72399400A | 2000-11-28 | 2000-11-28 | |
US09/723,994 | 2000-11-28 |
Publications (3)
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WO2002046885A2 true WO2002046885A2 (en) | 2002-06-13 |
WO2002046885A3 WO2002046885A3 (en) | 2002-08-22 |
WO2002046885A9 WO2002046885A9 (en) | 2003-08-07 |
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PCT/US2001/050992 WO2002046885A2 (en) | 2000-11-28 | 2001-11-09 | Handling conditional processing in a single instruction multiple datapath processor architecture |
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EP (1) | EP1348167A2 (en) |
CN (1) | CN1486465A (en) |
AU (1) | AU2002241759A1 (en) |
DE (1) | DE01988453T1 (en) |
TW (1) | TWI236622B (en) |
WO (1) | WO2002046885A2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005086017A1 (en) * | 2004-03-02 | 2005-09-15 | Imagination Technologies Limited | Method and apparatus for management of control flow in a simd device |
US8661225B2 (en) | 2009-06-05 | 2014-02-25 | Arm Limited | Data processing apparatus and method for handling vector instructions |
US9069938B2 (en) | 2006-11-03 | 2015-06-30 | Bluerisc, Inc. | Securing microprocessors against information leakage and physical tampering |
US9569186B2 (en) | 2003-10-29 | 2017-02-14 | Iii Holdings 2, Llc | Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control |
US9697000B2 (en) | 2004-02-04 | 2017-07-04 | Iii Holdings 2, Llc | Energy-focused compiler-assisted branch prediction |
US10101978B2 (en) | 2002-07-09 | 2018-10-16 | Iii Holdings 2, Llc | Statically speculative compilation and execution |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7996671B2 (en) | 2003-11-17 | 2011-08-09 | Bluerisc Inc. | Security of program executables and microprocessors based on compiler-architecture interaction |
CN100383728C (en) * | 2005-08-25 | 2008-04-23 | 应广科技股份有限公司 | Program address arithmetic organ framework capable of implementing waiting and delaying orders |
US8923510B2 (en) * | 2007-12-28 | 2014-12-30 | Intel Corporation | Method and apparatus for efficiently implementing the advanced encryption standard |
CN107491288B (en) * | 2016-06-12 | 2020-05-08 | 合肥君正科技有限公司 | Data processing method and device based on single instruction multiple data stream structure |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4410939A (en) * | 1979-07-17 | 1983-10-18 | Matsushita Electric Industrial Co. Ltd. | System for program interrupt processing with quasi-stack of register-sets |
US4434461A (en) * | 1980-09-15 | 1984-02-28 | Motorola, Inc. | Microprocessor with duplicate registers for processing interrupts |
US4992933A (en) * | 1986-10-27 | 1991-02-12 | International Business Machines Corporation | SIMD array processor with global instruction control and reprogrammable instruction decoders |
US5021993A (en) * | 1987-03-31 | 1991-06-04 | Kabushiki Kaisha Toshiba | Device for saving and restoring register information |
US6282628B1 (en) * | 1999-02-24 | 2001-08-28 | International Business Machines Corporation | Method and system for a result code for a single-instruction multiple-data predicate compare operation |
-
2001
- 2001-11-09 DE DE0001348167T patent/DE01988453T1/en active Pending
- 2001-11-09 EP EP01988453A patent/EP1348167A2/en not_active Withdrawn
- 2001-11-09 AU AU2002241759A patent/AU2002241759A1/en not_active Abandoned
- 2001-11-09 CN CNA01821987XA patent/CN1486465A/en active Pending
- 2001-11-09 TW TW90127897A patent/TWI236622B/en not_active IP Right Cessation
- 2001-11-09 WO PCT/US2001/050992 patent/WO2002046885A2/en not_active Application Discontinuation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4410939A (en) * | 1979-07-17 | 1983-10-18 | Matsushita Electric Industrial Co. Ltd. | System for program interrupt processing with quasi-stack of register-sets |
US4434461A (en) * | 1980-09-15 | 1984-02-28 | Motorola, Inc. | Microprocessor with duplicate registers for processing interrupts |
US4992933A (en) * | 1986-10-27 | 1991-02-12 | International Business Machines Corporation | SIMD array processor with global instruction control and reprogrammable instruction decoders |
US5021993A (en) * | 1987-03-31 | 1991-06-04 | Kabushiki Kaisha Toshiba | Device for saving and restoring register information |
US6282628B1 (en) * | 1999-02-24 | 2001-08-28 | International Business Machines Corporation | Method and system for a result code for a single-instruction multiple-data predicate compare operation |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10101978B2 (en) | 2002-07-09 | 2018-10-16 | Iii Holdings 2, Llc | Statically speculative compilation and execution |
US9569186B2 (en) | 2003-10-29 | 2017-02-14 | Iii Holdings 2, Llc | Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control |
US10248395B2 (en) | 2003-10-29 | 2019-04-02 | Iii Holdings 2, Llc | Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control |
US9697000B2 (en) | 2004-02-04 | 2017-07-04 | Iii Holdings 2, Llc | Energy-focused compiler-assisted branch prediction |
US10268480B2 (en) | 2004-02-04 | 2019-04-23 | Iii Holdings 2, Llc | Energy-focused compiler-assisted branch prediction |
WO2005086017A1 (en) * | 2004-03-02 | 2005-09-15 | Imagination Technologies Limited | Method and apparatus for management of control flow in a simd device |
US7428628B2 (en) | 2004-03-02 | 2008-09-23 | Imagination Technologies Limited | Method and apparatus for management of control flow in a SIMD device |
JP2007526571A (en) * | 2004-03-02 | 2007-09-13 | イマジネイション テクノロジーズ リミテッド | Method and apparatus for control flow management in SIMD devices |
US9069938B2 (en) | 2006-11-03 | 2015-06-30 | Bluerisc, Inc. | Securing microprocessors against information leakage and physical tampering |
US9940445B2 (en) | 2006-11-03 | 2018-04-10 | Bluerisc, Inc. | Securing microprocessors against information leakage and physical tampering |
US10430565B2 (en) | 2006-11-03 | 2019-10-01 | Bluerisc, Inc. | Securing microprocessors against information leakage and physical tampering |
US11163857B2 (en) | 2006-11-03 | 2021-11-02 | Bluerisc, Inc. | Securing microprocessors against information leakage and physical tampering |
US8661225B2 (en) | 2009-06-05 | 2014-02-25 | Arm Limited | Data processing apparatus and method for handling vector instructions |
Also Published As
Publication number | Publication date |
---|---|
CN1486465A (en) | 2004-03-31 |
DE01988453T1 (en) | 2004-04-22 |
WO2002046885A3 (en) | 2002-08-22 |
AU2002241759A1 (en) | 2002-06-18 |
TWI236622B (en) | 2005-07-21 |
EP1348167A2 (en) | 2003-10-01 |
WO2002046885A9 (en) | 2003-08-07 |
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