WO2002039475A2 - Electrically addressable matrix structure - Google Patents

Electrically addressable matrix structure Download PDF

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Publication number
WO2002039475A2
WO2002039475A2 PCT/IL2001/001032 IL0101032W WO0239475A2 WO 2002039475 A2 WO2002039475 A2 WO 2002039475A2 IL 0101032 W IL0101032 W IL 0101032W WO 0239475 A2 WO0239475 A2 WO 0239475A2
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WO
WIPO (PCT)
Prior art keywords
layer
voltage responsive
patterned
conductive material
matrix structure
Prior art date
Application number
PCT/IL2001/001032
Other languages
French (fr)
Other versions
WO2002039475A3 (en
Inventor
Gad Terliuc
Doron Marco
Original Assignee
Citala Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citala Ltd. filed Critical Citala Ltd.
Priority to AU2002223980A priority Critical patent/AU2002223980A1/en
Publication of WO2002039475A2 publication Critical patent/WO2002039475A2/en
Publication of WO2002039475A3 publication Critical patent/WO2002039475A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Definitions

  • the present invention relates to matrix structures and methods for producing such structures generally as well as to matrix structure particularly useful in specific applications, such as displays, memories and processors.
  • the present invention seeks to provide an improved matrix structure and method for constructing same.
  • the matrix structure may be used to construct various devices, such as displays, memories and processors, which are beyond the scope of the present invention.
  • a matrix structure including first and second arrays of conductors mutually arranged to define a matrix having matrix elements at intersections in two but not three dimensions of a conductor of said first array and a conductor of said second array, and voltage responsive conductive material disposed intermediate said first and second arrays of conductors at locations at said intersections and at locations not at said intersections and being operative to be conductive only at locations thereat where there exists at least a predetermined voltage difference thereacross.
  • the voltage responsive conductive material is adapted to have formed in at least partially overlying relationship therewith at said intersection an active material being adapted to be locally activated.
  • the voltage responsive conductive material includes a tunneling barrier.
  • the voltage responsive conductive material comprises a diode.
  • the voltage responsive conductive material comprises a Shottky barrier.
  • the voltage responsive conductor comprises a varistor.
  • the varistor comprises a zinc oxide varistor.
  • the tunneling barrier comprises a copper oxide tunneling barrier.
  • a matrix structure including an electrically insulative substrate core, conductors formed on opposite faces of said insulative substrate, holes formed in a matrix arrangement in said electrically insulative substrate core, and voltage responsive conductive material at said holes.
  • the matrix structure also includes an active material located in said holes.
  • a method of producing a matrix structure including the steps of: mutually arranging first and second arrays of conductors to define a matrix having matrix elements at intersections in two but not three dimensions of a conductor of said first array and a conductor of said second array, and providing voltage responsive conductive material intermediate said first and second arrays of conductors at locations at said intersections and at locations not at said intersections, wherein said voltage responsive conductor is conductive only at locations thereat where there exists, at least a predetermined voltage difference thereacross.
  • the method for producing a matrix structure also includes adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated.
  • the layer of active material is adapted to be locally activated by establishing a voltage difference thereacross.
  • the layer of active material is adapted to be locally activated by providing a current thereacross.
  • the step of mutually arranging and providing includes forming a first patterned conductive layer on a substrate, forming voltage responsive conductive material over at least part of said first patterned conductive layer, forming a second patterned conductive layer on said substrate, at least part of said second patterned conductive layer overlying at least part of said voltage responsive conductive material, said second patterned conductive layer overlying said first patterned layer at intersections therebetween at which said first and second patterned conductive layers are separated by said voltage responsive conductive material.
  • the method for producing a matrix structure also includes adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated.
  • the method also includes the steps of adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated.
  • the layer of active material is adapted to be locally activated by establishing a voltage difference thereacross.
  • the layer of active material is adapted to be locally activated by providing a current thereacross.
  • the steps of mutually arranging and providing include the following forming voltage responsive conductive material over at least part of a first conductive layer, patterning the voltage responsive conductive material and the first conductive layer to have generally the same pattern, forming a second patterned conductive layer on said substrate, at least part of said second patterned conductive layer overlying at least part of said voltage responsive conductive material, said second patterned conductive layer overlying said first patterned layer at intersections therebetween at which said first and second patterned conductive layers are separated by said voltage responsive conductive material.
  • mutually arranging and providing includes forming voltage responsive conductive material over at least part of a first patterned conductive layer, and forming a second patterned conductive layer on said substrate, at least part of said second patterned conductive layer overlying at least part of said voltage responsive conductive material, said second patterned conductive layer overlying said first patterned layer at intersections therebetween at which said first and second patterned conductive layers are separated by said voltage responsive conductive material.
  • the method for producing a matrix structure also includes adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated.
  • the method includes adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated.
  • the layer of active material is adapted to be locally activated ⁇ by establishing a voltage difference thereacross.
  • the layer of active material is adapted to be locally activated by providing a current thereacross. Additionally in accordance with a preferred embodiment of the present invention, the layer of active material is adapted to be locally activated by establishing a voltage difference thereacross.
  • the layer of active material is adapted to be locally activated by providing a current thereacross.
  • the active material is formed over at least part of a first patterned conductive layer and wherein said mutually arranging and providing includes forming voltage responsive conductive material over at least part of said active material, and forming a second patterned conductive layer on said substrate, at least part of said second patterned conductive layer overlying at least part of said voltage responsive conductive material and at least part of said active material, said second patterned conductive layer overlying said first patterned layer at intersections therebetween at which said first and second patterned conductive layers are separated by said voltage responsive conductive material and by said active material.
  • a method of producing a matrix structure which includes providing an electrically insulative substrate core, forming a conductor on opposite faces of said insulative substrate, forming holes in a matrix arrangement in said electrically insulative substrate core, and providing voltage responsive conductive material at said holes. Further in accordance with a preferred embodiment of the present invention, the method also includes the step of providing an active material in said holes.
  • Figs. 1A - IE together illustrate in a simplified manner, five stages in a method of constructing a matrix structure in accordance with a preferred embodiment of the present invention
  • FIG. 2 is a simplified illustration of a realization of the stage shown in Fig. IB;
  • FIG. • 3A and 3B are simplified illustrations of two alternative realizations of the stage shown in Fig. 1C;
  • Figs. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 41 and 4J are simplified illustrations often alternative realizations of the stage shown in Fig. ID;
  • Figs. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 51 and 5J are simplified illustrations of ten alternative realizations of the stage shown in Fig. IE;
  • FIG. 6A - 6E together illustrate in a simplified manner, five stages in a method of constructing a matrix structure in accordance with a preferred embodiment of the present invention
  • FIG. 7 is a simplified illustration of a realization of the stage shown in
  • Fig. 8 is a simplified illustration of the stage shown in Fig. 6C;
  • Figs. 9A, 9B, 9C, 9D and 9E are simplified illustrations of five alternative realizations of the stage shown in Fig. 6D;
  • Figs. 10A, 10B, IOC, 10D and 10E are simplified illustrations of five alternative realizations of the stage shown in Fig. 6E;
  • FIG. 1 1 A - 1 IE together illustrate in a simplified manner, five stages in a method of constructing a matrix structure in accordance with a preferred embodiment of the present invention
  • Figs. 12A, 12B, 12C, 12D and 12E are simplified illustrations of five alternative realizations of the stage shown in Fig. 11C;
  • Figs. 13A, 13B, 13C, 13D, 13E, 13F and 13G are simplified illustrations of seven alternative realizations of the stage shown in Fig. 1 ID;
  • Figs. 14 A, 14B, 14C, 14D, 14E, 14F and 14G are simplified illustrations of seven alternative realizations of the stage shown in Fig. 1 IE;
  • Figs. 15A - 15G together illustrate in a simplified manner, seven stages in a method of constructing a matrix structure in accordance with another preferred embodiment of the present invention
  • Figs. 16A - T6D together illustrate in a simplified manner, four stages in a method of constructing a matrix structure in accordance with yet another preferred embodiment of the present invention.
  • Figs. 17 A, 17B and 17C are simplified illustrations of three alternative realizations of a matrix produced by the method of Figs. 16A - 16D:
  • FIG. 1A - IE illustrate in a simplified manner, five stages in a method of constructing a matrix structure in accordance with a preferred embodiment of the present invention.
  • Fig. 1 illustrates an electrically insulative substrate 10, such as a silicon wafer, PCB substrate, polymeric sheet, glass or any other suitable dielectric material.
  • a patterned conductor 12 is formed over substrate 10 by any suitable technique, such as photolithography, laser printing, screen printing, selective metal growth, sputtering and patterning, or any other suitable technique.
  • an addressing layer 14 is formed over the patterned conductor and in electrical communication therewith, as illustrated in Fig. IC.
  • the addressing layer is operative to enable an electric signal to be provided to a selectable location on the substrate and may operate in any suitable manner.
  • Some examples of the nature of the addressing layer 14 include: a Shottky barrier, a tunneling barrier, a rectifier, a varistor, a diode and a semiconductor pn junction.
  • an active layer 16 may be applied over the addressing layer, as shown in Fig. ID.
  • the active layer 16 is outside the scope of the present invention.
  • a typical active layer 16 is a liquid crystal.
  • patterned conductor 18 is formed over the addressing layer 14. Where an active layer 16 is provided, the patterned conductor 18 is formed over the active layer 16.
  • patterned conductors 12 and 18 are embodied in arrays of elongate conductors arranged in respective orthogonal directions, such that conductors 12 and 18 together define an orthogonal grid. It is appreciated that such an orthogonal grid defines a two dimensional pixel array, wherein each crossing point of any two orthogonal elongate conductors defines a pixel.
  • the addressing layer is a diode or any other suitable rectifying layer
  • the only possible path for the electrical signal is from a particular selected horizontal conductor, through the addressing layer and to a particular selected vertical conductor. In all other paths, the electrical signal must also propagate through the pixels of the addressing layer of the opposite polarity and thus, such paths are blocked.
  • the addressing layer is a suitable tunnel barrier, electrical signals can pass through it in both directions (polarities). However, the voltage drop across the layer must be larger than a threshold value for the layer to conduct. Thus, if the operating voltage is tuned to be slightly above this threshold, only the addressed pixel conducts and all other pixels, which have a voltage lower than the threshold, do not conduct.
  • Fig. 2 shows the patterned conductor 12 embodied as such an array of elongate conductors 20.
  • Figs. 3 A and 3B are simplified illustrations of two alternative realizations of the stage shown in Fig. IC.
  • the addressing layer 14 (Fig. IC) is shown as a series of elongate shells 22, each formed over a discrete elongate conductor 20.
  • the embodiment of Fig. 3 A is typically realized by a chemical process, such as oxidation of the elongate conductor 20, or by applying a continuous layer and subsequently patterning the layer to form shells around the elongated conductors.
  • the addressing layer 14 (Fig. IC) is shown as a continuous layer 24 applied over both substrate 10 and the elongate conductors 20.
  • the embodiment of Fig. 3B may be realized, for example, by application and subsequent hardening of a viscous material, by sputtering, by evaporation or by chemical vapor deposition.
  • Figs. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 41 and 4J are simplified illustrations of ten alternative realizations of the optional stage shown in Fig. ID, it being appreciated that various additional alternative realizations may also be employed.
  • the active layer 16 may be a complicated structure and may involve few processing steps and techniques.
  • An example of such a complex layer 16, is a memory element of an array memory device, which may include capacitor dielectric and suitable gates structure.
  • Figs. 4A - 4E relate to the embodiment of Fig. 3 A
  • Figs. 4F - 4J relate to the embodiment of Fig. 3B.
  • Fig. 4A shows application of the active layer 16 as a viscous material.
  • Fig. 4B shows a process in which dividers 26 are provided in order to separate from each other portions of the active layer 16 of Fig. 4A corresponding to separate conductors.
  • the dividers 26 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators.
  • the dividers may be formed by any suitable technique, such as photolithography.
  • Fig. 4C shows a process in which dividers 28 are provided in order to separate from each other portions of the active layer 16 of Fig. 4A corresponding to separate pixels.
  • the dividers 28 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators.
  • the dividers may be formed by any suitable technique, such as photolithography.
  • Fig. 4D shows a process in which the active layer 16 of Fig. 4A is patterned over the addressing layer shells 22 overlying the elongate conductors 20.
  • Fig. 4E shows a process which is similar to that of Fig. 4D but wherein for example the active layer 16 is patterned over the addressing layer shells 22 in discrete tiles 30, corresponding to individual pixels.
  • Fig. 4F shows application of the active layer 16 as a viscous material.
  • Fig. 4G shows a process in which dividers 36 are provided in order to separate from each other portions of the active layer 16 of Fig. 4F corresponding to separate conductors.
  • the dividers 36 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators.
  • the dividers may be formed by any suitable technique, such as photolithography.
  • Fig. 4H shows a process in which dividers 38 are provided in order to separate from each other portions of the active layer 16 of Fig. 4F corresponding to separate pixels.
  • the dividers 38 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators.
  • the dividers may be formed by any suitable technique, such as photolithography.
  • Fig. 41 shows a process in which the active layer 16 of Fig. 4F is patterned to overlie the elongate conductors 20.
  • Fig. 4J shows a process which is similar to that of Fig. 41 but wherein for example the active layer 16 is patterned over the addressing layer 24 in discrete tiles 40, corresponding to individual pixels.
  • FIGs. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 51 and 5.1 are simplified illustrations of ten alternative realizations of the stage shown in Fig. IE. It may be appreciated that Figs. 5 A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 51 and 5J show the corresponding embodiments of Figs. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 41 and 4J, each with the addition of an additional layer of patterned conductors extending in a direction orthogonal to the direction of conductors 20.
  • Figs. 5 A - 5C each show an array of elongate conductor strips 50 formed over the active layer 16 of the corresponding embodiments of Figs. 4A - 4C and extending orthogonally to conductors 20.
  • Figs. 5D and 5E each show an array of elongate conductors 52 having varying thickness formed over the active layer 16 which overlies conductors 20 and over the substrate 10 in regions where an elongate conductor is not present, in correspondence with the embodiments of Figs. 4D and 4E.
  • Figs. 5F - 5H each show an array of elongate conductor strips 60 formed over the active layer 16 of the corresponding embodiments of Figs. 4F - 4H and extending orthogonally to conductors 20.
  • Figs. 51 and 5J each show an array of elongate conductors 62, having varying thickness, formed over the active layer 16 which overlies conductors 20 and over the substrate 10 in regions where an elongate conductor is not present.
  • FIG. 6A - 6E illustrate in a simplified manner, five stages in a method of constructing a matrix structure in accordance with another preferred embodiment of the present invention.
  • Fig. 6 A illustrates an electrically insulative substrate 110, such as a silicon wafer, PCB substrate, polymeric sheet, glass or any other suitable dielectric material.
  • a conductive layer 112 is formed over substrate 110 by any suitable technique, such as sputtering, evaporation, chemical vapor- deposition and conductive foil lamination.
  • an addressing layer 114 is formed over the conductive layer 112, by any suitable technique, such as that described hereinabove with reference to formation of the conductive layer 112 or by formation of an oxide layer, or by applying the addressing layer as a viscous liquid, and in electrical communication therewith.
  • the addressing layer is operative to enable an electric signal to be provided to a selectable location on the substrate and may operate in any suitable manner.
  • Some examples of the nature of the addressing layer 1 14 include: a Shottky barrier, a tunneling barrier, a rectifier, a varistor , a diode and a semiconductor pn junction.
  • both layers are patterned by any suitable technique, such as, for example, photolithography.
  • an active layer 1 16 may be applied over the addressing layer, as shown in Fig. 6D.
  • the active layer 1 16 is outside the scope of the present invention.
  • a typical active layer 1 16 is a liquid crystal.
  • a further patterned conductor 118 is formed over the addressing layer 1 14. Where an active layer 116 is provided, the patterned conductor 1 1.8 is formed over the active layer 116.
  • patterned conductors 112 and 118 are embodied in arrays of elongate conductors arranged in respective orthogonal directions, such that conductors 112 and 118 together define an orthogonal grid.
  • Fig. 7 shows conductive layer 112 having formed thereover addressing layer 1 14.
  • Fig. 8 is a simplified illustration of the stage shown in Fig. 6C following patterning of both the conductive layer 112 and the addressing layer 1 14. Such patterning may be achieved conveniently by employing a single mask and two different etchants, suitable for the materials of the addressing layer 1 14 and the conductive layer 112, respectively.
  • the addressing layer 1 14 (Fig. 6C) is shown as a series of elongate strips 122, each formed over a discrete elongate conductor 120.
  • Figs. 9A, 9B, 9C, 9D and 9E are simplified illustrations of five alternative realizations of the optional stage shown in Fig. 6D, it being appreciated that various additional alternative realizations may also be employed.
  • Figs. 9A - 9E all relate to the embodiment of Fig. 8.
  • Fig. 9A shows application of the active layer 116 as a viscous material.
  • Fig. 9B shows a process in which dividers 126 are provided in order to separate from each other portions of the active layer 116 of Fig. 9 A corresponding to separate conductors.
  • the dividers 126 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators.
  • the dividers may be formed by any suitable technique, such as photolithography.
  • Fig. 9C shows a process in which dividers 128 are provided in order to separate from each other portions of the active layer 116 of Fig. 9 A corresponding to separate pixels.
  • the dividers 128 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators.
  • the dividers may be formed by any suitable technique, such as photolithography.
  • Fig. 9D shows a process in which the active layer 1 16 of Fig. 9A is patterned in a shell configuration over the addressing layer strips 122 overlying the elongate conductors 120.
  • Fig. 9E shows a process which is similar to that of Fig. 9D but wherein for example the active layer 116 is patterned in a shell configuration over the addressing layer strips 122 in discrete tiles 130, corresponding to individual pixels.
  • Figs. 10A, 10B, IOC, 10D and 10E are simplified illustrations of five alternative realizations of the stage shown in Fig. 6E. It may be appreciated that Figs. 10A, 10B, IOC, 10D and 10E show the corresponding embodiments of Figs. 9A, 9B, 9C, 9D and 9E, each with the addition of an additional layer of patterned conductors extending in a direction orthogonal to the direction of conductors 120. Figs. 10A - IOC each show an array of elongate conductor strips 150 formed over the active layer 116 of the corresponding embodiments of Figs. 9A - 9C and extending orthogonally to conductors 120.
  • Figs. 10D and 10E each show an array of elongate conductors 152 having varying thickness formed over the active layer 116 which overlies conductors 120 and over the substrate 110 in regions where an elongate conductor is not present.
  • FIG. 11 A - 1 IE illustrate in a simplified manner, five stages in a method of constructing a matrix structure in accordance with another preferred embodiment of the present invention.
  • Fig. 11A illustrates an electrically insulative substrate 210, such as a silicon wafer, PCB substrate, polymeric sheet, glass or any other suitable dielectric material.
  • a patterned conductive layer 212 is formed over substrate 210 by any suitable technique, such as photolithography, laser printing, screen printing, selective metal growth, sputtering and patterning, or any other suitable technique.
  • an active layer 214 is optionally formed over the patterned conductive layer 212, by any suitable technique, such as sputtering, evaporation, chemical vapor deposition.
  • the active layer 214 may or may not be patterned.
  • Fig. 11A illustrates an electrically insulative substrate 210, such as a silicon wafer, PCB substrate, polymeric sheet, glass or any other suitable dielectric material.
  • a patterned conductive layer 212 is formed over substrate 210 by any suitable technique, such as photolithography, laser printing, screen printing, selective metal growth, sputtering and patterning, or any other suitable technique.
  • an addressing layer 216 is formed over the optional active layer 214 by any suitable technique, such as the techniques used for forming the conductive layer 212 or by formation of an oxide layer, or by applying it as a viscous liquid, and in electrical communication with the conductive layer.
  • the addressing layer is operative to enable an electric signal to be provided to a selectable location on the substrate and may operate in any suitable manner.
  • Some examples of the nature of the addressing layer 216 include: a Shottky barrier, a tunneling barrier, a rectifier, a varistor, a diode and a semiconductor pn junction.
  • a further patterned conductor 218 is formed over the addressing layer 216.
  • patterned conductors 212 and 218 are embodied in arrays of elongate conductors arranged in respective orthogonal directions, such that conductors 212 and 218 together define an orthogonal grid.
  • Figs. 12A - 12E are simplified illustrations of five alternative realizations of the stage shown in Fig. 1 IC following patterning of the conductive layer 212.
  • the conductive layer 212 (Fig. 1 IC) is shown as a series of elongate strips 220.
  • the optional active layer 214 (Fig. I IC) is shown as a series- of elongate shells 222, each formed over a discrete elongate conductor 220.
  • the optional active layer 214 (Fig. 1 IC) is shown as an array of tiles 224, formed at spaced intervals over discrete elongate conductors 220 and corresponding to individual pixels.
  • dividers 226 are provided in order to separate from each other portions of the optional active layer 214 of Fig. I IC corresponding to separate conductors 220.
  • the dividers 226 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators.
  • the dividers may be formed by any suitable technique, such as photolithography.
  • dividers 228 are provided in order to separate from each other portions of the optional active layer 214 of Fig. I IC corresponding to separate pixels.
  • the dividers 228 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators.
  • the dividers may be formed by any suitable technique, such as photolithography.
  • Fig. 12E shows application of the optional active layer 214 (Fig. I IC) as a viscous material over conductive strips 220.
  • FIG. 13A, 13B, 13C, 13D, 13E, 13F and 13G are simplified illustrations of seven alternative realizations of the stage shown in Fig. 1 I D, it being appreciated that various additional alternative realizations may also be employed.
  • Figs. 13A and 13B relate to the embodiment of Fig. 12A.
  • Figs. 13C and 13D relate to the embodiment of Fig. 12B.
  • Figs. 13E, 13F and 13G relate to the embodiments of Figs. 12C, 12D and 12E respectively.
  • Fig. 13A shows formation of the addressing layer 216 (Fig. 11D) in the form of elongate shells 230, each formed over an optional shell 222 of active layer 214, which is in turn formed over an elongate conductor strip 220.
  • Fig. 13B shows application of the addressing layer 216 (Fig. 11D) as a viscous material over and between optional shells 222 of active layer 214, which are in turn formed over an elongate conductor strip 220.
  • Fig. 13C shows formation of the addressing layer 216 (Fig. 11D) in the form of an array of tiles 234, formed at spaced intervals over discrete optional tiles 224 and corresponding to individual pixels.
  • Fig. 13D shows application of the addressing layer 216 (Fig. 11D) as a viscous material over and between optional tiles 224 of active layer 214, which are in turn formed over an elongate conductor strip 220.
  • Figs. 13E, 13F and 13G show the application of the addressing layer 216 as a viscous material over the structure shown in Figs. 12C, 12D and 12E respectively.
  • FIG. 14A, 14B, 14C “ , 14D, 14E, 14F and 14G are, simplified illustrations of seven alternative realizations of the stage shown in
  • Fig. 1 IE. It may be appreciated that Figs. 14A, 14B, 14C, 14D, 14E, 14F and 14G show the corresponding embodiments of Figs. 13A, 13B, 13C, 13D, 13E, 13F and 13G, each with the addition of an additional layer of patterned conductors extending in a direction orthogonal to the direction of conductors 220. Figs. 14A and 14C each show an array of elongate conductors 250 having varying thickness formed over the addressing layer 216 which overlies conductors 220 and over the substrate 210 in regions where an elongate conductor is not present.
  • Figs. 14B and 14D - 14G each show an array of elongate conductive strips 252 formed over the addressing layer 216 of the corresponding embodiments of
  • FIG. 12B and 12D - 12G and extending orthogonally to conductors 220.
  • FIGs. 15A - 15G illustrate in a simplified manner, six stages in a method of constructing a matrix structure in accordance with another preferred embodiment of the present invention.
  • Fig. 15A illustrates a typical complex substrate such as used in printed circuits which comprises an electrically insulative substrate core 310, such as a suitable dielectric, which is plated or laminated on both opposite surfaces thereof with a conductive plate, such as a copper layer.
  • the .copper layers are designated by reference numerals 312 and 314.
  • a regular patterned grid of holes 316 of any suitable shape is formed in copper layer 312.
  • corresponding holes 318 are etched, preferably by plasma etching, in substrate core 310, extending from each of holes 316 to but not through copper layer 314.
  • the copper layers 312 and 314 are patterned into respective arrays of strips 322 and 324 which extend in mutually orthogonal directions.
  • an addressing layer 330 is formed over each conductive strip 322 in a manner that a hole 332 is defined in addressing layer 330 corresponding to each hole 316 in strips 322.
  • the addressing layer 330 may be also provided over and onto copper layer 314 inside each hole 318 in registration with each hole 316.
  • the addressing layer 330 may conveniently be formed both over strips
  • Fig. 15F illustrates the structure of Fig. ' 15E, with holes 318 filled with an optional active layer 340.
  • Fig. 15G illustrates an optional stage wherein the optional active layer
  • dividers 344 such as those employed in the embodiments of Figs. 14E and 14F inter alia.
  • matrices of Figs. 15F and 15G may be produced alternatively by alternative techniques, such as employing laser drilling of holes 316 and
  • FIG. 16A - 16D illustrate in a simplified manner, four stages in a method of constructing a matrix structure in accordance with yet another preferred embodiment of the present invention.
  • Fig. 16A illustrates an electrically insulative substrate 410, such as a silicon wafer, PCB substrate, polymeric sheet, glass, or any other suitable dielectric material. As seen in Fig. 16B, a patterned conductive layer 412 is formed over substrate
  • a combined active layer and addressing layer 414 is formed over the patterned conductive layer 412, by any suitable technique, such as sputtering, evaporation, chemical vapor deposition, application as a viscous liquid.
  • the combined layer 414 may or may not be patterned.
  • patterned conductor 418 is formed over the combined layer 414.
  • patterned conductors 412 and 418 are embodied in arrays of elongate conductors arranged in respective orthogonal directions, such that conductors 412 and
  • FIGs. 17A, 17B and 17C are simplified illustrations of three alternative realizations of a matrix produced by the method of Figs. 16A - 16D.
  • Fig. 17A shows application of the combined layer 414 (Fig. 16C) as a viscous material over conductive strips 420 defining patterned conductive layer 412
  • dividers 426 are provided in order to separate from each other portions of the combined layer 414 of Fig. 16C corresponding to separate conductors 420.
  • the dividers 426 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators.
  • the dividers may be formed by any suitable technique, such as photolithography.
  • dividers 428 are provided in order to separate from each other portions of the combined layer 414 of Fig. 16C corresponding to separate pixels.
  • the dividers 428 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators.
  • the dividers may be formed by any suitable technique, such as photolithography.

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Abstract

A matrix structure including first and second arrays of conductors (20) mutually arranged to define a matrix having matrix elements at intersections in two but not three dimensions of a conductor of the first array and a conductor of the second array, and voltage responsive conductive material (22) disposed intermediate the first and second arrays of conductors at locations at the intersections and at locations not at the intersections and being operative to be conductive only at locations thereat where there exists at least a predetermined voltage difference thereacross. A method for producing said matrix structure is also disclosed.

Description

ELECTRICALLY ADDRESSABLE MATRIX STRUCTURE FIELD OF THE INVENTION The present invention relates to matrix structures and methods for producing such structures generally as well as to matrix structure particularly useful in specific applications, such as displays, memories and processors.
BACKGROUND OF THE INVENTION Various types of matrix structures useful in displays, memories and processors are known in the patent literature. The following U.S. Patents are believed to represent the state of the art: 4,933,296; 5,133,754; 5,498,573; 5,739,798; 5,783,910;
5,81 1,921 5,973,655; 5,986,737; 5,990,609; 5,990,912; 5,994,828; 5,994,834; 5,999,242 6,008,872; 6,010,927; 6,016,133; 6,020,864; 6,023,258; 6,024,619; 6,028,574 6,028,576
SUMMARY OF THE INVENTION The present invention seeks to provide an improved matrix structure and method for constructing same.
The matrix structure may be used to construct various devices, such as displays, memories and processors, which are beyond the scope of the present invention.
There is thus provided in accordance with a preferred embodiment of the present invention, a matrix structure including first and second arrays of conductors mutually arranged to define a matrix having matrix elements at intersections in two but not three dimensions of a conductor of said first array and a conductor of said second array, and voltage responsive conductive material disposed intermediate said first and second arrays of conductors at locations at said intersections and at locations not at said intersections and being operative to be conductive only at locations thereat where there exists at least a predetermined voltage difference thereacross. Further in accordance with a preferred embodiment of the present invention, the voltage responsive conductive material is adapted to have formed in at least partially overlying relationship therewith at said intersection an active material being adapted to be locally activated.
Still further in accordance with a preferred embodiment of the present invention, the voltage responsive conductive material includes a tunneling barrier.
Additionally in accordance with a preferred embodiment of the present invention, the voltage responsive conductive material comprises a diode.
Furthermore in accordance with a preferred embodiment of the present invention, the voltage responsive conductive material comprises a Shottky barrier.
Moreover in accordance with a preferred embodiment of the present invention, the voltage responsive conductor comprises a varistor. Preferably, the varistor comprises a zinc oxide varistor.
Additionally, the tunneling barrier comprises a copper oxide tunneling barrier.
There is also provided in accordance with a preferred embodiment of the present invention a matrix structure including an electrically insulative substrate core, conductors formed on opposite faces of said insulative substrate, holes formed in a matrix arrangement in said electrically insulative substrate core, and voltage responsive conductive material at said holes.
Further in accordance with a preferred embodiment of the present invention, the matrix structure also includes an active material located in said holes. There is further provided in accordance with another preferred embodiment of the present invention a method of producing a matrix structure including the steps of: mutually arranging first and second arrays of conductors to define a matrix having matrix elements at intersections in two but not three dimensions of a conductor of said first array and a conductor of said second array, and providing voltage responsive conductive material intermediate said first and second arrays of conductors at locations at said intersections and at locations not at said intersections, wherein said voltage responsive conductor is conductive only at locations thereat where there exists, at least a predetermined voltage difference thereacross.
Further in accordance with a preferred embodiment of the present invention, the method for producing a matrix structure also includes adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated. Preferably, the layer of active material is adapted to be locally activated by establishing a voltage difference thereacross.
Still further in accordance with a preferred embodiment of the present invention, the layer of active material is adapted to be locally activated by providing a current thereacross.
Additionally in accordance with a preferred embodiment of the present invention, the step of mutually arranging and providing includes forming a first patterned conductive layer on a substrate, forming voltage responsive conductive material over at least part of said first patterned conductive layer, forming a second patterned conductive layer on said substrate, at least part of said second patterned conductive layer overlying at least part of said voltage responsive conductive material, said second patterned conductive layer overlying said first patterned layer at intersections therebetween at which said first and second patterned conductive layers are separated by said voltage responsive conductive material. Further in accordance with a preferred embodiment of the present invention, the method for producing a matrix structure also includes adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated. Preferably, the method also includes the steps of adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated. Preferably, the layer of active material is adapted to be locally activated by establishing a voltage difference thereacross.
Additionally or alternatively the layer of active material is adapted to be locally activated by providing a current thereacross.
Still further in accordance with a preferred embodiment of the present invention, the steps of mutually arranging and providing include the following forming voltage responsive conductive material over at least part of a first conductive layer, patterning the voltage responsive conductive material and the first conductive layer to have generally the same pattern, forming a second patterned conductive layer on said substrate, at least part of said second patterned conductive layer overlying at least part of said voltage responsive conductive material, said second patterned conductive layer overlying said first patterned layer at intersections therebetween at which said first and second patterned conductive layers are separated by said voltage responsive conductive material.
Additionally in accordance with a preferred embodiment of the present invention, mutually arranging and providing includes forming voltage responsive conductive material over at least part of a first patterned conductive layer, and forming a second patterned conductive layer on said substrate, at least part of said second patterned conductive layer overlying at least part of said voltage responsive conductive material, said second patterned conductive layer overlying said first patterned layer at intersections therebetween at which said first and second patterned conductive layers are separated by said voltage responsive conductive material.
Additionally or alternatively the method for producing a matrix structure also includes adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated.
Further in accordance with a preferred embodiment of the present invention, the method includes adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated. Preferably, the layer of active material is adapted to be locally activated < by establishing a voltage difference thereacross.
Still further in accordance with a preferred embodiment of the present invention, the layer of active material is adapted to be locally activated by providing a current thereacross. Additionally in accordance with a preferred embodiment of the present invention, the layer of active material is adapted to be locally activated by establishing a voltage difference thereacross.
Additionally in accordance with a preferred embodiment of the present invention, .the layer of active material is adapted to be locally activated by providing a current thereacross.
Further in accordance with a preferred embodiment of the present invention, the active material is formed over at least part of a first patterned conductive layer and wherein said mutually arranging and providing includes forming voltage responsive conductive material over at least part of said active material, and forming a second patterned conductive layer on said substrate, at least part of said second patterned conductive layer overlying at least part of said voltage responsive conductive material and at least part of said active material, said second patterned conductive layer overlying said first patterned layer at intersections therebetween at which said first and second patterned conductive layers are separated by said voltage responsive conductive material and by said active material.
There is further provided in accordance with yet another preferred embodiment of the present invention a method of producing a matrix structure which includes providing an electrically insulative substrate core, forming a conductor on opposite faces of said insulative substrate, forming holes in a matrix arrangement in said electrically insulative substrate core, and providing voltage responsive conductive material at said holes. Further in accordance with a preferred embodiment of the present invention, the method also includes the step of providing an active material in said holes.
BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:
Figs. 1A - IE together illustrate in a simplified manner, five stages in a method of constructing a matrix structure in accordance with a preferred embodiment of the present invention;
Fig. 2 is a simplified illustration of a realization of the stage shown in Fig. IB;
Figs. • 3A and 3B are simplified illustrations of two alternative realizations of the stage shown in Fig. 1C; Figs. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 41 and 4J are simplified illustrations often alternative realizations of the stage shown in Fig. ID;
Figs. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 51 and 5J are simplified illustrations of ten alternative realizations of the stage shown in Fig. IE;
Figs. 6A - 6E together illustrate in a simplified manner, five stages in a method of constructing a matrix structure in accordance with a preferred embodiment of the present invention; Fig. 7 is a simplified illustration of a realization of the stage shown in
Fig. 6C;
Fig. 8 is a simplified illustration of the stage shown in Fig. 6C;
Figs. 9A, 9B, 9C, 9D and 9E are simplified illustrations of five alternative realizations of the stage shown in Fig. 6D; Figs. 10A, 10B, IOC, 10D and 10E are simplified illustrations of five alternative realizations of the stage shown in Fig. 6E;
Figs. 1 1 A - 1 IE together illustrate in a simplified manner, five stages in a method of constructing a matrix structure in accordance with a preferred embodiment of the present invention; Figs. 12A, 12B, 12C, 12D and 12E are simplified illustrations of five alternative realizations of the stage shown in Fig. 11C;
Figs. 13A, 13B, 13C, 13D, 13E, 13F and 13G are simplified illustrations of seven alternative realizations of the stage shown in Fig. 1 ID;
Figs. 14 A, 14B, 14C, 14D, 14E, 14F and 14G are simplified illustrations of seven alternative realizations of the stage shown in Fig. 1 IE;
Figs. 15A - 15G together illustrate in a simplified manner, seven stages in a method of constructing a matrix structure in accordance with another preferred embodiment of the present invention;
Figs. 16A - T6D together illustrate in a simplified manner, four stages in a method of constructing a matrix structure in accordance with yet another preferred embodiment of the present invention; and
Figs. 17 A, 17B and 17C are simplified illustrations of three alternative realizations of a matrix produced by the method of Figs. 16A - 16D:
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Reference is now made to Figs. 1A - IE, which together illustrate in a simplified manner, five stages in a method of constructing a matrix structure in accordance with a preferred embodiment of the present invention.
Fig. 1 illustrates an electrically insulative substrate 10, such as a silicon wafer, PCB substrate, polymeric sheet, glass or any other suitable dielectric material. As seen in Fig. IB, a patterned conductor 12 is formed over substrate 10 by any suitable technique, such as photolithography, laser printing, screen printing, selective metal growth, sputtering and patterning, or any other suitable technique. Following formation of the patterned conductor 12 onto the substrate 10, an addressing layer 14 is formed over the patterned conductor and in electrical communication therewith, as illustrated in Fig. IC. The addressing layer is operative to enable an electric signal to be provided to a selectable location on the substrate and may operate in any suitable manner. Some examples of the nature of the addressing layer 14 include: a Shottky barrier, a tunneling barrier, a rectifier, a varistor, a diode and a semiconductor pn junction.
Optionally an active layer 16 may be applied over the addressing layer, as shown in Fig. ID. The active layer 16 is outside the scope of the present invention. A typical active layer 16 is a liquid crystal.
In all cases a further patterned conductor 18 is formed over the addressing layer 14. Where an active layer 16 is provided, the patterned conductor 18 is formed over the active layer 16. In accordance with a preferred embodiment of the present invention, patterned conductors 12 and 18 are embodied in arrays of elongate conductors arranged in respective orthogonal directions, such that conductors 12 and 18 together define an orthogonal grid. It is appreciated that such an orthogonal grid defines a two dimensional pixel array, wherein each crossing point of any two orthogonal elongate conductors defines a pixel.
It is apparent to any skilled man of the art, that such a grid, and in accordance with the layer structure of Fig. IE, enables the selective addressing of any desired pixel in the array, by applying a suitable voltage difference across the two orthogonal elongate conductors which define it,taking inot account the electrical properties of the intermediate addressing layer 14.
For example, if the addressing layer is a diode or any other suitable rectifying layer, the only possible path for the electrical signal is from a particular selected horizontal conductor, through the addressing layer and to a particular selected vertical conductor. In all other paths, the electrical signal must also propagate through the pixels of the addressing layer of the opposite polarity and thus, such paths are blocked.
If the addressing layer is a suitable tunnel barrier, electrical signals can pass through it in both directions (polarities). However, the voltage drop across the layer must be larger than a threshold value for the layer to conduct. Thus, if the operating voltage is tuned to be slightly above this threshold, only the addressed pixel conducts and all other pixels, which have a voltage lower than the threshold, do not conduct.
Fig. 2 shows the patterned conductor 12 embodied as such an array of elongate conductors 20. Reference is now made to Figs. 3 A and 3B, which' are simplified illustrations of two alternative realizations of the stage shown in Fig. IC. In the embodiment of Fig. 3 A, the addressing layer 14 (Fig. IC) is shown as a series of elongate shells 22, each formed over a discrete elongate conductor 20. The embodiment of Fig. 3 A is typically realized by a chemical process, such as oxidation of the elongate conductor 20, or by applying a continuous layer and subsequently patterning the layer to form shells around the elongated conductors.
In the embodiment of Fig. 3B, the addressing layer 14 (Fig. IC) is shown as a continuous layer 24 applied over both substrate 10 and the elongate conductors 20. The embodiment of Fig. 3B may be realized, for example, by application and subsequent hardening of a viscous material, by sputtering, by evaporation or by chemical vapor deposition.
Reference is now made to Figs. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 41 and 4J, which are simplified illustrations of ten alternative realizations of the optional stage shown in Fig. ID, it being appreciated that various additional alternative realizations may also be employed. It is appreciated that the active layer 16 may be a complicated structure and may involve few processing steps and techniques. An example of such a complex layer 16, is a memory element of an array memory device, which may include capacitor dielectric and suitable gates structure. Figs. 4A - 4E relate to the embodiment of Fig. 3 A, while Figs. 4F - 4J relate to the embodiment of Fig. 3B. Fig. 4A shows application of the active layer 16 as a viscous material.
Fig. 4B shows a process in which dividers 26 are provided in order to separate from each other portions of the active layer 16 of Fig. 4A corresponding to separate conductors. The dividers 26 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators. The dividers may be formed by any suitable technique, such as photolithography.
Fig. 4C shows a process in which dividers 28 are provided in order to separate from each other portions of the active layer 16 of Fig. 4A corresponding to separate pixels. The dividers 28 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators. The dividers may be formed by any suitable technique, such as photolithography.
Fig. 4D shows a process in which the active layer 16 of Fig. 4A is patterned over the addressing layer shells 22 overlying the elongate conductors 20. Fig. 4E shows a process which is similar to that of Fig. 4D but wherein for example the active layer 16 is patterned over the addressing layer shells 22 in discrete tiles 30, corresponding to individual pixels.
Fig. 4F shows application of the active layer 16 as a viscous material. Fig. 4G shows a process in which dividers 36 are provided in order to separate from each other portions of the active layer 16 of Fig. 4F corresponding to separate conductors. The dividers 36 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators. The dividers may be formed by any suitable technique, such as photolithography. Fig. 4H shows a process in which dividers 38 are provided in order to separate from each other portions of the active layer 16 of Fig. 4F corresponding to separate pixels. The dividers 38 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators. The dividers may be formed by any suitable technique, such as photolithography. Fig. 41 shows a process in which the active layer 16 of Fig. 4F is patterned to overlie the elongate conductors 20. Fig. 4J shows a process which is similar to that of Fig. 41 but wherein for example the active layer 16 is patterned over the addressing layer 24 in discrete tiles 40, corresponding to individual pixels.
Reference is now made to Figs. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 51 and 5.1, which are simplified illustrations of ten alternative realizations of the stage shown in Fig. IE. It may be appreciated that Figs. 5 A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 51 and 5J show the corresponding embodiments of Figs. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 41 and 4J, each with the addition of an additional layer of patterned conductors extending in a direction orthogonal to the direction of conductors 20.
Figs. 5 A - 5C each show an array of elongate conductor strips 50 formed over the active layer 16 of the corresponding embodiments of Figs. 4A - 4C and extending orthogonally to conductors 20.
Figs. 5D and 5E each show an array of elongate conductors 52 having varying thickness formed over the active layer 16 which overlies conductors 20 and over the substrate 10 in regions where an elongate conductor is not present, in correspondence with the embodiments of Figs. 4D and 4E. Figs. 5F - 5H each show an array of elongate conductor strips 60 formed over the active layer 16 of the corresponding embodiments of Figs. 4F - 4H and extending orthogonally to conductors 20.
Figs. 51 and 5J each show an array of elongate conductors 62, having varying thickness, formed over the active layer 16 which overlies conductors 20 and over the substrate 10 in regions where an elongate conductor is not present.
Reference is now made to Figs. 6A - 6E, which together illustrate in a simplified manner, five stages in a method of constructing a matrix structure in accordance with another preferred embodiment of the present invention.
Fig. 6 A illustrates an electrically insulative substrate 110, such as a silicon wafer, PCB substrate, polymeric sheet, glass or any other suitable dielectric material. As seen in Fig. 6B, a conductive layer 112 is formed over substrate 110 by any suitable technique, such as sputtering, evaporation, chemical vapor- deposition and conductive foil lamination. Following formation of the conductive layer 112 onto the substrate 110, an addressing layer 114 is formed over the conductive layer 112, by any suitable technique, such as that described hereinabove with reference to formation of the conductive layer 112 or by formation of an oxide layer, or by applying the addressing layer as a viscous liquid, and in electrical communication therewith. The addressing layer is operative to enable an electric signal to be provided to a selectable location on the substrate and may operate in any suitable manner. Some examples of the nature of the addressing layer 1 14 include: a Shottky barrier, a tunneling barrier, a rectifier, a varistor , a diode and a semiconductor pn junction.
Following formation of the addressing layer 114 over the conductive layer 112, both layers are patterned by any suitable technique, such as, for example, photolithography.
Optionally an active layer 1 16 may be applied over the addressing layer, as shown in Fig. 6D. The active layer 1 16 is outside the scope of the present invention. A typical active layer 1 16 is a liquid crystal.
In all cases a further patterned conductor 118 is formed over the addressing layer 1 14. Where an active layer 116 is provided, the patterned conductor 1 1.8 is formed over the active layer 116. In accordance with a preferred embodiment of the present invention, patterned conductors 112 and 118 are embodied in arrays of elongate conductors arranged in respective orthogonal directions, such that conductors 112 and 118 together define an orthogonal grid.
Fig. 7 shows conductive layer 112 having formed thereover addressing layer 1 14.
Reference is now made to Fig. 8, which is a simplified illustration of the stage shown in Fig. 6C following patterning of both the conductive layer 112 and the addressing layer 1 14. Such patterning may be achieved conveniently by employing a single mask and two different etchants, suitable for the materials of the addressing layer 1 14 and the conductive layer 112, respectively. In the embodiment of Fig. 8, the addressing layer 1 14 (Fig. 6C) is shown as a series of elongate strips 122, each formed over a discrete elongate conductor 120.
Reference is now made to Figs. 9A, 9B, 9C, 9D and 9E, which are simplified illustrations of five alternative realizations of the optional stage shown in Fig. 6D, it being appreciated that various additional alternative realizations may also be employed. Figs. 9A - 9E all relate to the embodiment of Fig. 8. Fig. 9A shows application of the active layer 116 as a viscous material.
Fig. 9B shows a process in which dividers 126 are provided in order to separate from each other portions of the active layer 116 of Fig. 9 A corresponding to separate conductors. The dividers 126 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators. The dividers may be formed by any suitable technique, such as photolithography.
Fig. 9C shows a process in which dividers 128 are provided in order to separate from each other portions of the active layer 116 of Fig. 9 A corresponding to separate pixels. The dividers 128 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators. The dividers may be formed by any suitable technique, such as photolithography.
Fig. 9D shows a process in which the active layer 1 16 of Fig. 9A is patterned in a shell configuration over the addressing layer strips 122 overlying the elongate conductors 120. Fig. 9E shows a process which is similar to that of Fig. 9D but wherein for example the active layer 116 is patterned in a shell configuration over the addressing layer strips 122 in discrete tiles 130, corresponding to individual pixels.
Reference is now made to Figs. 10A, 10B, IOC, 10D and 10E, which are simplified illustrations of five alternative realizations of the stage shown in Fig. 6E. It may be appreciated that Figs. 10A, 10B, IOC, 10D and 10E show the corresponding embodiments of Figs. 9A, 9B, 9C, 9D and 9E, each with the addition of an additional layer of patterned conductors extending in a direction orthogonal to the direction of conductors 120. Figs. 10A - IOC each show an array of elongate conductor strips 150 formed over the active layer 116 of the corresponding embodiments of Figs. 9A - 9C and extending orthogonally to conductors 120.
Figs. 10D and 10E each show an array of elongate conductors 152 having varying thickness formed over the active layer 116 which overlies conductors 120 and over the substrate 110 in regions where an elongate conductor is not present.
Reference is now made to Figs. 11 A - 1 IE, which together illustrate in a simplified manner, five stages in a method of constructing a matrix structure in accordance with another preferred embodiment of the present invention.
Fig. 11A illustrates an electrically insulative substrate 210, such as a silicon wafer, PCB substrate, polymeric sheet, glass or any other suitable dielectric material. As seen in Fig. 1 IB, a patterned conductive layer 212 is formed over substrate 210 by any suitable technique, such as photolithography, laser printing, screen printing, selective metal growth, sputtering and patterning, or any other suitable technique. As seen in Fig. 1 1C, following formation of the patterned conductive layer 212 onto the substrate 210, an active layer 214 is optionally formed over the patterned conductive layer 212, by any suitable technique, such as sputtering, evaporation, chemical vapor deposition. The active layer 214 may or may not be patterned. As seen in Fig. 1 ID, an addressing layer 216 is formed over the optional active layer 214 by any suitable technique, such as the techniques used for forming the conductive layer 212 or by formation of an oxide layer, or by applying it as a viscous liquid, and in electrical communication with the conductive layer. The addressing layer is operative to enable an electric signal to be provided to a selectable location on the substrate and may operate in any suitable manner. Some examples of the nature of the addressing layer 216 include: a Shottky barrier, a tunneling barrier, a rectifier, a varistor, a diode and a semiconductor pn junction.
In all cases, as seen in Fig. HE, a further patterned conductor 218 is formed over the addressing layer 216. In accordance with a preferred embodiment of the . present invention, patterned conductors 212 and 218 are embodied in arrays of elongate conductors arranged in respective orthogonal directions, such that conductors 212 and 218 together define an orthogonal grid.
Reference is now made to Figs. 12A - 12E, which are simplified illustrations of five alternative realizations of the stage shown in Fig. 1 IC following patterning of the conductive layer 212. In the embodiments of Fig. 12A - 12E, the conductive layer 212 (Fig. 1 IC) is shown as a series of elongate strips 220.
In the embodiment of Fig. 12 A, the optional active layer 214 (Fig. I IC) is shown as a series- of elongate shells 222, each formed over a discrete elongate conductor 220.
In the embodiment of Fig. 12B, the optional active layer 214 (Fig. 1 IC) is shown as an array of tiles 224, formed at spaced intervals over discrete elongate conductors 220 and corresponding to individual pixels.
In the embodiment of Fig. 12C, dividers 226 are provided in order to separate from each other portions of the optional active layer 214 of Fig. I IC corresponding to separate conductors 220. The dividers 226 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators. The dividers may be formed by any suitable technique, such as photolithography.
In the embodiment of Fig. 12D, dividers 228 are provided in order to separate from each other portions of the optional active layer 214 of Fig. I IC corresponding to separate pixels. The dividers 228 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators. The dividers may be formed by any suitable technique, such as photolithography.
Fig. 12E shows application of the optional active layer 214 (Fig. I IC) as a viscous material over conductive strips 220.
Reference is now made to Figs. 13A, 13B, 13C, 13D, 13E, 13F and 13G, which are simplified illustrations of seven alternative realizations of the stage shown in Fig. 1 I D, it being appreciated that various additional alternative realizations may also be employed. Figs. 13A and 13B relate to the embodiment of Fig. 12A. Figs. 13C and 13D relate to the embodiment of Fig. 12B. Figs. 13E, 13F and 13G relate to the embodiments of Figs. 12C, 12D and 12E respectively. Fig. 13A shows formation of the addressing layer 216 (Fig. 11D) in the form of elongate shells 230, each formed over an optional shell 222 of active layer 214, which is in turn formed over an elongate conductor strip 220.
Fig. 13B shows application of the addressing layer 216 (Fig. 11D) as a viscous material over and between optional shells 222 of active layer 214, which are in turn formed over an elongate conductor strip 220.
Fig. 13C shows formation of the addressing layer 216 (Fig. 11D) in the form of an array of tiles 234, formed at spaced intervals over discrete optional tiles 224 and corresponding to individual pixels.
Fig. 13D shows application of the addressing layer 216 (Fig. 11D) as a viscous material over and between optional tiles 224 of active layer 214, which are in turn formed over an elongate conductor strip 220.
Figs. 13E, 13F and 13G show the application of the addressing layer 216 as a viscous material over the structure shown in Figs. 12C, 12D and 12E respectively.
Reference is now made to Figs. 14A, 14B, 14C", 14D, 14E, 14F and 14G, which are, simplified illustrations of seven alternative realizations of the stage shown in
Fig. 1 IE. It may be appreciated that Figs. 14A, 14B, 14C, 14D, 14E, 14F and 14G show the corresponding embodiments of Figs. 13A, 13B, 13C, 13D, 13E, 13F and 13G, each with the addition of an additional layer of patterned conductors extending in a direction orthogonal to the direction of conductors 220. Figs. 14A and 14C each show an array of elongate conductors 250 having varying thickness formed over the addressing layer 216 which overlies conductors 220 and over the substrate 210 in regions where an elongate conductor is not present.
Figs. 14B and 14D - 14G each show an array of elongate conductive strips 252 formed over the addressing layer 216 of the corresponding embodiments of
Figs. 12B and 12D - 12G and extending orthogonally to conductors 220. Reference is now made to Figs. 15A - 15G, which together illustrate in a simplified manner, six stages in a method of constructing a matrix structure in accordance with another preferred embodiment of the present invention.
Fig. 15A illustrates a typical complex substrate such as used in printed circuits which comprises an electrically insulative substrate core 310, such as a suitable dielectric, which is plated or laminated on both opposite surfaces thereof with a conductive plate, such as a copper layer. In the illustrated embodiment, the .copper layers are designated by reference numerals 312 and 314.
As seen in Fig. 15B, a regular patterned grid of holes 316 of any suitable shape is formed in copper layer 312. Thereafter, as shown in Fig. 15C, corresponding holes 318 are etched, preferably by plasma etching, in substrate core 310, extending from each of holes 316 to but not through copper layer 314.
Thereafter, as seen in Fig. 15D, the copper layers 312 and 314 are patterned into respective arrays of strips 322 and 324 which extend in mutually orthogonal directions. As shown in Fig. 15E, an addressing layer 330 is formed over each conductive strip 322 in a manner that a hole 332 is defined in addressing layer 330 corresponding to each hole 316 in strips 322. Optionally the addressing layer 330 may be also provided over and onto copper layer 314 inside each hole 318 in registration with each hole 316. The addressing layer 330 may conveniently be formed both over strips
322 and in holes 318 simultaneously by carrying out a suitable wet or dry oxidation process or by any other suitable technique.
Fig. 15F illustrates the structure of Fig. ' 15E, with holes 318 filled with an optional active layer 340. Fig. 15G illustrates an optional stage wherein the optional active layer
340 not only fills holes 318 but also is applied over the entire structure and is divided into tiles 342 by dividers 344, such as those employed in the embodiments of Figs. 14E and 14F inter alia.
It is noted that the matrices of Figs. 15F and 15G may be produced alternatively by alternative techniques, such as employing laser drilling of holes 316 and
318 before or after patterning of conductive strips 322 and 324. Reference is now made to Figs. 16A - 16D, which together illustrate in a simplified manner, four stages in a method of constructing a matrix structure in accordance with yet another preferred embodiment of the present invention.
Fig. 16A illustrates an electrically insulative substrate 410, such as a silicon wafer, PCB substrate, polymeric sheet, glass, or any other suitable dielectric material. As seen in Fig. 16B, a patterned conductive layer 412 is formed over substrate
410 by any suitable technique, such as photolithography, laser printing, screen printing, selective metal growth, sputtering and patterning, or any other suitable technique. As seen in Fig. 16C, following formation of the patterned conductive layer 412 onto the substrate 410, a combined active layer and addressing layer 414 is formed over the patterned conductive layer 412, by any suitable technique, such as sputtering, evaporation, chemical vapor deposition, application as a viscous liquid. The combined layer 414 may or may not be patterned.
As seen in Fig. 16D, a further patterned conductor 418 is formed over the combined layer 414. In accordance with a preferred embodiment of the present invention, patterned conductors 412 and 418 are embodied in arrays of elongate conductors arranged in respective orthogonal directions, such that conductors 412 and
418 together define an orthogonal grid.
Reference is now made to Figs. 17A, 17B and 17C, which are simplified illustrations of three alternative realizations of a matrix produced by the method of Figs. 16A - 16D. Fig. 17A shows application of the combined layer 414 (Fig. 16C) as a viscous material over conductive strips 420 defining patterned conductive layer 412
(Fig. 16B).
In the embodiment of Fig. 17B, dividers 426 are provided in order to separate from each other portions of the combined layer 414 of Fig. 16C corresponding to separate conductors 420. The dividers 426 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators. The dividers may be formed by any suitable technique, such as photolithography. In the embodiment of Fig. 17C, dividers 428 are provided in order to separate from each other portions of the combined layer 414 of Fig. 16C corresponding to separate pixels. The dividers 428 may be made of various types of materials, such as, for example, electrical insulators and thermal insulators. The dividers may be formed by any suitable technique, such as photolithography.
It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove as well as variations and modifications which would occur to persons skilled in the art upon reading the specification and which are not in the prior art.

Claims

C L A I M S
1. A matrix structure comprising: first and second arrays of conductors mutually arranged to define a matrix having matrix elements at intersections in two but not three dimensions of a conductor of said first array and a conductor of said second array; and voltage responsive conductive material disposed intermediate said first and second arrays of conductors at locations at said intersections and at locations not at said intersections and being operative to be conductive only at locations thereat where there exists at least a predetermined voltage difference thereacross.
2. A matrix structure according to claim 1 and wherein said voltage responsive conductive material is adapted to have formed in at least partially overlying relationship therewith at said intersection an active material being adapted to be locally activated.
3. A matrix structure according to claim 1 and wherein said voltage responsive conductive material comprises a tunneling barrier.
4. A matrix structure according to claim 1 and wherein said voltage responsive conductive material comprises a diode.
5. A matrix structure according to claim 1 and wherein said voltage responsive conductive material comprises a Shottky barrier.
6. A matrix structure according to claim 1 and wherein said voltage responsive conductor comprises a varistor.
7. A matrix structure according to claim 6 and wherein said varistor comprises a zinc oxide varistor.
8. A matrix structure according to claim 3 and wherein said tunneling barrier comprises a copper oxide tunneling barrier.
9. A matrix structure comprising: an electrically insulative substrate core; conductors formed on opposite faces of said insulative substrate; holes formed in a matrix arrangement in said electrically insulative substrate core; and voltage responsive conductive material at said holes.
10. A matrix structure according to claim 9 and also comprising an active material located in said holes.
1 1. A method of producing a matrix structure comprising: mutually arranging first and second arrays of conductors to define a matrix having matrix elements at intersections in two but not three dimensions of a conductor of said first array and a conductor of said second array; and providing voltage responsive conductive material intermediate said first and second arrays of conductors at locations at said intersections and at locations not at said intersections, wherein said voltage responsive conductor is conductive only at locations thereat where there exists at least a predetermined voltage difference thereacross.
12. A method for producing a matrix structure according to claim 11 and also comprising: adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated.
13. A method according to claim 12 and wherein said layer of active material is adapted to be locally activated by establishing a voltage difference thereacross.
14. A method according to claim 12 and wherein said layer of active material is adapted to be locally activated by providing a current thereacross.
15. A method according to claim 11 and wherein said mutually arranging and providing include: forming a first patterned conductive layer on a substrate; forming voltage responsive conductive material over at least part of said first patterned conductive layer; forming a second patterned conductive layer on said substrate, at least part of said second patterned conductive layer overlying at least part of said voltage responsive conductive material, said second patterned conductive layer overlying said first patterned layer at intersections therebetween at which said first and second patterned conductive layers are separated by said voltage responsive conductive material.
16. A method for producing a matrix structure according to claim 15 and also comprising: adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated.
17. A method for producing a matrix structure according to claim 16 and also comprising: adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated.
18. A method according to claim 17 and wherein said layer of active material is adapted to be locally activated by establishing a voltage difference thereacross.
19. A method according to claim 17 and wherein said layer of active material is adapted to be locally activated by providing a current thereacross.
20. A method according to claim 11 and wherein said mutually arranging and providing include: forming voltage responsive conductive material over at least part of a first conductive layer; patterning the voltage responsive conductive material and the first conductive layer to have generally the same pattern; forming a second patterned conductive layer on said substrate, at least part of said second patterned conductive layer overlying at least part of said voltage responsive conductive material, said second patterned conductive layer overlying said first patterned layer at intersections therebetween at which said first and second patterned conductive layers are separated by said voltage responsive conductive material.
21. A method according to claim 11 and wherein said mutually arranging and providing include: forming voltage responsive conductive material over at least part of a first patterned conductive layer; and forming a second patterned conductive layer on said substrate, at least part of said second patterned conductive layer overlying at least part of said voltage responsive conductive material, said second patterned conductive layer overlying said first patterned layer at intersections therebetween at which said first and second patterned conductive layers are separated by said voltage responsive conductive material.
22. A method for producing a matrix structure according to claim 20 and also comprising: adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated.
23. A method for producing a matrix structure according to claim 21 and also comprising: adapting said voltage responsive conductive material to have formed in at least partially overlying relationship therewith at said intersections a layer of active material which is adapted to be locally activated.
24. A method according to claim 22 and wherein said layer of active material is adapted to be locally activated by establishing a voltage difference thereacross.
25. A method according to claim 22 and wherein said layer of active material is adapted to be locally activated by providing a current thereacross.
26. A method according to claim 23 and wherein said layer of active material is adapted to be locally activated by establishing a voltage difference thereacross.
27. A method according to claim 23 and wherein said layer of active material is adapted to be locally activated by providing a current thereacross.
28. A method according to claim 12 wherein active material is formed over at least part of a first patterned conductive layer and wherein said mutually arranging and providing include: forming voltage responsive conductive material over at least part of said active material; and forming a second patterned conductive layer on said substrate, at least part of said second patterned conductive layer overlying at least part of said voltage responsive conductive material and at least part of said active material, said second patterned conductive layer overlying said first patterned layer at intersections therebetween at which said first and second patterned conductive layers are separated by said voltage responsive conductive material and by said active material.
29. A method of producing a matrix structure comprising: providing an electrically insulative substrate core; forming a conductor on opposite faces of said insulative substrate; forming holes in a matrix arrangement ' in said electrically insulative substrate core; and providing voltage responsive conductive material at said holes.
30. A method of producing a matrix structure according to claim 30 and also comprising providing an active material in said holes.
PCT/IL2001/001032 2000-11-07 2001-11-06 Electrically addressable matrix structure WO2002039475A2 (en)

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