WO2002027938A3 - High resolution, low jitter frequency synthesizer - Google Patents

High resolution, low jitter frequency synthesizer Download PDF

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Publication number
WO2002027938A3
WO2002027938A3 PCT/US2001/024648 US0124648W WO0227938A3 WO 2002027938 A3 WO2002027938 A3 WO 2002027938A3 US 0124648 W US0124648 W US 0124648W WO 0227938 A3 WO0227938 A3 WO 0227938A3
Authority
WO
WIPO (PCT)
Prior art keywords
current source
frequency synthesizer
output signal
pull
frequency
Prior art date
Application number
PCT/US2001/024648
Other languages
French (fr)
Other versions
WO2002027938A2 (en
Inventor
Sasan Cyrusian
Original Assignee
Infineon Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp filed Critical Infineon Technologies Corp
Publication of WO2002027938A2 publication Critical patent/WO2002027938A2/en
Publication of WO2002027938A3 publication Critical patent/WO2002027938A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Systems and methods for synthesizing frequencies with high solution and low jitter are described. In one aspect, a frequency synthesizer (10)for producing a series of output signal pulses spaced-apart by a characteristic period is described. The frequency synthesizer includes a phase-locked looped (11)having a multiphase counter (20) configured to produce a feedback signal pulse shifted in time by a programmable fraction of the output signal period relative to a period corresponding to a programmable number of output signal pulses. In another aspect, a hase shifter is configured to provide an over sampling clock signal with a frequency greater than the frequency of the output signal. In another aspect, the frequency synthesizer includes a phase-locked loop with a charge pump (14)having a pull up current source, a pull down current source, and an equalization circuit programmable to substantially offset mismatch between the pull up current source and the pull down current source.
PCT/US2001/024648 2000-09-28 2001-08-06 High resolution, low jitter frequency synthesizer WO2002027938A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67627700A 2000-09-28 2000-09-28
US09/676,277 2000-09-28

Publications (2)

Publication Number Publication Date
WO2002027938A2 WO2002027938A2 (en) 2002-04-04
WO2002027938A3 true WO2002027938A3 (en) 2002-10-17

Family

ID=24713885

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/024648 WO2002027938A2 (en) 2000-09-28 2001-08-06 High resolution, low jitter frequency synthesizer

Country Status (1)

Country Link
WO (1) WO2002027938A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60209329D1 (en) * 2002-11-21 2006-04-27 St Microelectronics Belgium Nv Accurate self-calibration of a multi-phase clock generating phase locked loop

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5059924A (en) * 1988-11-07 1991-10-22 Level One Communications, Inc. Clock adapter using a phase locked loop configured as a frequency multiplier with a non-integer feedback divider
US5889436A (en) * 1996-11-01 1999-03-30 National Semiconductor Corporation Phase locked loop fractional pulse swallowing frequency synthesizer
US6111468A (en) * 1998-02-06 2000-08-29 Fujitsu Limited Charge pump with charge/discharge amount control
US6114914A (en) * 1999-05-19 2000-09-05 Cypress Semiconductor Corp. Fractional synthesis scheme for generating periodic signals

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5059924A (en) * 1988-11-07 1991-10-22 Level One Communications, Inc. Clock adapter using a phase locked loop configured as a frequency multiplier with a non-integer feedback divider
US5889436A (en) * 1996-11-01 1999-03-30 National Semiconductor Corporation Phase locked loop fractional pulse swallowing frequency synthesizer
US6111468A (en) * 1998-02-06 2000-08-29 Fujitsu Limited Charge pump with charge/discharge amount control
US6114914A (en) * 1999-05-19 2000-09-05 Cypress Semiconductor Corp. Fractional synthesis scheme for generating periodic signals

Also Published As

Publication number Publication date
WO2002027938A2 (en) 2002-04-04

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