WO2002023630A2

WO2002023630A2 - Micromachined silicon block vias for transferring electrical signals to the backside of a silicon wafer

Info

Publication number: WO2002023630A2
Application number: PCT/US2001/026447
Authority: WO
Inventors: Harald S. Gross
Original assignee: Applied Materials, Inc.
Priority date: 2000-09-13
Filing date: 2001-08-23
Publication date: 2002-03-21
Also published as: AU2001286711A1; WO2002023630A3

Abstract

Electrical interconnects are implemented in a fully three dimensional manner at the wafer level for a column or module of integrated chips before the dicing of a wafer stack into chip stacks. In one aspect the present invention includes a method for making electrical interconnects by using portions of silicon chips themselves as electrical feedthroughs ('block vias'). The block vias are configured so as to lead to one layer of the column that is electrically connected to the environment. In another aspect the present invention includes a method for making electical interconnects by using cutouts from the chips. In contrast to the prior art, both the block via and and cutout techniques premit the transfer of multiple electrical signals from one side of a wafer to the other through the wafer itself.

Description

TITLE: MICROMACHINED SILICON BLOCK VIAS FOR

TRANSFERRING ELECTRICAL SIGNALS TO THE BACKSIDE OF A SILICON WAFER

Field Of The Invention The present invention relates to making electrical interconnects in columns or modules of integrated chips.

Background Of The Invention

There is a continuing interest in the field of IC (integrated circuit) fabrication in finding ways to increase the density of electronic parts like transistors and to shrink the electrical interconnections for these parts. Since the invention of microcolumns of silicon chips, only single columns have been assembled from a stack of micromachined silicon chips. In order to permit each chip to be accessed electrically, a pyramidal structure is used for the stack. The use of such a structure allows for wire bonding from each chip in the pyramid to a base plate. In the future arrays of microcolumns will be needed. In order to make such arrays feasible, the columns will have to assembled at the wafer stage and only subsequently diced into the required array sizes. Because the dicing will need to occur after assembly, the pyramidal structure will not be viable any more and new contacting methods will have to be found. U.S. Patent No. 5,656,553 illustrates a prior art approach to the problem of making microcolumns of chips. As in other prior art, the assembly and subsequent contacting of the IC's in the stack is done after dicing the chips or chip arrays out of the silicon wafers. Furthermore, the interconnections can be said to be "three dimensional" only in the rather limited sense that "side surface metallization" is applied to the peripheral edges of planar arrays of integrated chips subsequent to the dicing of the wafer stack. In contrast to this prior art, according to the present invention, the assembly and contacting of the chips in the stack is done at the wafer level prior to dicing. In the case where block vias are employed, the djcing is the last process step. In the case of the cutouts, no additional process steps after dicing are needed in order to form the contact pads on each layer of the chip stack, because again all pads are formed at the wafer level before dicing.

Thus, according the present invention, the interconnects are implemented in a fully three dimensional manner at the wafer level. The technique of the present invention permits the manufacturing of a stack of IC's and/or MEMS (microelectromechanical systems) that are electrically interconnected at the wafer level before dicing into chips. Such MEMS are typically made using the same fabrication techniques as are used in the semiconductor industry generally. (As used herein, the term "chip" is meant to be broad enough to include such MEMS.) Therefore, a much higher density of IC's and/or MEMS is possible compared to the conventional packaging of IC's and/or MEMS. In addition, the interconnects are more robust than with conventional wire bonding.

Summary of the Invention

In one aspect the present invention includes a method for making electrical interconnects by using portions of the silicon chips themselves as electrical feedthroughs ("block vias"). The block vias are configured so as to lead to one layer of the column that is electrically connected to the environment. Using block vias it is possible, for example, to assemble one hundred or more columns at the same time from a 4" wafer. In another aspect the present invention includes a method for making electrical interconnects by using "cutouts" from the chips. To make the cutouts, the same fabrication processes involved in forming block vias are used. The cutout technique allows the contacting of all the layers in the stack. In contrast to the prior art, both the block via and cutout techniques permit the transfer of multiple electrical signals from one side of a wafer to the other through the wafer itself. By using these block via and cutout techniques, the electrical interconnections are implemented in a novel manner at the wafer level prior to dicing.

Brief Description of the Figures

Figure 1 a is a side cut-away view of a stack of three chips showing the use of block vias according to the present invention.

Figure 1 b is a side view of a stack of three chips showing the use of cutouts according to the present invention. Figures 2a, 2b, 2c, and 2d show a series of cross-sectional and top views of a wafer at different points during a fabrication process according to the present invention.

Figure 3 shows an exploded view of a chip stack and illustrates the formation of electrical interconnects according to the present invention.

Figure 4 shows a perspective view of a portion of one wafer (with a block via) of a wafer stack (after the stack has been diced) and a top view of a portion of the wafer (with block via) prior to dicing.

Detailed Description Of The invention.

Figure 1a illustrates the use of the block vias in a stack of three chips. As used herein, a "block via" is a region of a wafer layer or chip layer that has been isolated from the rest of the layer so as to serve as an electrical feedthrough through the layer. Between block via A and the rest of chip I, a trench is etched through the wafer. The same is done with respect to block via B and chip II as well as block via C and chip III. To avoid electrical shorting of the chips, an insulating material such as silicon oxide may be deposited on the backside of chips I and II except for the via regions A and B. Region A could be an octupol electrode of the microcolumn and is therefore electrically connected to C by way of block via B. B could be as small as a contact pad on an IC. Block vias can be used in the fabrication of a variety of microcolumns, such as a microcolumn of a miniaturized scanning electron microscope, for example, for leading all the electrical signals of the microcolumn to a cpmmon carrier such as an I C header.

Figure 1b shows a stack of three chips I'.ll', and III' with two cutouts D and E. As used herein, a "cutout" is a recess passing through one or more layers in a stack of chip layers or wafer layers so as to provide a contact pad for an electrical interconnect to be made at the bottom of the recess. In the case of the cutouts, the electrical connections to the chips can be made by wire bonding to the contact pads provided by the cutouts. Figure 1b shows a wire bond connection 10 to a pad created by cutout D and another wire bond connection 20 to a second pad created by cutout E.

For cutouts the same fabrication processes are used as with the block vias. However, with the cutouts the patterns of all the blocks may preferably be the same because it is necessary that all the blocks drop out of the wafers during the etching of the trenches. Then each chip in the stack can readily be electrically contacted using the cutouts, for example, by wire bonding from the top. The cut outs may also be used in a variety of microcolumns, for example microcolumns comprising glass chips (which are portions of wafers in which a thin silicon layer is bonded to a glass layer made of pyrex glass or other glass, and circuit features are formed on the silicon layer) and microcolumns comprising chips which are portions of "silicon on insulator" (SOI) wafers. Glass chips are sometimes used in applications in which very high voltages are applied to circuit elements, and ultrasonic drilling instead of etching can be employed to manufacture microcolumns comprising glass chips. Figures 2a, 2b, 2c, and 2d show an example of a fabrication methodology for making block vias in a wafer 40. The block via 30 can be fabricated from the backside of the wafer either after or before the manufacturing of an IC or MEMS is completed on the front side. The cross-sectional view of Fig. 2a shows the wafer at a stage where a photoresist mask 47 has been placed on the wafer for Deep Reactive Ion Etching (DRIE) through the wafer. The mask shape in this case is in the form of a "U" as is shown in the top view (on the right side) of Fig. 2a. Other etching or drilling techniques such as laser drilling, or even cutting with a saw, are employed in alternative embodiments to form the trench for defining the block via. Where etching is employed, a photoresist layer 48 on the bottom can serve as an etch stop or other materials can also be employed for this purpose. The width T of the etched trench 35 depends on the breakdown voltage of the application. At the current time minimum gaps of 15 micrometers can be etched successfully through a wafer. If necessary the gap can be extended to a width of a few hundreds of micrometers if high voltages are to be used. In this case a recess also has to be fabricated on parts of the chip near the block via. After the stripping of the photo resist (the two views comprising

Fig. 2b), an insulating material 68 is grown onto the wafer as shown in the cross-sectional view of Fig. 2c by an appropriate deposition technique such as the evaporation of silicon oxide through a shadow mask. (The portion of Fig. 2c on the right is a top view of the wafer corresponding to the cross-sectional view on the left side of Fig. 2c). In some cases a thermal oxide that grows not only on the surface but also on the side wall of the block vias may used in order to meet particular requirements. Finally, as shown by the two views comprising Fig. 2d, a conductive material 78 like gold is grown onto the block vias and parts of the insulating layer 68. Afterwards a stack of wafers (including one or more wafers with the block vias formed as described above) is assembled and connected such as by eutectic bonding. Other bonding techniques like soldering or gluing could also be applied.

Finally, the whole wafer stack is diced into chips. The right portion of Fig. 4 is a top view of a portion of a wafer (in which block via 30 of Fig. 2d has been formed) of a wafer stack prior to dicing, showing a dicing line (DL) along which the wafer is to be diced. The left portion of Figure 4 is a perspective view of a portion of the wafer (with block via 3.0) after the wafer stack has been diced along line DL. During dicing the electrical connection between the block via and the chip is removed so that the outline of the "U" shaped trench becomes a closed curve. Accordingly, the block vias have to differ in size from one chip to another in the stack in order to carry each other.

If the etched shape (trench) is a square (closed curve) instead of a "U", a "cutout" is formed at the edge of each chip before dicing. The square shaped blocks then fall out of the wafer during processing. The cutout technique aflows the contacting of a chip in the wafer without the need for a cutout further down in the stack, for example by wire bonding from the top.

Fig. 3 shows an exploded view of a chip stack formed in accordance with the invention with different block via sizes. After assembly and dicing of a wafer stack which includes the structures shown in Fig. 3, part 3 of layer 90 (which layer may be a MEMS) is ultimately connected electrically to pad 125 of the IC carrier 120. Part 3 could be a freestanding electrode that is etched out of the wafer. Part 3 is also electrically connected to an electrical contact on the top of IC 1 in chip layer 110 using block vias 105 and 115 and with a press on contact f. The ground of IC 1 is connected to a contact on the IC carrier 120. A contact pad on top of IC 2 (on chip layer 100) is connected to block via 108 with a press on contact e and the block vias 108 and 118 are connected with the IC carrier 120 using contact 123. The ground of IC 2 is connected with a contact on the IC carrier. Part 4 of the MEMS is connected using contact d to another pad of IC 2. The scope of the present invention is meant to be that set forth in the claims that follow and equivalents thereof, and is not limited to any of the specific embodiments described above.

Claims

What is claimed is:

1. A method for forming a chip stack comprising the steps of:

(a) providing a plurality of wafers wherein each of at least two of the wafers defines at least one chip and further wherein at least a subset of said wafers include electrical feedthroughs for electrical interconnects in the chip stack;

(b) forming a wafer stack by aligning and stacking said wafers; and (c) after steps (a) and (b), dicing said wafer stack to form the chip stack.

2. A method as recited in claim 1 wherein said electrical feedthroughs are block vias.

3. A method as recited in claim 2, further comprising the step of forming said block vias using deep reactive ion etching.

4. A method as recited in claim 2, further comprising the step of forming said block vias using laser drilling.

5. A method as recited in claim 1, further comprising the step of forming said. electric feedthroughs using deep reactive ion etching.

6. A method as recited in claim 1 , further comprising the step of forming said electric feedthroughs using laser drilling.

7. A method for forming a chip stack comprising the steps of:

(a) providing a plurality of wafers wherein each of at least two of the wafers defines at least one chip, and the wafers define recesses, with each wafer of at least a subset of said wafers defining at least one recess passing therethrough;

(b) forming a wafer stack by aligning and stacking said wafers so that said recesses form cutouts that provide contact pads for electrical interconnects in the chip stack; and

(c) after steps (a) and (b), dicing said wafer stack to form the chip stack.

8. A method as recited in claim 7, further comprising the step of making electrical interconnects to layers in the chip stack by wire bonding to the contact pads provided by said cutouts.

9. A method as recited in claim 7, further comprising the step of forming said recesses using deep reactive ion etching through said each wafer of at least a subset of said wafers.

10. A method as recited in claim 7, further comprising the step of forming said recesses using laser drilling through said each wafer of at least a subset of said wafers.

11. A chip stack including block vias wherein said block vias provide electrical feedthroughs for electrical interconnects in the chip stack.

12. A chip stack including cutouts wherein said cutouts provide contact pads for electrical interconnects in the chip stack.