WO2002009159A2 - Thin-film metallic oxide structure and process for fabricating same - Google Patents

Thin-film metallic oxide structure and process for fabricating same Download PDF

Info

Publication number
WO2002009159A2
WO2002009159A2 PCT/US2001/022679 US0122679W WO0209159A2 WO 2002009159 A2 WO2002009159 A2 WO 2002009159A2 US 0122679 W US0122679 W US 0122679W WO 0209159 A2 WO0209159 A2 WO 0209159A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
monocrystalline
perovskite oxide
growing
perovskite
Prior art date
Application number
PCT/US2001/022679
Other languages
French (fr)
Other versions
WO2002009159A3 (en
Inventor
Kurt Eisenbeiser
Jeffrey M. Finder
Jamal Ramdani
Ravindranath Droopad
William Jay Ooms
Original Assignee
Motorola, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Priority to AU2001276989A priority Critical patent/AU2001276989A1/en
Priority to JP2002514770A priority patent/JP2004505444A/en
Publication of WO2002009159A2 publication Critical patent/WO2002009159A2/en
Publication of WO2002009159A3 publication Critical patent/WO2002009159A3/en

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02Epitaxial-layer growth
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/16Oxides
    • C30B29/22Complex oxides
    • C30B29/32Titanates; Germanates; Molybdates; Tungstates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02269Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00Piezoelectric or electrostrictive devices
    • H10N30/01Manufacture or treatment
    • H10N30/07Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/074Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
    • H10N30/076Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing by vapour phase deposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0268Manufacture or treatment of devices comprising copper oxide
    • H10N60/0296Processes for depositing or forming copper oxide superconductor layers
    • H10N60/0576Processes for depositing or forming copper oxide superconductor layers characterised by the substrate
    • H10N60/0604Monocrystalline substrates, e.g. epitaxial growth
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

Definitions

  • This invention relates generally to microelectronic structures and devices and to a method for their fabrication, and more specifically to thin-film, metallic oxide structures and devices and to the fabrication and use of thin-film, metallic oxide structures and devices.
  • metallic oxides exhibit desirable characteristics such as piezoelectric, ferroelectric, ferromagnetic, colossal magnetic resistance, and super conductivity properties. Such oxides may be included or used in connection with microelectronic devices that take advantage of these characteristics. For example, metallic oxides may be used to form ferroelectric memory devices and the like.
  • the desirable characteristics of the metallic oxide films increase as the crystallinity of the oxide film increases.
  • superconductive materials exhibit the highest conductivity when the material is in a monocrystalline form.
  • integration of such oxides with semiconductor components to form devices such as memory devices is also desirable. Accordingly, methods and apparatus for growing thin-film, monocrystalline metallic oxides on semiconductor substrates are desired.
  • a large area thin film of high quality monocrystalline metallic oxide material was available at low cost, a variety of semiconductor devices could advantageously be fabricated using that film at a low cost compared to the cost of fabricating such devices on a bulk wafer of the metallic oxide material or in an epitaxial film of such material on a bulk wafer of oxide material .
  • a thin film of high quality monocrystalline metallic oxide material could be realized on a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the metallic oxide material .
  • FIGS. 1 - 3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention
  • FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer .
  • FIG. 1 illustrates schematically, in cross section, a portion of a microelectronic structure 20 in accordance with an embodiment of the invention.
  • Microelectronic structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline metallic oxide material.
  • accommodating buffer layer 24 comprising a monocrystalline material
  • a layer 26 of a monocrystalline metallic oxide material in this context, the term
  • monocrystalline shall have the meaning commonly used within the semiconductor industry.
  • the term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
  • structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24.
  • Structure 20 may also include a template layer 30 between the accommodating buffer layer and monocrystalline oxide layer 26.
  • the template layer helps to initiate the growth of the metallic oxide layer on the accommodating buffer layer.
  • the amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and, by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.
  • Substrate 22 in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter.
  • the wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA.
  • Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
  • Substrate 22 can also be of a compound semiconductor material.
  • the compound semiconductor material of substrate 22 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds) , mixed III-V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds.
  • Examples include gallium arsenide (GaAs) , gallium indium arsenide (GalnAs) , gallium aluminum arsenide (GaAlAs) , indium phosphide (InP) , cadmium sulfide (CdS) , cadmium mercury telluride (CdHgTe) , zinc selenide (ZnSe) , zinc sulfur selenide (ZnSSe) , and the like.
  • GaAs gallium arsenide
  • GaAs gallium indium arsenide
  • GaAlAs gallium aluminum arsenide
  • InP indium phosphide
  • CdS cadmium sulfide
  • CdHgTe cadmium mercury telluride
  • ZnSe zinc selenide
  • ZnSSe zinc sulfur selenide
  • substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate.
  • amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer 24. The amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer.
  • lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline metallic oxide layer 26.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying metallic oxide material.
  • the material could be an oxide or nitride having a lattice structure matched to the substrate and to the subsequently applied metallic oxide material .
  • Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer.
  • metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates
  • these materials are insulators, although strontium ruthenate, for example, is a conductor.
  • these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements.
  • Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide.
  • the thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24.
  • layer 28 has a thickness in the range of approximately 0.5-5 run.
  • the metallic oxide material of layer 26 can be selected, as desired for a particular structure or application.
  • layer 26 can include a metallic oxide material having a desired property such as a material which exhibits piezoelectric, pyroelectric, ferromagnetic, colossal magneto resistive, or super conductive characteristics.
  • Such materials include monoclinic, tetragonal, cubic, or perovskite metallic oxide structures with the a general chemical formula AB0 3 where A is selected from the group consisting of lead, lanthanum, niobium, scandium, and combinations thereof, and B is selected from the group consisting of zirconium, titanium, and combinations thereof:
  • (Pb,La,Na,Sc) (Zr,Ti)0 3 e.g., PbZrTi0 3 , PbNbZrTi0 3 , PbScZrTi0 3 , PbSrNbZrTi0 3 , PbLiZrTiO., PbTi0 3 ; ABO.
  • A is selected from the group consisting of strontium, barium, calcium, and combinations thereof and B is selected from the group consisting of zirconium, hafnium, titanium, and combinations thereof: (Sr,Ba, Ca) (Zr, Hf , i) 0 3 , e.g., SrTiO., BaTi0 3 , BaSrTi0 3 , CaTi0 3 , BaZr0 3 ; ACoO- where A is selected from the group consisting of lanthanum, strontium, barium, zirconium, and combinations thereof: (La,Sr,Ba, Zr)Co0 3 , e.g., LaSrCo0 3 , LaZrCo0 3 ; ABMnO.
  • A is a rare earth element (e.g., lanthanum) and B is an alkali earth metal element (e.g., calcium, barium, or strontium): (La, Sr, Ba, Ca)Mh0 3 , e.g., LaSrMn0 3 , LaCaMhO.; ABa 2 Cu 3 O n where A is selected from the group consisting of yttrium, praseodymium, and combinations thereof and n is 7 or 8: (Y, Pr)Ba 2 Cu 3 0 7 _ 8 , e.g., YBa 2 Cu 3 0, YPrBa 2 Cu 3 0; ARu0 3 where A is selected from the group consisting of strontium, barium, and combinations thereof: (Sr, Ba) Ru0 3 ; PbA0 3 where A is selected from the group consisting of magnesium, niobium, and combinations thereof :
  • Alkali earth metal element e.g., calcium, barium,
  • template layer 30 has a thickness ranging from about one to about ten onolayers .
  • FIG. 2 illustrates, in cross section, a portion of a microelectronic structure 40 in accordance with a further embodiment of the invention.
  • Structure 40 is similar to the previously described structure 20, except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline metallic oxide material 26.
  • the additional buffer layer is positioned between optional template layer 30 (or layer 24 if no template layer exists) and the overlying layer of moncrystalline metallic oxide material.
  • the additional buffer layer formed of a monocrystalline oxide material, serves to provide a lattice compensation when the lattice constant of the accommodating buffer layer cannot be adequately matched to the overlying metallic oxide material layer.
  • FIG. 3 schematically illustrates, in cross section, a portion of a microelectronic structure 34 in accordance with another exemplary embodiment of the invention.
  • Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional metallic oxide layer 38.
  • amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline metallic oxide layer 38 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer.
  • Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers.
  • amorphous layer 36 between substrate 22 and metallic oxide layer 38 relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing--e.g. , metallic oxide layer 26 formation.
  • the processes previously described above in connection with FIGS. 1 and 2 are adequate for growing monocrystalline metallic oxide layers over a monocrystalline substrate.
  • the process described in connection with FIG. 3, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer may be better for growing monocrystalline metallic oxide layers because it allows any strain in layer 38 to relax prior to forming layer 26.
  • Metallic oxide layer 38 may include any of the materials described throughout this application in connection with either of metallic oxide layer 26 or additional buffer layer 32.
  • layer 38 may include the perovskite metallic oxides listed above as materials suitable for layer 26.
  • layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent metallic oxide layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline metallic oxide (often less than about ten monolayers) .
  • monocrystalline metallic oxide layer 38 comprises a metallic oxide material (e.g., a material discussed above in connection with layer 26) that is thick enough to use a film for a desired microelectronic device.
  • a microelectronic structure in accordance with the present invention does not include layer 26.
  • the microelectronic structure in accordance with this embodiment only includes one metallic oxide layer disposed above amorphous oxide layer 36.
  • monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction.
  • the silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200- 300 mm.
  • accommodating buffer layer 24 is a monocrystalline layer of Sr.Ba 1.z Ti0 3 where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiO x ) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26.
  • the accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (run) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the metallic oxide layer from the substrate to obtain the desired properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed.
  • the amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm.
  • metallic oxide material layer 26 is a layer of strontium ruthenate (SrRu0 3 ) having a thickness of about 5 to about 500 nm and preferably a thickness of about 10 to about 100 nm. The thickness generally depends on the application for which the layer is being prepared.
  • SrRu0 3 strontium ruthenate
  • a structure is provided that is suitable for the growth of an epitaxial film of (Pb, La,Nb, Sc) (Zr,Ti)0 3 film overlying a silicon substrate.
  • the substrate is preferably a silicon wafer as described above.
  • a suitable accommodating buffer layer material is Sr x Ba._ x Ti0 3 , where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm.
  • the metallic oxide material can be, for example PbZrTi0 3 , having a thickness of about 50 nm to about 500 nm.
  • substrate 22 is a monocrystalline substrate such as a monocrystalline silicon or gallium arsenide substrate.
  • the crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation.
  • accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation.
  • the lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved.
  • the terms "substantially equal” and “substantially matched” mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer .
  • FIG. 4' graphically illustrates the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal.
  • Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.
  • substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate.
  • Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer.
  • the inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer.
  • a high quality, thick, monocrystalline titanate layer is achievable.
  • layer 26 is a layer of epitaxially grown metallic oxide material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation.
  • the lattice constant of layer 26 differs from the lattice constant of substrate 22.
  • the accommodating buffer layer must be of high crystalline quality.
  • substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired.
  • a crystalline buffer layer between the host oxide and the grown metallic oxide layer can be used to reduce strain in the grown monocrystalline metallic oxide layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline metallic oxide layer can thereby be achieved.
  • the following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a microelectronic structure such as the structures depicted in FIGS. 1 - 3.
  • the process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium.
  • the semiconductor substrate is a silicon wafer having a (100) orientation.
  • the substrate is preferably oriented on axis or, at most, about 0.5° off axis.
  • At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
  • the term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material.
  • bare silicon is highly reactive and readily forms a native oxide.
  • the term "bare" is intended to encompass such a native oxide.
  • a thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention.
  • the native oxide layer In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention.
  • MBE molecular beam epitaxy
  • the native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus.
  • strontium the substrate is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer.
  • the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface.
  • the resultant surface which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon.
  • the ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide.
  • the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer .
  • the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature, a solid state reaction takes place between the strontium oxide and the native silicon oxide, causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.
  • an alkali earth metal oxide such as strontium oxide, strontium barium oxide, or barium oxide
  • the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources.
  • the ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
  • the overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer.
  • the growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate.
  • the strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.
  • the monocrystalline strontium titanate may be capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired metallic oxide material.
  • the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen.
  • the metallic oxide material is grown using MBE or other suitable techniques .
  • the structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step.
  • the buffer layer is formed overlying the template or accommodating buffer layer before the deposition of the monocrystalline metallic oxide layer. If the buffer layer is an oxide superlattice, such a superlattice can be deposited, by MBE for example, on the template described above.
  • Structure 34 may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing metallic oxide layer 38 over the accommodating buffer layer, as described above.
  • the accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36.
  • Layer 26 is then subsequently grown over layer 38.
  • the anneal process may be carried out subsequent to growth of layer 26.
  • layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 10 seconds to about 10 minutes.
  • suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention.
  • laser annealing or "conventional" thermal annealing processes may be used to form layer 36.
  • an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process.
  • layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26.
  • any deposition or growth methods described in connection with either layer 32 or 26 may be employed to deposit layer 38.
  • the process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline metallic oxide layer by the process of molecular beam epitaxy.
  • the process can also be carried out by the process of chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like.
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PVD physical vapor deposition
  • CSSD chemical solution deposition
  • PLD pulsed laser deposition
  • other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, peroskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
  • other metallic oxide layers can be deposited overlying the monocrystalline oxide accommodating buffer layer.
  • the metallic oxide may be grown via PLD, by ablating a target of the desired material with an eximer laser and heating the substrate to a temperature of about 300 °C to about 500 °C
  • Each of the variations of metallic oxide materials and monocrystalline oxide accommodating buffer layer may use an appropriate template for initiating the growth of the respective layer.
  • suitable template materials may be grown according to the methods described above in connection with growing layer 26.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Optics & Photonics (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

High quality epitaxial layers (26) of oxide materials can be grown overlying large silicon wafers (22) by first growing an accommodating buffer layer (24) on a silicon wafers. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. The oxyde materials may be piezoelectric, ferroelectric, pyroelectric, ferromagnetic, magnetorensitive, or supurconductive materials, preferably of perovskite type.

Description

THIN-FILM METALLIC OXIDE STRUCTURE AND PROCESS FOR FABRICATING SAME
Field of the Invention
This invention relates generally to microelectronic structures and devices and to a method for their fabrication, and more specifically to thin-film, metallic oxide structures and devices and to the fabrication and use of thin-film, metallic oxide structures and devices.
Background of the Invention Various metallic oxides exhibit desirable characteristics such as piezoelectric, ferroelectric, ferromagnetic, colossal magnetic resistance, and super conductivity properties. Such oxides may be included or used in connection with microelectronic devices that take advantage of these characteristics. For example, metallic oxides may be used to form ferroelectric memory devices and the like.
Generally, the desirable characteristics of the metallic oxide films increase as the crystallinity of the oxide film increases. For example, superconductive materials exhibit the highest conductivity when the material is in a monocrystalline form. Moreover, integration of such oxides with semiconductor components to form devices such as memory devices is also desirable. Accordingly, methods and apparatus for growing thin-film, monocrystalline metallic oxides on semiconductor substrates are desired.
Because of the desirable characteristics of various metallic oxide materials, and because of their present generally high cost and low availability in bulk form, for many years attempts have been made to grow thin films of the desired metallic oxide materials on a foreign substrate. To achieve optimal characteristics of metallic oxide material, however, a monocrystalline film of high crystalline quality is desired. Attempts have been made, for example, to grow layers of a monocrystalline metallic oxide material on substrates such as silicon. These attempts have generally been unsuccessful because lattice mismatches between the host crystal and the grown crystal have caused the resulting thin film of metallic oxide material to be of low crystalline quality. Metallic oxides of higher quality have been grown over oxide substrates such as bulk strontium titanate. Metallic oxides grown over oxide substrates are often expensive because, in part, the oxide substrate is small and expensive. If a large area thin film of high quality monocrystalline metallic oxide material was available at low cost, a variety of semiconductor devices could advantageously be fabricated using that film at a low cost compared to the cost of fabricating such devices on a bulk wafer of the metallic oxide material or in an epitaxial film of such material on a bulk wafer of oxide material . In addition, if a thin film of high quality monocrystalline metallic oxide material could be realized on a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the metallic oxide material .
Accordingly, a need exists for a microelectronic structure that provides a high quality monocrystalline metallic oxide film over another monocrystalline material and for a process for making such a structure. Brief Description of the Drawings
The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:
FIGS. 1 - 3 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention; and FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer .
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
Detailed Description of the Drawings
FIG. 1 illustrates schematically, in cross section, a portion of a microelectronic structure 20 in accordance with an embodiment of the invention. Microelectronic structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline metallic oxide material. In this context, the term
"monocrystalline" shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
In accordance with one embodiment of the invention, structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24. Structure 20 may also include a template layer 30 between the accommodating buffer layer and monocrystalline oxide layer 26. As will be explained more fully below, the template layer helps to initiate the growth of the metallic oxide layer on the accommodating buffer layer. The amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and, by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.
Substrate 22, in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter. The wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
Substrate 22 can also be of a compound semiconductor material. The compound semiconductor material of substrate 22 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds) , mixed III-V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds. Examples include gallium arsenide (GaAs) , gallium indium arsenide (GalnAs) , gallium aluminum arsenide (GaAlAs) , indium phosphide (InP) , cadmium sulfide (CdS) , cadmium mercury telluride (CdHgTe) , zinc selenide (ZnSe) , zinc sulfur selenide (ZnSSe) , and the like.
Preferably, substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate. In accordance with one embodiment of the invention, amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer 24. The amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer. As used herein, lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline metallic oxide layer 26.
Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying metallic oxide material. For example, the material could be an oxide or nitride having a lattice structure matched to the substrate and to the subsequently applied metallic oxide material . Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements.
Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide. The thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24. Typically, layer 28 has a thickness in the range of approximately 0.5-5 run.
The metallic oxide material of layer 26 can be selected, as desired for a particular structure or application. For example, layer 26 can include a metallic oxide material having a desired property such as a material which exhibits piezoelectric, pyroelectric, ferromagnetic, colossal magneto resistive, or super conductive characteristics. Such materials include monoclinic, tetragonal, cubic, or perovskite metallic oxide structures with the a general chemical formula AB03 where A is selected from the group consisting of lead, lanthanum, niobium, scandium, and combinations thereof, and B is selected from the group consisting of zirconium, titanium, and combinations thereof:
(Pb,La,Na,Sc) (Zr,Ti)03, e.g., PbZrTi03, PbNbZrTi03, PbScZrTi03, PbSrNbZrTi03, PbLiZrTiO., PbTi03; ABO. where A is selected from the group consisting of strontium, barium, calcium, and combinations thereof and B is selected from the group consisting of zirconium, hafnium, titanium, and combinations thereof: (Sr,Ba, Ca) (Zr, Hf , i) 03, e.g., SrTiO., BaTi03, BaSrTi03, CaTi03, BaZr03; ACoO- where A is selected from the group consisting of lanthanum, strontium, barium, zirconium, and combinations thereof: (La,Sr,Ba, Zr)Co03, e.g., LaSrCo03, LaZrCo03; ABMnO. where A is a rare earth element (e.g., lanthanum) and B is an alkali earth metal element (e.g., calcium, barium, or strontium): (La, Sr, Ba, Ca)Mh03, e.g., LaSrMn03, LaCaMhO.; ABa2Cu3On where A is selected from the group consisting of yttrium, praseodymium, and combinations thereof and n is 7 or 8: (Y, Pr)Ba2Cu307_8, e.g., YBa2Cu30, YPrBa2Cu30; ARu03 where A is selected from the group consisting of strontium, barium, and combinations thereof: (Sr, Ba) Ru03; PbA03 where A is selected from the group consisting of magnesium, niobium, and combinations thereof :
Pb(Mg,Nb)03; GdFe03; YA103; LaAl03; SrV03; SrCr03; BaA03 where A is selected from the group consisting of lead, bismuth, and combinations thereof: Ba (Pb, Bi) 03; LaCo03; KNb03; NaW03; BiTi.O.- ; YMn03; and LaA03 where A is selected from the group consisting of aluminum, scandium, and combinations thereof: La(Al, Sc)03.
Suitable template materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent metallic oxide layer 26. When used, template layer 30 has a thickness ranging from about one to about ten onolayers .
FIG. 2 illustrates, in cross section, a portion of a microelectronic structure 40 in accordance with a further embodiment of the invention. Structure 40 is similar to the previously described structure 20, except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline metallic oxide material 26. Specifically, the additional buffer layer is positioned between optional template layer 30 (or layer 24 if no template layer exists) and the overlying layer of moncrystalline metallic oxide material. The additional buffer layer, formed of a monocrystalline oxide material, serves to provide a lattice compensation when the lattice constant of the accommodating buffer layer cannot be adequately matched to the overlying metallic oxide material layer.
FIG. 3 schematically illustrates, in cross section, a portion of a microelectronic structure 34 in accordance with another exemplary embodiment of the invention. Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional metallic oxide layer 38.
As explained in greater detail below, amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline metallic oxide layer 38 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and metallic oxide layer 38 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing--e.g. , metallic oxide layer 26 formation. The processes previously described above in connection with FIGS. 1 and 2 are adequate for growing monocrystalline metallic oxide layers over a monocrystalline substrate. However, the process described in connection with FIG. 3, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer, may be better for growing monocrystalline metallic oxide layers because it allows any strain in layer 38 to relax prior to forming layer 26.
Metallic oxide layer 38 may include any of the materials described throughout this application in connection with either of metallic oxide layer 26 or additional buffer layer 32. For example, layer 38 may include the perovskite metallic oxides listed above as materials suitable for layer 26. In accordance with one embodiment of the present invention, layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent metallic oxide layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline metallic oxide (often less than about ten monolayers) . In accordance with another embodiment of the invention, monocrystalline metallic oxide layer 38 comprises a metallic oxide material (e.g., a material discussed above in connection with layer 26) that is thick enough to use a film for a desired microelectronic device. In this case, a microelectronic structure in accordance with the present invention does not include layer 26. In other words, the microelectronic structure in accordance with this embodiment only includes one metallic oxide layer disposed above amorphous oxide layer 36.
The following non-limiting, illustrative examples illustrate various combinations of materials useful in structures 20, 40, and 34 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.
Example 1
In accordance with one embodiment of the invention, monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction. The silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200- 300 mm. In accordance with this embodiment of the invention, accommodating buffer layer 24 is a monocrystalline layer of Sr.Ba1.zTi03 where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiOx) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26. The accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (run) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the metallic oxide layer from the substrate to obtain the desired properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed. The amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm.
In accordance with this embodiment of the invention, metallic oxide material layer 26 is a layer of strontium ruthenate (SrRu03) having a thickness of about 5 to about 500 nm and preferably a thickness of about 10 to about 100 nm. The thickness generally depends on the application for which the layer is being prepared. Example 2
In accordance with another embodiment of the invention, a structure is provided that is suitable for the growth of an epitaxial film of (Pb, La,Nb, Sc) (Zr,Ti)03 film overlying a silicon substrate. The substrate is preferably a silicon wafer as described above. A suitable accommodating buffer layer material is SrxBa._xTi03 , where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm. The metallic oxide material can be, for example PbZrTi03, having a thickness of about 50 nm to about 500 nm.
Referring again to FIGS. 1 - 3, substrate 22 is a monocrystalline substrate such as a monocrystalline silicon or gallium arsenide substrate. The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In similar manner, accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms "substantially equal" and "substantially matched" mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer .
FIG. 4' graphically illustrates the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal. Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.
In accordance with one embodiment of the invention, substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate. Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer. The inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer. As a result, in accordance with an embodiment of the invention, a high quality, thick, monocrystalline titanate layer is achievable.
Still referring to FIGS. 1 - 3, layer 26 is a layer of epitaxially grown metallic oxide material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation. In accordance with one embodiment of the invention, the lattice constant of layer 26 differs from the lattice constant of substrate 22. To achieve high crystalline quality in this epitaxially grown monocrystalline layer, the accommodating buffer layer must be of high crystalline quality. In addition, in order to achieve high crystalline quality in layer 26, substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired. With properly selected materials, this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal. In some instances, a crystalline buffer layer between the host oxide and the grown metallic oxide layer can be used to reduce strain in the grown monocrystalline metallic oxide layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline metallic oxide layer can thereby be achieved.
The following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a microelectronic structure such as the structures depicted in FIGS. 1 - 3. The process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium. In accordance with a preferred embodiment of the invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate is preferably oriented on axis or, at most, about 0.5° off axis. At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term "bare" is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention. In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon. The ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer . In accordance with an alternate embodiment of the invention, the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature, a solid state reaction takes place between the strontium oxide and the native silicon oxide, causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.
Following the removal of the silicon oxide from the surface of the substrate, in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate. - The strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.
After the strontium titanate layer has been grown to the desired thickness, the monocrystalline strontium titanate may be capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired metallic oxide material. For example, the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen. Following the formation of the template (if one is formed) , the metallic oxide material is grown using MBE or other suitable techniques .
The structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer deposition step. The buffer layer is formed overlying the template or accommodating buffer layer before the deposition of the monocrystalline metallic oxide layer. If the buffer layer is an oxide superlattice, such a superlattice can be deposited, by MBE for example, on the template described above.
Structure 34, illustrated in FIG. 3, may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing metallic oxide layer 38 over the accommodating buffer layer, as described above. The accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36. Layer 26 is then subsequently grown over layer 38. Alternatively, the anneal process may be carried out subsequent to growth of layer 26.
In accordance with one aspect of this embodiment, layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 10 seconds to about 10 minutes. However, other suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention. For example, laser annealing or "conventional" thermal annealing processes (in the proper environment) may be used to form layer 36. When conventional thermal annealing is employed to form layer 36, an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process.
As noted above, layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26.
Accordingly, any deposition or growth methods described in connection with either layer 32 or 26 may be employed to deposit layer 38. The process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline metallic oxide layer by the process of molecular beam epitaxy. The process can also be carried out by the process of chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like. Further, by a similar process, other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, peroskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown. Further, by a similar process such as MBE, other metallic oxide layers can be deposited overlying the monocrystalline oxide accommodating buffer layer. For example, the metallic oxide may be grown via PLD, by ablating a target of the desired material with an eximer laser and heating the substrate to a temperature of about 300 °C to about 500 °C
Each of the variations of metallic oxide materials and monocrystalline oxide accommodating buffer layer may use an appropriate template for initiating the growth of the respective layer. In such a case, suitable template materials may be grown according to the methods described above in connection with growing layer 26. In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element (s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. As used herein, the terms "comprises," "comprising, " or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

CLAIMS We claim:
1. A perovskite oxide structure comprising:
a monocrystalline semiconductor substrate;
an amorphous layer overlying the monocrystalline semiconductor substrate;
a monocrystalline layer comprising SrxBa1.xTi03 where x ranges from 0 to 1 overlying the amorphous layer; and
a monocrystalline perovskite oxide layer overlying the monocrystalline layer.
2. The perovskite oxide structure of claim 1 wherein the monocrystalline semiconductor substrate comprises silicon.
3. The perovskite oxide structure of claim 2 wherein the amorphous layer comprises silicon oxide.
. The perovskite oxide structure of claim 3 wherein the amorphous oxide layer has a thickness sufficient to relieve strain in the monocrystalline layer.
5. The perovskite oxide structure of claim 1 wherein the monocrystalline perovskite oxide layer comprises a material having a property selected from the group consisting of piezoelectricity, ferroelectricity, pyroelectricity, ferromagnetism, colossal magneto resistivity, and superconductivity.
6. The perovskite oxide structure of claim 1 wherein the monocrystalline layer is characterized by a first lattice constant determined, in part, by the value of x and wherein the perovskite oxide layer is characterized by a second lattice constant and wherein the value of x is varied to substantially match the first and second lattice constants .
7. The perovskite oxide structure of claim 1 wherein the monocrystalline perovskite oxide layer has a composition
AB03 where A is selected from the group consisting of lead, lanthanum, niobium, scandium, and combinations thereof, and B is selected from the group consisting of zirconium, titanium, and combinations thereof.
8. The perovskite oxide structure of claim 1 wherein the monocrystalline perovskite oxide layer has a composition ABO3 where A is selected from the group consisting of strontium, barium, calcium, and combinations thereof and B is selected from the group consisting of zirconium, hafnium, titanium, and combinations thereof.
9. The perovskite oxide structure of claim 1 wherein the monocrystalline perovskite oxide layer has a composition ACo03 where A is selected from the group consisting of lanthanum, strontium, barium, zirconium, and combinations thereof .
10.. The perovskite oxide structure of claim 1 wherein the monocrystalline perovskite oxide layer has a composition ABMn03 where A is a rare earth element and B is an alkali earth metal element.
11. The perovskite oxide structure of claim 10 wherein the rare earth element comprises lanthanum and the alkali earth metal element is selected from the group consisting of calcium, strontium, and barium.
12. The perovskite oxide structure of claim 1 wherein the monocrystalline perovskite oxide layer has a composition ABa2Cu3On where A is selected from the group consisting of yttrium, praseodymium, and combinations thereof and n is 7 or 8.
13. The perovskite oxide structure of claim 1 wherein the monocrystalline perovskite oxide layer has a composition ARu03 where A is selected from the group consisting of strontium, barium, and combinations thereof.
14. The perovskite oxide structure of claim 1 wherein the monocrystalline perovskite oxide layer has a composition PbA03 where A is selected from the group consisting of magnesium, niobium, and combinations thereof.
15. The perovskite oxide structure of claim 1 wherein the monocrystalline perovskite oxide layer has a composition BaA03 where A is selected from the group consisting of lead, bismuth, and combinations thereof.
16. The perovskite oxide structure of claim 1 wherein the monocrystalline perovskite oxide layer has a composition LaA03 where A is selected from the group consisting of aluminum, scandium, and combinations thereof .
17. The perovskite oxide structure of claim 1 wherein the monocrystalline perovskite oxide layer has a composition selected from the group consisting of GdFe03, YA103, LaAl03, SrCr03, SrV03, LaCo03, KNb03, NaW03, Bi4Ti3012, YMn03, and LaSc03.
18. A perovskite oxide structure comprising:
a monocrystalline semiconductor substrate;
a first perovskite layer epitaxially grown on the semiconductor substrate;
a strain relief oxide layer formed on the semiconductor substrate underlying the first perovskite layer; and
a second perovskite layer having a different composition than the first perovskite layer epitaxially grown on the first perovskite layer.
19. The perovskite oxide structure of claim 18 wherein the monocrystalline semiconductor substrate comprises a Group IV element .
20. The perovskite oxide structure of claim 19 wherein the monocrystalline semiconductor substrate comprises silicon.
21. The perovskite oxide structure of claim 20 wherein the strain relief oxide comprises silicon oxide.
22. The perovskite oxide structure of claim 18 wherein the second perovskite layer is substantially lattice matched to the first perovskite layer.
23. The perovskite oxide structure of claim 18 wherein the second perovskite layer comprises a material • having a property selected from the group consisting of piezoelectricity, ferroelectricity, pyroelectricity, ferromagnetism, colossal magneto resistivity, and superconductivity.
24. The perovskite oxide structure of claim 18 wherein the first perovskite layer comprises SrxBa1.xTi03 where x ranges from 0 to 1.
25. A perovskite oxide structure comprising:
a monocrystalline silicon substrate;
a silicon oxide overlying the substrate;
a layer of SrxBa1.xTi03 where x ranges from 0 to 1 epitaxially grown overlying the substrate; and
a perovskite oxide layer epitaxially grown overlying and substantially lattice matched to the layer of Sr^-Ba^ xTi03.
26. A process for fabricating a perovskite oxide structure comprising the steps of:
providing a monocrystalline silicon substrate; forming a first template layer overlying the substrate;
growing a first layer of monocrystalline oxide overlying the first template layer;
growing a first amorphous layer of silicon oxide on the substrate during the step of growing a first layer;
forming a second template layer overlying the first layer; and
growing a second layer of monocrystalline perovskite oxide overlying the second template layer.
27. The process of claim 26 wherein the step of forming a first template layer comprises the steps of:
depositing a layer of strontium overlying the substrate; and
heating the substrate to react the strontium.
28. The process of claim 26 wherein the step of forming a first template layer comprises the step of forming a layer comprising silicon, strontium, and oxygen.
29. The process of claim 26 wherein the step of forming a first template layer comprises the steps of:
depositing a layer of strontium oxide overlying the substrate; and
heating the substrate to react the strontium oxide.
30. The process of claim 26 wherein the step of growing a first layer of monocrystalline oxide comprises the step of growing a layer of monocrystalline SrxBax_ xTi03 where x ranges from 0 to 1.
31. The process of claim 30 wherein the step of growing a first layer of monocrystalline oxide comprises growing a first layer of monocrystalline oxide by a process selected from the group consisting of molecular beam epitaxy, chemical vapor deposition, metal organic chemical vapor deposition, migration enhanced epitaxy, atomic layer epitaxy, physical vapor deposition, chemical solution deposition, and pulsed laser deposition.
32. The process of claim 30 wherein the step of forming a second template layer comprises the step of forming 1 - 10 monolayers of a material selected to nucleate the monocrystalline growth of the second layer,
33. The process of claim 30 wherein the step of growing a second layer comprises the step of growing a monocrystalline perovskite oxide substantially lattice matched to the SrxBa1.xTi03.
34. The process of claim 30 wherein the step of growing a second layer comprises growing a monocrystalline perovskite oxide by a process selected from the group consisting of molecular beam epitaxy, chemical vapor deposition, metal organic chemical vapor deposition, . migration enhanced epitaxy, atomic layer epitaxy, physical vapor deposition, chemical solution deposition, and pulsed laser deposition.
35. The process of claim 26 wherein the step of growing a second layer comprises the steps of :
placing the substrate in a pulsed laser deposition system;
providing a perovskite oxide target in the pulsed laser deposition system;
heating the substrate to a temperature between about 300ξ£ C and about 50θg C; and
ablating the target using a laser.
36. The process of claim 35 wherein the process of ablating the target comprises the step of ablating the target with an eximer laser.
37. A process for fabricating a perovskite oxide structure comprising the steps of:
providing a monocrystalline substrate;
growing a first layer of monocrystalline oxide overlying the substrate;
growing a strain release layer underlying the first layer; and
growing a monocrystalline perovskite oxide layer overlying the first layer.
38. The process of claim 37 wherein the step of growing a first layer comprises the step of growing a layer comprising SrxBa1_xTi03 where x ranges from 0 to 1.
39. The process of claim 37 wherein the step of growing a monocrystalline perovskite oxide layer comprises the step of growing a perovskite oxide layer substantially lattice matched to the first layer.
40. The process of claim 37 wherein the step of growing a monocrystalline perovskite oxide layer comprises the step of growing a perovskite oxide layer by a process selected from the group consisting of molecular beam epitaxy, chemical vapor deposition, metal organic chemical vapor deposition, migration enhanced epitaxy, atomic layer epitaxy, physical vapor deposition, chemical solution deposition, and pulsed laser deposition.
41. A process for fabricating a perovskite oxide structure comprising the steps of:
growing a first layer comprising SrxBa1.xTi03 where x ranges from 0 to 1; and
growing a second layer of monocrystalline perovskite oxide overlying the first layer.
42. The process of claim 41 wherein the step of growing a second layer comprises growing a second layer substantially lattice matched to the first layer.
PCT/US2001/022679 2000-07-24 2001-07-19 Thin-film metallic oxide structure and process for fabricating same WO2002009159A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2001276989A AU2001276989A1 (en) 2000-07-24 2001-07-19 Thin-film metallic oxide structure and process for fabricating same
JP2002514770A JP2004505444A (en) 2000-07-24 2001-07-19 Thin film metal oxide structure and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62487700A 2000-07-24 2000-07-24
US09/624,877 2000-07-24

Publications (2)

Publication Number Publication Date
WO2002009159A2 true WO2002009159A2 (en) 2002-01-31
WO2002009159A3 WO2002009159A3 (en) 2002-04-25

Family

ID=24503701

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/022679 WO2002009159A2 (en) 2000-07-24 2001-07-19 Thin-film metallic oxide structure and process for fabricating same

Country Status (4)

Country Link
JP (1) JP2004505444A (en)
CN (1) CN1449458A (en)
AU (1) AU2001276989A1 (en)
WO (1) WO2002009159A2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004058958A1 (en) * 2004-12-08 2006-06-14 Forschungszentrum Jülich GmbH High band gap material and dielectric constant
US7072093B2 (en) 2003-04-30 2006-07-04 Hewlett-Packard Development Company, L.P. Optical interference pixel display with charge control
CN100359648C (en) * 2002-05-03 2008-01-02 飞思卡尔半导体公司 Method for growing a monocrystalline oxide on semiconductor device
JP2008120100A (en) * 2008-02-12 2008-05-29 Seiko Epson Corp Head manufacturing method and printer manufacturing method
CN101913860A (en) * 2010-08-19 2010-12-15 西北工业大学 Bismuth titanate based piezoelectric ceramic with high curie temperature and preparation method thereof
JP2012151174A (en) * 2011-01-17 2012-08-09 Ricoh Co Ltd Field-effect transistor, display element, image display device, and system
CN115418718A (en) * 2022-09-07 2022-12-02 武汉大学 Product based on two-dimensional spinel type ferrite film and preparation method and application thereof

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101789260B (en) * 2010-01-19 2013-03-20 湘潭大学 Epitaxial strain ferroelectric film for ferroelectric memory and method for regulating and controlling strain thereof
CN106277041B (en) * 2016-11-14 2018-01-12 东北大学 A kind of preparation method of lanthanum gallate solid solution barium titanate amorphous
US10697090B2 (en) * 2017-06-23 2020-06-30 Panasonic Intellectual Property Management Co., Ltd. Thin-film structural body and method for fabricating thereof
CN112537799B (en) * 2019-09-20 2021-09-28 中国科学院物理研究所 Method for regulating oxygen vacancy sequence phase of perovskite phase cobalt oxide material
CN111926295B (en) * 2020-09-01 2022-08-09 深圳大学 Huge tetragonal phase PbTiO 3 Method for producing thin film

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6450575A (en) * 1987-08-21 1989-02-27 Nec Corp Substrate for electronic device
US5270298A (en) * 1992-03-05 1993-12-14 Bell Communications Research, Inc. Cubic metal oxide thin film epitaxially grown on silicon
EP0568064B1 (en) * 1992-05-01 1999-07-14 Texas Instruments Incorporated Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer
US5650362A (en) * 1993-11-04 1997-07-22 Fuji Xerox Co. Oriented conductive film and process for preparing the same
US5830270A (en) * 1996-08-05 1998-11-03 Lockheed Martin Energy Systems, Inc. CaTiO3 Interfacial template structure on semiconductor-based material and the growth of electroceramic thin-films in the perovskite class

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100359648C (en) * 2002-05-03 2008-01-02 飞思卡尔半导体公司 Method for growing a monocrystalline oxide on semiconductor device
US7072093B2 (en) 2003-04-30 2006-07-04 Hewlett-Packard Development Company, L.P. Optical interference pixel display with charge control
DE102004058958A1 (en) * 2004-12-08 2006-06-14 Forschungszentrum Jülich GmbH High band gap material and dielectric constant
DE102004058958B4 (en) * 2004-12-08 2006-10-26 Forschungszentrum Jülich GmbH Semiconductor device made of a high band gap material and dielectric constant
JP2008120100A (en) * 2008-02-12 2008-05-29 Seiko Epson Corp Head manufacturing method and printer manufacturing method
CN101913860A (en) * 2010-08-19 2010-12-15 西北工业大学 Bismuth titanate based piezoelectric ceramic with high curie temperature and preparation method thereof
CN101913860B (en) * 2010-08-19 2012-11-21 西北工业大学 Bismuth titanate based piezoelectric ceramic with high curie temperature and preparation method thereof
JP2012151174A (en) * 2011-01-17 2012-08-09 Ricoh Co Ltd Field-effect transistor, display element, image display device, and system
CN115418718A (en) * 2022-09-07 2022-12-02 武汉大学 Product based on two-dimensional spinel type ferrite film and preparation method and application thereof

Also Published As

Publication number Publication date
WO2002009159A3 (en) 2002-04-25
JP2004505444A (en) 2004-02-19
AU2001276989A1 (en) 2002-02-05
CN1449458A (en) 2003-10-15

Similar Documents

Publication Publication Date Title
US7020374B2 (en) Optical waveguide structure and method for fabricating the same
US6563118B2 (en) Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same
US7211852B2 (en) Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate
US6709776B2 (en) Multilayer thin film and its fabrication process as well as electron device
US6555946B1 (en) Acoustic wave device and process for forming the same
WO2003094218A2 (en) Method of growing monocrystalline oxide having a semiconductor device thereon
KR100827216B1 (en) Microelectronic piezoelectric structure
WO2002009159A2 (en) Thin-film metallic oxide structure and process for fabricating same
US6693298B2 (en) Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US20020088970A1 (en) Self-assembled quantum structures and method for fabricating same
WO2002009158A2 (en) Semiconductor structure including a magnetic tunnel junction
US6482538B2 (en) Microelectronic piezoelectric structure and method of forming the same
WO2002009191A2 (en) Non-volatile memory element
US6890816B2 (en) Compound semiconductor structure including an epitaxial perovskite layer and method for fabricating semiconductor structures and devices
US7169619B2 (en) Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process
WO2002082515A1 (en) Semiconductor structure and device including a carbon film
US20020003238A1 (en) Structure including cubic boron nitride films and method of forming the same
US20020000584A1 (en) Semiconductor structure and device including a monocrystalline conducting layer and method for fabricating the same
US20020153524A1 (en) Structure and method for fabricating semiconductor structures and devices utilizing perovskite stacks
US20030019423A1 (en) Structure and method for fabricating semiconductor structures and devices utilizing the formation of a compliant gallium nitride substrate
US20030020068A1 (en) Structure and method for integrating compound semiconductor structures and devices utilizing the formation of a compliant substrate for materials used to form the same
EP1338029A1 (en) Semiconductor structure having high dielectric constant material
US20040164315A1 (en) Structure and device including a tunneling piezoelectric switch and method of forming same
US20020158245A1 (en) Structure and method for fabricating semiconductor structures and devices utilizing binary metal oxide layers
WO2002009157A2 (en) Alkali earth metal oxide gate insulators

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWE Wipo information: entry into national phase

Ref document number: 01813243X

Country of ref document: CN

Ref document number: 1020037001026

Country of ref document: KR

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2001954765

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 2001954765

Country of ref document: EP

WWR Wipo information: refused in national office

Ref document number: 1020037001026

Country of ref document: KR

WWW Wipo information: withdrawn in national office

Ref document number: 1020037001026

Country of ref document: KR