WO2002003465A2 - Semiconductor package with stacked flip chip and wire bonded upper die - Google Patents

Semiconductor package with stacked flip chip and wire bonded upper die Download PDF

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Publication number
WO2002003465A2
WO2002003465A2 PCT/US2001/018223 US0118223W WO0203465A2 WO 2002003465 A2 WO2002003465 A2 WO 2002003465A2 US 0118223 W US0118223 W US 0118223W WO 0203465 A2 WO0203465 A2 WO 0203465A2
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WO
WIPO (PCT)
Prior art keywords
die
substrate
side surfaces
chip
circuit assembly
Prior art date
Application number
PCT/US2001/018223
Other languages
French (fr)
Other versions
WO2002003465A3 (en
Inventor
Melissa Siow-Liu Lee
Edwin Fontecha
Bruce Symons
Original Assignee
Advanced Micro Devices, Inc.
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Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to AU2001275268A priority Critical patent/AU2001275268A1/en
Publication of WO2002003465A2 publication Critical patent/WO2002003465A2/en
Publication of WO2002003465A3 publication Critical patent/WO2002003465A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to semiconductor packaging technology.
  • the present invention has particular applicability to semiconductor packages containing multiple semiconductor dies and to bonding stacked dies to substrates.
  • Multi-chip modules have evolved comprising a printed circuit board substrate to which a series of separate components are directly attached. Multi-chip devices advantageously increase circuit density with attendant improvements in signal propagation speed and overall device weight.
  • Integrated circuit devices are typically electronically packaged by mounting one or more chips to a ceramic or organic, e.g., alumina circuitize substrate, sometimes referred to as a package. Wire bonds are employed to electrically connect input/output (IO) contact pads on each chip to corresponding contact pads and to corresponding fan-out circuitry on the circuitized package substrate. The resulting package is then typically mounted on a printed circuit board (PCB) and, employing circuitry on the PCB, electrically coupled to other such packages and/or other electronic components mounted on the PCB.
  • PCB printed circuit board
  • circuitized substrates contain two or more routing layers of fan-out circuitry.
  • Such layers of fan-out circuitry are electrically interconnected by mechanically drilled holes known as vias which are plated and/or filled with electrically conductive material, e.g., tungsten.
  • Some of the holes extend from the layers of fan-out circuitry to respective lands on the chip carrier substrates, on which are mounted solder balls forming a grid array, thereby generating the expression "ball grid array”.
  • the solder balls are mechanically and electrically connected to corresponding solderable contact pads on the PCB.
  • a so-called flip-chip technology has arisen.
  • a bumped integrated circuit having a pad arrangement on a major top surface is turned upside-down, i.e., flipped, thereby allowing direct coupling between the pads and matching context on the package substrate.
  • the direct connection is fabricated by growing solder bumps formed on the integrated circuit I/O terminals.
  • the flipped bumped integrated circuit is otherwise referred to as a flip-chip.
  • the flip-chip is then aligned to the package substrate and all connections are made simultaneously by reflowing the solder.
  • An advantage of the present invention is a circuit assembly comprising stacked upper and lower dies, wherein the size of the lower die is substantially the same as or smaller than the size of the upper die.
  • Another advantage of the present invention is a method of manufacturing a circuit assembly comprising stacked upper and lower dies, wherein the size of the lower die is substantially the same as or smaller than the size of the upper die.
  • a circuit assembly comprising: a package substrate having a main surface; a flip- chip first die having an upper surface, a lower surface and side surfaces, the lower surface of the first die positioned on and electrically connected to the main surface of the substrate with reflowed solder balls; and a second die having an upper surface, a lower surface and side surfaces, the second positioned with its lower surface on the first die and electrically connected to the main surface of the substrate by bond wires wire bonded to bond pads on the upper surface of the second die.
  • Another aspect of the present invention is a method of manufacturing a circuit assembly, the method comprising: providing a package substrate having a main surface; positioning a flip-chip first die, having an upper surface, a lower surface with solder balls thereon and side surfaces, such that the solder balls are on the main surface of the substrate; heating to bond and electrically connect the first die to conductors on the main surface of the substrate by reflowing the solder balls; positioning a second die, having an upper surface containing bond pads, a lower surface and side surfaces, such that the lower surface of the second die is on the upper surface of the first die; and electrically connecting the second die to the substrate by wire bonding bond wires to the bond pads, the bond wires being electrically connected to conductors on the main surface of the substrate.
  • Embodiments of the present invention comprise bonding the second die to the first die with a dielectric bonding material, such as a non-conductive epoxy.
  • Embodiments of the present invention further comprise the use of a lower die having substantially the same size as the upper die, as well as a lower die which is smaller than the upper die.
  • Fig. 1 schematically illustrates, in cross-sectional view, a stacked die structure in accordance with an embodiment of the present invention.
  • the present invention addresses and solves the problem of electrically connecting lower and upper dies to a package substrate wherein the lower die is substantially the same size as or even smaller than the upper die, thereby improving design flexibility and increasing circuit density.
  • This objective is obtained by the strategic utilization of a flip- chip for the lower die and a die having bond pads on the upper surface for the upper die.
  • the strategic combination of a lower flip-chip die and a wire bonding upper die enables the use of first and second dies having substantially the same size such that there is substantially no overlap between the side surfaces of the first and second dies.
  • Embodiments of the present invention provide even greater flexibility by enabling the use of a lower die having a size smaller than that of the upper die, such that the side surfaces of the upper die overlap the side surfaces of the lower die.
  • the upper die can be bonded to the lower die by employing a conventional dielectric adhesive, such as a non-conductive epoxy, such as QMI 536 obtainable from Quantum Materials, Inc. located in San Diego, California.
  • Embodiments of the present invention comprise positioning the flip-chip lower die having terminations on the lower surface thereof in the form of solder pads or bump contacts on the upper surface of the package substrate. Solder reflowing is then implemented to bond and electrically connect the flip-chip lower die to the circuitized package substrate. The dielectric bonding material is then applied to the upper surface of the flip-chip lower die and the upper wire bonding die mounted on the upper surface of the lower die. The upper die contains a plurality of bond pads on its upper surface. Wire bonding is then conducted to electrically connect bond wires to the bond pads on the upper surface of the upper die. Subsequent methodology is conducted in accordance with conventional practices and includes, inter alia, encapsulating the stacked dies with a molding resin.
  • suitable conventional package circuitized substrates for use in embodiments of the present invention typically comprise plated via holes therethrough and solder balls on the underside for bonding to a conventional PCB.
  • FIG. 1 An embodiment of the present invention is schematically illustrated in Fig. 1 and comprises circuitized package substrate 10 having mounted thereon flip-chip lower die 11 by means of reflow solder balls 12.
  • Upper die 14 is bonded to lower flip-chip die 12 by means of dielectric adhesive 13.
  • Upper die 14 contains a plurality of bond pad 16 on its upper surface which are electrically connected to conductors (not shown) of the circuitized package substrate 10 means of bond wires 15 wire bonded thereto.
  • the stacked dies are encapsulated by resin 17.
  • Solder balls 18 are provided on the lower surface of substrate 10 for mounting to a PCB.
  • the present invention advantageously enables the manufacture of stacked die configurations, wherein the lower die is substantially the same size as or even smaller than the upper die in a cost effective, efficient manner.
  • the present invention is applicable to any of various types of integrated circuit packages.
  • the present invention is applicable to both high and low density integrated circuit packaging comprising multi-chip modules.

Abstract

A circuit assembly is formed with a lower flip-chip die, a wire bonded upper die stacked on the lower die and a non-conductive adhesive therebetween. The combination of a lower flip-chip die and upper wire bonded die enables efficient electrical connection of both dies with a similar size to a chip carrying substrate thereby enhancing flexibility and circuit density.

Description

SEMICONDUCTOR PACKAGE WITH STACKED FLIP CHIP AND WIRE BONDED UPPER DIE
Technical Field
The present invention relates to semiconductor packaging technology. The present invention has particular applicability to semiconductor packages containing multiple semiconductor dies and to bonding stacked dies to substrates.
Background Art
Ongoing advances in solid-state electronic devices impose continuous demands for integrated circuit devices with increased functionality, density, and performance. In response, multi-chip modules have evolved comprising a printed circuit board substrate to which a series of separate components are directly attached. Multi-chip devices advantageously increase circuit density with attendant improvements in signal propagation speed and overall device weight. Integrated circuit devices are typically electronically packaged by mounting one or more chips to a ceramic or organic, e.g., alumina circuitize substrate, sometimes referred to as a package. Wire bonds are employed to electrically connect input/output (IO) contact pads on each chip to corresponding contact pads and to corresponding fan-out circuitry on the circuitized package substrate. The resulting package is then typically mounted on a printed circuit board (PCB) and, employing circuitry on the PCB, electrically coupled to other such packages and/or other electronic components mounted on the PCB.
Conventional circuitized substrates contain two or more routing layers of fan-out circuitry. Such layers of fan-out circuitry are electrically interconnected by mechanically drilled holes known as vias which are plated and/or filled with electrically conductive material, e.g., tungsten. Some of the holes extend from the layers of fan-out circuitry to respective lands on the chip carrier substrates, on which are mounted solder balls forming a grid array, thereby generating the expression "ball grid array". The solder balls are mechanically and electrically connected to corresponding solderable contact pads on the PCB. The continuing increase in the size of large scale integrated circuit chips results in a corresponding increase in the number of I/O connections required to be made to a chip. The increase in the number of I/O connections results in an increase in process complexity since thin wires must be manually or automatically placed between the chip pads and the package substrate for electrical connections.
In an attempt to reduce the expense and complexity of the wire bonding process and/or to improve electrical performance, a so-called flip-chip technology has arisen. In the flip-chip technology, a bumped integrated circuit having a pad arrangement on a major top surface is turned upside-down, i.e., flipped, thereby allowing direct coupling between the pads and matching context on the package substrate. The direct connection is fabricated by growing solder bumps formed on the integrated circuit I/O terminals. The flipped bumped integrated circuit is otherwise referred to as a flip-chip. The flip-chip is then aligned to the package substrate and all connections are made simultaneously by reflowing the solder.
The trend toward increased functionality, density and performance has also given rise to the practice of superimposing semiconductor dies on a package substrate. This practice is difficult to implement in situations where the stacked dies are of similar size, because it is difficult to effect wire bonding to the bond pads on the upper surface of the lower die. However, if the lower die is made larger than the upper die, the number of dies that can be accommodated on a substrate and/or PCB is reduced. Thus, the use of stacked dies for purposes of achieving increased functionality, density and performance is limited.
Accordingly, there exists a need for a semiconductor package comprising a circuit assembly with stacked dies having substantially the same size. There also exists a need for a method of manufacturing a packaged semiconductor device comprising a circuit assembly with stacked dies having substantially the same size.
Summary of the Invention
An advantage of the present invention is a circuit assembly comprising stacked upper and lower dies, wherein the size of the lower die is substantially the same as or smaller than the size of the upper die.
Another advantage of the present invention is a method of manufacturing a circuit assembly comprising stacked upper and lower dies, wherein the size of the lower die is substantially the same as or smaller than the size of the upper die. Additional advantages and features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a circuit assembly comprising: a package substrate having a main surface; a flip- chip first die having an upper surface, a lower surface and side surfaces, the lower surface of the first die positioned on and electrically connected to the main surface of the substrate with reflowed solder balls; and a second die having an upper surface, a lower surface and side surfaces, the second positioned with its lower surface on the first die and electrically connected to the main surface of the substrate by bond wires wire bonded to bond pads on the upper surface of the second die.
Another aspect of the present invention is a method of manufacturing a circuit assembly, the method comprising: providing a package substrate having a main surface; positioning a flip-chip first die, having an upper surface, a lower surface with solder balls thereon and side surfaces, such that the solder balls are on the main surface of the substrate; heating to bond and electrically connect the first die to conductors on the main surface of the substrate by reflowing the solder balls; positioning a second die, having an upper surface containing bond pads, a lower surface and side surfaces, such that the lower surface of the second die is on the upper surface of the first die; and electrically connecting the second die to the substrate by wire bonding bond wires to the bond pads, the bond wires being electrically connected to conductors on the main surface of the substrate.
Embodiments of the present invention comprise bonding the second die to the first die with a dielectric bonding material, such as a non-conductive epoxy. Embodiments of the present invention further comprise the use of a lower die having substantially the same size as the upper die, as well as a lower die which is smaller than the upper die. Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawing and description is to be regarded as illustrative in nature, and not as restrictive. Brief Description of the Drawing
Fig. 1 schematically illustrates, in cross-sectional view, a stacked die structure in accordance with an embodiment of the present invention.
Description of the Present Invention
The present invention addresses and solves the problem of electrically connecting lower and upper dies to a package substrate wherein the lower die is substantially the same size as or even smaller than the upper die, thereby improving design flexibility and increasing circuit density. This objective is obtained by the strategic utilization of a flip- chip for the lower die and a die having bond pads on the upper surface for the upper die. The strategic combination of a lower flip-chip die and a wire bonding upper die enables the use of first and second dies having substantially the same size such that there is substantially no overlap between the side surfaces of the first and second dies. Embodiments of the present invention provide even greater flexibility by enabling the use of a lower die having a size smaller than that of the upper die, such that the side surfaces of the upper die overlap the side surfaces of the lower die. The upper die can be bonded to the lower die by employing a conventional dielectric adhesive, such as a non-conductive epoxy, such as QMI 536 obtainable from Quantum Materials, Inc. located in San Diego, California.
Embodiments of the present invention comprise positioning the flip-chip lower die having terminations on the lower surface thereof in the form of solder pads or bump contacts on the upper surface of the package substrate. Solder reflowing is then implemented to bond and electrically connect the flip-chip lower die to the circuitized package substrate. The dielectric bonding material is then applied to the upper surface of the flip-chip lower die and the upper wire bonding die mounted on the upper surface of the lower die. The upper die contains a plurality of bond pads on its upper surface. Wire bonding is then conducted to electrically connect bond wires to the bond pads on the upper surface of the upper die. Subsequent methodology is conducted in accordance with conventional practices and includes, inter alia, encapsulating the stacked dies with a molding resin. It should be understood that except as set forth herein, the materials and bonding techniques employed in the various embodiments of the present invention are conventional and, hence, not set forth here and in detail in order not to obscure the present invention. For example, suitable conventional package circuitized substrates for use in embodiments of the present invention typically comprise plated via holes therethrough and solder balls on the underside for bonding to a conventional PCB.
An embodiment of the present invention is schematically illustrated in Fig. 1 and comprises circuitized package substrate 10 having mounted thereon flip-chip lower die 11 by means of reflow solder balls 12. Upper die 14 is bonded to lower flip-chip die 12 by means of dielectric adhesive 13. Upper die 14 contains a plurality of bond pad 16 on its upper surface which are electrically connected to conductors (not shown) of the circuitized package substrate 10 means of bond wires 15 wire bonded thereto. The stacked dies are encapsulated by resin 17. Solder balls 18 are provided on the lower surface of substrate 10 for mounting to a PCB.
The present invention advantageously enables the manufacture of stacked die configurations, wherein the lower die is substantially the same size as or even smaller than the upper die in a cost effective, efficient manner. The present invention is applicable to any of various types of integrated circuit packages. The present invention is applicable to both high and low density integrated circuit packaging comprising multi-chip modules.
Only the preferred embodiment of the present invention and an example of its versatility are shown and described in the present disclosure. It is to be understood that the present invention is capable of use in various other combinations and environments, and is capable of changes or modifications within the scope of the inventive concept as expressed herein.

Claims

What is Claimed Is:
1. A circuit assembly comprising: a package substrate having a main surface; a flip-chip first die having an upper surface, a lower surface and side surfaces, the lower surface of the first die positioned on and electrically connected to the main surface of the substrate with reflowed solder balls; and a second die, having an upper surface, a lower surface and side surfaces, the second die positioned with its lower surface on the first die and electrically connected to the main surface of the substrate by bond wires wire bonded to bond pads on the upper surface of the second die.
2. The circuit assembly according to claim 1, further comprising a dielectric bonding material between the upper surface of the first die and lower surface of the second die.
3. The circuit assembly according to claim 2, wherein the bonding material comprises a non-conductive epoxy.
4. The circuit assembly according to claim 2, wherein the first and second dies are substantially the same size such that the side surfaces of the first and second dies are substantially coextensive with no substantial overlap therebetween.
5. The circuit assembly according to claim 2, wherein the first die is smaller than the second die such that the side surfaces of the second die overlap the side surfaces of the first die.
6. A semiconductor device comprising the circuit assembly according to claim 2 wherein the substrate is bonded to a printed circuit board.
7. A method of manufacturing a circuit assembly, the method comprising: providing a package substrate having a main surface; positioning a flip-chip first die, having an upper surface, a lower surface with solder balls thereon and side surfaces, such that the solder balls are on the main surface of the substrate; heating to bond and electrically connect the first die to conductors on the main surface of the substrate by reflowing the solder balls; positioning a second die, having an upper surface containing bond pads, a lower surface and side surfaces such that the lower surface of the second die is on the upper surface the first die; and electrically connecting the second die to the substrate by wire bonding bond wires to the bond pads, the bond wires being electrically connected to conductors on the main surface of the substrate.
8. The method according to claim 7, further comprising bonding the second die to the first die with a dielectric bonding material.
9. The method according to claim 8, wherein the bonding material comprises a non-conductive epoxy.
10. The method according to claim 8 wherein the first and second dies are substantially the same size such that the side surfaces of the first and second dies are substantially coextensive with no substantial overlap therebetween.
11. The method according to claim 8, wherein the first die is smaller than the second die such that the side surfaces of the second die overlap the side surfaces of the first die.
12. The method according to claim 11, further comprising bonding and electrically connecting the substrate to a printed circuit board.
PCT/US2001/018223 2000-06-29 2001-06-05 Semiconductor package with stacked flip chip and wire bonded upper die WO2002003465A2 (en)

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US21477100P 2000-06-29 2000-06-29
US60/214,771 2000-06-29
US62158000A 2000-07-21 2000-07-21
US09/621,580 2000-07-21

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0915505A1 (en) * 1997-11-06 1999-05-12 Sharp Kabushiki Kaisha Semiconductor device package, manufacturing method thereof and circuit board therefor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0915505A1 (en) * 1997-11-06 1999-05-12 Sharp Kabushiki Kaisha Semiconductor device package, manufacturing method thereof and circuit board therefor

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WO2002003465A3 (en) 2003-02-27
AU2001275268A1 (en) 2002-01-14
TW503555B (en) 2002-09-21

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