WO2001090828A2

WO2001090828A2 - Ac power line signalling system

Info

Publication number: WO2001090828A2
Application number: PCT/CA2001/000671
Authority: WO
Inventors: Alexei Bogdan; Marc Oliver Hoffknecht
Original assignee: Lumion Corporation
Priority date: 2000-05-09
Filing date: 2001-05-08
Publication date: 2001-11-29
Also published as: AU2001258119A1; WO2001090828A3

Abstract

A transmitter produces a control signal which preferably has no DC component (i.e. its average magnitude is 0). The control signal is synchronized with an AC power signal on the AC power line and is embedded into it by summation to produce a modified AC power signal. A transmitter with an active load dropping circuit to provide a precisely shaped control signal is provided and a wave form with a small magnitude during the highest power portion of the AC power signal is provided, reducing the power consumption of the signalling system. A receiver calculates the area under each positive half wave of the modified power signal and compares it to a threshold to distinguish between '0' and '1' bits. In another embodiment, the receiver incorporates an asymmetric low pass filter. The filtered signal is attenuated (at a selected magnitude) when a '1' (or '0') bit is received. The receiver detects the attenuation by measuring the time for which the filtered signal exceeds the selected magnitude.

Description

Title: AC Power Line Signalling System

FIELD OF THE INVENTION

[01] This invention relates to signalling systems used to control devices powered by alternating current power supplies. More particularly, this invention relates to a signalling system which may be used to transmit a digital signal to a receiver which controls the power supply to a device connected to an AC power line.

BACKGROUND OF THE INVENTION

[02] Many modern commercial and industrial establishments have complex and varied lighting, climate control (or heating, ventilation and air conditioning systems ("HVAC"), security and other needs. For example, a large office tower may have dozens of tenants, each with different requirements with respect to the times at which different services are to be switched into different configurations. A particular tenant may require that, during office hours, all lights be on, the HVAC system be set for full ventilation and air conditioning to 22° C and security system be disarmed. The same tenant may require that during evening periods, only hallway lighting be on, the HVAC system be set for 25% ventilation and the air conditioning to 26° C and that the security system be armed to allow any employee to enter with a pass card. During night time, on weekends and during statutory holidays, the tenant may require that only minimal lighting required for safety be on, the HVAC system be off and the security system permit only specified persons to enter with a pass card. In addition, the tenant may require that a manual override must be available to change any of these settings at any time.

[03] One can easily imagine the multitude of different combinations and variations of services which different tenants may require in a large building. It is impractical to employ individuals to change the settings for each service every time a new configuration is required. [04] A number of signalling systems have been developed to allow the configuration of such services to be controlled from a single control panel or control system.

[05] Some of these systems require that each device to be controlled must be physically wired to the control system using control or signal wires. For example, one system developed by Tridontic Corporation uses signal wires to transmit digital information representing a desired brightness level between a control panel and a ballast which controls the power delivered to a lamp. The use of signal wires to connect control panels such as light switches and loads such as lamps is expensive, since these wires are in addition to the power lines which are required in any case. Furthermore, such a system is difficult to install in existing locations since the signal wires must be installed within walls and ceilings which may be difficult to access. [06] Prior art signalling system which can transmit a control signal over AC power lines are also known. However, these system typically require access to both the hot and neutral power lines. Such access is not available in many electrical power systems.

[07] Prior art signalling systems which transmit data over AC power lines using a high frequency control signal are also known. These systems transmit their high frequency control signal by adding it to the AC power signal with the result that the high frequency control signal propagates towards both the load and supply sides of the circuit (relative to the transmitter). High power filters are required to remove the high frequency control signal from the supply side of the circuit, or alternatively, only a single high frequency data signal may be transmitted in all circuits that are coupled together. [08] Accordingly, there is a need for a signalling system which can transmit a control signal across an AC power transmission line to a receiver coupled to a load without the use of signal or control wires. It is desirable that the system be adaptable for use with power systems where the transmitter can access both hot and neutral wires and power systems in which only the hot wire may be accessed. In addition, there is a need for a signalling system with a high frequency control signal that propagates only to the load side of a signal transmitter. SUMMARY OF THE INVENTION

[09] The present invention provides a signalling system for controlling loads on an AC power line. A transmitter receives an AC power signal and modifies it by adding a control signal. The modified power signal is received by one or more receivers connected on the power line. Each of the receivers decodes the control signal from the modified power signal and provides a digital bit stream corresponding to the control signal to a signal processing block, which in turn controls the operation of a device or system connected to it. [10] The control signal affects positive and negative half waves of the AC power signal equally to reduce the DC component added into the modified power signal as a result of the super-addition of the control signal. The AC power signal is left unaffected to indicate a 'low' or logical '0' data bit. The AC power signal is attenuated in a controlled manner to indicate a 'high' or logical data bit. [11] In one embodiment of a transmitter according to the present invention, the control signal is essentially a square wave signal which attenuates the amplitude of the AC power signal. Each cycle of the modified power signal is used to encode one data bit.

[12] In another embodiment of a transmitter according to the present invention, an active wave shaping circuit is used in the transmitter, allowing a control signal of almost any shape to be generated. This transmitter may be used to generate high frequency signals as part of the control signal. Such high frequency frequency signals may be easier to detect reliably and may be used to encode a high frequency data stream. [13] Another embodiment of a transmitter may be coupled in a one signal mode, in which it can be used to provide a precisely balanced control signal on an AC power line or a two signal mode in which it can provide two independent and generally balanced control signals to two independent devices on two AC power lines. This embodiment includes a pair of control signal generation sub-stages, which may be coupled in series in the one signal mode. The two control signal generation sub- stages are controlled by a single control signal control block in the one signal mode and may be controlled by a single control signal control block in the two signal mode. [14] In one embodiment of a receiver according to the present invention, the receiver determines whether a particular cycle of the modified power signal encodes a '0' or '1 ' bit by calculating the area of the positive half wave of the cycle.

[15] In a second embodiment of a receiver according to the present invention, the receiver includes an asymmetric filter which affects the positive and negative half waves of the modified power signal differentially. This filtered signal is recitified, providing a rectified signal with a series of pulses corresponding to the positive half waves of the modified power signal.

[16] When a '1' bit is encoded into a cycle of the modified power signal, the corresponding pulse of the rectified signal exhibits a time shift in its rising and falling portions. Due to the asymmetric filter, the rising edge of the pulse exhibits a lagging time shift but the falling edge exhibits a leading time shift. The magnitude of the rectified signal is compared to a reference threshold to determine whether the time shift exists in the reference signal, and accordingly, if the cycle was encoded as a '1' bit. If not, then it is known to be have encoded a '0' bit.

[17] In a third embodiment of a receiver according to the present invention, the second embodiment is modified by comparing the falling edge of the rectified signal to a second voltage threshold, which is selected to be at a voltage that is not affected regardless of whether a '0' or '1' bit was transmitted. The time at which the rising and falling edges cross the first threshold is compared to the time at which the falling edge crosses the second threshold, thereby identifying separately whether the rising edge has been time shifted and whether the falling edge has been time shifted. This allows two data bits to be transmitted per cycle of the modified power signal, be selecting an appropriate control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[18] The present invention will now be explained, by way of example only, with reference to the drawings, in which: Figure 1 is a block diagram of a circuit configured with a first embodiment of a signalling system according to the present invention;

Figure 2 is a block diagram of a transmitter of the signalling system of Figure 1 ; Figure 3 is a schematic diagram of a DC power supply circuit of the transmitter of Figure 2;

Figure 4 is a schematic diagram of a control signal control block of the transmitter of Figure 2;

Figure 5a illustrates an AC power signal produced by an AC power source of the circuit of Figure 1 ;

Figure 5b illustrates a synchronization signal produced in the control signal control block of Figure 4;

Figure 6a illustrates an input signal produced by a first switch of the control signal control block of Figure 4; Figure 6b illustrates a data signal produced by the control signal control block of Figure 4 in response to the input signal of Figure 6a;

Figure 7a illustrates an input signal produced by a second switch of the control signal control block of Figure 4;

Figure 7b illustrates a data signal produced by the control signal control block of Figure 4 in response to the input signal of Figure 7a;

Figure 8a illustrates an input signal produced by a third switch of the control signal control block of Figure 4;

Figure 8b illustrates a data signal produced by the control signal control block of Figure 4 in response to the input signal of Figure 8a; Figure 9 is a schematic diagram of a control signal generation block of the transmitter of Figure 2;

Figure 10a illustrates the AC power signal of Figure 5;

Figure 10b illustrates the data signal of Figure 6b;

Figure 10c illustrates a control signal produced in the control signal generation block of Figure 9 in response to the data signal of Figure 10b; Figure 10d illustrates a modified power signal produced by the control signal generation block of Figure 9 in response to the data signal of Figure 10b;

Figure 11 is a schematic diagram of a second control signal generation block which may be used with the transmitter of Figure 2; Figure 12 is a schematic diagram of a second control signal control block and a third control signal generation block which may be used with the transmitter of Figure 2;

Figure 13a illustrates a pulse width modulated signal generated by the control signal control block of Figure 12; Figure 13b illustrates a control signal produced in the control signal generation block of Figure 12 in response to the pulse width modulated signal of Figure 13a;

Figure 13c illustrates a modified power signal produced by the control signal generation block of Figure 12 in response to the pulse width modulated signal of Figure 13a;

Figure 14 illustrates the modified power signal of Figure 13c in greater detail;

Figure 15a illustrates the AC power signal of Figure 5;

Figure 15b illustrates another control signal; Figure 15c illustrates a modified power signal which may be produced in response to the control signal of Figure 15b;

Figure 16 is a block diagram of a receiver of the signalling system of Figure 1 ;

Figure 17 is a schematic diagram of a control signal detection block of the receiver of Figure 16;

Figure 18a illustrates the modified power signal of Figure 10d;

Figure 18b illustrates a filtered signal produced in the control signal detection block of Figure 17 in response to the modified power signal of Figure 18a;

Figure 18c illustrates a data stream produced by the control signal detection block of Figure 17 in response to the modified power signal of Figure 18a; Figure 19 is a schematic diagram of a control signal conversion block of Figure 16;

Figure 20 is a block diagram of a second receiver which may be used with the transmitter of Figure 2; Figure 21 is a schematic diagram of a control signal detection block of the receiver of Figure 20;

Figure 22a illustrates an AC power signal produced by the AC power source of Figure 1 ;

Figure 22b illustrates a data signal produced by the transmitter of Figure 2;

Figure 22c illustrates a control signal which may be used with the receiver of Figure 20;

Figure 22d illustrates a modified power signal which may be generated by the control signal generation block of Figure 12 if the control signal of Figure 22c is used;

Figure 22e illustrates a filtered signal generated in the receiver of Figure 20;

Figure 22f illustrates a rectified signal generated in the receiver of Figure 20; Figure 23 illustrates the rectified signal of Figure 22f in greater detail;

Figure 24 is a schematic diagram of a second control signal detection block which may be used with the receiver of Figure 20;

Figure 25a illustrates an AC power signal produced by the AC power source of Figure 1 ; Figure 25b illustrates a data signal produced by a transmitter which may be used with the control signal detection block of Figure 24;

Figure 25c illustrates a control signal which may be used with the control signal detection block of Figure 24;

Figure 25d illustrates a modified power signal which may be used with the control signal detection block of Figure 24; Figure 25e illustrates a filtered signal generated in control signal detection block of Figure 24;

Figure 25f illustrates a rectified signal generated in the control signal detection block of Figure 24; Figure 26 illustrates the rectified signal of Figure 25f in greater detail;

Figure 27 is a block diagram of a second circuit configured with a second signalling system according to the present invention;

Figure 28 is a block diagram of a transmitter of the signalling system of Figure 27; Figure 29 is a schematic diagram of a transmitter of the signalling system of Figure 27;

Figure 30a illustrates an AC power signal produced by an AC power source of the circuit of Figure 29

Figure 30b illustrates a synchronization signal produced in a control signal control block of the transmitter of Figure 29;

Figure 30c illustrates an input signal received on a switch coupled to the control signal control block of the transmitter of Figure 29;

Figure 30d illustrates a data on signal produced by the control signal control block of the transmitter of Figure 29; Figure 30e illustrates a data off signal produced by the control signal control block of the transmitter of Figure 29;

Figure 30f illustrates a control signal produced by a control signal generation block of the transmitter of Figure 29;

Figure 30g illustrates a modified power signal produced by the transmitter of Figure 29;

Figure 30h illustrates a maximum load current which may flow through the transmitter of Figure 29;

Figure 30i illustrates a power supply control signal produced in the transmitter of Figure 29; Figure 30j illustrates a status of the transmitter of Figure 29;

Figure 31a illustrates an AC power signal; Figure 31b illustrates a control signal having a constant high frequency component;

Figure 31c illustrates a modified power signal produced in response to the control signal of Figure 31b; Figure 32a illustrates an AC power signal;

Figure 32b illustrates a control signal having a frequency modulated high frequency component;

Figure 32c illustrates a modified power signal produced in response to the control signal of Figure 32b; Figure 33 is a schematic diagram of a third control signal control block and a fourth control signal generation block which may be used with the transmitter of Figure 2, coupled in a one-signal mode;

Figure 34a illustrates a pulse width modulated signal generated by the control signal control block of Figure 12; Figure 34b illustrates a control signal produced in the control signal generation block of Figure 12 in response to the pulse width modulated signal of Figure 13a;

Figure 34c illustrates a modified power signal produced by the control signal generation block of Figure 12 in response to the pulse width modulated signal of Figure 13a; and

Figure 35 shows the control signal control block and control signal generation block of Figure 33 coupled in a two signal mode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT [19] Reference is first made to Figure 1 , which shows an electrical circuit 20 configured with a signalling system 22 according to the present invention. Signalling system 22 includes a signal transmitter 24 and one or more receivers, including receiver 40. Transmitter 24 receives an AC power signal 28 from AC power source 26 at terminals AC1 and AC2. Transmitter 24 provides a modified AC power signal 30 at terminals AC3 and AC4. Modified power signal 30 includes a control signal 32, which is generated by transmitter 24.

[20] Circuit 20 includes three load blocks 34, 36, 38.

[21] Load block 34 includes receiver 40, a power supply 42 and a load 44. Receiver 40, which is also part of signalling system 22, receives modified power signal 30 and controls power supply 42 by means of control lines 46, 48. Power supply 42 provides power to the load 44. Load block 34 is representative of a load which requires a regulated variable power supply to control its operations. For example, load 44 may be a gas discharge lamp such as a fluorescent tube. Power supply 42 may be an electronic ballast which is responsive to a well-known "0 to 10V" signalling protocol to control the intensity of light output from the gas discharge lamp. In this case, receiver 40 would be configured to translate control signal 32 into a 0 to 10 V protocol control signal for use by the ballast to control the intensity of the lamp. [22] Load block 36 includes a load 54 with an integrated receiver 52. Receiver 52 receives modified power signal 30 and controls the operation of load 54 in response to control signal 32. Load block 36 is representative of a load which may be configured to operate in different states at different times. For example, load 54 may be a HVAC system. Receiver 52 may turn various portions of the HVAC system on or off or change the temperature setting for heating or air conditioning in response to control signal 32.

[23] Load block 38 includes a load 56 which is not controlled by a receiver.

Load 56 may be an emergency lighting system or other device which must be powered at all times and which does not require periodic adjustment. [24] Transmitter 24 may be mounted within a conventional wall switch box (not shown) and may be used to operate one or more devices in response to a switch or switches (for example, switches SW1 , SW2 and SW3 in Figure 4) mounted on transmitter 24. For example, if transmitter 24 is simply used to control the intensity of a lamp (load 44) using the 0 to 10 V protocol, then transmitter 24 may have an "on/off' switch, a "dim up" switch and "dim down" switch. In response to a user pressing one of the switches, transmitter 24 may generate modified power signal 30 including a pre-determined control signal 32. Receiver 40 will receive the control signal 32 and modify the 0 to 10 V protocol signal to power supply 42 (an electronic ballast which is responsive to the 0 to 10 V protocol), which will turn load 44 (the gas discharge lamp) on or off or modify the intensity of lamp 44 accordingly. Alternatively, transmitter 24 may be part of a complex computer system (not shown) configured to control many devices and systems on circuit 20 simultaneously. The computer system may control transmitter 24 to generate control signals required to control the various devices and systems.

[25] For simplicity, an example of the invention will now be described in the context of a simple wall mounted transmitter which is used to control a single gas discharge lamp, according to the structure of load block 34 described above.

[26] Reference is next made to Figure 2, which shows a block diagram of transmitter 24. Transmitter 24 has a DC power supply block 80, a control signal control block 82 and a control signal generation block 84. [27] DC power supply block 80 is coupled to terminal AC1 and AC2 and receives AC power signal 28 from AC power source 26. DC power supply block 80 produces a regulated DC power supply VDD at terminal DC1 in known manner. DC power supply block 80 may be any AC to DC power conversion circuit. [28] For example, one circuit which may be used for DC power supply block

80 is shown in Figure 3. This exemplary DC power supply block 80 has a linear regulator IC1. In this embodiment of the invention, IC1 is a high voltage linear regulator power IC, model number VB408, manufactured by ST Microelectronics, although any such device may be used. A data sheet for the VB408 linear regulator power IC is available from ST Microelectronics' Internet web site at www.st.com. IC1 has a voltage input terminal Vin, a voltage output terminal Vout and an output voltage adjustment terminal ADJ. Diode D1 and capacitor C1 are coupled in series between terminals AC2 and AC1 , which is coupled to ground. Diode D1 rectifies power signal 28 and provides a positively rectified power signal Vrect at voltage input terminal Vin. Capacitor C1 is chosen to ensure that Vrect is positive at all times. The ADJ terminal is coupled between resistors R1 and R2, which operate as a voltage divider between output terminal Vout and ground. Output terminal Vout is coupled to DC output voltage terminal DC1. Capacitor C2 is used to reduce ringing in the regulated DC power supply VDD at terminal DC1. A person skilled in the art will be able to show that regulated DC power supply VDD may be calculated as follows:

VDD = VR1 (1+R2/R1) + IADJ * R2,

where: VR1 is the voltage drop across resistor R1 ; and

IADJ is the current drawn from adjustment terminal ADJ.

and where the voltage at input terminal Vin is at least 30 volts greater than the desired output voltage VDD.

[29] Power supply VDD is used to power control signal control block 82. In the present embodiment of transmitter 24, control signal control block 82 (Figure 2) requires a DC power supply of 5 volts. It has been found that the use of the following components in DC power supply block 80 provides a DC supply voltage VDD of 5 V at terminal DC1 :

Reference Numb er Component or Value

IC1 VB408

D1 1 N4007

C1 2.2 μF

C2 220 nF

R1 1 kΩ

R2 3 kΩ

[30] Reference is next made to Figure 4, which illustrates control signal control block 82. Control signal control block 82 includes a microcontroller 90, resistor R3, zener diode D2, switches SW1 , SW2, SW3 and a signal control terminal 92.

[31] Resistor R3 and zener diode D2 are connected between terminal AC1 and ground. Node 94, which is at the cathode of zener diode D2 provides a zero- crossing synchronization signal 96 for microcontroller 90 at input terminal IN4. Figure 5a shows AC power signal 28 at terminal AC1. Figure 5b shows the synchronization signal 96. Resistor R3 has a value of 100 kΩ and zener diode D2 has a breakdown voltage of 4.7 volts. Synchronization signal 96 is approximately a square wave signal with a high level of 4.7 volts and a low level of 0 volts (neglecting the voltage drop across diode D2 during negative half waves of power signal 28). The high parts of the synchronization signal 96 correspond to the positive half waves of power signal 28. Microcontroller 90 uses synchronization signal 96 to ensure that control signal 32 is synchronized with power signal 28. This is discussed in further detail below. [32] Microcontroller 90 also receives input signals from switches SW1 , SW2 and SW3 (Figure 4) at input terminal IN1 , IN2 and IN3, respectively. As noted above, the present embodiment of signalling system 22 is designed to provide a 0 to 10 V protocol control signal for a gas discharge lamp (load 44 in Figure 1). Switch SW1 provides an "on/off' input, switch SW2 provides a "dim up" input and switch SW3 provides a "dim down" input to control the operation of the lamp. Switches SW1 , SW2 and SW3 are normally open switches connected between ground and an input terminal of microcontroller 90. When they are closed, they provide a momentary "low" input signal to microcontroller 90.

[33] Microcontroller 90 may be any conventional microcontroller and may be provided with internal or external memory. In the preferred embodiment of signalling system 22, a model 87LPC764 microcontroller manufactured by Philips

Semiconductor has been used. A person skilled in the art will be capable of programming such a microcontroller to provide the functionality described below. Microcontroller 90 receives power from terminal DC1 , at which DC power supply block 80 produces DC supply voltage VDD. [34] Microcontroller 90 has been programmed to provide a 3-bit code word on a data signal 98 at signal control terminal 92 in response to inputs received on switches SW1 , SW2 and SW3, as indicated in the following chart:

Switch Data word SW1 101

SW2 1 10 SW3 1 11

[35] For the purpose of this relatively simple and exemplary embodiment, a coding system which utilizes only three bits is sufficient. The first bit of each code word is a "start" bit which signifies to the receiver that a code word is being transmitted. The last two bits represent the switch from which an input signal was received. Each code word on data signal 98 may have any number of bits, and may include error detection and error correction bits, as is well known in the art. A person skilled in the art will be capable of designing a set of code words which is appropriate to the specific system in which another embodiment of a signalling system according to the present invention is used.

[36] When microcontroller 90 receives an input from any of switches SW1 ,

SW2 or SW3, it generates the appropriate code word on data signal 98 at terminal 92 beginning at the start of the next high pulse of synchronization signal 96. Data signal 98 has the same frequency as power signal 28. Figures 6a and 6b show data signal 98 (Figure 6b) when switch SW1 is momentarily closed by a user at time t1 (Figure 6a). Microcontroller 90 receives a low input signal at terminal IN1. At the beginning of the next high pulse of synchronization signal 96, microcontroller 90 starts to send a code word consisting of bits 101 on data signal 98. Each bit commences at the start of consecutive high pulses of synchronization signal 96 with the result that data signal 98 has a frequency identical to power signal 28.

[37] Figures 7a and 7b similarly show data signal 98 (Figure 7b) when an input signal is received at terminal IN2 from switch SW2 (Figure 7a). Figures 8a and 8b show data signal 98 (Figure 8b) when an input signal is received at terminal IN2 from switch SW2 (Figure 8a).

[38] Reference is next made to Figure 9 which shows a first embodiment of a control signal generation block 84. Control signal generation block 84 includes four diodes D3, D4, D5 and D6 and a switch SW4. Diodes D3 and D4 are connected in series between terminals AC1 and AC3 such that they may conduct during positive half waves of power signal 28. Diodes D5 and D6 are connected in series between terminals AC1 and AC3 such that they may conduct during negative half waves of power signal 28. Switch SW4 is connected between terminals AC1 and AC3. Switch SW4 is operated by data signal 98 such that switch SW4 is closed when data signal 98 is low and switch SW4 is open when data signal 98 is high. [39] The operation of control signal generation block 84 will be explained with reference to Figures 10a - 10d, which share a common time scale, but which are out of scale with respect to the magnitude of the signals shown. Figure 10a shows AC power signal 28 and is identical to Figure 5a. Figure 10b shows data signal 98 after microcontroller 90 (Figure 4) has received an input from switch SW1 (Figure 4) and is the same as Figure 6b. Figure 10c shows control signal 32, which is generated by control signal generation block 84 as described below. Modified power signal 30, which is a summation of power signal 28 and control signal 32 is shown in Figure 10d.

[40] When switch SW4 is closed (i.e. data signal 98 is low), both the positive and negative half waves of power signal 28 are conducted through switch SW4 (which has a negligible voltage loss) with the result that control signal 32 has a magnitude of 0 volts. Modified power signal 30, which appears on terminal AC3, is identical to power signal 28.

[41] When SW4 is open (i.e. data signal 98 is high), positive half waves of signal 28 are conducted through series connected diodes D3 and D4 and negative half waves of signal 28 are conducted through series connected diodes D5 and D6. As is well known, each diode will cause a voltage drop, with the result that modified power signal 30 has a smaller magnitude than power signal 28 when switch SW4 is open. In this embodiment of control signal generation block 84, diodes D3 - D6 are model number 10ETS08 diodes, manufactured by International Rectifier. Each of these diodes produces a voltage drop of approximately 0.7 volts. Accordingly, when SW4 is open, control signal 32 (Figure 10c) is generated by diodes D3-D6. During this period, control signal 32 has a magnitude of 1.4 volts and is 180° out of phase with power signal 28. Control signal 32 is essentially a square wave. The rising and falling edges of control signal 32 will have the same magnitude as power signal 28 during the brief period (about 60 microseconds) at the beginning of each half wave of power signal 28 when power signal 28 has a magnitude of less than 1.4 volts. When switch SW4 is open, the magnitude of modified power signal 30 is 0 volts while the magnitude of power signal 28 is less than 1.4 volts and is 1.4 volts less than the magnitude of power signal 28 at other times.

[42] Modified power signal 30 exhibits only a small power loss compared to AC power signal 28, and then only during the transmission of a '1' bit. At most times, no data will be transmitted by transmitter 24 and modified power signal 30 will be identical to AC power signal 28 (Figure 10a). The small difference between modified power signal 30 and AC power signal 28 will be transparent to almost all loads on circuit 20. [43] Since control signal 32 is equal to 0 volts when SW4 is closed and is balanced about 0 volts when SW4 is open, modified power signal 30 is also balanced about 0 volts at all times (assuming that power signal 28 is itself balanced about 0 volts). As a result, modified power signal 30 has no DC component and avoids the inefficiencies of prior art systems which generate a control signal that is not balanced about 0 volts.

[44] Reference is next made to Figure 11 , which shows a second embodiment of a control signal generation block 84b. Control signal generation block 84b has diodes D3 and D4, which operate in the same manner as in control signal generation block 84. However, diodes D5 and D6 and switch SW4 of control signal generation block 84 have been replaced with a MOSFET type transistor Q1 and an inverter 93 in control signal generation block 84b. The drain of transistor Q1 is coupled to terminal AC1 and the source of transistor Q1 is coupled to terminal AC3. The gate of transistor Q1 is coupled to terminal 92 through inverter 93. The operation of control signal generation block 84b is similar to the operation of control signal generation block 84. When data signal 98 (on terminal 92) is low, the gate input of transistor Q1 is high due to inverter 93. Transistor Q1 conducts and acts as a closed switch between terminal AC1 and AC3. When signal 98 is high, the gate input of transistor Q1 is low and transistor Q3 is off and acts as an open switch with respect to positive half wave of power signal 28. During negative half waves of power signal 28, the internal reverse diode of transistor Q1 produces a voltage drop. In the preferred embodiment of control signal generation block 84b, transistor Q1 is a model number IRLIZ44N transistor produced by International Rectifier. The internal reverse diode of this transistor produces a voltage drop of approximately 1 volt. As noted earlier, diodes D3 and D4 together produce a voltage drop of about 1.4 volts. The imbalance introduced into the modified power signal 30 (which is the sum of AC power signal 28 and control signal 32) as a result of this imbalance is very small. Assuming that AC power signal 28 has a magnitude of 120 volts, then positive half wave of modified power signal 30 will have a magnitude of approximately 118.6 volts (120 volts - 1.4 volts dropped by diodes D3 and D4) and negative half waves of modified power signal 30 will have a magnitude of approximately 119 volts (120 volts - 1 volt dropped across the internal reverse diode of transistor Q1). The percentage difference between the magnitude of the two half waves is only about 0.34% (( 19-118.6)/119). Accordingly, the control signal 32 and modified power signal 30 produced by control signal generation block 84b are essentially the same as those produced by control signal generation block 84, as shown in Figures 10c and 10d. Control signal generation block 84b therefore provides the benefit of an essentially balanced modified power signal 30 at terminal AC3 and AC4. The small imbalance of 0.34% is negligible and provides a good compromise between the desire to reduce the DC component added to modified power signal 30 and the need to provide a transmitter at a commercially feasible cost. [45] Control signal generation blocks 84 and 84b produce an essentially square wave control signal 32, as described above. It has been found that harmonic frequencies produced and RFI emitted in generating control signal 32 are negligible since all the rising and falling transitions of the control signal occur when current flowing in circuit 20 is almost zero (since the transitions occur at zero-crossings of AC power signal 28).

[46] Reference is next made to Figure 12 which shows a second control signal control block 82b and a third control signal generation block 84c. Control signal control block 82b is identical to control signal block 82 except that microcontroller 90' is programmed to provide a pulse width modulated (PWM) signal 102 at output terminal 100 in addition to data signal 98. [47] Data signal 98 generated by control signal control block 82b is identical to data signal 98 generated by control signal control block 82 and is shown in Figure 10b. Figure 13a shows PWM signal 102. PWM signal 102 has a magnitude of 0 volts when (i) data signal 98 is 0 (i.e. no control signal is being sent or a '0' bit is being sent); or (ii) during the negative half wave of power signal 28 when a '1' bit is being sent. PWM signal 102 is used to control the shape of a control signal 32' generated by control signal generation block 84c.

[48] In control signal generation block 84c, transistor Q2 operates in the same way as transistor Q1 operates in control signal generation block 84b. Transistor Q2 conducts both positive and negative half waves of power signal 28 when data signal 98 is low. When data signal 98 is high, the internal reverse diode of transistor Q2 provide a voltage drop during the negative half wave of power signal 28. Diodes D3 and D4 have been replaced with an active voltage dropping circuit comprising resistors R4, R5, R6, capacitor C3, operational amplifier 104 and power transistors Q3 and Q4. Resistor R4 is coupled to terminal 100 to receive PWM signal 102. Resistor R4 and capacitor C3 are connected as a low pass filter which provides a smoothed signal 106 corresponding to PWM signal 102 at the non-inverting input of op-amp 104. Amplifier 104 and resistors R5 and R6 are configured as an inverting amplifier with a "virtual" ground at its negative input. The emitter of pnp power transistor Q3 is coupled to terminal AC1. The base of transistor Q3 is coupled to the output of amplifier 104. The collector of transistor Q3 is coupled to the base of transistor Q4. The collector of transistor Q4 is coupled to terminal AC1 and the emitter of transistor Q4 is coupled to terminal AC3. [49] During positive half waves of power signal 28 when a '1' bit is to be sent, resistor R4 and capacitor C3 filter higher order frequency components from PWM signal 102 to produce smoothed signal 106 corresponding to PWM signal 102 at the inverting input of amplifier 104. Amplifier 104 inverts and amplifies the difference between power signal 28 at terminal AC1 and the smoothed signal 106 and produces a corresponding amplified signal 108 at the base of transistor Q3. Transistor Q3 converts this amplified signal 108 (which is essentially a voltage signal) into a current signal 110 at the base of transistor Q4, which operates in its active region to produce a voltage drop Vdrop across its collector and emitter. Voltage drop Vdrop corresponds to smoothed signal 106. Control signal 32' is defined by the summation of voltage drop Vdrop and the voltage dropped across the internal reverse diode of transistor Q2. Control signal 32' is shown in Figure 13b. Modified power signal 30' is the sum of control signal 32' and power signal 28 and is shown in Figure 13c. [50] Reference is next made to Figure 14, which shows one wavelength of modified power signal 30' during the transmission of a '1' bit, corresponding to time period t2 in Figure 13c. Modified power signal 30' is shown in solid outline. Power signal 30, during the same time period, is shown in dotted outline. The positive half wave of modified power signal 30' is shaped to be relatively smooth, in contrast to the negative half wave of power signal 30'. This is accomplished by selecting PWM signal 102 such that smoothed signal 106 has no sharp transitions and by selecting the amplification factors of amplifier 104 and transistor Q3 such voltage drop Vdrop also has no sharp transitions, including at its leading and trailing edges. [51] PWM signal 102 is selected such that the average voltage of the positive half wave of modified power signal 30' is approximately equal to the average during the negative half wave of modified power signal 30'. This ensures that there is no DC component in modified power signal 30', even though the shapes of the positive and negative half waves are different. This may be done by ensuring that the area A under the positive half wave of the voltage curve of modified power signal 30' is approximately equal to the area B under the negative half wave of the voltage curve of modified power signal 30'. Microcontroller 90' (Figure 12) is programmed to generate PWM signal 102 to provide this result. [52] Control signal generation block 84c provides an important advantage over control signal generation block 84 (Figure 9) and 84b (Figure 11). Control signal generation block 84 relies on diodes D3-D6 to produce control signal 32. Control signal generation block 84b relies on diodes D3 and D4 to produce control signal 32. As the load on circuit 20 increases (i.e. the current drawn by loads 44, 54, 56 (Figure 1)), the power consumed in circuit 20 will increase (Power = voltage x current). Diodes D3-D6 are in series with these loads and therefore all current drawn by the loads 44, 54, 56 passes through diodes D3-D6, during the appropriate half wave of AC power signal 28. Since the voltage drop across a diode is somewhat dependent on the current flowing through it, the power consumed by the diodes will increase as the load current rises. It is preferable to limit this power loss by generating a control signal which is independent of the current flowing in circuit 20. Control signal generating block 84c provides this result. The voltage drop Vdrop produced by control signal generation block 84c may be precisely controlled by regulating PWM signal 102. Accordingly, it may be desirable to use control signal control block 82b and control signal generation block 84c even where a square wave control signal 32 is required in order to provide a more precise control signal 32' which is substantially independent of the load applied to circuit 20.

[53] One skilled in the art will recognize that control signal control block 82b and control signal generation block 84c may be used to produce many differently shaped waveforms in the positive half cycle of modified power signal 30' by appropriately selecting PWM signal 102. As long as area A of the modified power signal 30' is approximately equal to area B of the modified power signal 30', the advantage that no DC component is introduced into modified power signal 30' which is ultimately used to power various loads, such as loads 44, 54 and 56 (Figure 1) will be retained. [54] Control signal generating block 84c provides the advantage of reduced power losses and control over the shape of modified power signal 30' only during the positive half wave of AC power signal 28, since the internal reverse diode of transistor Q2 is still used to generate control signal 32' in the negative half wave. In another embodiment of a signalling system according to the present invention, both the positive and negative half cycles of modified power signal 30' may be shaped by adding a voltage dropping circuit between terminals AC3 and AC1 which operates when transistor Q3 is not conducting and power signal 28 is in its negative half cycle. By using two voltage dropping circuits in this manner, modified power signal 30' may be precisely shaped during both the positive and negative half waves, independently of the current flowing through the circuits, thereby providing the benefit of reduced power losses during the positive and negative half waves of AC power signal 28. A control signal generation block with active voltage dropping circuits for both halves of the control signal may also be used to achieve other objectives, such as reducing the generation of EMI or harmonics in the signalling system.

[55] For example, one possible control signal 32a which may be generated by a control signal generation block having two active voltage dropping circuits is shown in Figure 15b. Figure 15a shows two cycles of AC power signal 28. During the first cycle of AC power signal 28, control signal 32 has a zero magnitude. During the second cycle of AC power signal 28, control signal 32a is non-zero for part of each half wave of the cycle. During time periods t3 and t5, control signal 32a is a smoothed negative curve. During time period t4, control signal 32a has a zero magnitude. Modified power signal 30a, which is summation of AC power signal 28 and control signal 32a is shown in Figure 15c. During time periods t3 and t5, modified power signal 30a has a magnitude smaller than that of AC power signal 28 (shown in dotted outline in Figure 15c). However, during time period t4, modified power signal 30a has the same magnitude as AC power signal 28. The use of control signal 32a reduces the voltage drop on AC power signal 28 during time period t4, when AC power signal 28 is maximized. This reduces the power consumption of the transmitter. [56] A control signal generation block with two active voltage dropping circuit has the disadvantage that the additional circuitry increases the cost and complexity of the transmitter. Additional power electronic components are required to generate control signal 32a during the negative half wave. As a result, it is more cost effective and simpler to shape control signal 32 only during the positive half wave and to rely on the internal reverse diode of transistor Q1 during the negative half wave. Control signal generation block 84c, which has an active voltage dropping circuit for only the positive half wave of AC power signal 28 is considered a reasonable compromise between the desire to reduce power consumption in the transmitter and the desire to reduce the complexity and cost of the transmitter.

[57] Despite these disadvantages, a control signal generation block with two active voltage dropping circuits may be desirable in an environment where a precisely balanced control signal 32 is required. Figure 33 illustrates a third control signal control block 82c and a fourth control signal generation block 84d. [58] Control signal generation block 84d comprises two control signal generation sub-blocks 84e and 84f. Control signal generation sub-block 84e is identical to control signal generation block 84c (Figure 12). The collector of transistor Q4 is coupled to a terminal 402 and the source of transistor Q2 is coupled to a terminal 404.

[59] Control signal generation sub-block 84f is symmetrical to control signal generation sub-block 84e and the corresponding elements are indicated with similar reference numerals with a prime (') mark. The collector of transistor Q4' is coupled to a terminal 406. The drain of transistor Q2' is coupled to a terminal 406 and the source of transistor Q2' is coupled to a terminal 408.

[60] A switch SW8 is coupled between the sources of transistors Q2 and Q2'.

[61] Control signal control block 82c includes a microcontroller 90" which is similar to microcontroller 90'. In addition to PWM signal 102 and data signal 98 at terminals 100 and 92, respectively, control signal control block 82c also generates a second PWM signal 102' at a terminal 100' and a second data signal 98' at a terminal 92'. It may be preferably to isolate control signal generation sub-blocks 84e and 84f from each other, particularly where the two control signal generation sub-blocks 84e and 84f do not share a common reference point. Optical isolation blocks 414 and 416 are provided for this purpose. Optical isolation block 414 is coupled between terminal 100' and resistor R4'. Optical isolation block 416 is coupled between terminal 96' and diode 93'. Optical isolation blocks 84e and 84f allow PWM signal 102' and data signal 98' to be level shifted or otherwise adjusted. A person skilled in the art will be capable of adjusting signal 102' and 98' for use in controlling the operation of control signal generation sub-block 84f. [62] Control signal control block 82c and control signal generation block 84d may be configured to operate in two modes: a one control signal mode and a two- control signal mode. The one control signal mode is illustrated in Figure 33. In this mode, terminal 402 is coupled to terminal AC1 , terminal 406 is coupled to terminal AC3 and switch SW8 is closed. [63] Control signal control block 82c generates PWM signal 102 and data signal 98 in response to signals from switches SW1 , SW2 and SW3, as described above in relation to control signal control block 82b. Data signal 98 is high when a '1' bit in a control word is to be transmitted. PWM signal 102 controls the shape of the control signal 30' (Figure 13b) during positive half waves of power signal 28 when a '1' bit is transmitted. Control signal generation sub-block 84e operates in a manner analogous to control signal generation sub-block 84c.

[64] Reference is made to Figure 33 and Figures 34a - 34c. These Figures have a common time scale with Figures 10a - 10d and 13a - 13c. Control signal control block 82c generates PWM signal 102' and data signal 98' so that control signal generation sub-block 84f operates as follows. When no data word is being sent or when a '0' bit in a data word is being sent, data signal 98' is low and PWM Signal . When a '1' bit is transmitted, data signal 98' is high and, during negative half waves of power signal 28, PWM control signal 102' is non-zero. PWM control signal operates the active portion of control signal generation sub-block 84f so that a voltage drop Vdrop' is generated across the emitter and collector of transistor Q4' during negative half waves of power signal 28.

[65] Control signal generation sub-blocks 84e and 84f and coupled in series between terminals AC1 and AC3 and cooperate to provide a highly controllable control signal 32f (Figure 34b). Control 32f is generated as follows. When no data is to be transmitted, or when a '0' bit is to be transmitted, data signal 98 and 98' are low and transistors Q2 and Q2' conduct both the positive and negative half waves of power signal 28 between terminals AC1 and AC3. Control signal 32f thus has a magnitude of 0 volts. When a '1' bit is to be transmitted, data signals 98 and 98' are high and PWM signals 102 and 102' are non-zero during the positive and negative half-waves of power signal 28. During positive half waves of power signal 28, current flows from terminal AC1 , through transistor Q4, through transistor Q2' and to terminal AC3, as indicated by dashed line 410. Transistor Q4 has a voltage drop Vdrop (controlled by PWM signal 102) across it and the internal reverse diode of transistor Q2' creates an additional voltage drop between terminals AC1 and AC3. Control signal 32f is equal to the sum of these voltage drops during positive half waves of power signal 28. [66] During negative of power signal 28 when a '1' bit is transmitted, current flows from terminal AC3, through transistor Q4', through transistor Q2 to terminal AC1 , as indicated by dashed line 412. During these negative half waves, there is a voltage drop Vdrop' across transistor Q4' and a voltage drop due to the internal reverse diode of transistor Q4. Control signal 32f is equal to the sum of these voltage drops during positive negative waves of power signal 28. [67] A modified power signal 30f (Figure 34c) equal to the sum of power signal 28 and control signal 32f is produced at terminal AC3, which is coupled to a load (for example, load 44 in Figure 1).

[68] As illustrated in Figure 34b, control signal 32f may be precisely controlled during both the positive and negative half waves of power signal 28 by controlling PWM signals 102 and 102'. If control signal generation sub-blocks 84e and 84f are assembled from matched components and if PWM signals 102 and 102' are correlated with one another, it is possible to generate control signal 32f with an almost zero DC component. Such precision may be required in some circumstances, and the circuit of Figure 33 may be used. [69] However, in many cases such precision is not required and the degree of balancing provided by control signal control block 82b and control signal generation block 84c (Figure 12) is sufficient. In their two signal mode, control signal control block 82c and control signal generation block 84d may be used to produce two such signals. This is illustrated in Figure 35. In the two signal mode, switch SW8 is opened so that control signal generation sub-blocks 84e and 84d operated independently of one another. A set of switches SW9, SW10 and SW11 are coupled to input terminals IN5, IN6 and IN7 of microcontroller 90". Switches SW9, SW10 and SW11 are analogous to switches SW1 , SW2 and SW3, but are operated independently. As is described below, switch sets SW1-SW3 and SW9-SW11 are used to independently control to different loads.

[70] Microcontroller 90" generates data signal 98 and PWM control signal

102 in response to switches SW1 , SW2 and SW3 as in the case of control signal control block 90'. Control signal generation sub-block 84e is coupled between terminals AC1 and AC3 and operates in the manner described in relation to control signal generation block 84c to produce a modified power signal (i.e. power signal 30') at terminal AC3. [71] Control signal generation sub-block 84f is coupled between between terminal AC1 (at node 406) and a terminal AC3', which is coupled to a second load (not shown) which may be similar to load 44 (Figure 1). This second load will typically be independent of the load 44 coupled to terminal AC3. In this two signal mode, microcontroller 90" generates data signal 98' and PWM control signal 102' in response to switches SW9, SW10 and SW11. Control signal generation sub-block 84f receives data signal 98' and PWM control signal 102' and operates in a manner analogous to control signal generation sub-block 84e to produce a modified power signal at terminal AC3', from which it may be received by the second load. [72] Control signal control block 82c and control signal generation block 84d may thus be used to provide a single highly balanced control signal (in the one signal mode) or to provide two independent generally balanced control signals at terminals AC3 and AC3'. This embodiment of control signal control block 82c and control signal generation block 84d provide a highly flexible product which may be manufactured and used cost effectively to provide the quality of control signal required for a particular use of the present invention. Microcontroller 90" may be configured with software required to operate in both the one and two signal modes and switch 8 may be either a physical or electronic switch. This will allow a single product to be manufactured and subsequently configured for use in either mode. [73] Control signal generation sub-blocks 84e and 84f have been described with an active control signal generation circuit analogous to that of control signal generation block 84b (Figure 12). In another embodiment of the present invention, these sub-blocks may have the structure of control signal generation block 84 (Figure 9) or of control signal generation block 84b (Figure 11). [74] The remainder of this disclosure assumes that transmitter 24 is configured with control signal control block 82 (Figure 4) and control signal generation block 84 (Figure 9), except as otherwise indicated.

[75] Reference is next made to Figure 16 which shows a block diagram of receiver 40. Receiver 40 includes a DC power supply block 120, a control signal detection block 122 and a control signal conversion block 124. [76] DC power supply block 120 is coupled to terminals AC3 and AC4 on which it receives modified power signal 30. DC power supply block 120 produces a regulated DC power supply Vcc at terminal DC2. Power supply Vcc is used to power control signal detection block 122 or control signal conversion block 124. Low voltage power supply block 120 may be the same as DC power supply block 80 or may be any other circuit that provides a regulated DC power supply from an AC power signal such as modified power signal 30.

[77] Control signal detection block 122 is coupled to terminals AC3 and AC4 on which it receives modified power signal 30. Control signal detection block 122 detects control signal 32 and provides a data stream 128 corresponding to digital data signal 98 (Figures 4, 6b, 7b and 8b) at terminal 126. [78] Control signal conversion block 124 receives data stream 128 and generates a 0 to 10 V protocol control signal at terminals 46 and 48 which may be used with known electronic ballasts (power supply 42 (Figure 1) in the present example) to control the operation of a gas discharge lamp (load 44 in the present example). The 0 to 10 V control signal has a positive component LAMP+ and a negative component LAMP-.

[79] Reference is next made to Figure 17 which illustrates control signal detection block 122. Control signal detection block 122 includes resistors R7 and R8, a capacitor C4, a diode D7, a microcontroller 134 which includes an analog to digital (A/D) converter and a microcontroller 136.

[80] The anode of diode D7 is coupled to terminal AC3 and the cathode of diode D7 is coupled to ground through resistors R7 and R8. Capacitor C4 is coupled across resistor R8. Diode D7 rectifies modified power signal 30 so that rectified signal 142 with only the positive half waves of modified power signal 30 appear at node 138. Resistors R7 and R8 form a voltage divider so that a portion of the rectified signal 142 appears at the node between resistors R7 and R8. As is well known, AC power distribution lines are highly susceptible to and often highly polluted with high frequency noise such as power spikes. Resistor R7 and capacitor C4 form a low pass filter which filters such high frequency noise from the signal across resistor R8, providing a filtered signal 144 at node 140. [81] An input terminal IN1 of microcontroller 134 is coupled to node 140 and receives filtered signal 144. Microcontroller 134 is programmed to calculate the area under the voltage curve for each positive half wave of filtered signal 144. Modified power signal 30 is shown in Figure 18a, which is identical to Figure 10d. Figure 18b shows the corresponding filtered signal 144. Microcontroller 134 is a model

PIC12C671 microcontroller with a built-in A/D converter, manufactured by Microchip Technology Inc. Microcontroller 134 is programmed to calculate the area under the voltage curve for each positive half wave of filtered signal 144 (i.e. integrating the voltage curve). This is done by sampling the magnitude of filtered signal 144 periodically and summing each sample to provide an estimate of the area. At the end of each positive half wave of filtered signal 144, microcontroller 134 provides a data word indicating the area of the preceding positive half wave at node 146, which is coupled to an output terminal OUT1 of microcontroller 134. In this manner, microcontroller 134 provides a data stream 148 of raw area values (Figure 18c) corresponding to the area under each successive positive half wave of filtered signal 144. Filtered signal 144 must be sampled sufficient times during each positive half wave to provide an accurate estimate of area. In the present exemplary embodiment, microcontroller 134 is programmed to sample filtered signal every 32 μs (approximately 300 samples per half wave) to provide an accurate measurement of the area of each half wave.

[82] Depending on the selection of microcontroller 134, terminal OUT1 and node 146 may consist of a number of parallel lines or a serial line. [83] An input IN of microcontroller 136 is coupled to node 146 to receive data stream 148. Microcontroller 136 is programmed to convert data stream 148 into data stream 128 corresponding to the data signal 98. Data stream 128 is generated at terminal OUTof microcontroller 136, which is coupled to terminal 126. Microcontroller 136 reads each successive raw area value from data stream 148 and determines whether (i) a code word originally generated by control signal control block 80 as part of data signal 90 (Figure 4) is being received and (ii) if so, whether the raw area value corresponds to a "0" bit or a "1" bit. [84] As described above, the present exemplary embodiment of signalling system 22 uses three code words (101 , 110 and 111) to represent input received on switches SW1 , SW2 and SW3, respectively (see Figure 4). The first bit of each of these code words is a start bit, which indicates to microcontroller 136 that transmission of a code word has started. Microcontroller 136 is programmed to interpret the following two bits to determine which input was received by the transmitter 24 (i.e. which switch was pressed by the user) and to generate a corresponding data stream 128 at terminal OUT of microcontroller 136. [85] Power distribution lines suffer from three primary types of disturbances: pulses, fluctuations and drifts. Pulses (or spikes) are high frequency noise, generally of short duration. A pulse which has sufficient magnitude or duration may affect the interpretation of a data bit encoded into the half wave.

[86] Signalling system 22 addresses the problem of pulse disturbances in two ways. The first is the use of a low pass filter consisting of resistor R7 and capacitor C4 in signal detection block 122, as described above. The second is the use of an integrated value to represent each positive half wave of filtered signal 144 rather than using a peak value or other measure which would be susceptible to pulse disturbances. [87] To address the problems of voltage fluctuations (disturbances with a smaller amplitude than a pulse and with a frequency of about 2-3 Hz, in general) and voltage drifts (which have a frequency of about 0.1 Hz or less), signalling system 22 uses an interpolation algorithm to determine whether a particular raw area value corresponds to a "0" or "1" bit. Since a bit is represented in signalling system by a cycle of modified power signal 30 in which the magnitude of both the positive and negative half wave have been reduced, the raw area value for a '1' bit will be less than the raw area value for a '0' bit. Microcontroller 136 is programmed to establish two threshold values TH0 and TH1. Threshold value TH0 represents the minimum raw area value that will automatically be considered to be a 'low' or logical '0' bit. Threshold value TH1 represents the maximum raw area value that will automatically be considered to be a 'high' or logical '1' bit. In general, the difference between threshold values TH0 and TH1 will be fixed. As raw area values are received which exceed THO or are less than TH1 , microcontroller 136 modifies threshold values THO and TH1 to track fluctuations and drifts in modified power signal 30. When a raw area value which falls between THO and TH1 is received, microcontroller 136 uses a soft decision viterbi algorithm to determine whether the raw area value corresponds to a '0' or '1'. Microcontroller 136 also changes threshold values THO and TH1 to be centred between the expected raw area values for subsequent '0' and '1' bits. This viterbi algorithm will be well known to persons skilled in the art and is not further explained here. [88] In addition to using an interpolation algorithm, the communication protocol of signalling system 22 may be configured such that no more than a selected number of '1' bits may be transmitted consecutively. If more than the selected number of '1' bits are received by the receiver 40, then microcontroller assumes that its threshold values THO and TH1 are incorrect and adjusts them so that the raw area values previously deemed to be '1' bits will now be deemed to be '0' bits. This and other methods of detecting errors in data transmitted by transmitter 24 will be familiar to persons skilled in the art. Further, a person skilled in the art will also be familiar with error correcting codes and will be able to select code words that implement an error correction mechanism to allow receiver 40 to correctly interpret a code word even if one or more bits in the code word have been erroneously received. [89] As described above, high frequency pulses are effectively filtered out of filtered signal 144. As a result, the interpolation algorithm programmed into microcontroller 136 is only required to deal with fluctuations and drifts. These relatively low frequency disturbances generally do not cause rapid changes in the raw area values in data stream 148. As a result, the interpolation algorithm reliably produces a bit stream 128 at node 126 that accurately corresponds to the data signal 98 generated by control signal control block 82.

[90] In this exemplary embodiment, microcontroller 136 is model

P87LPC764 microcontroller manufactured by Philips Semiconductor. The functions performed by microprocessors 134 and 136 are separated into two processing units to provide sufficient computing power to complete each function without loss of data. A single appropriately selected microcontroller may be configured to perform all of these functions, if it is desired.

[91] Reference is next made to Figure 19 which illustrates control signal conversion block 124. Control signal conversion block 124 includes a microcontroller 202, a microcontroller 204, capacitors C5 and C6, resistors R9, R10, R11 , R12, R13 and zener diode D8.

[92] An input terminal IN2 of microcontroller 202 is coupled to node 126 to receive bit stream 128. Bit stream 128 contains each code word transmitted by control signal control 82 in response to input signals received on switches SW1 , SW2 and SW3 (Figure 4). Microcontroller 202 is programmed to maintain a "Brightness" variable for the gas discharge lamp (load 44 in Figure 1) coupled to receiver 40. Microcontroller 202 receives bit stream 128, assembles the code words and then adjusts the Brightness variable in response to the code words. The 0 to 10 V protocol used by power supply 42 (Figure 1) has 30 steps which allow a gas discharge lamp to be set at any of 30 intensity levels. Microcontroller 202 may be programmed to maintain the Brightness variable as an integer in the range of 0-30, where 0 represents a lamp that is off and 30 represents a lamp at full brightness. In addition, microcontroller 202 maintains a "Last Intensity" variable. When code word 101 , which corresponds to SW1 (on/off), is received microcontroller is programmed to: (i) if the Brightness variable is not 0, then (a) store the value of the

Brightness value in the Last Intensity variable and (b) set Brightness = 0; or (ii) if Brightness = 0, then set the Brightness to the value of the Last Intensity variable. [93] When code word 110, which corresponds to SW2 (dim up), is received, microcontroller 202 increments the Brightness variable to a maximum of 30. When code word 111 , which corresponds to SW3 (dim down), is received, microcontroller 202 decrements the Brightness variable to a minimum of 0. Microcontroller 202 is programmed to output the value of the Brightness variable at terminal OUT2, which is coupled to node 206. [94] Microcontroller 204 is coupled to node 206 to receive the value of the

Brightness variable. Microcontroller 204 is programmed to produce a pulse width modulated (PWM) brightness signal 212 corresponding to the value of the Brightness variable at node 210. [95] In this exemplary embodiment, microcontroller 202 is a P87LPC764 model microcontroller manufactured by Philips Semiconductor. In the preferred embodiment of the present invention, microcontroller 202 is the same unit as microcontroller 136 and the single unit is programmed to perform all functions described for both microprocessors 136 and 202. [96] Microcontroller 204 is a microcontroller manufactured by Microchip

Technology Inc. In preferred embodiment of the present invention, microcontroller 204 is the same unit as microcontroller 134 and the single unit is programmed to perform all functions described for both microprocessors 134 and 204. [97] A person skilled in the art will be able to program microprocessors 134/204 and 136/202 to perform the functions described above. In addition, a person skilled in the art will be able to select different microprocessors than those described here to perform the same functions.

[98] Resistors R9 and R10 are coupled in series between node 210 and ground. Capacitor C5 is coupled across resistor R10. Together, resistors R9, R10 and capacitor C5 form a low pass filter which smooths PWM brightness signal 212 to form a smoothed brightness signal 216 at node 214. Comparator 206 receives smoothed brightness signal 216 at its positive input node. Comparator 206 produces signal LAMP+ at terminal 46 through resistor R12. Resistors R11 and R13 are coupled in series between output terminal 46 and ground to form a voltage divider which produces an image signal 222 at node 220. Image signal 222 is a portion of the signal LAMP+. The negative input terminal of comparator 206 is coupled to node 220 such that image signal 222 is received at the negative input terminal. Comparator 206 compares smoothed brightness signal 216 with image signal 222. If smoothed brightness signal 216 is greater than image signal 222, then signal LAMP+ is reduced through resistor R12. If smoothed brightness signal 216 is less than image signal 222, then signal LAMP+ is increased through terminal 46, which acts as a current source, in accordance with the 0 to 10 V standard protocol. Capacitor C6, which is coupled between output terminal 46 and ground, smooths these transitions of signal LAMP+ to ensure that the intensity of the gas discharge lamp coupled to terminals 46 and 48, which is coupled to ground, does not change too rapidly.

[99] Microcontroller 204 is programmed to produce PWM brightness signal

212 such that the signal LAMP+ is within the range of 0 to 10 volts, as is required for the 0 to 10 V protocol of the present example. Zener diode D8, which has a breakdown voltage of 15 V is coupled between output terminal LAMP+ and ground to ensure that the output signal 118 cannot exceed 15 volts in any case. Zener diode D8 is used to prevent damage to receiver 40 and components connected to terminals LAMP+ and LAMP-.

[100] An electronic ballast (power supply 42 in Figure 1) is coupled to terminals 46 and 48 to receive signal LAMP+ and LAMP- and is responsive to signals LAMP+ and LAMP- to control the light intensity of a gas discharge lamp (load 44 in Figure 1). Such electronic ballasts and gas discharge lamps are well known and are not further described here.

[101] Control signal detection block 122 of receiver 40 uses an integration algorithm to detect and '0' bits in modified power signal 30. This algorithm is computation intensive and requires a fairly powerful microcontroller 134 with an integrated (or coupled) A/D converter. Figure 20 shows an alternative receiver 40'. Receiver 40' is identical to receiver 40, except for control signal detection block 122'. Control signal detection block 122' is coupled to terminals AC3 and AC4 to receive modified power signal 30" (Figure 22d) which includes control signal 32", which was added to modified power signal 30" by a transmitter such as transmitter 84c. Control signal detection block 122' produces a digital data stream 128' at a terminal 126', which corresponds to terminal 126 of receiver 40. Data stream 128' corresponds to data stream 128 of receiver 40. [102] Reference is next made to Figure 21 , which is a schematic diagram of control signal detection block 122'. Control signal detection block 122' includes resistors R20, R21 , R22, R23, capacitors C14, C15, diode D14, DC voltage source Vref and a microcontroller 135. Resistors R20 and R21 are coupled in series between terminals AC3 and AC4. Capacitor C14 is coupled across resistor R21. Resistors R20, R21 and capacitor C14 form a low pass filter 131. Resistor R22 and capacitor C15 are coupled in series across capacitor C14 and form a second low pass filter 133. Diode D14 and resistor R23 are coupled in series across capacitor C15 with the cathode of diode D14 connected to terminal AC4 through resistor R23. Diode D14 and resistor R23 will conduct only during positive half waves of modified power signal 30". This has the effect of producing an asymmetry in the operation of low pass filter 133. During a positive half wave of modified power signal 30", current may flow between nodes from node 137 to node 139 through capacitor C15 and resistor R23. However during a negative half wave of modified power signal 30", current may flow from node 139 to node 137 only through capacitor C15. As a result, a filtered signal 144' at node 140' exhibits different positive and negative half wave characteristics. [103] Reference is next made to Figures 22a - 22f, which are shown on the same time scale but are out of scale with respect to the magnitudes of the signals shown. Figure 22a shows AC power signal 28. Figure 22b shows data signal 98 as it appears when an input signal is received on switch SW1 (Figures 4, 6a and 6b). Figure 22c shows a control signal 32", which is selected to provide a modified power signal 30" which may be detected by control signal detection block 122'. Control signal 32" is also chosen to have a zero amplitude during the peak of AC power signal 28, to reduce power consumption, as described above in relation to control signal 32a (Figure 15b). Figure 22d shows the modified power signal 30" which results from the use of control signal 32". Figure 22e shows filtered signal 144'. During cycles of power signal 30" when a '0' bit is transmitted, the positive portion of filtered signal 144' has a greater amplitude and a longer width than the corresponding sections of filtered signal 144' when a '1' bit is transmitted. Although the negative section of filtered signal 144' also exhibits a greater amplitude when a '0' bit is transmitted than when a '1' bit is transmitted, the effect is negligible and is not shown in Figure 22e. [104] Referring again to Figure 21 , a rectified signal 147 (Figure 22f) is produce by diode D14 at node 145. Due to the asymmetry introduced into low pass filter 133, rectified signal 147 exhibits a longer positive half wave when a '0' bit is transmitted than when a '1' bit is transmitted. [105] Microcontroller 135 is coupled to node 145 to receive rectified signal 147 at a terminal IN1. A terminal IN2 of microcontroller 135 is coupled to voltage source Vref. An output node OUT2 of microcontroller 135 is coupled to terminal 126'. [106] Reference is next made to Figure 23, which shows rectified signal 147 and reference voltage Vref. Time period t21 corresponds to a positive half wave of modified signal 30" during which a '1' bit was transmitted and time period t22 corresponds to a positive half wave of modified signal 30" when a '0' bit was transmitted. During period t21 , rectified signal 147 exceeds voltage Vref for time period t23. During period t22, rectified signal 147 exceeds voltage Vref for time period t24. [107] Referring again to Figure 21 , microcontroller 135 is programmed to produce data stream 128' at terminal 126'. To do so, microcontroller 135 is programmed to compare rectified signal 147 with reference voltage Vref and to measure the time period during each positive section of rectified signal 147 that rectified signal 147 exceeds the reference voltage Vref. When the measured time period is equal to or greater than a threshold Th (not shown), then a '0' is deemed to have been received. When the measured time period is less than or equal to a threshold TI (not shown), then a '1' bit is deemed to have been received. Thresholds Th and TI are chosen such that microcontroller is reliably able to detect '0' and '1' bit from modified power signal 30". Microcontroller generates data stream 128' in response to data bits detected. Data stream 128' is processed by control signal conversion block as described earlier in respect of receiver 40. [108] Reference is next made to Figure 24, which is a schematic diagram of another control signal detection block 122". Control signal detection block 122" may be used in place of control signal detection block 122' in receiver 40'. Control signal detection block 122" allows 2 bits of data to be transmitted during each positive half wave of modified power signal 30" (Figure 22d). Control signal detection block 122" is identical to control signal detection block 122' with the following exceptions: (i) microprocessor receives two DC voltage reference signals VREF1 and VREF2 at terminals IN1 and IN2; and (ii) microprocessor 135' receives filtered signal 147 at terminal IN1 and produces a data stream 128" at terminal 126". [109] Reference is next made to Figures 25a - 25f, which have a common time scale but do not have a common magnitude scale. Figure 25a shows AC power signal 28a. Figure 25b shows a data signal 98'. Data signal 98' is similar to data signal 98 (Figure 22b), except that data signal 98' includes two data bits in the period corresponding to the positive half wave of each cycle of AC power signal 28. The four periods of data signal 98' shown represent '00', '01', '10' and '11' bit combinations. When a '00' bit combination is to be transmitted, signal 98' is low during the period corresponding to the negative half wave of AC power signal 28. When a '01' or '10' bit combination is to be transmitted, signal 98' is high during the first half of the period corresponding to the negative half wave of AC power signal 28 and during the second half of this period. When a '00' bit combination is to be transmitted, signal 98' is high during the period corresponding to the negative half wave of AC power signal 28. [110] A control signal 32"' generated by control signal generation block 84c

(Figure 12) in response to data signal 98' and a PWM signal 102' (not shown) is shown in Figure 25c. As shown, when a '11 ' bit combination is transmitted, control signal 32'" is identical to control signal 32" (Figure 22c). However when a '10' or a '01' bit combination is transmitted, control signal 32'" includes a non-zero component only during the first portion or last portion, respectively, of the positive half wave of AC signal 28. When a '00' bit combination is transmitted, control signal 32'" has a magnitude of zero. A person skilled in the art will be capable of programming microcontroller 90' of Figure 12 to produce data signal 98' and PWM signal 102'. When a '01' or a '10' bit combination is to be transmitted, control signal 32'" has a magnitude of 1 volt during the first half of the negative half wave of AC power signal 28 and 0 volts during the second half of the negative half wave, in response to control signal 32'". This is done to reduce any DC component introduced into modified power signal 30'". [111] Figure 25d shows modified power signal 30'" produced on at terminal

AC3 by control signal generation block 84c, in response to control signal 32"'. Figures 25e and 25f show a filtered signal 144" and a rectified signal 147' (also shown in Figure 24). [112] The operation of microcontroller 135' to detect each of the two bits encoded into a single half wave of filtered signal 147' will be explained with reference to Figure 26, which shows rectified signal 147' during the reception of a '11' bit pair and a '10' bit pair in solid outline. The magnitude that rectified signal 147' would have when a '00' bit combination is received is shown in dotted outline. Rectified signal 147' may exhibit a time shift in both its rising and falling edges. A time shift s in the rising edge of rectified signal 147' will occur when a '10' or a '11' bit combination was transmitted. A time shift u in the falling edge of rectified signal 147' will occur when a '01' or '11' bit combination was transmitted. [113] Microcontroller 135' compares rectified signal 147' to voltage reference signals VREF1 and VREF2. Voltage reference signal VREF1 is selected to be at a magnitude that will be time shifted during the rising edge and during the falling edge of rectified signal 147' when a '11' bit combination is received. VREF2 is selected to be at a magnitude that will not be time shifted during the falling edge of rectified signal 147' when a '01' or '11' bit combination is received. The value of the first digit and the last digit of a received bit combination may be determined as follows:

[114] During each pulse of rectified signal 147', microcontroller 135' records:

(i) the time t10 at which the rising edge of rectified pulse 147' is equal to VREF1 ; (ii) the time t11 at which the falling edge of rectified pulse 147' is equal to VREF1 ; and (iii) the time t12 at which the falling edge of rectified pulse 147' is equal to VREF2. Microcontroller 135' then calculates the following time periods: TR = t12-t10 and TF = t12-t11.

[115] If the first bit of the received bit combination is a '0' (i.e. a '00' or '01 ' bit combination was received), then the time period TR will equal TR0. If the first bit of the received bit combination is a '1' (ie. a '10' or '11' bit combination was received), then time period TR will equal TR1. [116] If the second bit of a received bit combination is a '0' (i.e. if a '00' or '10' bit combination was received), then time period TF will equal TF0. If the second bit of a received bit combination is a '1' (i.e. if a '01 ' or '11' bit combination was received), then time period TF will equal TF1. [117] In this way, both bits of each bit combination may be determined. The two pulses of rectified signal 147' shown in Figure 26 represent a '11' bit combination and a '10' bit combination.

[118] A signalling system configured with receiver 40' and with a control signal control block and a control signal generation block modified as described above may be used in this manner to transmit two data bits during each cycle of AC power signal 28. This increased data bandwidth may be used to increase the speed at which code words are transmitted or may be used to add additional error correction bits to code words without any loss in the effective data transmission rate. [119] The combination of receiver 40' and a properly configured transmitter form a generic communication system that is not limited to signalling systems such as signalling system 22. A modified power signal is analogous to a data transmission signal in such a generic communication system. The transmitter of such a system may add a signal waveform which may be received and filtered through an asymmetric filter to detect a time shift at one or two selected magnitudes, such as Vrefl and Vref2. The output of such a filter may be analyzed by microprocessor with very little processing overhead to produce entirely digital output signal.

[120] Signalling system 22 has been described above in the context of a circuit

20. Circuit 20 is representative of North American power distribution circuits in which both a hot wire and a neutral wire are accessible in all switch boxes. This is not generally the case in Europe and other parts of the world. In a typical European power distribution circuit, only a hot wire is accessible in a switch box, although a neutral wire is generally accessible at a load. Accordingly, it is necessary to provide a transmitter which can function without access to the neutral wire. [121] Reference is next made to Figure 27, which shows a circuit 300 configured with a signalling system 302. Signalling system 302 is similar to signalling system 22, except that signalling system 302 includes a transmitter 304 that is coupled to terminal AC1 , which is coupled to the hot line of circuit 300. Transmitter 304 is not coupled to terminal AC2, which is coupled to the neutral line of circuit 300. Transmitter 304 receives power signal 28 from terminal AC1 , generates a control signal 306 and produces a modified power signal 308 at terminal AC3. The remaining components of circuit 300 and signalling system 302 are identical to the corresponding components in circuit 20 and signalling system 22 and are identified with the same reference numerals as in Figure 1. [122] Like signalling system 22, signalling system 302 is configured to provide a 0 to 10 V protocol control signal for a gas discharge lamp (load 44 in Figure 27). Like signalling system 22, signalling system 302 may be configured to operate more than one device and may be configured to operate many different types of devices. [123] Reference is next made to Figure 28, which is a block diagram of transmitter 304. Transmitter 304 includes a DC power supply block 310, control signal control block 312 and control signal generation block 318. DC power supply block 310 is coupled to terminals AC1 and AC3 to receive AC power signal 28. DC power supply block 310 produces a DC power supply consisting of DC power signals +VDC and - VDC across nodes DC3 and DC4. DC power supply block 310 also produces a DC power signal VAA at node DC5. DC power signal VAA is a positive voltage signal used to power various components of transmitter 304. [124] Control signal control block 312 receives DC power supply +VDC / -

VDC at nodes DC3 and DC4. Control signal control block 312 is also coupled to terminal AC1. Control signal control block 312 produces a pair of control signals 320 and 322 synchronized with AC power signal 28 at terminals 314 and 316. Control signal generation block 318 is coupled to terminal AC1 to receive AC power signal 28, to terminals 314, 316 to receive control signal 320 and to node DC5 to receive DC power supply VAA. Control signal generation block produces a modified AC power signal 308 at terminal AC3 in response to control signals 320 and 322. [125] Reference is next made to Figure 29, which is a schematic diagram of transmitter 304. The operation of transmitter 304 will be explained with reference to Figures 30a - 30j, which share a common time scale, but which are out of scale with respect to the magnitude of the signals shown.

[126] Control signal control block 312 comprises resistors R17, R18, switches SW5, SW6, SW7 and a microcontroller 326. [127] Microcontroller 326 receives power from nodes DC3 and DC4, at which power supply block 310 produces DC power signal +VDC and -VDC, as is explained below. The positive power input terminal VDD of microcontroller 326 is coupled to terminal DC3 and the negative power input terminal VSS is coupled to terminal DC4. [128] Microcontroller 326 is coupled to switches SW5, SW6 and SW7 at input terminals IN1 , IN2 and IN3, respectively. As noted above, signalling system 302 is configured to control a gas discharge lamp (load 44 in Figure 27). Switches SW5, SW6 and SW7 correspond to switches SW1 , SW2 and SW3 of transmitter 24 (Figure 4). Switch SW5 provides an "on/off' input, switch SW6 provides a "dim up" input and switch SW7 provides a "dim down" input to control the operation of the lamp. Switches SW5, SW6 and SW7 are normally open switches connected between terminal DC4 and an input terminal of microcontroller 326. When they are closed, they provide a momentary "low" signal to microcontroller 326, with a magnitude equal to -VDC, which is the same as the voltage applied to the negative power input terminal VSS of microcontroller 326. Microcontroller 326 is similar to microcontroller 90 and may be any conventional microcontroller. In the present embodiment, microcontroller 326 is a model 87LPC764 microcontroller manufactured by Philips Semiconductor. [129] The operation of control signal generation block 318 will be described in detail below. However, it is necessary to briefly review one aspect of the operation of control signal generation block 318 to understand the operation of control signal control block 312. Control signal generation block 318 includes diodes D15, D16, and D17 and a MOSFET type transistor Q5. Diodes D15, D16 and D 7 operate in a manner analogous to diodes D3 and D4 of control signal generation block 84b. Transistor Q5 operates in a manner analogous to transistor Q1 of control signal generation block 84b, described above. Diodes D15, D16 and D17 are selected such that each of them has a voltage drop of about 0.6 volts and as a group they provide a total voltage drop of about 1.8 volts. [130] Transistor Q5 is connected between terminals AC1 and AC3. When transistor Q5 is conducting, modified power signal 308 at terminal AC3 will be identical to AC power signal 28 at terminal AC1. When transistor Q1 is not conducting, diodes D15, D16 and D17 will reduce the magnitude of modified power signal 308 by approximately 1.8 volts during positive half waves and the internal reverse diode of transistor Q5 will reduce the magnitude of modified power signal 308 by approximately 1 volt during negative half waves. Terminal AC3 is coupled to ground. As a result when transistor Q1 is not conducting, there will be a potential of approximately 1.8 volts between node 322 and ground during positive half waves of AC power signal 28. Although the use of diodes D15, D16 and D17 produces a greater voltage drop than diodes D3 and D4 produce in control signal generation block 84b and accordingly produce a larger asymmetry between the magnitude of the positive half wave of modified power signal 308 and the negative half wave of modified power signal 308, the effect is still quite small. The percentage difference in the magnitude of the positive and negative half waves of modified power signal 308 is only about 0.7% ( (119 - 118.2)/119).

[131] This asymmetry between the magnitude of the positive and negative half waves of modified voltage signal 308 is not generally desired and, in general, should be minimized. The reason for creating a 1.8 volt drop across diodes D15, D16 and D17 is discussed below in relation to DC power supply block 310.

[132] Node 328 is connected to terminal AC3 (and ground) through resistor

R17. Node 330 is connected to terminal AC1 (and node 322) through resistor R18. The 1.8 volt potential and the -1 volt potential which appears between node 322 and ground when transistor Q5 is not conducting provides a synchronization signal 340 at nodes 328 and 330. Input terminals IN4 and IN5 of microcontroller 326 are coupled to nodes 328 and 330 to receive synchronization signal 340. Synchronization signal 340 is the negative of control signal 306, which is described below. Synchronization signal 340 (Figure 30f) is used by microcontroller 326 to synchronize the output signals (described below) of microcontroller 326 with AC power signal 28. Figure 30a shows AC power signal 28. Figure 30b shows synchronization signal 340 over a corresponding time period. [133] Output nodes OUT1 and OUT2 of microcontroller 326 are coupled respectively to signal on control terminal 332 and signal off control terminal 334.

Microcontroller 326 has been programmed to provide a three bit code word on a data on signal 336 and a data off signal 338 at signal on control terminal 332 and signal off control terminal 334, respectively. Data on signal 336 and data off signal 338 are mirror image signals such that when data on signal 336 is high, data off signal 338 is low. When a '1' bit is to be transmitted, data on signal 336 will be high and data off signal 338 will be low. When a '0' bit is to be transmitted, or no data is to be transmitted at all, data on signal 336 will be low and data off signal 338 will be high.

[134] As discussed above in relation to transmitter 24 (Figure 1), the use of a three bit coding system is only exemplary and the actual code words used in a practical embodiment of the present invention may include error correction or detection bits and may be of any length. Data on signal 336 is identical to data signal 98 (Figures 6b, 7b and 8b) of transmitter 24. Figures 30d and 30e show data on signal 336 and data off signal 338 when switch SW5 is momentarily closed by a user at time t6 (Figure 30c).

[135] An output terminal OUT3 of microcontroller 326 is coupled to power supply control terminal 342. Microcontroller 326 provides a power supply control signal 344 at power supply control terminal 342. Power supply control signal 344 is used to control the operation of DC power supply block 310. The timing and function of power supply control signal 344 is explained below. [136] Referring again to Figure 29, control signal generation block 318 includes Q6, Q7, Q8 and resistors R19, R24 and R25, in addition to diodes D15, D16, D17 and transistor Q5 which were discussed above. The base of transistor Q6 is coupled to terminal 332 through resistor R24 to receive data on signal 336. The base of transistor Q7 is coupled to terminal 334 through resistor R25 to receive data off signal 338. The collector of transistor Q6 is coupled to the collector of pnp transistor Q8 and also to the gate of transistor Q5. The collector of transistor Q7 is coupled to the base of transistor Q8 through resistor R19. The emitter of transistor Q8 is coupled to terminal DC5 where it receives DC power signal VAA. The emitters of transistors Q6 and Q7 are coupled to terminal DC4. As noted above, the negative power input terminal VSS of microcontroller 326 is coupled to terminal DC4, at which DC power supply block 310 produces a DC voltage signal -VDC. As a result, data on signal 336 and data off signal 338 are referenced to voltage signal -VDC, rather than to ground. As a result, it is necessary to reference transistor Q7 and Q8 to voltage signal -VDC.

[137] The operation of control signal generation block 318 is as follows.

When data on signal 336 is high, and data off signal 338 is conversely low, transistor Q6 will be switched on and transistor Q7 will be switched off. When transistor Q7 is off, its collector will be high, and accordingly pnp transistor Q8 will be off. This will cause the gate of transistor Q5 to be pulled down to voltage signal -VDC (at terminal DC4) through transistor Q6. Transistor Q5 will be off and diodes D15, D16 and D17 and the internal reverse diode of transistor Q5 will operate to add control signal 306 to AC power signal 28 to produce modified power signal 308 at terminal AC3, as described above. When data on signal 336 is low, and data off signal 338 is high, transistor Q6 will be off and transistor Q7 will be on. When transistor Q7 is on, transistor Q8 will be on, causing the gate of transistor Q5 to be pulled up to voltage signal VAA at terminal DC5. This will cause transistor Q5 to conduct, and modified power signal 308 will be identical to AC power signal 28. In this way, control signal 306, consisting of a stream of '0' and '1 ' bits, is superimposed onto AC power signal 28 to form modified power signal 308. Control signal 306 and modified power signal 308 are shown in Figures 30f and 30g, during the period corresponding to Figures 30d and 30e. [138] Since synchronization signal 340 (Figure 30b) is not a periodic signal (since it has a zero magnitude when transistor Q5 is conducting), microcontroller 326 uses an internal timer to synchronize transitions in data on signal 336 and data off signal 338 with zero crossing of AC power signal 28. When a '1' bit is transmitted, microcontroller 326 monitors synchronization signal 340 and uses the transition from +1.8 volts to -1 volt to resynchronize its internal timer with synchronization signal 340. [139] DC power generation block 310 includes transistors Q9, Q10, Q11 and

Q12, resistors R14, R15 and R16, R26, capacitors C7, C8, C9, C10, C11 and C12, diodes D12, D13 and a charge pump voltage inverter 324. Resistor R14 and capacitor C7 are coupled in series between node 322 and ground. The base of transistor Q9 is coupled between resistor R14 and capacitor C7. The emitter of transistor Q9 is coupled to ground. The collector of transistor Q9 is coupled to the base of pnp transistor Q10 and to the base of pnp transistor Q11 through resistor R15. The collectors of transistors Q10 and Q11 are coupled to node 322. The emitter of transistor Q10 is coupled to ground through transistor C8 and also to node DC3. The collector and emitter of Q12 are coupled across capacitor C7, with the emitter of Q12 coupled to ground. The base of transistor Q12 is coupled to power supply control terminal 342 through resistor R26 to receive power supply control signal 344. [140] In the present embodiment of transmitter 304, charge pump voltage inverter 324 is a model SP6829 low voltage power inverter IC manufactured by Sipex Corporation. This integrated circuit has five terminals: Vin, Vout, C1+, C1- and GND. A charge pump capacitor C9 is coupled between terminals C1+ and C1-. Terminal Vin is coupled to terminal DC5 through forward connected diodes D12 and D13. Capacitor C10 is coupled between terminal C1+ and the cathode of diode D12. Terminal DC5 is coupled to capacitor C11 , which is coupled to terminal 334 to receive data off signal 338. Charge pump voltage inverter 324 provides a voltage equal to -Vin at terminal Vout. [141] As described above, a voltage potential of 1.8 volts will exist between node 322 and ground during positive half waves of AC power signal 28 when a '1 ' bit is being transmitted on modified power signal 308. During this time, the 1.8 voltage potential between node 322 and ground will charge capacitor C7 through resistor R14. When capacitor C7 is sufficiently charged, transistor Q9 will turn on, causing the voltage at the collector of transistor Q9 to fall. This will turn pnp transistors Q10 and Q11 on. When transistor Q10 enters its saturation region, terminal DC3, at the collector of transistor Q10 will have a voltage of 1.8 volts (equal to the potential between node 322 and ground). This voltage at terminal DC3 is voltage signal +VDC. Voltage signal +VDC will charge capacitor C8. [142] Simultaneously, terminal Vin of charge pump voltage inverter 324 will receive a 1.8 volt signal through the collector of transistor Q11. Charge pump voltage inverter 324 will produce a -1.8 volt signal at terminal DC4. This is voltage signal - VDC. Voltage signal -VDC will charge capacitor C12.

[143] Capacitor C10, diodes D12, D13, capacitor C11 and R16 operate as a second charge pump. One skilled in the art will be able to show that the voltage at the cathode of diode D13 is equal to

2Vin - voltage drop across diodes D12 and D13.

[144] Diodes D12 and D13 are selected to have a voltage drop of 0.7 volts, giving a voltage of 2.2 volts (2 x 1.8 - 2 x 0.7). Since a '1 ' bit is being transmitted during this time, data off signal 338 will be low and will have a voltage equal to -VDC ( -1.8 volts), which is supplied to the negative power input terminal VSS of microcontroller 326. The voltage across capacitor C11 and R16 is approximately 4 volts (2.2 + 1.8) and capacitor C11 will charge to 4 volts. [145] The charge across capacitor C11 is used only when transistor Q8 is on.

This occurs only when data off signal is high, at which time it will have a voltage of approximately 1.8 volts. Voltage signal VAA at terminal DC5 will be equal to this voltage plus the voltage across capacitor C11 and will be approximately 5.8 volts (1.8 + 4). [146] The derivation of voltage VAA here is based on idealized operation of the components in DC power supply block 310 and ignores voltage drops through various components. For example, a small voltage will be dropped in transistor Q11 even when it is fully saturated, with the result that the voltage at terminal Vin of charge pump voltage inverter 324 will be slightly less than 1.8 volts. In addition, a small voltage will be dropped in resistor R16 while capacitor C11 is charging and when capacitor C11 is being used to provide voltage signal VAA. It has been found the use of the following components provides a voltage signal VAA of 5.4 volts during the transmission of a '0' bit and voltage signals +VDC and -VDC of approximately 1.8 volts and -1.8 volts: Reference Number Component or Value

Q9, Q10, Q11 2N3904

R14 10kΩ

R15 1kΩ

R16 10kΩ

R17 10kΩ

R18 10kΩ

R19 10kΩ

R24 10kΩ

R25 10kΩ

R26 10kΩ

C7 100nF

C8 470μF

C9 4.7μF

C10 4.7μF

C11 220nF

C12 470μF

D12, D13 2N4148

D15, D16, D17 SB540

[147] Voltage signals +VDC, -VDC and VAA are generated directly by DC power supply block 310 only when there is a voltage potential between node 322 and ground. At other times, voltage signals +VDC, -VDC and VAA are supplied by capacitors C8, C12 and C11 , respectively. One skilled in the art will recognize that the charge across each of these capacitors must be refreshed periodically in order to maintain a sufficient voltage at terminal DC3, DC4 and DC5. It has been found the transmitter 304 operates properly when capacitors C8, C12 and C11 are refreshed once every 64 cycles of AC power signal 28. Accordingly, microcontroller 326 is configured to transmit a '1' bit if no '1' bit has been transmitted in the preceding 63 cycles. The data communication protocol of signalling system 302 is selected such that this transmission of a '1' bit does not affect the operation of load 44, and may in fact be used to synchronize receiver 40 with transmitter 24.

[148] As noted above, microcontroller 326 of control signal control block 312 is powered by voltage signal +VDC and -VDC. Microcontroller 326 is selected so that it may be powered by this 3.6 volt potential.

[149] Transmitter 304 is connected in series with the load on circuit 300 (i.e. loads 44, 48 and 50, which are in parallel) coupled to terminals AC3 and AC4 (Figure 27). The current flowing through transmitter 304 will depend primarily on resistance (or reactance) of load 44. Figure 30h shows an exemplary maximum load current signal 346, which represents the maximum current that may flow in circuit 300 over time. During each positive half wave of AC power signal 28, maximum load current signal 346 initially has an amplitude of zero (since the voltage of AC power signal is zero) and rises to a maximum imax. Load current signal 346 then falls to zero. Each negative half wave of load current signal 346 has a similar shape. [150] DC power supply block 310 requires a measurable amount of current icharge from terminal AC1 to charge capacitors C8, C12 and C11 during positive half waves of AC power signal 28. The magnitude of current icharge will depend primarily on the size of capacitors C8, C12 and C11 and other characteristics of DC power supply 310. The magnitude of current icharge may be measured or calculated by known methods. One skilled in the art will recognize that DC power supply block 310 may receive current icharge from terminal AC1 only when load current signal 346 has a magnitude larger than current icharge.

[151] DC power supply block 310 begins to draw current when transistor Q9 switches on in response to capacitor C7 becoming sufficiently charged. If DC power supply block 310 switches on before the magnitude of load current signal 346 exceeds icharge at time t6, DC power supply block 310 will draw almost all of the current flowing through transmitter 304. This will result in insufficient current flowing through control signal generation block 318 and control signal generation block 318 will not be able to properly form control signal 306 and modified power signal 308. As a result, it is necessary to ensure that DC power supply block 310 does not draw any current from terminal AC1 until after time t6. Similarly, DC power supply block 310 must be prevented from drawing any current from terminal AC1 current after time t7. This is accomplished by ensuring that transistor Q9 remains off before time t6 and after time t7 during each positive half wave of AC power signal when a '1' bit is being sent. [152] Capacitor C7 begins to charge when transistor Q5 turns off at the beginning of the transmission of a '1' bit. The time between the beginning of the transmission of a '1' bit and between the turn on of transistor Q9 will be defined by the time constant of resistor R14 and capacitor C7. This time constant is selected to ensure that transistor Q9 does not switch on until after time t6. [153] As long as capacitor C7 remains charged, transistor Q9 will remain on.

Power supply control signal 344 is used to discharge capacitor C7, thereby switching transistor Q9 off prior to time t7. Normally, power supply control signal 344 is held low by microcontroller 326 and transistor Q12 is held off. When transistor Q9 is to be switched off, microcontroller 326 switches power supply control signal 344 to a high signal, causing transistor Q12 to switch on. Capacitor C7 discharges through capacitor Q12 and transistor Q9 switches off.

[154] Figure 30i shows power supply control signal 344. Figure 30j shows the on/off status of transistor Q9. [155] Reference is again made to Figure 12, which shows control signal control block 82b and control signal generation block 84c. Control signal generation block 84c may be used to produce a control signal of almost any shape by programming microcontroller 90' to produce an appropriate PWM signal 102. [156] Reference is next made to Figures 31a - 31c, which are drawn with a common time scale but are out of scale with respect to the magnitude of the signals shown. Figure 31a shows AC power signal 28. Figure 31b shows a control signal 32b. Figure 31c shows a modified power signal 30b corresponding to control signal 32b. During the transmission of a '0' bit, control signal 32b has a magnitude of zero. During the transmission of a '1' bit, control signal 32b consists of a sine wave with a fixed frequency during the positive half wave of AC power signal 28 and of the voltage drop across the internal reverse diode of transistor Q2 during the negative half wave of AC power signal 28. In order to ensure that no DC component is introduced in modified power signal 30b, control signal 32b selected such that the area A under the positive half wave of the voltage curve of modified power signal 30b is approximately equal to the area B under the negative half wave of the voltage curve of modified power signal 30b. Control signal 32b has an advantage over control signals 30 (Figure 10c), 30' (Figure 13c) and 30a (Figure 15b). When modified power signal 30b is received by a receiver, the presence or absence of the high frequency component of control signal 32b may easily be detected by using a high pass filter, or more preferably, a band pass filter, which allows the high frequency component to be isolated and then detected. It has been found that such a receiver can detect the data encoded in modified power signal 30b with great accuracy. In particular, such a receiver is not susceptible to errors resulting from fluctuations and drifts in the voltage of modified power signal 30b. A person skilled in the art will be capable of designing a receiver capable of receiving modified power signal 30b and detecting control signal 32b. The use of high frequency control signal in a signalling system according to the present invention has another substantial benefit not found in prior art systems. Since modified power signal 30b is produced by removing energy corresponding to the magnitude of control signal 32b from AC power signal 28, the resulting high frequency component of modified power signal 30b only propagates from the transmitter to the load, and is not propagated back to the power supply. As a result, AC power signal 28 is not affected by the frequency of control signal 30b and no filters are required to remove control 30b from AC power signal 28. [157] In prior art high frequency AC power line signalling systems, the AC power signal is modified by adding power corresponding to the desired high frequency signal to the AC power signal. This results in the high frequency signal propagating in both the load and supply directions from the transmitter. As a result, prior art systems required high power filters to remove the high frequency signal from the supply side of the transmitter, or had to use a protocol in which only one transmitter connected to any group of interconnected circuits could send a code word at one time. In the present invention a transmitter may transmit a code word to any device on the load side of its own circuit, even if that circuit is coupled to other circuits and a junction box or circuit breaker box. [158] Reference is next made to Figures 32a - 32c, which are drawn with a common time scale but are out of scale with respect to the magnitude of the signals shown. Figure 32a shows two wavelengths of AC power signal 28. Control signal generation block 84c (Figure 12) may be used to create a control signal 32c (Figure 32b) with a high frequency component that is modulated to contain more than one data bit during a single positive half wave of modified power signal 30c, shown in Figure 32c. During the first wavelength shown, no data is transmitted and control signal 32c has a magnitude of zero volts. During the second wavelength of AC power signal 28, a data stream is transmitted. During the positive half wave of the second wavelength of AC power signal 28, control signal 32c is a frequency modulated sine wave. Control signal 32c may be used to transmit many data bits during the positive half wave of modified signal 32c by frequency modulating a sine wave control signal with a DC offset. Receivers 40 and 40' described earlier are not suitable to detect data transmitted in such a modified power signal 32c. However, a person skilled in the art will be capable of making a receiver which can detect the frequency modulated signal. For example, such a receiver may sample modified power signal 30c at a frequency at least twice that of the high frequency used to modulate control signal 32c. In order to ensure that no DC component is introduced into modified power signal 32c, control signal 32b is configured such that the area A under the positive half wave of the voltage curve of modified power signal 30c is approximately equal to the area B under the negative half wave of the voltage curve of modified power signal 30c. [159] The preferred embodiments described herein relate to a signalling system used to control the operation of gas discharge lamp based on three inputs (on/off, dim up and dim down). The present invention may be used to control the operation of many different devices or system. A single transmitter may control the operation of more than one device by incorporating an "address" field into the code words transmitted. Each receiver in such a system would be responsive only to code words which contain the address of the receiver. [160] The present invention may also be used in a multiple stage system where one signalling system is used to transmit code words from a main transmitter to a number of main receivers, all connected on a main circuit. Some (or all) of the main receivers may operate to control a sub-transmitter which transmits code words on a sub-circuit to a number of sub-receivers which actually operate a device or service.

[161] The signalling system of the preset invention may be used to allow a number of different devices and services to be simultaneously configured to be in a pre-selected configuration. For example, if a group of services, such as HVAC, lighting and security, must be switched simultaneously into different configurations at different times of the day or on different days of the week, a number of "scenes" may be programmed into the receiver which control the operation of each device or service. For example, a group of scenes may include: working hours, weekday evening, weekday night and weekend. A transmitter may transmit a code word indicating the particular scene that is desired and transmit it on a circuit. Some (or possibly all) of the receivers on that circuit may be responsive to the code word to switch the device or service associated with that receiver to the characteristics which have been previously programmed for that scene.

[162] A person skilled in the art will be capable of implementing these and other variations of the present invention, all of which fall within the spirit and scope of the present invention.

Claims

WE CLAIM:

1. A transmitter circuit for transmitting a control signal on an AC power line carrying an AC power signal having positive half waves and negative half waves, the circuit comprising: (a) a control signal control block for generating a data signal, the data signal having a plurality of signal levels; and (b) a control signal generation block coupled to the control signal control, the control signal generation block including: (i) a first voltage dropping element, said first voltage dropping element having an engaged state in which the first voltage dropping element induces a first voltage drop during said positive half waves and a disengaged state; (ii) a second voltage dropping element, said second voltage dropping element having an engaged state in which the second voltage dropping element induces a second voltage drop during said negative half waves and a disengaged state; and (iii) a switch responsive to said data signal block for engaging and disengaging the first voltage dropping element and for engaging and disengaging the second voltage dropping element.

2. The transmitter circuit of claim 1 wherein the first voltage drop and second voltage drop are balanced such that substantially no DC voltage is added to the AC power signal when said first and second voltage dropping elements are engaged for one cycle of said AC power signal.

3. The transmitter circuit of claim 1 further including a power supply block coupled to said AC power line to receive said AC power signal and to said control signal control block for providing a DC power signal at a power input of said control signal control block.

4. The transmitter circuit of claim 1 wherein said control signal control block is coupled to one or more input devices for receiving one or more input signals and wherein said control signal control block is configured to generate said data signal in response to said one or more input signals.

5. The transmitter circuit of claim 1 further including a synchronization signal block coupled to said AC power line and to said control signal control block for providing a synchronization signal to a synchronization signal input of said control signal control block, wherein said synchronization signal has the same frequency as the AC power signal.

6. The transmitter circuit of claim 5 wherein said data signal is synchronized with said synchronization signal.

7. The transmitter circuit of claim 6 wherein said first voltage dropping element includes a diode and wherein said second voltage dropping element includes a diode.

8. The transmitter circuit of claim 6 wherein said first voltage dropping element includes a diode and wherein said switch includes a switching transistor and wherein said second voltage dropping element is an internal reverse diode of said switching transistor, and wherein said first and second voltage dropping elements are disengaged when said switching transistor is on and wherein said first and second voltage dropping elements are engaged when said switching transistor is off.

9. The transmitter circuit of claim 6 wherein:

(a) said control signal control block is configured to provide a control signal shaping signal; and

(b) said first voltage dropping element includes a first voltage dropping transistor for providing said first voltage drop in response to said control signal shaping signal.

10. The transmitter circuit of claim 9 wherein said switch includes a switching transistor and wherein said second voltage dropping element is an internal reverse diode of said switching transistor, and wherein said first and second voltage dropping elements are disengaged when said switching transistor is on and wherein said first and second voltage dropping elements are engaged when said switching transistor is off.

11. The transmitter circuit of claim 9 wherein the average voltage of the first voltage drop and average voltage of the second voltage drop are balanced such that substantially no DC voltage is added to the AC power signal when said first and second voltage dropping elements are engaged for one cycle of said AC power signal.

12. The transmitter circuit of claim 9 wherein said control signal shaping signal is a PWM signal.

13. The transmitter circuit of claim 9 wherein:

(a) said control signal control block is configured to provide a second control signal shaping signal;

(b) said second voltage dropping element includes a second voltage dropping transistor, for providing said second voltage drop in response to said second control signal shaping signal.

14. The transmitter circuit of claim 13 wherein the average voltage of the first voltage drop and average voltage of the second voltage drop are balanced such that substantially no DC voltage is added to the AC power signal when said first and second voltage dropping elements are engaged for one cycle of said AC power signal.

15. The transmitter circuit of claim 14 wherein said first and second control signal shaping signals are PWM signals.

16. A transmitter circuit for transmitting a control signal on an AC power line carrying an AC power signal having positive half waves and negative half waves, the circuit comprising:

(a) a control signal control block for generating a data signal, the data signal having a plurality of signal levels;

(b) a control signal generation block coupled to the control signal control, the control signal generation block including:

(i) a first forward voltage dropping element having an engaged mode in which said first forward voltage dropping element creates a first forward voltage drop in the AC power signal during positive half waves and having a disengaged mode; (ii) a first reverse voltage dropping element having an engaged mode in which said first reverse voltage dropping element creates a first reverse voltage drop in the AC power signal during negative half waves and having a disengaged mode; (iii) a second forward voltage dropping element having an engaged mode in which said second forward voltage dropping element creates a second forward voltage drop in the AC power signal during positive half waves and having a disengaged mode; (iv) a second reverse voltage dropping element having an engaged mode in which said second reverse voltage dropping element creates a second reverse voltage drop in the AC power signal during negative half waves and having a disengaged mode; (v) a first switch responsive to said data signal for engaging and disengaging said first forward voltage dropping element and for engaging and disengaging said second reverse voltage dropping element; and (vi) a second switch responsive to said data signal for engaging and disengaging said first reverse voltage dropping element and for engaging and disengaging said second forward voltage dropping element, wherein said first forward voltage dropping element corresponds to said first reverse voltage dropping element and wherein said second forward voltage dropping element corresponds to said second reverse voltage dropping element.

17. The transmitter of claim 16 wherein said first forward voltage dropping element and said second forward voltage dropping element are engaged simultaneously.

18. The transmitter of claim 17 wherein said first reverse voltage dropping element and said second reverse voltage dropping element are engaged simultaneously.

19. The transmitter of claim 16 wherein said first forward voltage dropping element and said first reverse voltage dropping element comprise matched active voltage dropping circuits.

20. The transmitter of claim 19 wherein said first reverse voltage dropping element and said first reverse voltage dropping element comprise internal reverse diodes of matched switch transistors.

21. The transmitter of claim 19 wherein said first switch and said second switch comprise said matched switch transistors.

22. A method of transmitting a control signal on an AC power line carrying an AC power signal having positive half waves and negative half waves, comprising:

(a) generating a digital data signal;

(b) selectively engaging a first voltage dropping element during positive half waves in response to said data signal to generate a first portion of said control signal; (c) selectively engaging a second voltage dropping element during negative half waves in response to said data signal to generate a second portion of said control signal;

(d) summing said control signal with said AC power signal to provide a modified AC power signal, wherein the average magnitude of the first portion of said control signal is approximately equal to the average magnitude of the second portion of said control signal.

23. The method of claim 22 wherein the control signal has a negative magnitude during positive half waves and a positive magnitude during negative half waves.

24. The method of claim 22 wherein the first voltage dropping element is a first voltage dropping transistor operated in response to a first portion shaping signal.

25. The method of claim 24 wherein the magnitude of the first portion increases progressively from zero volts to a maximum and then decreases progressively to 0 volts.

26. A method of receiving a control signal embedded into an AC power signal and providing a bit stream corresponding to said control signal, comprising:

(a) calculating approximately the integral of a selected portion of a cycle of an AC power signal;

(b) If the result of step (a) exceeds a first threshold value, then transmitting a selected bit value in the bit stream; and

(b) If the result of step (a) does not exceed the first threshold value, transmitting a different bit value in the bit stream.

27. The method of claim 26 wherein step (a) is repeated for more than one cycle of the AC power signal and wherein the threshold is varied based on the result of step (a) during at least some repetitions.

28. The method of claim 26 wherein the selected bit value is "0" and wherein the different bit value is "1".

29. The method of claim 26 wherein the selected bit value is "1" and wherein the different bit value is "0".

30. A method of receiving a control signal embedded into an AC power signal and providing a bit stream corresponding to said control signal, comprising: (a) differentially low pass filtering said AC power signal to provide a filtered signal in which the wave form of a positive half wave is compressed, at least at a selected magnitude, when the control signal has a selected level and wherein the waveform is not compressed, at the selected magnitude, when the control signal has a different level; (b) comparing the filtered wave form, or an image of the filtered wave form, to the selected magnitude to determine the time during which the filtered wave form exceeds the selected magnitude; (c) If the result of step (a) exceeds a threshold value, then transmitting a selected bit value in the bit stream; and (b) If the result of step (a) does not exceed the threshold value, transmitting a different bit value in the bit stream.