WO2001073739A1 - Changes introduced on matrix analog system for the reproduction of images - Google Patents

Changes introduced on matrix analog system for the reproduction of images Download PDF

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Publication number
WO2001073739A1
WO2001073739A1 PCT/BR2001/000037 BR0100037W WO0173739A1 WO 2001073739 A1 WO2001073739 A1 WO 2001073739A1 BR 0100037 W BR0100037 W BR 0100037W WO 0173739 A1 WO0173739 A1 WO 0173739A1
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WO
WIPO (PCT)
Prior art keywords
matrix
analog
images
reproduction
image
Prior art date
Application number
PCT/BR2001/000037
Other languages
French (fr)
Inventor
Nereu GOUVÊA
Ricardo Tramujas
Ronaldo Tramujas
Original Assignee
Gouvea Nereu
Ricardo Tramujas
Ronaldo Tramujas
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gouvea Nereu, Ricardo Tramujas, Ronaldo Tramujas filed Critical Gouvea Nereu
Priority to AU2001243973A priority Critical patent/AU2001243973A1/en
Publication of WO2001073739A1 publication Critical patent/WO2001073739A1/en

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers

Definitions

  • This invention patent refers to the improvements of an electronic system to command a matrix display for the reproduction of video images by means of pixels in a way that the image reproduced on the matrix had the same advantages and the same performance of a cathode ray tube that function in an analog way, that is that may present composite video images in real time without the need for previous processing of the video signal through analog/digital or digital/analog converter, without the need for microprocessors and not even the need of computers and processors that normally are needed to generate a matrix of pixels.
  • Photolurninescent displays have a similar performance to cathode rays tubes, while the former need a high voltage for working mainly due to a long light retention time the latter work with low voltages making possible the building of matrixes for the reproduction of images however with a shorter retention time.
  • a way for obtaining an excellent light retention time on photolurninescent matrixes is by a parallel scanning, in other word doing in a way that the duty cycle or the enabling time in percentage be not much below the 1/250, which is far from the 90,000 of the conventional kinescopes.
  • the vertical parallel scan system is the materialisation of a concept that applied to the analog control makes possible to increase the retention time of any type of photolurninescent matrix.
  • This concept consists on the principle that the image scanning system is horizontal, that is the image is plotted from left to right by means of lines that will form a frame of the image.
  • This same analog principle requires different times to form a line or an image frame being obvious that to form an image frame takes much longer than to form an image line.
  • This plotting time differential only allows for a horizontal parallel scanning if all the pixels of the frame are memorised which makes the system very expensive and very complex.
  • the proposal is of different optic with a parallel vertical scanning; this system does not need to memorise for example all the 90,000 pixels of the framed image but only about 250 to 300 pixels of only one image line in a memorising binary; are presented herein the improvements that add a bivalent memory system that may be digital or analog controlled by the horizontal video signal synchronism or columns enabling synchronism, this system consists of the arrangement of a number of switches and other components for the construction of memory cells in a way that with these memory cells be established in two memory banks interconnected in a way so as to create the PARALLEL VERTICAL SCANNING SYSTEM; these such interconnected banks are used both for registering the video information that need to be plotted in a matrix line as well as in a second moment restore such line pattern for the sequential output that enable the matrix columns to be converted into an array of video output adequate to the polarisation of all the elements of the image of the matrix line during the same time lapse, in a way that the enabling time of the luminosity device of the matrix is now
  • Drawing 1 shows a general view of the matrix being controlled by two sequential distribution devices called PARALLEL VERTICAL SCANNING SYSTEM.
  • Drawing 2 shows a detailed view of the analog memory cell.
  • Drawing 3 shows a memory bank and the array of memory cells within the bank with single control for the video input.
  • Drawing 4 shows the interconnection of the two memory banks fo ⁇ ning one single system.
  • Each memory cell (1) is constituted by a switch (2) that controls the input (4) of a video signal for this, through the input command (11) when the switch (2) is commuted, be stored as tension in a capacitor (3) being then memorised analogicaly the tension level of the signal at he input switch (4) of the switch (2).
  • an operational amplifier (6) configured as non inverter of tension with high input impedance and low output impedance.
  • a switch (7) that will only switch the output (8) through the output command (9).
  • the memory bank (10) is then composed of an array of memory cells (1) arranged so that the output commands (9) of the memory cells (1) are connected in parallel composing the output control of the bank (12).
  • the video inputs (4) of the memory cells (1) also connected in parallel, are controlled by means of a bank switch (13) that only allows the access of the video input signal (14) when the switch (13) is activated by the video command of the bank (15).
  • the input command (11) of each memory cell (1) will produce a sequence of inputs (18) on the memory bank (10); the output (8) of the memory cells will produce the sequence of output (19) of the memory bank (10).
  • the PARALLEL VERTICAL SCANNING SYSTEM (16) is composed of two memory banks (10) and a flip-flop system (17) connected so that the input commands (18) and the output commands (19) of both memory banks (10) be connected in parallel.
  • the video command (15) of one bank is connected with the output control (12) of the other bank.
  • the video control (15) and the output command (12) are respectively connected to the "S" output (20) and "S-" (21) of the flip-flop (17).
  • the video inputs (14) of both memory banks (10) are connected in parallel and produce the video input (22) of the PARALLEL VERTICAL SCANNING SYSTEM (16).
  • the clock input (23) of the flip-flop (17) produces the synchronism input (24) of the PARALLEL VERTICAL SCANNING SYSTEM (16).
  • the input sequence (18) of both the memory banks (10) that are connected in parallel will constitute the input sequences (25) of the PARALLEL VERTICAL SCANNING SYSTEM (16), in the same way the output sequences (19) of the two banks that are also in parallel will constitute the output sequences (26) of the PARALLEL VERTICAL SCANNING SYSTEM (16).
  • the PARALLEL VERTICAL SCANNING SYSTEM (16) is energised the output (20) of the flip-flop (17) adopts the logical status "0" or "1", as a consequence the refused output (21) adopts the opposite status "1” or "0", this way while one memory bank (10) is memorising data of one video line the other one will be providing video data at the output sequence (26).

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

This invention patent refers to the improvements of an electronic system produced to command a video image matrix by means of pixels in such a way that the image reproduced on the matrix has the same advantages and the same performance of the cathode rays tubes that function in an analog way. It may present composite video images in real time without the need of previous processing of the video data through converters analog/digital or digital/analog, without the use of microprocessors or computers or converters that are normally needed to generate an image onto a pixel matrix. The improvement is characterised by the addition of the so called PARALLEL VERTICAL SCANNING SYSTEM (16) between the output sequence of one of the sequential distribution devices of the MATRIX ANALOG SYSTEM FOR THE REPRODUCTION OF IMAGES and the connections of the matrix itself. This allows for the excitation of photoluminescent displays with a much lower duty-cycle.

Description

. { _
CHANGES INTRODUCED ON MATRIX ANALOG SYSTEM FORTHE REPRODUCTION OF IMAGES.
This invention patent refers to the improvements of an electronic system to command a matrix display for the reproduction of video images by means of pixels in a way that the image reproduced on the matrix had the same advantages and the same performance of a cathode ray tube that function in an analog way, that is that may present composite video images in real time without the need for previous processing of the video signal through analog/digital or digital/analog converter, without the need for microprocessors and not even the need of computers and processors that normally are needed to generate a matrix of pixels.
Photolurninescent displays have a similar performance to cathode rays tubes, while the former need a high voltage for working mainly due to a long light retention time the latter work with low voltages making possible the building of matrixes for the reproduction of images however with a shorter retention time. According to the patent PI 9802700-0 for a better emission of the brightness of the phosphor and therefore for better images generated on the photolurninescent matrix it is necessary a considerable increase of the tension on the electrodes of the photolurninescent matrix which it becomes unfeasible in practice when there is a large number of pixels (something around 90,000 for the monochromatic version that is 300x300 pixels) and this because the retention time becomes also very high once the analog system for the matrix control is similar to conventional kinescopes.
This problem can be solved by adding a series of transversal crates and a sole cathode system with a high tension with the objective of producing a final acceleration of the electron thus increasing the light retention time. However the cost of production as well as the complexity of the matrix are higher and the results are not totally satisfactory, furthermore this additional condition regards only the matrix and not the analog command.
A way for obtaining an excellent light retention time on photolurninescent matrixes is by a parallel scanning, in other word doing in a way that the duty cycle or the enabling time in percentage be not much below the 1/250, which is far from the 90,000 of the conventional kinescopes.
The vertical parallel scan system is the materialisation of a concept that applied to the analog control makes possible to increase the retention time of any type of photolurninescent matrix.
This concept consists on the principle that the image scanning system is horizontal, that is the image is plotted from left to right by means of lines that will form a frame of the image. This same analog principle requires different times to form a line or an image frame being obvious that to form an image frame takes much longer than to form an image line. This plotting time differential only allows for a horizontal parallel scanning if all the pixels of the frame are memorised which makes the system very expensive and very complex. The proposal is of different optic with a parallel vertical scanning; this system does not need to memorise for example all the 90,000 pixels of the framed image but only about 250 to 300 pixels of only one image line in a memorising binary; are presented herein the improvements that add a bivalent memory system that may be digital or analog controlled by the horizontal video signal synchronism or columns enabling synchronism, this system consists of the arrangement of a number of switches and other components for the construction of memory cells in a way that with these memory cells be established in two memory banks interconnected in a way so as to create the PARALLEL VERTICAL SCANNING SYSTEM; these such interconnected banks are used both for registering the video information that need to be plotted in a matrix line as well as in a second moment restore such line pattern for the sequential output that enable the matrix columns to be converted into an array of video output adequate to the polarisation of all the elements of the image of the matrix line during the same time lapse, in a way that the enabling time of the luminosity device of the matrix is now multiplied by the number of columns of the matrix.
For better understanding the invention patent named PARALLEL VERTICAL SCANNING SYSTEM we are hereby describing it in detail making reference to the annexed drawings.
Drawing 1 shows a general view of the matrix being controlled by two sequential distribution devices called PARALLEL VERTICAL SCANNING SYSTEM.
Drawing 2 shows a detailed view of the analog memory cell. Drawing 3 shows a memory bank and the array of memory cells within the bank with single control for the video input.
Drawing 4 shows the interconnection of the two memory banks foπning one single system.
This invention patent report presents the improvement over the patent PI 9802700-0 of 11th August 1998 the so called PARALLEL VERTICAL
SCANNING SYSTEM. Each memory cell (1) is constituted by a switch (2) that controls the input (4) of a video signal for this, through the input command (11) when the switch (2) is commuted, be stored as tension in a capacitor (3) being then memorised analogicaly the tension level of the signal at he input switch (4) of the switch (2). To activate satisfactorily the luminosity devices using the tension level stored in the capacitor memory (3) it is used an operational amplifier (6) configured as non inverter of tension with high input impedance and low output impedance. For the control of the output signal of the operational amplifier (6) it is used a switch (7) that will only switch the output (8) through the output command (9). The memory bank (10) is then composed of an array of memory cells (1) arranged so that the output commands (9) of the memory cells (1) are connected in parallel composing the output control of the bank (12). The video inputs (4) of the memory cells (1) also connected in parallel, are controlled by means of a bank switch (13) that only allows the access of the video input signal (14) when the switch (13) is activated by the video command of the bank (15). The input command (11) of each memory cell (1) will produce a sequence of inputs (18) on the memory bank (10); the output (8) of the memory cells will produce the sequence of output (19) of the memory bank (10). The PARALLEL VERTICAL SCANNING SYSTEM (16) is composed of two memory banks (10) and a flip-flop system (17) connected so that the input commands (18) and the output commands (19) of both memory banks (10) be connected in parallel. The video command (15) of one bank is connected with the output control (12) of the other bank. The video control (15) and the output command (12) are respectively connected to the "S" output (20) and "S-" (21) of the flip-flop (17). The video inputs (14) of both memory banks (10) are connected in parallel and produce the video input (22) of the PARALLEL VERTICAL SCANNING SYSTEM (16). The clock input (23) of the flip-flop (17) produces the synchronism input (24) of the PARALLEL VERTICAL SCANNING SYSTEM (16). The input sequence (18) of both the memory banks (10) that are connected in parallel, will constitute the input sequences (25) of the PARALLEL VERTICAL SCANNING SYSTEM (16), in the same way the output sequences (19) of the two banks that are also in parallel will constitute the output sequences (26) of the PARALLEL VERTICAL SCANNING SYSTEM (16). When the PARALLEL VERTICAL SCANNING SYSTEM (16) is energised the output (20) of the flip-flop (17) adopts the logical status "0" or "1", as a consequence the refused output (21) adopts the opposite status "1" or "0", this way while one memory bank (10) is memorising data of one video line the other one will be providing video data at the output sequence (26).

Claims

CLAIM
CHANGES INTRODUCED ON MATRIX ANALOG SYSTEM FOR THE REPRODUCTION OF IMAGES.
Characterised for containing electronic devices such as electronic switches, capacitors and other components arranged as discreet components or rniniaturised as a single chip to constitute a device called PAR AT T FT, VERTICAL SCANNING SYSTEM (16). Device this that can produce the vertical scanning needed for the reproduction of video images on photoluminescent pixel matrixes with a low duty cycle. This configuration of analog memory cells(l) controlled in a way as to memorise horizontal lines of an image ad reproducing it as a group of vertical parallel lines.
PCT/BR2001/000037 2000-02-12 2001-03-27 Changes introduced on matrix analog system for the reproduction of images WO2001073739A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001243973A AU2001243973A1 (en) 2000-03-28 2001-03-27 Changes introduced on matrix analog system for the reproduction of images

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US76287600A 2000-02-12 2000-02-12
BRPI0000932-6 2000-03-28

Publications (1)

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WO2001073739A1 true WO2001073739A1 (en) 2001-10-04

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485380A (en) * 1981-06-11 1984-11-27 Sony Corporation Liquid crystal matrix display device
EP0362948A2 (en) * 1988-10-07 1990-04-11 Philips Electronics Uk Limited Matrix display device
US5301031A (en) * 1990-01-23 1994-04-05 Hitachi Ltd. Scanning conversion display apparatus
EP0678848A1 (en) * 1994-04-22 1995-10-25 Sony Corporation Active matrix display device with precharging circuit and its driving method
JPH0990894A (en) * 1995-09-28 1997-04-04 Toshiba Corp Matrix display device
JPH10198321A (en) * 1997-01-10 1998-07-31 Sony Corp Active matrix display device
JPH10268833A (en) * 1997-03-26 1998-10-09 Hitachi Ltd Time-division signal processing system and matrix display device using the same
WO1999012339A1 (en) * 1997-09-01 1999-03-11 Seiko Epson Corporation A display type image sensor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485380A (en) * 1981-06-11 1984-11-27 Sony Corporation Liquid crystal matrix display device
EP0362948A2 (en) * 1988-10-07 1990-04-11 Philips Electronics Uk Limited Matrix display device
US5301031A (en) * 1990-01-23 1994-04-05 Hitachi Ltd. Scanning conversion display apparatus
EP0678848A1 (en) * 1994-04-22 1995-10-25 Sony Corporation Active matrix display device with precharging circuit and its driving method
JPH0990894A (en) * 1995-09-28 1997-04-04 Toshiba Corp Matrix display device
JPH10198321A (en) * 1997-01-10 1998-07-31 Sony Corp Active matrix display device
JPH10268833A (en) * 1997-03-26 1998-10-09 Hitachi Ltd Time-division signal processing system and matrix display device using the same
WO1999012339A1 (en) * 1997-09-01 1999-03-11 Seiko Epson Corporation A display type image sensor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN *

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