WO2001067496A1 - Method for opening key patterns on semiconductor - Google Patents

Method for opening key patterns on semiconductor Download PDF

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Publication number
WO2001067496A1
WO2001067496A1 PCT/KR2001/000287 KR0100287W WO0167496A1 WO 2001067496 A1 WO2001067496 A1 WO 2001067496A1 KR 0100287 W KR0100287 W KR 0100287W WO 0167496 A1 WO0167496 A1 WO 0167496A1
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WO
WIPO (PCT)
Prior art keywords
etchant
injection tube
opaque layer
wet
pattern
Prior art date
Application number
PCT/KR2001/000287
Other languages
French (fr)
Inventor
Young Il Jang
Willy Eom
Original Assignee
Sambon Tlg Co., Ltd.
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Publication date
Application filed by Sambon Tlg Co., Ltd. filed Critical Sambon Tlg Co., Ltd.
Priority to AU2001237740A priority Critical patent/AU2001237740A1/en
Publication of WO2001067496A1 publication Critical patent/WO2001067496A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/16—Acidic compositions
    • C23F1/20—Acidic compositions for etching aluminium or alloys thereof
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/16—Acidic compositions
    • C23F1/26—Acidic compositions for etching refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Definitions

  • the key open etching process which can disclose the key pattern hidden below the opaque material layer , forms following six steps: 1) photosensitive resist coating process 2) key open mask exposure process 3) development process 4) key open etching process 5) photosensitive resist strip process and 6) post- etching cleaning process.
  • FIG. 1 shows cross sectional view of prior process for opening key pattern.
  • Fig. 2a through fig. 2c show another embodiment of opening key pattern process in the prior semiconductor process.
  • Fig. 3 shows layout of the contact hole and bit line in fig. 2
  • the etchant injection tube according to the present invention should not be etched with wet etchant and worn away from frequent contacts on the pattern of the semiconductor substrate. Because of this reason, it is preferable that the etchant injection tube is made of at lease one of materials such as diamond, cubic boron nitride (c-BN), sapphire, Teflon, polyethelene, polypropylene, acetal and so on.
  • materials such as diamond, cubic boron nitride (c-BN), sapphire, Teflon, polyethelene, polypropylene, acetal and so on.
  • the interval for this should be maintained precisely.
  • height of the pattern is measured by use of laser displacement sensor or focused by a camera.
  • the interval between the etchant injection tube and the pattern is 10 um to 1mm, which is related to diameter of tip of the etchant injection tube.
  • Fig. 7 illustrates peripheral system construction for explaining movement of a wafer to be partially wet etched.
  • a plurality of wafers are placed in wafer cassette 210, and wafer handler 230 is used to put out wafer to be inspected, and the wafer is loaded in precise location by use of wafer aligner 220, and the wafer is placed on the process stage 190.
  • Fig. 8 shows an apparatus for partially wet-etching semiconductor circuit used for carrying out the present invention.
  • the apparatus for partially wet- etching semiconductor circuit is comprised of process stage 190 which moves a wafer 1 in the X and Y directions, which is placed on the apparatus; etchant cartridge 110 which stores etchant; etchant injection tube 30 which injects etchant on certain part of semiconductor substrate; means for holding the etchant cartridge 120; z axis moving bar 130 which is connected with the means for holding etchant cartridge 120 and main body 150 of the apparatus for wet etching; z axis moving motor 140 which moves the z axis moving bar 130; means for holding and moving process stage 170; x & y axis moving motor 160 which drives means for holding and moving process stage 170.
  • wet etchant In performing the process for opening key patterns by using wet etchant suggested by the present invention.
  • hard mask oxide film (Si02) is wet etched, the line/space layer of the lower layer is not etched but hard mark oxide layer to be inspected is etched. Because of this reason, it is preferable that wet etchant with HF and H20 included is used as a wet-etchant.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Weting (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present invention relates to methods for opening key pattern, and more particularly, to opening methods that can etch an opaque part formed on key pattern by injecting wet etchant using narrow and hollow tube with nanometer or micrometer diameter. The present invention reduces the number of processing steps for opening key patterns.

Description

TITLE OF INVENTION
METHOD FOR OPENING KEY PATTERNS ON SEMICONDUCTOR
TECHICAL FIELD
The present invention relates to a method for opening key patterns on semiconductor, and more particularly, to the method that etches partial area on the semiconductor substrate by injecting wet etchant' using narrow and hollow tube in nanometer or micrometer diameter.
BACKGROUND ART
The common problem encountered in the photomasking process, one of processes in manufacturing semiconductor wafers, is irregularity of the key pattern aligning between the upper and the lower layer.
Chemical-mechanical polishing, or CMP, which is a commonly used method in process of planarizing wafers, particularly, in manufacturing a semiconductor device above 64 mega dynamic random access memory (DRAM), involves the chemical etching of a surface while also mechanical grinding or polishing it. However, while very useful in a particular process of planarizing wafers, CMP can complicate matters in the manufacture of semiconductor wafers, such as irregularities of the align key pattern between the upper and the lower layer. After CMP action there are times when materials, such as polysilicon or conductor metals, that are opaque to the observing beam are deposited over polished flat wafers. In that case, the align key pattern is hidden below the opaque material layer and cannot be reckoned by the alignment system. To solve the problem cited above, in prior art, called optical lithography, light is used to etch partially patterns on a semiconductor substrate. For example, in case opaque materials are deposited over regions of the key pattern in the process of planarizing semiconductor wafers, the key open etching process, which can disclose the key pattern hidden below the opaque material layer , forms following six steps: 1) photosensitive resist coating process 2) key open mask exposure process 3) development process 4) key open etching process 5) photosensitive resist strip process and 6) post- etching cleaning process.
The prior key open etching process is shown in FIG. 1. In FIG. la, there is shown a state of nitride film 20 having been chemical-mechanical polished after a device separating process in the prior manufacturing process of semiconductor wafers. On the semiconductor wafer 10 oxide film 30 are layered in the key pattern and nitride film 20 remains in theirs intervals. In FIG. lb, there is shown a state of having been gotten rid of nitride film. In FIG. lb, there is shown a state of having been equipped with a key open mask to remove the oxidized film layered in the key pattern. If the prior art, called optical lithography, is made use of to remove the oxidized film layered in the key pattern as shown in FIG. lb, after six steps cited above that is: 1) photosensitive resist coating process 2) key open mask exposure process (shown in FIG. lc) 3) development process 4) key open etching process 5) photosensitive resist stript process and 6) post- etching cleaning process, are gone thorough the key pattern is exposed as shown FIG. 1 d.
Another prior key open etching process is shown in from FIG. 2a to FIG. 2c. In FIG. 2a, there is shown a state of being layered polysilicon, tungsten siliside, and hard mask oxidized film one after another to form a gate 13 on the silicon wafer after form the field oxidized film on the said silicon wafer. And then form nitride space in the side of a said gate and after that apply the oxidized film. And then form a bit line contact hall by using a lithography method and after that form a bit line by filling up contact hall with metal. And then apply second oxidized film on the said bit line and after that form a contact hall by using a lithography method. In this case a bit line and poly 3 contact are in state of being insulated because they keep apart each other. And then fill up said contact hall with poly 3 contact poly plug; after that planarizing wafers by chemical-mechanical polishing or etching; after that apply nitride 25; after that layer a thick capacitor oxidized film; after that apply a poly hard mask on the capacitor oxidized film for a mask process. Therefore key patterns are hidden, at this time, must go through following steps to open key patterns: 1) coating the photosensitive resist; 2) exposing the key open mask; 3) developing; 4) opening the opaque polysilicon film to open key patterns; 5) removing the photosensitive resist; 6) cleaning. After key patterns opening process cited above and etching the capacitor oxide film, finally form the capacitor as polysilicon.
According to a prior process cite above, there is a problem that the process turn around time (TAT) is long because a lithography method is used for opening key patterns.
DISCLOSURE OF INVENTION
It is an object of the present invention to provide a method for opening key patterns on semiconductor to solve the above described problems.
The above object can be accomplished by the first embodiment of a method for opening key patterns on a semiconductor by removing an optic opaque layer piled on upper part of key patterns which used for aligning in a semiconductor process, said method comprising steps of, placing an etchant injection tube on an optic opaque layer which piled on a upper part of said key pattern; injecting wet etchant on said opaque layer; injecting de-ionized water on said opaque layer; and removing said de-ionized water which diluted with said wet etchant, wherein said optic opaque layer is selectively etched.
The above object can also be accomplished by the second embodiment of a method for opening key patterns by removing optic opaque layer piled on upper part of said patterns which used for aligning in a semiconductor process, wherein said opaque layer formed on said upper part of key patterns is selectively etched and removed by using an etchant injection tube with wet etchant inside and a certain size of diameter.
BRIEF DESCRIPTION OF DRAWINGS
The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Fig. 1 shows cross sectional view of prior process for opening key pattern. Fig. 2a through fig. 2c show another embodiment of opening key pattern process in the prior semiconductor process. Fig. 3 shows layout of the contact hole and bit line in fig. 2
Fig. 4a through fig. 4b shows cross sectional view of the key pattern opening process by using the etchant injection tube after removing nitride film according to one embodiment of the present invention.
Fig. 5 illustrates the pattern analysis according to the present invention. Fig. 6 shows cross sectional view of the etchant injection tube according to the present invention.
Fig. 7 shows construction of peripheral system to explain movement of a wafer to be partially wet etched.
Fig. 8 shows construction of an apparatus for wet-etching semiconductor circuit to carry out the present invention.
Fig. 9 shows flowchart explaining a method for inspecting pattern of the present invention.
Fig. 10 is a view illustrating the reason for key 'pattern etching in the process for forming capacitor oxide film according to the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
Fig. 4a shows the process of fig. 1 (b) after removing nitride film, which is a cross sectional view on the key pattern opening etching process.
As shown in fig. 4a, after removing the nitride film, etchant 70 is injected out of the etchant injection tube 60 in nanometer or micrometer size and high density plasma oxide is removed to form the key pattern. The etchant 70 is put out on part of oxide film of the key pattern so that the part of the key pattern is etched.
Fig. 4b shows that the oxide film which is opaque film is removed by use of the etchant injection tube of the present invention. As shown in fig. 4b, the etchant 70 is injected out of the etchant injection tube 60 in nanometer or micrometer size on oxide part to be wet-etched, and it is possible to open key pattern 50 by wet etching just one time.
Fig 5 illustrates a method for partially wet etching the pattern according to the present invention, (a) shows that a plurality of stream-shaped oxide films 2 are formed on the semiconductor substrate 1. It is preferable that a wafer is 6 to 12 inches in size. It is shown that a plurality of oxide films are formed in large interval on a portion of the semiconductor substrate in (a) of Fig. 5, but this is an enlarged figure for explanation. Actually, a plurality of oxide films are formed at nanometer or micrometer interval. According to the present invention, etchant 70 is contacted on the pattern, out of the nanometer or micrometer sized etchant injection tube 60 to inspect that the pattern of oxide films is properly formed. Part of pattern which is to be analyzed is etched on the semiconductor substrate and the pattern may be easily inspected without damaging the whole semiconductor substrate, as shown in (b) of Fig. 2. Fig. 6 shows cross-sectional view of the etchant injection tube of the present invention, (a) shows longitudinal section of the etchant injection tube. The injection tube gets narrow down to its end part, (b) shows cross section of body of etchant injection tube, and (c) shows enlarged sectional view of ending part of the etchant injection tube. The ending part of the etchant injection tube is 10 nm to 1 mm in diameter as shown in (a) and (c).
The etchant injection tube according to the present invention should not be etched with wet etchant and worn away from frequent contacts on the pattern of the semiconductor substrate. Because of this reason, it is preferable that the etchant injection tube is made of at lease one of materials such as diamond, cubic boron nitride (c-BN), sapphire, Teflon, polyethelene, polypropylene, acetal and so on.
A method for injecting a small amount of etchant selectively on specific area is used to prevent wafer loss for pattern inspection and time delay needed for inspection. In detail, etchant is contacted vertically on the pattern by use of the etchant injection tube in nanometer or micrometer size, and the pattern is etched in vertical direction, and the etched section is inspected. Inspection can be made very fast through this partial wet etching method, and the rest part of a wafer except the part to be inspected can be used. It will prevent a wafer from being lost and result in cost-down effects.
The reason for prevent of wafer loss and cost down is that the inspection operation may be performed in the clean room under the high temperature and high pressure condition, and only small area of pattern is etched so that the inspection does not affect the rest area of the pattern on a wafer except area to be etched and circuit characteristics.
There are two different method for contacting etchant out of the etchant injection tube on pattern formed on a substrate of a semiconductor. One is a contact method in which the etchant injection tube is directly contacted on a substrate and the etchant is sprayed. The other is non-contact method in which the etchant injection tube is not contacted but only the etchant is contacted. According to the contact method, the etchant injection tube is directly contacted on the substrate, and the surface of the etchant in the nanometer or micrometer sized tube maintains concave shape, under the capillary phenomenon caused by surface tension of wet etchant. Before it begins etching, the etchant may not be contacted on a wafer. And then it starts etching the pattern by putting pressure on the etchant, putting pressure on surface of etchant which is located the other side of part to be etched, or increasing the temperature and bulk of etchant. According to the second method, the etchant is put out of the etchant injection tube in the same or similar way to the contact method. And the etchant maintains the state in which it clings to the tip of the injection tube in a hemisphere shape. In detail, it is a state from the moment a drop of the etchant starts to come out of the tip of the injection tube by surface tension phenomenon till the drop falls down. In this way, only the etchant is contacted on the substrate.
In the non-contact method, because it is important that only the etchant is contacted on the pattern but the etchant injection tube should not, the interval for this should be maintained precisely. And for maintaining precise interval, height of the pattern is measured by use of laser displacement sensor or focused by a camera. And it is preferable that the interval between the etchant injection tube and the pattern is 10 um to 1mm, which is related to diameter of tip of the etchant injection tube.
Fig. 7 illustrates peripheral system construction for explaining movement of a wafer to be partially wet etched. As shown in fig. 4, a plurality of wafers are placed in wafer cassette 210, and wafer handler 230 is used to put out wafer to be inspected, and the wafer is loaded in precise location by use of wafer aligner 220, and the wafer is placed on the process stage 190.
Fig. 8 shows an apparatus for partially wet-etching semiconductor circuit used for carrying out the present invention. The apparatus for partially wet- etching semiconductor circuit is comprised of process stage 190 which moves a wafer 1 in the X and Y directions, which is placed on the apparatus; etchant cartridge 110 which stores etchant; etchant injection tube 30 which injects etchant on certain part of semiconductor substrate; means for holding the etchant cartridge 120; z axis moving bar 130 which is connected with the means for holding etchant cartridge 120 and main body 150 of the apparatus for wet etching; z axis moving motor 140 which moves the z axis moving bar 130; means for holding and moving process stage 170; x & y axis moving motor 160 which drives means for holding and moving process stage 170. The z axis moving bar 130 may move in the x, y and z axis, and the process stage 190 may move in the x, y and.z axis while the process stage or the z axis moving bar 130 is fixed. The apparatus for partially wet etching semiconductor circuit is placed in the chamber separated by vertical separation wall 180. Wafer moves to inside chamber and is placed on the process stage 190 by use of the robot arm 240. The etchant injection tube 30 is placed on area to be wet etched by driving x & y moving motor 160 and z axis moving motor 140. The etchant should not be contacted on a wafer to be etched until it starts etching. The etchant is ejected out of the etchant injection tube by putting pressure on the etchant directly or the other side of the etchant or by use of means for increasing temperature of the etchant (means for transferring heat which is connected with means for increasing temperature 200 in Fig. 5 and the etchant cartridge or the etchant injection tube)
Fig. 9 is a flowchart showing a method for inspecting pattern according to the present invention. The substrate of a semiconductor is loaded on the apparatus, on which pattern to be inspected is formed SI . Inspection point is designated and nanometer sized etchant injection tube moves to the inspection point S2. In this case, the substrate of a semiconductor may move instead of the etchant injection tube. The etchant is put out on location to be inspected for wet etching S3. De-ionized water is injected at the next step S4. If etchant remains on the surface of a wafer, the pattern keeps being etched. The de-ionized water injection will dilute the etchant and control the extent of pattern's being etched.
In this case, it is preferable that the amount of de-ionized injection is 1 to 100 times more than that of the etchant. And then, de-ionized water injected is sucked. S5 This step is needed to remove chemical residue on the pattern by using difference in pressure. Finally, the substrate which is partially wet-etched is unloaded from the apparatus S6. In accordance with these steps, inspection for shape of the etched pattern may be easily processed, after partial etching of pattern.
Fig. 10 is a view illustrating the reason for key pattern etching in the process for forming capacitor oxide film according to the present invention.
Nitride layer is formed on upper area of key patterns, and very thick capacitance oxide layer (12000 angstrom) is formed on upper area, and polysilicon opaque layer is formed on it. Because key patterns in lower area are not optically recognized it causes a problem that the construction is not exactly aligned.
Conventionally, 6 step process using lithography method is performed to open key patterns to solve the above problem. Key patterns can be open by using the process for partial wet etching according to the present invention.
According to the method for opening semiconductor key patterns of the present invention, chemical and mechanical polishing process is performed after isolation during semiconductor manufacturing process. In case the key patterns are buried, the buried key patterns does not proceed to the conventional lithography 6 step process but can be open by one step process in which the etchant injection tube in nanometer or micrometer size is used for injecting wet etchant.
In performing the process for opening key patterns by using wet etchant suggested by the present invention. In case hard mask oxide film (Si02) is wet etched, the line/space layer of the lower layer is not etched but hard mark oxide layer to be inspected is etched. Because of this reason, it is preferable that wet etchant with HF and H20 included is used as a wet-etchant.
HF is used to etch the hard mask oxide layer. In this case, the ratio of water to HF is preferably 10: 1 to 100: 1. If HF which is more than 10: 1 is used, it is etched down to the line/space layer of lower layer. And if ratio of HF: H20 is less than 100:1, it will not etched.
When polysilicon pattern is etched, which is formed on oxide layer in between lower layers, the oxide layer in between lower layers is not etched but polysilicon to be inspected is etched. Because of this reason, it is preferable that wet-etchant having HN03 and HF in should be used. HN03 oxidizes polysilicon, and HF etches polysilicon. In this case, the ratio of HN03 to HF is preferably 50: 1 to 1000: 1. If the ratio of HN03 to HF is more than 50:1, it is etched down to oxide layer in between layers in lower layer. And if ratio of HN03 to HF is less than 1000 : 1 , it cannot be etched.
When tungsten pattern is etched, which is formed on oxide layer in between lower layers, the oxide layer in between lower layers is not etched but tungsten to be inspected is etched. Because of this reason, it is preferable that wet-etchant having HN03 and HF in should be used. HN03 oxidizes tungsten, and HF etches polysilicon. In this case, the ratio of HN03 to HF is preferably 1 : 1 to 100: 1. If the ratio of HN03 to HF is more than 1 : 1, it is etched down to oxide layer in between layers in lower layer. And if ratio of HN03 to HF is less than 100: 1, it cannot be etched.
When aluminum pattern is etched, which is formed on oxide layer in between lower layers, the oxide layer in between lower layers is not etched but aluminum to be inspected is etched. Because of this reason, it is preferable that wet-etchant having H3P04 and HN03 should be used. H3P04 oxidizes aluminum, and HN03 etches it. In this case, the ratio of H3P04 to HN03 is preferably 1 : 1 to 100: 1. If the ratio of H3P04 to HN03 is more than 1 :1, it is etched down to oxide layer in between layers in lower layer. And if ratio of H3 P04 to HN03 is less than 100 : 1 , it cannot etched.
INDUSTRIAL APPLICABILITY
According to the method for opening key patterns on semiconductor of the present invention, key opening process can be reduced to 1 step process by using the etchant injection tube in nanometer or micrometer diameter from the conventional 6 step process by lithography. The align fail problem which is occurred in the photo mask process by optic opaque thin film formed on the upper part of key pattern can be solved by partial wet etching by use of the etchant injection tube. The process for opening the align key pattern necessary for the photo mask process can be reduced to one step etching process from the conventional 6 step process by lithography. The present invention makes TAT (turn around time) to be reduced and results in reduction in cost loss
Although the preferred embodiments of the present invention have been described in detail herein, it is to be understood that these descriptions are merely illustrative. The inventive system may be modified in a variety of ways and equivalents in order to suit a particular purpose while still employing the unique concepts set forth.

Claims

ClaimsWhat is claimed is:
1. A method for opening key patterns on a semiconductor by removing an optic opaque layer piled on upper part of key patterns which used for aligning in a semiconductor process, said method comprising steps of, placing an etchant injection tube on an optic opaque layer which piled on a upper part of said key pattern; injecting wet etchant on said opaque layer; injecting de-ionized water on said opaque layer; and removing said de-ionized water which diluted with said wet etchant, wherein said optic opaque layer is selectively etched.
2. The method as in claim 1, said step of injecting said wet etchant further comprising steps of, contacting said etchant injection tube on said opaque layer, while said wet etchant is not put out of said etchant injection tube; and injecting said wet etchant on said opaque layer
3. The method as in claim 1. said step of injecting wet etchant further comprising steps of, exposing said some wet etchant out of said etchant injection tube in convex shape by use of a capillary phenomenon; and contacting said exposed wet etchant on said opaque layer, wherein said wet etchant is injected out of said etchant injection tube, while a tip of said etchant injection tube is not contacted on said opaque layer.
4. A method for opening key patterns by removing optic opaque layer piled on upper part of said patterns which used for aligning in a semiconductor process, wherein said opaque layer formed on said upper part of key patterns is selectively etched and removed by using an etchant injection tube with wet etchant inside and a certain size of diameter.
5. The method as in claim 4, wherein said etchant injection tube is made of at least one of materials selected among diamond, cubic boron nitride and sapphire.
6. The method as in claim 4, wherein said etchant injection tube is made from at least one of polymer materials selected among teflon, polyethelene, polypropylene and acetal.
7. The method as in claim 4, wherein said etchant injection tube is 10 nm through lOOOum in diameter.
PCT/KR2001/000287 2000-02-25 2001-02-26 Method for opening key patterns on semiconductor WO2001067496A1 (en)

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KR2000/0009447 2000-02-25
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KR2000/0012183 2000-03-10
KR1020000012183A KR20010085166A (en) 2000-02-25 2000-03-10 Semiconductor key pattern opening method

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6015760A (en) * 1992-06-15 2000-01-18 Micron Technology, Inc. Method for enhancing oxide to nitride selectivity through the use of independent heat control
US6022766A (en) * 1995-09-29 2000-02-08 International Business Machines, Inc. Semiconductor structure incorporating thin film transistors, and methods for its manufacture
US6043133A (en) * 1998-07-24 2000-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of photo alignment for shallow trench isolation chemical-mechanical polishing
US6054361A (en) * 1999-02-11 2000-04-25 Chartered Semiconductor Manufacturing, Ltd. Preserving the zero mark for wafer alignment

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6015760A (en) * 1992-06-15 2000-01-18 Micron Technology, Inc. Method for enhancing oxide to nitride selectivity through the use of independent heat control
US6022766A (en) * 1995-09-29 2000-02-08 International Business Machines, Inc. Semiconductor structure incorporating thin film transistors, and methods for its manufacture
US6043133A (en) * 1998-07-24 2000-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of photo alignment for shallow trench isolation chemical-mechanical polishing
US6054361A (en) * 1999-02-11 2000-04-25 Chartered Semiconductor Manufacturing, Ltd. Preserving the zero mark for wafer alignment

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KR20010085166A (en) 2001-09-07

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