WO2001048911A2

WO2001048911A2 - Locally-adapted parallel t-spaced linear predistorter

Info

Publication number: WO2001048911A2
Application number: PCT/US2000/033309
Authority: WO
Inventors: Richard Steven Griph; Albert Howard Higashi
Original assignee: Motorola, Inc.
Priority date: 1999-12-28
Filing date: 2000-12-08
Publication date: 2001-07-05
Also published as: AU2073901A; WO2001048911A3

Abstract

A transmission system (58) including an amplifier (22) and a locally-adapted, parallel T-spaced linear predistorter (60). The predistorter (60) includes a plurality of parallel adaptive filters (62-68) that receive a modulated in-phase and quadrature phase signal. A separate sampling input is applied to each adaptive filter (62-68) during a symbol period. For each sampling time input, an error is calculated which corresponds to its position in the eye portion of an eye diagram, and is correlated to a modulator output using a zero-forcing algorithm. The output of each adaptive filter (62-68) is multiplexed sequentially by a multiplexer (70) to provide a predistorter waveform. The predistorter (60) allows independent equalization at each sampling point in the symbol period of the eye portion.

Description

LOCALLY-ADAPTED PARALLEL T-SPACED LINEAR PREDISTORTER

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to a predistorter used in connection with a power amplifier and, more particularly, to a locally-adapted, parallel T-spaced linear predistorter used in connection with a high power amplifier that independently samples the signal at multiple times during a symbol period to invert the analog filtering caused by the amplifier so as to reduce transmission distortions.

Discussion

High power amplifiers (HPA), such as traveling wavetube amplifiers (TWTA) and solid state power amplifiers (SSPA), are typically employed in transmitters used in high data rate communications systems. For example, HPAs are utilized in certain satellite communications systems. These high data rate communications systems typically require a relatively high output power so that the transmitted signal can travel greater distances before attenuation becomes significant. Furthermore, these high data rate communications systems generally use a low frequency digital baseband signal comprising a stream of digital data bits transmitted through modulation onto a high frequency carrier wave. Different modulation schemes have been used to distinguish the digital data bits of low frequency digital baseband signals. For example, amplitude-shift keying (ASK), frequency-shift keying (FSK), binary phase-shift keying (BPSK), quadrature-phase shift keying (QPSK), and quadrature amplitude modulation (QAM) have been utilized to distinguish the digital data bits of low frequency digital baseband signals. However, because digital baseband signals may be multilevel (M-ary) signals requiring multilevel modulation methods, the quadrature modulation schemes are preferable as both complex and imaginary representations of the signal are used to provide both amplitude and phase modulation of the carrier.

The quadrature modulation schemes, such as QAM, convert each bit to a multi- bit symbol representing a complex value having an in-phase (real) component and a quadrature-phase (imaginary) component. The bits are transmitted in groups, and each group is mapped into a constellation pattern. The constellation pattern has multiple points corresponding to the number of transmitted bits, positioned within a circle around the origin of an imaginary axis and a real axis, with the distance from the origin of the imaginary and real axis representing the amount of transmitted power. For example, a group of four bits transmitted at a particular time is represented as sixteen points (2⁴) in the circle. Each point in the pattern identifies a complex voltage value having an in-phase component and a quadrature-phase component of a symbol, and the voltage value for a particular symbol period that is the time period for each symbol transmission. The analog voltage value for each point is used to modulate the carrier wave. The points in the constellation pattern are geometrically spread so that they are equally spaced apart in order to more readily distinguish the points and reduce bit errors. Therefore, as may be appreciated, it is desirable to process the constellation patterns through the transmitter without introducing distortion so that the bits are readily distinguishable from each other at the receiver.

FIG. 1 is an eye diagram with time on the horizontal axis and voltage on the vertical axis. Eye diagrams are used to show the possible transmission paths of a signal through a transmitter, where each line in the eye diagram represents a transmission path for a particular symbol. The lower signal pattern 7 in FIG. 1 illustrates a typical input signal into a high power amplifier, such as a TWTA, that has been filtered by the transmitter hardware before the amplifier and the upper signal pattern 8 illustrates the filtering effects of the HPA due to memory effects. Because the amplifier has memory, the symbol can take on different paths, depending on what symbols were transmitted before the current symbol period. FIG. 1 illustrates that non-linearity of the amplifier will distort the filtered input signal due to its non-constant envelope. The signal patterns shown in FIG. 1 are the complex in-phase and quadrature-phase baseband representations of the RF signal being transmitted through the transmitter. The upper signal pattern 8 in FIG. 1 shows four (4) different fractional time periods T1 -T4 across an eye portion in the diagram. As is apparent, the signal paths at time periods T1 and T4 show a relative wide area for the number of available paths depicting the ISI caused by the filtering of the amplifier. By applying memory predistortion techniques to pinch down the paths in the eye portions of the diagram, the ISI of the amplifier can be reduced, thus limiting the distortion. By pinching the paths in the eye portion of the diagram, the transmission paths of the signals become more like a square wave. Therefore, it should be appreciated that it is desirable to perform additional predistortion techniques beyond memoryless mapping to correct for the filtering effect of the amplifier's memory and the filtering effect of the transmission hardware. The known techniques of memory predistortion have employed inverse filters that invert the filtering of the amplifier for predistortion purposes. In these inverse filtering techniques, the voltage is maintained constant across a symbol period, and a linear predistortion is used that adds some of the adjacent symbols to that particular symbol period. This technique is known as T-spaced predistortion. In the T-spaced predistorter, the bit points that were transmitted at any point in time as a symbol period also included a linear combination of the other symbols transmitted near that symbol period. This technique only reduced the ISI at a single sampling instant during the symbol period, or at a single location in the eye diagram. The linear combination of the voltages at the current symbol period, plus the weighted voltages from previous symbol periods, is maintained constant across the entire symbol period, limiting the ability to generate the desired square-wave. Because the amplifiers that are being used in these applications vary across a symbol period, the T- spaced predistorter is limited in its ability to provide a complete inversion. Additionally, T-spaced predistortion cannot completely invert the input filtering of the amplifier because of the aliasing of the frequency domain caused by the T-spaced structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an eye diagram with time on the horizontal axis and voltage on the vertical axis showing the input and output of a HPA without predistortion; FIG. 2 is a schematic block diagram of a transmitter and receiver system employing a fractionally-spaced predistorter in the transmitter, according to an embodiment of the present invention;

FIG. 3 is an eye diagram showing the input and output to a HPA when using the fractionally-spaced predistortion technique of the invention; FIG. 4 is a graph with frequency on the horizontal axis and gain on the vertical axis showing the filtering and predistorter response generated by the fractionally- spaced predistorter of the invention; FIG. 5 is a schematic block diagram showing a transmitter and receiver system employing a parallel, T-spaced predistorter at the transmitter, according to another method of the present invention;

FIG. 6 is a schematic block diagram showing a more detailed depiction of the adaptive filters used in the parallel, T-spaced predistorter shown in FIG. 5; and

FIGs. 7-10 are four (4) eye diagrams each showing an output from one of the adaptive filters shown in FIG. 6, and the total multiplexed predistortion output for all of the adaptive filters.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following discussion of the preferred embodiment is merely exemplary in nature, and is in no way intended to limit the invention or its applications or uses.

In accordance with the teachings of one embodiment of the present invention, a locally-adapted, fractional-spaced linear predistorter is disclosed that allows transmission of a signal without significant distortion. The linear predistorter provides an inverse of amplifier and transmission hardware filtering to completely cancel the distortion caused by the amplifier and hardware. For quadrature type modulation formats which pass through a memoryless amplifier without distortion, the optimum predistorter to filter the data prior to the amplifier is an inverse filter which cancels the filtering of the amplifier. The combined effect is to create a data output of the amplifier which approaches a square-wave. The desired square-wave format is achieved by calculating an error at multiple points in the eye portion of an eye diagram, and correlating the error with the modulated waveforms using a zero-forcing algorithm. This forces the eye portions to be more open at multiple points.

FIG. 2 is a block diagram of a communications system 10 including a transmitter 12 employing a fractionally-spaced predistortion technique, according to one embodiment of the present invention. A digital data stream at a baseband frequency is sent to a modulator 14 that provides quadrature modulation by modulating the bits onto an analog carrier wave. In this process, the modulator 14 identifies a symbol for each bit that includes an in-phase and quadrature-phase component, and maps the symbols into a constellation pattern, as previously discussed. The modulated signal has an analog voltage for each symbol to be transmitted. The modulator 14 can be any suitable quadrature modulator for the purposes described herein, as would be apparent to those skilled in the art.

According to this exemplary embodiment of the present invention, the modulated bits that are mapped into the constellation pattern by the modulator 14 are rearranged by a locally adapted, fractionally-spaced predistorter 16. What is meant by "fractionally spaced" is that the predistorter 16 performs multiple calculations during each symbol period so that the ISI is reduced at a plurality of locations during that period. As will be discussed in more detail below, the predistorter 16 receives voltage input signals from a predistorter update 18 as an input to set the pattern. The predistorter update 18 receives the amplified signal that has been distorted by an amplifying device 20.

The predistorter 16 is an inverse filter that changes the linear combination of various points in the constellation pattern by performing a weighted sum on the points to change the complex voltage value from the modulator 14. The predistorter 16 can be a linear finite impulse response (FIR) or infinite impulse response (MR) filter. For example, the predistorter 16 can employ a tapped delay-line digital filter to provide the digital filtering. The weighted sum is based on the voltage of previous and future symbols that have already been transmitted. This inverse filtering adjustment predistorts the constellation pattern representing the complex signal so that when the distortion from the amplifying device 20 occurs, the signal is actually in a desirable undistorted state for transmission. In this embodiment, the predistorter 16 is positioned after the modulator 14, and acts as an analog type predistorter. However, the predistorter 16 can be a digital predistorter that operates on the digital baseband bits from the modulator 14. For example, the modulator 14 can output digital bits that have been modulated, where the predistorter 16 operates on the digital bits and a digital-to- analog converter (not shown) after the predistorter 16 can provide the digital to analog conversion.

In this embodiment, the amplifying device 20 includes a HPA 22 that acts as a power amplifier. A filter 24 in the amplifying device 20 represents the filtering effect of the HPA 22 that is to be inverted by the predistorter 16. The intentionally distorted signal from the predistorter 16 is shown being applied to a pre-HPA filter 26. The pre- HPA filter 26 represents the filtering effect of the hardware in the transmitter 12 before the HPA 22. The RF signal from the modulator 14 that is predistorted by the predistorter 16 is at a baseband frequency, and thus needs to be upconverted to a higher frequency for transmission. To perform this upconversion, a mixer 28 is provided where the baseband frequency is mixed with a higher frequency signal, cosω_ct. In the mixer 28, the in-phase and quadrature-phase representations of the complex voltage from the modulation process are converted to a single high frequency RF signal. The predistortion technique of the present invention can also be done at an RF frequency, where the predistorter 16 would be located after the mixer 28. The upconverted RF signal is then applied to the amplifying device 20 that significantly increases its gain for transmission. The operation of the mixing step and amplification step in a transmitter of this type is well understood to those skilled in the art.

The upconverted, amplified signal from the amplifying device 20, that has been distorted back to its desirable pattern, is applied to an RF filter 30 for subsequent RF filtering in order to put the high power signal in conformance with FCC requirements, and then to an antenna (not shown) for transmission. The amplified signal from the amplifying device 20 is also applied to the predistorter update 18 from a test point 32 after the amplifying device 20. A suitable power coupler (not shown) would be provided at the test point 32 to remove a small portion of the high power signal from the HPA 22. Any type of suitable power splitter can be used to split the signal at a test point 32 to send a portion of the signal to the predistorter update 18.

The predistorter update 18 is continually providing a voltage signal to the predistorter 16 to make adaptive changes in the arrangement of the constellation pattern to invert the filtering caused by the HPA 22, which changes over time. It is necessary to provide this type of test of the amplified signal because it is not possible to measure the filtering generated by the HPA 22.

The signal is broadcast across a channel 38 to a receiver 40. The signal is received in the receiver 40 by an antenna (not shown) of the receiver 40 that applies a signal to a receiver filter 42. The receiver filter 42 provides initial filtering of the received signal, for filtering channel noise and the like, and is typically closely matched to the transmitted signal. The receiver filter 42 rejects thermal noise and allows optimal reception. A mixer 44 downconverts the RF signal to an intermediate frequency signal. The downconverted signal from the mixer 44, that includes the baseband in-phase and quadrature-phase components, is applied to a low-pass filter 46 to provide filtering at baseband frequencies. The receiver filter 42 typically acts as a course filter, and the low-pass filter 46 acts as a fine filter.

The filtered baseband signal from the filter 46 is applied to a linear equalizer 48 that removes the ISI from transmission of the signal through the channel 38. This ISI can also come from the receiver filter 42 and the low-pass filter 46. The linear equalizer 48 typically includes a tapped delay line filterwhere the taps are adjusted by a data estimator 50. The data estimator 50 takes the voltage represented by the in- phase and quadrature-phase values, and converts it to bits. The data estimator 50 can use any suitable algorithm to perform this function, such as zero-forcing algorithm. The data estimator 50 makes a measurement of the bit locations, and generates an estimate of the error between the actual bit locations and the desired bit locations. That is, the data estimator 50 gives an error correction between the constellation pattern it did receive and the constellation pattern that it should have received. An equalizer update signal is sent from the data estimator 50 to the linear equalizer 48 to provide a filter correction therein to achieve the desired constellation pattern based on the error calculation. Linear equalizers of the type being discussed herein that reduce ISI in received signals and use zero-forcing algorithms, are known in the art.

FIG. 3 shows an eye diagram having lower signal pattern 72 and upper signal pattern 74 for the input paths of the baseband. The lower signal pattern 72 represents the complex signals entering the amplifying device 20, and the upper signal pattern is a representation of the amplified signal from the amplifying device 20. A significant improvement of the widening of the eye portion can see by comparing the upper signal pattern 74 of FIG. 3 to the upper signal pattern 8 of FIG. 1. Furthermore, the lower signal pattern 72 of FIG. 3 has less ISI than the lower signal pattern 7 of FIG. 1 as a result of the predistortion generated by the predistorter 16. This predistortion translates into an inverse of the filtering of the HPA 22, which narrows the paths across the eye portions in the upper signal pattern.

Known equalizers and predistorters typically employ an algorithm that is only interested in adjusting the eye diagram by reducing the ISI where the eyes are most open. This is the location between times T2 and T3. The algorithm typically samples the signal at that single point and generates a data estimate and an error estimate, where the error estimate is representative of the ISI at that point in time. A zero-forcing algorithm is then used to remove the ISI at that time period based on the error estimate. According to the invention, the ISI is removed across the entire eye portion in the eye diagram. In other words, the eye portion is not pinched at a single location to remove the ISI, but is pinched at several locations to make the eye diagram more of a square wave. This is accomplished by adjusting the taps in the tap filter at several locations. As mentioned above, the predistortion technique of the present invention provides distortion sampling at multiple locations across the eye portion for each symbol period, for example, the four (4) locations represented by time T1-T4. Of course, other fractional periods can also be used. The predistorter 16 outputs a value for each sub-period in the symbol period that is a linear sum of the sub-symbols that are around that sub-period. The predistorter 16 generates a series of linear equations for each sub-period, and solves those equations to reduce the ISI. From these equations, the predistorter 16 generates an error signal that is a voltage representation of the difference between the desired or ideal voltage and the voltage at that sub- period. The error calculations are determined across the eye portion by doing correlations between the error signal and the baseband signal. Various algorithms can be used to perform this process, such as the zero-forcing algorithms that are used in the equalizers. The zero-forcing algorithms multiplies the complex in-phase and quadrature-phase components by a complex coefficient, and sums them to generate a finite impulse response. By performing these calculations across various symbol periods, the tap filter can be adjusted to provide the desirable distortion.

Once a square wave is achieved, the filtering effect is inverted. Then, the only thing left is the memoryless, non-linear filtering effect in the HPA 22. In other words, by forcing the eye diagram to be more like a square wave in function, there is only a single output voltage for that symbol period, which can be changed using a memoryless mapping function.

FIG. 4 is a graph with frequency on the horizontal axis and amplifier gain on the vertical axis that shows that the predistorter 16 does in fact invert the filtering caused by the HPA 22. The bottom graph line 52 is the filter response generated by the HPA 22, and the top graph line 54 is the filter response generated by the predistorter 16. As is apparent, by adding the two graph lines 52 and 54 together, the combined line will go substantially flat at zero gain overly a fairly wide frequency band.

For the embodiment discussed above, it is assumed that the HPA 22 operates like a filter cascaded with memoryless non-linearity. If the HPA 22 did operate exactly like this model, then the predistortion technique discussed above would more completely invert the filtering effects of the HPA 22. However, the HPA 22 may not always act exactly like a cascaded filter having memoryless non-linearity. Further, as is apparent by FIG. 4, the filtering response has a lot of attenuation (beyond 16dB) within the desired bandwidth. Therefore, the inverse filter generated by the predistorter 16 has to have a lot of gain, which means that it has to have a high Q factor to provide the inversion. Thus, there are hardware restrictions in building a predistorter that actually has this much gain. Herefore, the discussion above of generating an inverse of the filtering in the HPA 22 by reducing the ISI across the eye portion can be extended to an inverse filtering technique that improves the degrees of freedom of the filtering, according to another embodiment of the present invention.

Due to the high gains and high Q factors, the inverse filter being adaptively generated is difficult to synthesize. This difficulty is most clearly seen when the sub- correlations of the error and data for each of the positions within the eye diagram are calculated. These sub-correlations are the same zero forcing tap updates that would be used to open the eye portions at a single location within the eye diagram. The algorithm averages the updates of the sub-correlations to insure that the eye portion is opened across the complete period of the symbol. However, each of the sub- correlations has a plurality of preferred tap settings that opens the eye portion where the sub-correlations are being calculated. The multiple solutions occur because the fractional spaced filter structure has more degrees of freedom than are required to open the eye portion at the location of the sub-correlation. The desired tap setting for the overall algorithm is the one set of taps that is a member of the set of taps preferred by each sub-correlation. This set of taps can be thought of as the intersection of the set of taps which could be synthesized if each of the sub-correlations adapted the system independently.

Since the algorithm is an adaptive approach, the convergence speed of the algorithm is important. From an unknown starting point, each of the sub-correlations has a direction of travel at each of the iterations of the algorithm. This direction of travel can be thought of as a vector, where each of the sub-correlations has different update vectors. The plurality of solutions preferred by each sub-correlation can be thought of as a plane of solutions. If the starting point happens to be one of these planes, then the update vector for that part of the algorithm is small because that particular sub-correlation is at a preferred tap solution. If the solution required to solve all of the equations happens to lie in a direction which is perpendicular to one of the planes desired by one of the part of the algorithm, then that part of the algorithm will try to fight the movement towards the correct solution. The other parts of the algorithm insures that the final solution is achieved, but the movements toward the final solution can be slow and may take a less than direct path.

Therefore, it is desirable to decouple the sub-correlations such that each part of the algorithm is not fighting the update vector preferred by the other parts of the algorithm. An alternate embodiment of the invention includes predistorting that significantly decouples the updates. This embodiment differs from the embodiment previously discussed above in that the predistorted signal input into the amplifier is independently controlled during each portion of the symbol period. In the embodiment previously discussed, there was a single fractional spaced filter that was used to generate the signal at each point within the predistorted signal. One difference for this embodiment was a simple time shift of the input signal. If one sub-correlation decided to change a tap to eliminate the ISI that it was seeing, then this update would also directly change the ISI seen by the other sub-correlations due to the structure of the predistorter. This is the symptom of the fighting for control of the tap solutions discussed above.

In this alternate embodiment, a parallel equalizer structure insures that the tap updates performed by each of the sub-correlations do not directly change the signal seen by the other parts of the algorithm. The memory of the HPA will cause the updates performed by one of the sub-correlators to slightly change the signal seen by the other parts of the algorithm. However, the effect will be significantly less pronounced than having the parts of the algorithm sharing the same tap controls as occurs in the invention discussed above. This alternate embodiment can synthesize the solution of the prior invention and has the added benefit of having more degrees of freedom which could assist in mitigating the HPA distortion if the HPA varies from its modeled characteristic. This alternate embodiment also more quickly and consistently arrives at the desired adaptive solution due to the independent nature of the parts of the algorithm.

In accordance with the teachings of this alternate embodiment of the present invention, a locally-adapted, parallel T-spaced linear predistorter is used to determine the predistortion. The predistorter includes a plurality of parallel adaptive filters that receive a modulated in-phase and quadrature-phase signal. A separate sampling input is applied to each adaptive filter during a symbol period. For each sampling input, an error is calculated which corresponds to its position in the eye portion of an eye diagram, and is correlated to the modulator output using a zero-forcing algorithm. The output of each adaptive filter is multiplexed sequentially to provide a predistorter waveform. The predistorter allows independent equalization at each sampling point in the symbol period of the eye portion.

FIG. 5 shows a block diagram of a communications system 58 employing a parallel, T-spaced predistorter 60, according to this alternate embodiment of the present invention. The communications system 58 is similar to the communications system 10, and therefore, like components are labeled the same and operate in the same manner. As discussed above, the fractionally spaced predistorter 16 uses algorithms to determine the error at various time slots. In this design, one sub-period is depended on the preceding sub-period. In the predistorter 60, each of the algorithms used at the various time slots are independent of each other and reduce the ISI independently.

FIG. 6 is a block diagram showing a combination of the modulator 14 and the parallel, T-spaced predistorter 60. The predistorter 60 includes four (4) separate adaptive predistorters 62-68 that each receive the complex in-phase and quadrature- phase modulated signals from the modulator 14, as shown. The input signal T1-T4 being applied to the predistorters 62-68, respectively, are the signals from the predistorter update 18 that gives the output voltage at that instant in time. For each sampling time input, an error is calculated which corresponds to its position in the eye, and is correlated to the modulator output using a zero-forcing algorithm. Each separate sub-symbol period within the symbol period at times T1-T4 are independently correlated based on the previous sub-symbol period. Each input signal T1-T4 being applied to the predistorter 62-64, respectively, is the signal for that sub-period that is a weighted sum of previous and future sub-symbols. Each baseband voltage output from the predistorters 62-68 is applied to a 4:1 multiplexer 70 that sequentially multiplexes the output from the predistorter 62-68 through time as the predistorted voltage.

FIGs. 7-10 show the eye diagram signal pattern outputs for each of the predistorters 62-68, respectfully. Particularly, the upper signal 76 pattern in FIG. 7 is the output of predistorter 62, the upper signal pattern 78 in FIG. 8 is the output of predistorter 64, the upper signal pattern 80 in FIG. 9 is the output of predistorter 66, and the upper signal pattern 82 in FIG. 10 is the output of predistorter 68. The lower signal patterns 82, 84, 86, 88 in each of FIG.s 7-10 shows the complete multiplexed combination of all of the predistorter 62-68. As is apparent, the ISI has been significantly reduced across the entire eye portion.

The foregoing discussion discloses and describes merely exemplary embodiments of the present invention. One skilled in the art will readily recognize from such discussion, and from the accompanying drawings and claims, that various changes, modifications and variations can be made therein without departing from the spirit and scope of the invention as defined in the following claim.

Claims

CLAIMSWhat is claimed is:

1. A transmission system for transmitting a signal, said system comprising: a modulator for modulating a stream of digital data onto the signal, said modulator being a quadrature modulator that converts bits in the stream of digital data into bit symbols where each bit symbol is transmitted during a symbol period; a amplifier for amplifying the signal prior to transmission, said amplifier including a filtering effect that distorts the signal; and a predistortion system receiving the signal before the amplifier and receiving the signal after being amplified, said predistortion system generating an inverse of distortion caused by the amplifier, said predistortion system including a plurality of parallel adaptive filters, each of the plurality of parallel adaptive filters receiving a separate input from the amplifier at different time periods during the symbol period and generating an error output that corresponds to that time period, each error output of each of the plurality of parallel adaptive filters being independent of the other error outputs.

2. The transmission system according to claim 1 wherein the adaptive filters employ a zero-forcing algorithm to generate the error output.

3. The transmission system according to claim 1 wherein the predistortion system reduces intersymbol interference at multiple locations across an eye diagram representing available transmission paths.

4. The transmission system according to claim 1 wherein the predistortion system includes a parallel, T-spaced linear predistorter.

5. The transmission system according to claim 1 wherein the predistortion system employs a filter selected from the group consisting of T-spaced linear finite impulse response filters and T-spaced linear infinite impulse response filters.

6. The transmission system according to claim 1 wherein the predistortion system receives the signal after being amplified from a sampling point immediately following the amplifier.

7. The transmission system according to claim 1 further comprising a multiplexer, said multiplexer being responsive to each error output and sequentially providing the inverse of distortion.

8. The transmission system according to claim 1 wherein the amplifier is selected from the group consisting of travelling wave tube amplifiers and solid-state power amplifiers.

9. A transmission system for transmitting a signal, said system comprising: a modulator for modulating a stream of digital data onto the signal; a amplifier for amplifying the signal prior to transmission, said amplifier including a filtering effect that distorts the signal; and a parallel T-spaced predistorter receiving the signal before the amplifier and receiving the signal after being amplified, said predistorter generating an inverse of distortion caused by the amplifier, said predistorter including a plurality of parallel adaptive filters, each of the adaptive filters receiving a separate input from the amplifier at different time periods across an eye portion of an eye diagram representing the available transmission paths of the signal and generating an error output that corresponds to each time period, each error output of each of the adaptive filters being independent of the other error outputs.

10. The transmission system according to claim 9 wherein the adaptive filters employ a zero-forcing algorithm to generate the error output.

11. The transmission system according to claim 9 wherein the predistorter reduces intersymbol interference at multiple locations across the eye diagram.

12. The transmission system according to claim 9 further comprising a multiplexer, said multiplexer being responsive to each error output of each of the adaptive filters and sequentially providing the inverse of distortion.

13. The transmission system according to claim 9 wherein the amplifier is selected from the group consisting of travelling wave tube amplifiers and solid-state power amplifiers.

14. The transmission system according to claim 9 wherein the predistorter employs a filter selected from the group consisting of T-spaced linear finite impulse response filters and T-spaced linear infinite impulse response filters.

15. A method of transmitting a signal, said method comprising the steps of: modulating a stream of digital data onto a signal, said step of modulating including converting digital data bits into bit symbols where each bit symbol is transmitted during a symbol period; predistorting the signal prior to amplification, said step of predistorting including sampling the signal at multiple times during the symbol period and generating an error output that corresponds to each time period where each error output is independent of every other error output around the sampling time; and amplifying the distorted signal from the predistortion step for transmission, said step of amplifying including a filtering effect that distorts the modulated signal wherein the step of correlating provides an inverse of the filtering effect of the amplifying step.

16. The method according to claim 15 wherein the step of predistorting includes using a zero-forcing algorithm to process the error output.

17. The method according to claim 15 wherein the step of predistorting includes employing a plurality of adaptive filters, where each adapted filter receives a signal from the amplifier at separate sampling times.

18. The method according to claim 15 further comprising the step of sequentially multiplexing each of the error outputs.