WO2001029829A1

WO2001029829A1 - Architecture for a hard disk drive write amplifier circuit with programmable controls

Info

Publication number: WO2001029829A1
Application number: PCT/US2000/028740
Authority: WO
Inventors: Soon-Gil Jung; Shang-Ching Dong; Hiroshi Takeuchi; Norio Shoji; Keiji Narusawa
Original assignee: Sony Electronics Inc.
Priority date: 1999-10-21
Filing date: 2000-10-17
Publication date: 2001-04-26
Also published as: JP2003512691A; AU1093801A

Abstract

A write amplifier circuit in a magnetic storage system has an overshoot control circuit (85) and a plurality of delay elements (90, 95) coupled to a top switch driver (30) and to a bottom switch (40) for providing the write amplifier circuit the capacity of supplying a write current (Iw(t)) to different types of heads which write the data onto the data media within the magnetic storage system. The overshoot control circuit and the plurality of delay elements receive a plurality of programmable signals (Td-B, Td-T, Td-P, Ios, Irw). Thus, proper selection of the plurality of programmable signals allows control of the write current to reduce distortions caused by a plurality of response characteristics associated with different types of heads. In particular, the overshoot control circuit allows control of an overshoot of the write current supplied to the head. The overshoot control circuit includes a pulse generating circuit (84) for generating a plurality of signals having a plurality of pulses that control a duration of the overshoot of the write current and an overshoot magnitude circuit (85) for generating an overshoot current that controls a magnitude of the overshoot of the write current. Additionally, each of the plurality of delay elements (90, 95) provide a delay to a different data input signal having a first data input signal (WDX2) and a second data input signal (WDY2) and supplied to the top switch driver and to the bottom switch driver. The plurality of delay elements (90, 95) reduce distortion in the write current supplied to the head by the amplifier circuit.

Description

ARCHITECTURE FOR A HARD DISK DRIVE WRITE AMPLIFIER CIRCUIT WITH PROGRAMMABLE CONTROLS

Related Applications:

This application claims priority under 35 U.S.C. § 119(e) of the co-pending U.S. provisional application Serial Number 60/160,800 filed on October 21, 1999 and entitled "Architecture For A Hard Disk Drive Write Amplifier Circuit With Programmable Controls." The provisional application Serial Number 60/160,800 filed on October 21,

1999 and entitled "Architecture For A Hard Disk Drive Write Amplifier Circuit With Programmable Controls" is also hereby incorporated by reference.

Field of the Invention The present invention relates to the field of write amplifier circuits within magnetic storage systems. More particularly, the present invention relates to write amplifier circuits supplying a write current and having programmable circuitry to improve response time and quality when recording data on a magnetic storage system.

Background of the Invention

A magnetic storage system, such as a conventional hard disk drive, is generally used for mass storage of data. Typically, the conventional hard disk drive includes a magnetic medium, an inductive element positioned near the surface of the magnetic medium, and a write amplifier circuit which provides a write current to the inductive element. The magnetic medium usually includes one or more disks composed of a metallic material such as an aluminum alloy. A magnetizable coating is deposited on the disk surface and serves as a data medium.

Generally, the inductive element comprises a head which writes data onto the disk as small magnetizations in the data medium by converting the write current into a magnetic field which magnetizes the surface area of the disk below the head. The small magnetizations align according to the generated magnetic field and a "1" is written. By inverting the polarity of the magnetic field, the small magnetizations are also aligned, but in another direction, thus a "0" is written. The polarity of the magnetic field is inverted by changing the direction of the write current supplied to the head. The head is generally a ferrite head or a thinfilm head. The thinfilm head typically is smaller and lighter in weight than the ferrite head. The thinfilm head can be positioned closer to the disk surface than the ferrite head, thus requiring a less intense magnetic field to write data to the disk. Figure 1 illustrates a schematic diagram of the conventional write amplifier circuit

100. The conventional write amplifier circuit includes differential input signals WDX and WDY, a top switch driver 30, a bottom switch driver 40, output terminals HX and HY, and H-switch transistors Ql, Q2, Q3, and Q4. The head 50 is coupled to the output terminals HX and HY. In practice, the differential data input signals WDX and WDY determine whether the npn transistor Q3 and the npn transistor Q4 are turned on or whether the npn transistor Ql and the npn transistor Q2 are turned on. If the transistors Q3 and Q4 are turned on, the write current Iw(t) travels from the emitter of the transistor Q3 to the output terminal HX. From the output terminal HX, the write current Iw(t) enters the head 50 and then returns to the output terminal HY. From the output terminal HY, the write current Iw(t) enters the collector of the transistor Q4. In essence, the transistor Q3 sources the write current Iw(t) while the transistor Q4 sinks the write current Iw(t).

If the transistors Ql and Q2 are turned on, the transistor Ql sources the write current Iw(t) while the transistor Q2 sinks the write current Iw(t). However, the write current Iw(t) enters the head 50 through the output terminal HY and then returns to the output terminal HX. Hence, the direction of the write current Iw(t) through the head 50 is opposite of the direction described above with respect to the situation when the transistors Q3 and Q4 are turned on. This change in the direction of the write current Iw(t) facilitates writing data as a "1" and a "0" on the disk surface. The top switch driver 30 defines the DC voltages of the output terminals HX and

HY and controls the H-switch transistors Ql and Q3. The bottom switch driver 40 controls the H-switch transistors Q2 and Q4 and determines the DC current of the write current Iw(t). Additionally, the bottom switch driver 40 is coupled to a variable current source Iw/K. The conventional write amplifier circuit 100 has a number of deficiencies. In particular, the top switch driver 30, the bottom switch driver 40, and the transistors Ql, Q2, Q3, and Q4 are optimized to supply the write current Iw(t) to a head 50 having a particular response characteristic, where the response characteristic is dependent on the composition of the head. Because different types of heads have different response characteristics, a write amplifier circuit 100 optimized for operation with a particular type of head may not be optimized for use with a head of a different type. Further, the process parameters of the manufacturing process generally cause the actual manufactured head 50 to have a response characteristic which is different from the particular response characteristic for which the write amplifier circuit 100 was optimized. Such differences in the response characteristic of the head 50 leads to a slow down in the recording speed of the magnetic storage system and to distortions in the write current Iw(t) to an extent that causes data recording errors. Similarly, variation due to the process parameters of the manufacturing process typically cause the components of the manufactured write amplifier circuit to deviate from an optimized configuration, leading to a drop in the recording speed of the magnetic storage system and to distortions in the write current Iw(t) to an extent that causes data recording errors. Additionally, the conventional write amplifier circuit 100 is not suited for supplying the write current Iw(t) to different types of heads which are manufactured by a variety of companies and can usually supply the write current Iw(t) only to one type of head. Since each type of head 50 has a unique response characteristic, the write current Iw(t) supplied by the conventional write amplifier circuit 100 to heads 50 having a response characteristic other than the particular response characteristic for which the write amplifier circuit 100 was optimized, is distorted and does not have smooth rise times and fall times. In order to optimize the performance of the write amplifier circuit 100, the write amplifier circuit 100 must somehow compensate for the different response characteristics of different types of heads and which also could be due to the manufacturing and assembly process. As advancements in hard disk drive systems have occurred, the operational speeds of typical write driver amplifier circuits have increased, enabling the write driver amplifier circuits to perform circuit operations at greater speeds. At the head 50, these advancements have caused a lowering of the output load inductance at the output of the write driver amplifier circuit. Because of these speed advancements, the sensitivity of the typical write driver amplifier circuit with respect to such external items as bond wires, the integrated circuit (IC) package and the external output lines in the flexible cable coupled to the hard disk drive, has increased. When designing a write driver amplifier circuit, the head model including the external items is modelled as an equivalent or distributed circuit including a distributed network of capacitors, inductors and resistors, as appropriate, in order to design the write amplifier circuit for optimal performance. However, the actual performance of the head and the characteristics of the external items will occasionally vary from the equivalent or distributed circuit when the write amplifier circuit is implemented. This variance will cause degradation in the performance of the implemented write amplifier circuit. Accordingly, in order to optimize the performance of the implemented write amplifier circuit, it would be beneficial to include some control functions which allow the characteristics of the write amplifier circuit to be adjusted to optimize the actual write current waveform characteristics.

Moreover, the write current Iw(t) supplied by the conventional write amplifier circuit 100 has a large undershoot and a long ringing. The undershoot and the ringing slow down the writing speed of the magnetic storage system, such as a hard disk drive, and distort the written data when the head converts the write current Iw(t) into a magnetic field. Therefore, the undershoot and the ringing affect the speed and the performance of a magnetic storage system including a conventional write amplifier circuit such as illustrated in Figure 1.

Summary of the Invention A write amplifier circuit in a magnetic storage system has an overshoot control circuit and a plurality of delay elements coupled to a top switch driver and to a bottom switch driver for providing the write amplifier circuit the capability of supplying a write current to different types of heads which write the data onto the data media within the magnetic storage system. The overshoot control circuit and the plurality of delay elements receive a plurality of programmable signals. Thus, proper selection of the plurality of programmable signals allows control of the write current to reduce distortions caused by a plurality of response characteristics associated with different types of heads.

In particular, the overshoot control circuit allows control of an overshoot of the write current supplied to the head. The overshoot control circuit includes a pulse generating circuit for generating a plurality of signals having a plurality of pulses that control a duration of the overshoot of the write current and an overshoot magnitude circuit for generating an overshoot current that controls a magnitude of the overshoot of the write current.

Additionally, each of the plurality of delay elements provide a delay to a differential data input signal having a first data input signal and a second data input signal and supplied to the top switch driver and to the bottom switch driver. The plurality of delay elements reduce distortion in the write cuπent supplied to the head by the write amplifier circuit.

In one aspect of the present invention, an overshoot control circuit for controlling an overshoot of a write current supplied to an inductive element within a magnetic storage system by a write amplifier circuit including a driving circuit and a switching circuit coupled to the driving circuit and to the inductive element for providing the write current, wherein the inductive element writes data to a magnetic medium, includes a pulse generating circuit configured to receive a differential data input signal including a first data input signal and a second data input signal for generating a plurality of signals having a plurality of pulses that control a duration of overshoot of the write current, wherein the pulse generating circuit is further configured to receive a duration delay signal for controlling the plurality of pulses, and an overshoot magnitude circuit coupled to the pulse generating circuit and to the driving circuit for generating an overshoot current through a differential overshoot output that controls a magnitude of the overshoot of the write current, wherein the overshoot magnitude circuit is configured to receive the plurality of signals from the pulse generating circuit and to receive a reference current control signal for controlling the overshoot current, and further wherein the overshoot current provided to the driving circuit causes formation of an amplified overshoot current at the switching circuit providing the write current to the inductive element.

In another aspect of the present invention, a write amplifier circuit for supplying a write current to an inductive element that writes data to a magnetic medium, wherein the inductive element includes one of a plurality of response characteristics, the write amplifier circuit includes a switching circuit coupled to the inductive element for providing the write current to the inductive element, a first driving circuit configured for coupling to and driving the switching circuit, a second driving circuit configured for coupling to and driving the switching circuit, wherein the second driving circuit includes a current amplifier, a first delay element coupled to the first driving circuit and configured to receive a differential data input signal including a first data input signal and a second data input signal and to receive a first delay signal, wherein the first delay element provides a first delay to the first data input signal corresponding to the first delay signal, thereby forming a first delayed data input signal, and provides the first delay to the second data input signal corresponding to the first delay signal, thereby forming a second delayed data input signal, and a second delay element coupled to the second driving circuit and configured to receive the differential data input signal including the first data input signal and the second data input signal and to receive a second delay signal, wherein the second delay element provides a second delay to the first data input signal corresponding to the second delay signal, thereby forming a third delayed data input signal, and provides the second delay to the second data input signal corresponding to the second delay signal, thereby forming a fourth delayed data input signal.

In still another aspect of the present invention, a write amplifier circuit for supplying a write current to an inductive element that writes data to a magnetic medium, wherein the inductive element includes one of a plurality of response characteristics, the write amplifier circuit includes a switching circuit coupled to the inductive element for providing the write cuπent to the inductive element, a first driving circuit configured for coupling to and driving the switching circuit, a second driving circuit configured for coupling to and driving the switching circuit, wherein the second driving circuit includes a current amplifier, and an overshoot control circuit coupled to the second driving circuit for controlling an overshoot of the write current.

In yet another aspect of the present invention, a magnetic storage system includes a magnetic medium for storing data; an inductive element for writing data to the magnetic medium by converting a write current to a magnetic field, wherein the inductive element includes one of a plurality of response characteristics; a write amplifier circuit for supplying the write cuπent to the inductive element, the write amplifier circuit including a switching circuit coupled to the inductive element for providing the write current to the inductive element, a first driving circuit configured for coupling to and driving the switching circuit, a second driving circuit configured for coupling to and driving the switching circuit, wherein the second driving circuit includes a current amplifier, and an overshoot control circuit coupled to the second driving circuit for controlling an overshoot of the write cuπent; and an interface coupled to the write amplifier circuit for providing a plurality of control signals and a plurality of delay signals to the write amplifier circuit. In still yet another aspect of the present invention, a magnetic storage system includes a magnetic medium for storing data; an inductive element for writing data to the magnetic medium by converting a write cuπent to a magnetic field, wherein the inductive element includes one of a plurality of response characteristics; a write amplifier circuit for supplying the write cuπent to the inductive element, the write amplifier circuit including a switching circuit coupled to the inductive element for providing the write cuπent to the inductive element, a first driving circuit configured for coupling to and driving the switching circuit, a second driving circuit configured for coupling to and driving the switching circuit, wherein the second driving circuit includes a cuπent amplifier, a first delay element coupled to the first driving circuit and configured to receive a differential data input signal including a first data input signal and a second data input signal and to receive a first delay signal, wherein the first delay element provides a first delay to the first data input signal coπesponding to the first delay signal thereby forming a first delayed data input signal and provides the first delay to the second data input signal corresponding to the first delay signal thereby forming a second delayed data input signal, and a second delay element coupled to the second driving circuit and configured to receive the differential data input signal including the first data input signal and the second data input signal and to receive a second delay signal, wherein the second delay element provides a second delay to the first data input signal coπesponding to the second delay signal thereby forming a third delayed data input signal and provides the second delay to the second data input signal coπesponding to the second delay signal thereby forming a fourth delayed data input signal; and an interface coupled to the write amplifier circuit for providing a plurality of control signals and a plurality of delay signals to the write amplifier circuit.

Brief Description of the Drawings

Figure 1 illustrates a schematic diagram of a write amplifier circuit according to the prior art.

Figure 2 illustrates a schematic diagram of a write amplifier circuit according to the present invention. Figure 3 illustrates a schematic diagram of a pulse generating circuit according to the present invention.

Figure 4 illustrates a timing diagram at certain locations within a pulse generating circuit according to the present invention.

Figure 5 illustrates a detailed schematic diagram of the prefeπed embodiment of an overshoot magnitude circuit of the present invention.

Figure 6 illustrates a plurality of waveforms representing the write cuπent supplied by a write amplifier circuit of the present invention.

Detailed Description of the Prefeπed Embodiment

A magnetic storage system of the present invention preferably includes a magnetic medium for storing data, an inductive element for writing data to the magnetic medium by converting a write cuπent to a magnetic field, wherein the inductive element includes one of a plurality of response characteristics, a write amplifier circuit for supplying the write cuπent to the inductive element, and an interface coupled to the write amplifier circuit for providing a plurality of control signals and a plurality of delay signals to the write amplifier circuit. The interface facilitates selectively programming the plurality of control signals and the plurality of delay signals to improve recording speed and reliability of the magnetic storage system.

Figure 2 illustrates a schematic diagram of a write amplifier circuit 200 in a magnetic storage system according to the present invention. For clarity, unchanged components from the write amplifier 100 of Figure 1 retain the same labels. As shown in Figure 2, the write amplifier circuit 200 includes an overshoot control circuit 80 comprising a pulse generating circuit 84 and an overshoot magnitude circuit 85. The overshoot magnitude circuit 85 is coupled to a bottom switch driver 40 through a plurality of cuπent amplifiers 65A and 65B. Additionally, a variable current source Ios is coupled to the overshoot magnitude circuit 85. The pulse generating circuit 84 is coupled to the overshoot magnitude circuit 85.

Also, the pulse generating circuit 84 is coupled to a first data buffer 10. Moreover, the pulse generating circuit 84 includes a delay element 82. The pulse generating circuit 84 receives the differential data input signals WDY1 and WDX1 which are output from the first data buffer 10. The first data buffer 10 is coupled to receive the differential input signals WDX and WDY as inputs.

The write amplifier circuit 200 further includes a first delay element 90 and a second delay element 95. The first delay element 90 is coupled to the top switch driver 30 and to a second data buffer 15. The second delay element 95 is coupled to the bottom switch driver 40 and to the second data buffer 15. The first and second delay elements 90 and 95 receive the differential data input signals WDY2 and WDX2 which are output from the second data buffer 15. The second data buffer 15 is coupled to receive the differential input signals WDX and WDY as inputs. Additionally, a variable cuπent source Irw is coupled to the bottom switch driver 40.

The write amplifier circuit 200 further includes a damping circuit 55 having a first resistor Rdl, a second resistor Rd2, a first capacitor Cdl, and a second capacitor Cd2. The damping circuit 55 is coupled to the output terminals HX and HY and to the bottom switch driver 40. The damping circuit 55 is coupled to the bottom switch driver 40 through a plurality of cuπent amplifiers (not shown).

In addition to the write amplifier circuit 200, the magnetic storage system includes an interface 45 which is coupled to the first and second delay elements 90 and 95, to the pulse generating circuit 84, to the overshoot magnitude circuit 85, and to the bottom switch driver 40. Preferably, the interface 45 is a serial interface. It should be understood that, alternately, the interface 45 can be implemented in any other format. The interface 45 is configured to program a plurality of programmable signals for use by the write amplifier circuit 200. The plurality of programmable signals include a first delay Td_B, a second delay Td_T, a duration delay Td_P, a reference current control signal for the variable cuπent source Ios, and a reference cuπent control signal for the variable cuπent source

Irw. The interface 45 is configured for receiving data external from the magnetic storage system through the signals sclk, senb, and sdata.

The reference current control signal for the variable cuπent source Irw is used to control the DC bias cuπent for the write cuπent Iw(t). The overshoot control circuit 80 is configured for controlling an overshoot of a write current Iw(t) supplied to the head 50 by the write amplifier circuit 200, allowing the write amplifier circuit 200 of the present invention to meet the requirements of various types of heads 50. The first delay element 90 and the second delay element 95 provide delay to the differential data input signals WDX2 and WDY2 provided to the top switch driver 30 and the bottom switch driver 40, reducing distortion in the write current Iw(t) supplied to various types of heads 50 by the write amplifier circuit 200. The inclusion of the overshoot control circuit 80 and the first and second delay elements 90 and 95 gives the write amplifier circuit 200 design flexibility and helps to obtain the best performance from the magnetic storage system with a variety of heads.

The damping circuit 55 reduces an undershoot and settling time associated with the write cuπent Iw(t). A detailed explanation of the damping circuit 55 can be found in the concuπently filed U.S. Patent Application Serial No. by the inventors of the present invention, entitled "ARCHITECTURE FOR A HARD DRIVE WRITE AMPLIFIER CIRCUIT WITH DAMPING CONTROL", which is hereby incorporated by reference.

Figure 3 illustrates a schematic diagram of a pulse generating circuit 84 according to the present invention.

The pulse generating circuit 84 is configured for generating the signals OSNX, OSNY, OSPY, and OSPY which are supplied to the overshoot magmtude circuit 85 (Figure 2). The signals OSNX and OSNY are differential signals. The signals OSPX and OSPY are differential signals. As will be described below, the pulse generating circuit 84 adds a plurality of pulses to the signals OSNX, OSNY, OSPY, and OSPY. The plurality of pulses control a duration of the overshoot of the write cuπent Iw(t) in conjunction with the overshoot magnitude circuit 85. The duration delay signal Td_P controls the plurality of pulses.

The pulse generating circuit 84 preferably includes the delay element 82, a first NAND circuit 310, an inverting circuit 340, a noninverting buffer 350, and a second

NAND circuit 320. The delay element 82 provides an output at a node a, which is coupled to the input of the inverting circuit 340 and to the input of the noninverting buffer 350. The output of the noninverting buffer 350 is coupled to a first input of the first NAND circuit 310. The output of the inverting circuit 340 is coupled to a first input of the second NAND circuit 320. A second input of the first NAND circuit 310 is coupled to receive the signal WDY1. A second input of the second NAND circuit 320 is coupled to receive the signal WDX1.

The delay element 82 preferably includes a plurality of delay circuits 372, 374, 376, and 378 and a switch 360 which is controlled by the duration delay signal Td_P, which is programmable. Alternately, the delay element 82 can be implement in any other manner for providing a programmable delay to a signal. The delay circuits^' 372, 374, 376, and 378 are coupled to each other and to the switch 360 to provide a plurality of signal paths between an input of the delay element 82 and an output of the delay element 82. The delay element 82 is configured to receive the differential data input signal WDXl and to receive the duration delay signal Td_P. The delay element 82 provides a delay to the differential data input signal WDXl, where the delay is programmed by the duration delay signal Td_P. The node a receives a delayed version of the differential data input signal

WDXl . In practice, the duration delay signal Td_P configures the switch 360 to select one of the plurality of signal paths.

The input signal WDXl is coupled to an input of the delay circuit 372. An output of the delay circuit 372 is coupled to a first input of the switch 360 and to an input of the delay circuit 374. An output of the delay circuit 374 is coupled to a second input of the switch 360 and to an input of the delay circuit 376. An output of the delay circuit 376 is coupled to a third input of the switch 360 and to an input of the delay circuit 378. An output of the delay circuit 378 is coupled to a fourth input of the switch 360. The switch 360 is coupled to receive the duration delay signal Td_P which controls which one of the inputs of the switch 360 is coupled to the output of the switch 360.

The first NAND circuit 310 is configured for receiving the differential data input signal WDYl and the delayed version of the differential data input signal WDXl. The first NAND circuit 310 generates the differential signals OSNX and OSNY, each including one or more pulses. The signal OSNY is an inverse of the signal OSNX. The inverting circuit 340 is configured for inverting the delayed version of the differential data input signal WDXl. The node b at the output of the inverting circuit 340 receives an inverted signal representing an inverted version of the delayed version of the differential data input signal WDXl.

The second NAND circuit 320 is configured for receiving the inverted signal from the output of the inverting circuit 340 and the differential data input signal WDXl. The second NAND circuit 320 generates the differential signals OSPX and OSPY, each including one or more pulses. The signal OSPY is an inverse of the signal OSPX.

Figure 4 illustrates a timing diagram at certain locations within the pulse generating circuit 84 according to the present invention. At the time TO, the signal WDXl, the signal at the node a, the signal OSPY, and the signal OSNY are all at a logical low voltage level while the signal WDYl, the signal at the node b, the signal OSPX, and the signal OSNX are all at a logical high voltage level. At the time Tl, the signal WDXl transitions from a logical low voltage level to a logical high voltage level. Coπespondingly, at the time Tl, the signal WDYl transitions from a logical high voltage level to a logical low voltage level. Because of the delay Td provided by the delay element 82, the changes in the signals WDXl and WDYl are not seen at the node a and the node b until the time T2. This delay Td causes the signal OSPX to transition to a logical low voltage level and the signal OSPY to transition to a logical high voltage level for a period of time beginning at the time Tl and ending at the time T2. The difference between the times Tl and T2 is equal to the delay time Td.

At the time T3, the signal WDXl transitions from a logical high voltage level to a logical low voltage level. Coπespondingly, at the time T3, the signal WDYl transitions from a logical low voltage level to a logical high voltage level. Because of the delay Td provided by the delay element 82, the changes in the signals WDXl and WDYl are not seen at the node a and the node b until the time T4. This delay Td causes the signal OSNX to transition to a logical low voltage level and the signal OSNY to transition to a logical high voltage level for a period of time beginning at the time T3 and ending at the time T4. The difference between the times T3 and T4 is equal to the delay time Td. A similar analysis is applicable for the transitions which occur at the times T5, T6, T7, T8, T9, and TlO.

When the signal WDXl transitions to a logical high voltage level and the signal WDYl transitions to a logical low voltage level, the differential signals OSPX and OSPY form pulses having a pulse width determined by the delay Td controlled by the delay element 82. When the signal WDXl transitions to a logical low voltage level and the signal WDYl transitions to a logical high voltage level, the differential signals OSNX and OSNY form pulses having a pulse width determined by the delay Td controlled by the delay element 82.

Figure 5 illustrates a detailed schematic diagram of the prefeπed embodiment of the overshoot magnitude circuit 85 of the present invention.

The overshoot magnitude circuit 85 includes the pnp input transistors Q10, Q20, Q30, and Q40. The emitters of the input transistors Q10, Q20, Q30, and Q40 are coupled to each other and to the variable current source Ios. The base of the input transistor Q30 is coupled to the differential signal OSNY from the pulse generating circuit 84. The base of the input transistor Q10 is coupled to the differential signal OSNX from the pulse generating circuit 84. The base of the input transistor Q20 is coupled to the differential signal OSPX from the pulse generating circuit 84. The base of the input transistor Q40 is coupled to the differential signal OSPY from the pulse generating circuit 84. The collectors of the input transistors Q30 and Q40 are coupled to the cuπent source II, to a first terminal of the resistor Rl, to a first terminal of the resistor R2, and to the collector and base of the npn transistor Q5. The collector of the input transistor Q10 is coupled to a second terminal of the resistor Rl and to provide the output signal OSY. The collector of the input transistor Q20 is coupled to a second terminal of the resistor R2 and to provide the output signal OSX. Additionally, the emitter of the transistor Q5 is coupled to the collector and base of the npn transistor Q6. The emitter of the transistor Q6 is coupled to the collector and base of the npn transistor Q7. The emitter of the transistor Q7 is coupled to ground.

The input transistors Q30 and Q10 form a first half of a current switch. The input transistors Q20 and Q40 form a second half of the current switch. A differential overshoot output signal OSY is taken from the collector of the input transistor Q10. A differential overshoot output signal OSX is taken from the collector of the input transistor Q20. The transistors Q5, Q6, and Q7 are always on.

The overshoot magnitude circuit 85 generates an overshoot cuπent through the differential overshoot output signals OSX and OSY. The overshoot cuπent controls a magnitude of the overshoot of the write current Iw(t). The overshoot cuπent is sent to a cuπent amplifier within the bottom switch driver 40, causing an amplified overshoot cuπent to form at the collector of the H-switch Q2 or Q4 (Figure 2) that is sinking the write current Iw(t). In practice, a "LOW" value of the signals OSNY, OSNX, OSPX, and OSPY, which are applied to the bases of the input transistors Q30, Q10, Q20, and Q40, respectively, causes the respective input transistor to turn. The overshoot cuπent is generated at the differential overshoot output signals OSX or OSY only when either of the differential signals OSNX or OSPX is "LOW", where the differential signals OSNX and OSPX are "LOW" only during the pulse caused by the delay Td (Figure 4) provided by the delay element 82 (Figure 3) of the pulse generating circuit 84 (Figure 3). In other words, the pulse caused by the delay Td (Figure 4) controls the duration of the overshoot of the write cuπent.

Moreover, the overshoot magnitude circuit 85 receives a reference cuπent control signal which controls the variable cuπent source Ios and which is programmable. A magnitude of the overshoot cuπent is dependent on a magnitude of the variable cuπent source Ios. Hence, the reference cuπent control signal controls the magnitude of the overshoot cuπent. Referring to Figure 2, the first delay element 90 receives the differential data input signals WDY2 and WDX2, adds a delay to the differential data input signals WDY2 and WDX2, and then sends a delayed version of each of the differential data input signals WDY2 and WDX2 to the top switch driver 30. The delay of the first delay element 90 is programmed by the first delay signal Td_T received from the interface 45. The first delay element 90 comprises a plurality of delay circuits. It should be apparent to one skilled in the art that the delay circuits can be aπanged in many different aπangements to perform the function of the first delay element. The first delay element 90 can be implemented similarly to the delay element 82 (Figure 3) of the pulse generating circuit 84 (Figure 3).

The second delay element 95 receives the differential data input signals WDY2 and WDX2, adds a delay to the differential data input signals WDY2 and WDX2, and then sends a delayed version of each of the differential data input signals WDY2 and WDX2 to the bottom switch driver 40. The delay of the second delay element 95 is programmed by the second delay signal Td_B received from the interface 45. The second delay element 95 comprises a plurality of delay circuits. It should be apparent to one skilled in the art that the delay circuits can be aπanged in many different arrangements to perform the function of the second delay element. The second delay element 95 can be implemented similarly to the delay element 82 (Figure 3) of the pulse generating circuit 84 (Figure 3).

The first and second delay signals Td_T and Td_B are configured to reduce distortion in the write cuπent Iw(t) supplied to different types of heads, each having a different natural resonant frequency. Thus, by changing the delay signals Td_T and Td_B appropriately, the write cuπent Iw(t) can have smooth rise times and fall times for heads of different natural resonant frequencies.

Figure 6 illustrates a plurality of waveforms representing the write cuπent Iw(t) supplied by the write amplifier circuit 200 of the present invention. The waveforms 610 and 620 represent the write cuπent Iw(t) supplied by the write amplifier circuit 200 of the present invention, where the first and second delay signals Td T and Td B each have a zero value. The waveform 610 shows the distortion of the write cuπent Iw(t) caused by a positive transition in the write cuπent Iw(t). The waveform 620 shows the distortion of the write cuπent Iw(t) caused by a negative transition in the write cuπent Iw(t).

The waveforms 630 and 640 represent the write current Iw(t) supplied by the write amplifier circuit 200 of the present invention, where the first and second delay signals

Td_T and Td_B each have a 0.6 ns value. The waveform 640 shows a reduction in distortion of the write current Iw(t) caused by a positive transition in the write cuπent Iw(t). The waveform 630 shows a reduction in distortion of the write current Iw(t) caused by a negative transition in the write cuπent Iw(t). As described herein, the write amplifier circuit 200 of the present invention can be optimized for use with write heads 50 having different characteristics. Utilizing the pulse generator 84 which provides pulses of programmed duration to the overshoot magnitude circuit 85, the characteristics of the write cuπent Iw(t) can be changed to reduce the distortion of the write current Iw(t) during transitions. These programmable functions allow the write amplifier circuit 200 of the present invention to be utilized in different magnetic storage systems having heads with different characteristics. This allows the system designer flexibility and aids in achieving high performance of the magnetic storage system.

The above figures are merely intended to illustrate a particular implementation of the present invention, but are not intended to limit the scope of the present invention to this particular implementation.

The present invention has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of the invention. Such reference herein to specific embodiments and details thereof is not intended to limit the scope of the claims appended hereto. While the prefeπed embodiment of the present invention has been illustrated and described as a circuit using bipolar transistors, it will be apparent to a person of ordinary skill in the art that the circuit of the present invention may be implemented using another device technology such as CMOS, MOS, or any other appropriate device technology. It will be apparent to those skilled in the art that modifications may be made in the embodiments chosen for illustration without departing from the spirit and scope of the invention.

Claims

CLAIMS What is claimed is:

1. An overshoot control circuit for controlling an overshoot of a write cuπent supplied to an inductive element within a magnetic storage system by a wnte amplifier circuit including a driving circuit and a switching circuit coupled to the driving circuit and to the inductive element for providing the write cuπent, wherein the inductive element writes data to a magnetic medium, the overshoot control circuit comprising: a. a pulse generating circuit configured to receive a differential data input signal including a first data input signal and a second data input signal for generating a plurality of signals having a plurality of pulses that control a duration of overshoot of the write cuπent, wherein the pulse generating circuit is further configured to receive a duration delay signal for controlling the plurality of pulses; and b. an overshoot magmtude circuit coupled to the pulse generating circuit and to the driving circuit for generating an overshoot cuπent through a differential overshoot output that controls a magnitude of the overshoot of the write current, wherein the overshoot magnitude circuit is configured to receive the plurality of signals from the pulse generating circuit and to receive a reference cuπent control signal for controlling the overshoot cuπent, and further wherein the overshoot current provided to the driving circuit causes formation of an amplified overshoot cuπent at the switching circuit providing the write cuπent to the inductive element.

2. The overshoot control circuit according to claim 1 wherein the pulse generating circuit includes: a. a delay element configured to receive the first data input signal and to receive the duration delay signal such that the delay element provides a delay to the first data input signal coπesponding to the duration delay signal, thereby forming a first delayed data input signal; b. a first NAND circuit coupled to the delay element for receiving the second data input signal and the first delayed data input signal and for generating a first differential output signal including a first output signal and a second output signal, wherein the first differential output signal includes one or more of the plurality of pulses; c. an inverting circuit coupled to the delay element for inverting the first delayed data input signal, thereby forming an inverted first delayed data input signal; and d. a second NAND circuit coupled to the inverting circuit for receiving the first data input signal and the inverted first delayed data input signal and for generating a second differential output signal including a third output signal and a fourth output signal, wherein the second differential output signal includes one or more of the plurality of pulses.

3. The overshoot control circuit according to claim 1 wherein the overshoot magnitude circuit includes a plurality of input transistors, each coupled to one of the signals generated by the pulse generating circuit and to an overshoot reference cuπent that is controlled by the reference cuπent control signal, wherein the overshoot cuπent is dependent on the overshoot reference current, and wherein the plurality of input transistors are coupled in a cuπent switch aπangement.

4. A write amplifier circuit for supplying a write cuπent to an inductive element that writes data to a magnetic medium, wherein the inductive element includes one of a plurality of response characteristics, the write amplifier circuit comprising: a. a switching circuit coupled to the inductive element for providing the wnte cuπent to the inductive element; b. a first driving circuit configured for coupling to and driving the switching circuit; c. a second driving circuit configured for coupling to and driving the switching circuit, wherein the second driving circuit includes a cuπent amplifier; d. a first delay element coupled to the first driving circuit and configured to receive a differential data input signal including a first data input signal and a second data input signal and to receive a first delay signal, wherein the first delay element provides a first delay to the first data input signal coπesponding to the first delay signal, thereby forming a first delayed data input signal, and provides the first delay to the second data input signal coπesponding to the first delay signal, thereby forming a second delayed data input signal; and e. a second delay element coupled to the second driving circuit and configured to receive the differential data input signal including the first data input signal and the second data input signal and to receive a second delay signal, wherein the second delay element provides a second delay to the first data input signal coπesponding to the second delay signal, thereby forming a third delayed data input signal, and provides the second delay to the second data input signal coπesponding to the second delay signal, thereby forming a fourth delayed data input signal.

5. The write amplifier circuit according to claim 4 wherein the first and second delay signals are configured to reduce distortion in the wnte current supplied to the head by the wnte amplifier circuit.

6. The wnte amplifier circuit according to claim 4 wherein the first and second delay signals are selectively programmable.

7. The write amplifier circuit according to claim 4 further including an overshoot control circuit coupled to the second driving circuit for controlling an overshoot of the write cuπent.

8. The write amplifier circuit according to claim 7 wherein the overshoot control circuit includes: a. a pulse generating circuit configured to receive the differential data input signal including a first data input signal and a second data input signal for generating a plurality of signals having a plurality of pulses that control a duration of overshoot of the write cuπent, wherein the pulse generating circuit is further configured to receive a duration delay signal for controlling the plurality of pulses; and b. an overshoot magnitude circuit coupled to the pulse generating circuit and to the cuπent amplifier of the second driving circuit for generating an overshoot cuπent through a differential overshoot output that controls a magnitude of the overshoot of the write current, wherein the overshoot magnitude circuit is configured to receive the plurality of signals from the pulse generating circuit and to receive a reference current control signal for controlling the overshoot cuπent, and further wherein the overshoot cuπent provided to the second driving circuit causes formation of an amplified overshoot cuπent at the switching circuit providing the wnte cuπent to the inductive element.

9. The write amplifier circuit according to claim 8 wherein the pulse generating circuit includes: a. a delay element configured to receive the first data input signal and to receive the duration delay signal such that the delay element provides a delay to the first data input signal coπesponding to the duration delay signal, thereby forming a fifth delayed data input signal; b. a first NAND circuit coupled to the delay element for receiving the second data input signal and the fifth delayed data input signal and for generating a first differential output signal including a first output signal and a second output signal, wherein the first differential output signal includes one or more of the plurality of pulses; c. an inverting circuit coupled to the delay element for inverting the fifth delayed data input signal, thereby forming an inverted fifth delayed data input signal; and d. a second NAND circuit coupled to the inverting circuit for receiving the first data input signal and the inverted fifth delayed data input signal and for generating a second differential output signal including a third output signal and a fourth output signal, wherein the second differential output signal includes one or more of the plurality of pulses.

10. The write amplifier circuit according to claim 8 wherein the overshoot magmtude circuit includes a plurality of input transistors, each coupled to one of the signals generated by the pulse generating circuit and to an overshoot reference cuπent that is controlled by the reference cuπent control signal, wherein the overshoot cuπent is dependent on the overshoot reference cuπent, and wherein the plurality of input transistors are coupled in a cuπent switch aπangement.

11. The write amplifier circuit according to claim 4 further including a damping circuit coupled to the switching circuit and to the second driving circuit for reducing an undershoot and a settling time of the write cuπent.

12. A wnte amplifier circuit for supplying a write cuπent to an inductive element that writes data to a magnetic medium, wherein the inductive element includes one of a plurality of response characteristics, the write amplifier circuit comprising: a. a switching circuit coupled to the inductive element for providing the write cuπent to the inductive element; b. a first driving circuit configured for coupling to and driving the switching circuit; c. a second driving circuit configured for coupling to and driving the switching circuit, wherein the second driving circuit includes a cuπent amplifier; and d. an overshoot control circuit coupled to the second driving circuit for controlling an overshoot of the wnte cuπent.

13. The write amplifier circuit according to claim 12 wherein the overshoot control circuit includes: a. a pulse generating circuit configured to receive a differential data input signal including a first data input signal and a second data input signal for generating a plurality of signals having a plurality of pulses that control a duration of overshoot of the write cuπent, wherein the pulse generating circuit is further configured to receive a duration delay signal for controlling the plurality of pulses; and b. an overshoot magnitude circuit coupled to the pulse generating circuit and to the cuπent amplifier of the second driving circuit for generating an overshoot cuπent through a differential overshoot output that controls a magnitude of the overshoot of the write cuπent, wherein the overshoot magnitude circuit is configured to receive the plurality of signals from the pulse generating circuit and to receive a reference cuπent control signal for controlling the overshoot cuπent, and further wherein the overshoot cuπent provided to the second driving circuit causes formation of an amplified overshoot cuπent at the switching circuit providing the wnte current to the inductive element.

14. The write amplifier circuit according to claim 13 wherein the pulse generating circuit includes: a. a delay element configured to receive the first data input signal and to receive the duration delay signal such that the delay element provides a delay to the first data input signal coπesponding to the duration delay signal, thereby forming a first delayed data input signal; b. a first NAND circuit coupled to the delay element for receiving the second data input signal and the first delayed data input signal and for generating a first differential output signal including a first output signal and a second output signal, wherein the first differential output signal includes one or more of the plurality of pulses; c. an inverting circuit coupled to the delay element for inverting the first delayed data input signal, thereby forming an inverted first delayed data input signal; and d. a second NAND circuit coupled to the inverting circuit for receiving the first data input signal and the inverted first delayed data input signal and for generating a second differential output signal including a third output signal and a fourth output signal, wherein the second differential output signal includes one or more of the plurality of pulses.

15. The write amplifier circuit according to claim 13 wherein the overshoot magnitude circuit includes a plurality of input transistors, each coupled to one of the signals generated by the pulse generating circuit and to an overshoot reference cuπent that is controlled by the reference cuπent control signal, wherein the overshoot cuπent is dependent on the overshoot reference cuπent, and wherein the plurality of input transistors are coupled in a cuπent switch aπangement.

16. The write amplifier circuit according to claim 12 further including: a. a first delay element coupled to the first driving circuit and configured to receive the differential data input signal including the first data input signal and the second data input signal and to receive a first delay signal, wherein the first delay element provides a first delay to the first data input signal coπesponding to the first delay signal, thereby forming a second delayed data input signal, and provides the first delay to the second data input signal coπesponding to the first delay signal, thereby forming a third delayed data input signal; and b. a second delay element coupled to the second driving circuit and configured to receive the differential data input signal including the first data input signal and the second data input signal and to receive a second delay signal, wherein the second delay element provides a second delay to the first data input signal coπesponding to the second delay signal, thereby forming a fourth delayed data input signal, and provides the second delay to the second data input signal coπesponding to the second delay signal, thereby forming a fifth delayed data input signal.

17. The write amplifier circuit according to claim 16 wherein the first and second delay signals are configured to reduce distortion in the wnte cuπent supplied to the head by the wnte amplifier circuit.

18. The write amplifier circuit according to claim 16 wherein the first and second delay signals are selectively programmable.

19. The write amplifier circuit according to claim 12 further including a damping circuit coupled to the switching circuit and to the second driving circuit for reducing an undershoot and a settling time of the write current.

20. A magnetic storage system comprising: a. a magnetic medium for storing data; b. an inductive element for writing data to the magnetic medium by converting a wnte cuπent to a magnetic field, wherein the inductive element includes one of a plurality of response characteristics; c. a write amplifier circuit for supplying the write cuπent to the inductive element, the write amplifier circuit including: i. a switching circuit coupled to the inductive element for providing the write cuπent to the inductive element; ii. a first driving circuit configured for coupling to and driving the switching circuit; iii. a second driving circuit configured for coupling to and driving the switching circuit, wherein the second driving circuit includes a current amplifier; and iv. an overshoot control circuit coupled to the second driving circuit for controlling an overshoot of the write cuπent; and d. an interface coupled to the write amplifier circuit for providing a plurality of control signals and a plurality of delay signals to the write amplifier circuit.

21. The magnetic storage system according to claim 20 wherein the overshoot control circuit includes: a. a pulse generating circuit configured to receive a differential data input signal including a first data input signal and a second data input signal for generating a plurality of signals having a plurality of pulses that control a duration of overshoot of the write cuπent, wherein the pulse generating circuit is further configured to receive a duration delay signal for controlling the plurality of pulses; and b. an overshoot magnitude circuit coupled to the pulse generating circuit and to the current amplifier of the second driving circuit for generating an overshoot cuπent through a differential overshoot output that controls a magnitude of the overshoot of the write cuπent, wherein the overshoot magnitude circuit is configured to receive the plurality of signals from the pulse generating circuit and to receive a reference cuπent control signal for controlling the overshoot cuπent, and wherein the overshoot current provided to the second driving circuit causes formation of an amplified overshoot cuπent at the switching circuit providing the wnte cuπent to the inductive element.

22. The magnetic storage system according to claim 21 wherein the pulse generating circuit includes: a. a delay element configured to receive the first data input signal and to receive the duration delay signal such that the delay element provides a delay to the first data input signal corresponding to the duration delay signal, thereby forming a first delayed data input signal; b. a first NAND circuit coupled to the delay element for receiving the second data input signal and the first delayed data input signal and for generating a first differential output signal including a first output signal and a second output signal, wherein the first differential output signal includes one or more of the plurality of pulses; c. an inverting circuit coupled to the delay element for inverting the first delayed data input signal, thereby forming an inverted first delayed data input signal; and d. a second NAND circuit coupled to the inverting circuit for receiving the first data input signal and the inverted first delayed data input signal and for generating a second differential output signal including a third output signal and a fourth output signal, wherein the second differential output signal includes one or more of the plurality of pulses.

23. The magnetic storage system to claim 21 wherein the overshoot magnitude circuit includes a plurality of input transistors, each coupled to one of the signals generated by the pulse generating circuit and to an overshoot reference cuπent that is controlled by the reference cuπent control signal, wherein the overshoot cuπent is dependent on the overshoot reference cuπent, and wherein the plurality of input transistors are coupled in a cuπent switch aπangement.

24. The magnetic storage system according to claim 20 further including: a. a first delay element coupled to the first driving circuit and configured to receive the differential data input signal including the first data input signal and the second data input signal and to receive a first delay signal, wherein the first delay element provides a first delay to the first data input signal coπesponding to the first delay signal, thereby forming a second delayed data input signal, and provides the first delay to the second data input signal coπesponding to the first delay signal, thereby forming a third delayed data input signal; and b. a second delay element coupled to the second driving circuit and configured to receive the differential data input signal including the first data input signal and the second data input signal and to receive a second delay signal, wherein the second delay element provides a second delay to the first data input signal coπesponding to the second delay signal, thereby forming a fourth delayed data input signal, and provides the second delay to the second data input signal coπesponding to the second delay signal, thereby forming a fifth delayed data input signal.

25. The magnetic storage system according to claim 24 wherein the first and second delay signals are configured to reduce distortion in the write cuπent supplied to the head by the write amplifier circuit.

26. The magnetic storage system according to claim 24 wherein the first and second delay signals are selectively programmable.

27. The magnetic storage system according to claim 20 further including a damping circuit coupled to the switching circuit and to the second driving circuit for reducing an undershoot and a settling time of the write cuπent.

28. A magnetic storage system comprising: a. a magnetic medium for storing data; b. an inductive element for wnting data to the magnetic medium by converting a write cuπent to a magnetic field, wherein the inductive element includes one of a plurality of response characteristics; c. a write amplifier circuit for supplying the write cuπent to the inductive element, the write amplifier circuit including: i. a switching circuit coupled to the inductive element for providing the write cuπent to the inductive element; ii. a first driving circuit configured for coupling to and driving the switching circuit; iii. a second driving circuit configured for coupling to and driving the switching circuit, wherein the second driving circuit includes a cuπent amplifier; iv. a first delay element coupled to the first driving circuit and configured to receive a differential data input signal including a first data input signal and a second data input signal and to receive a first delay signal, wherein the first delay element provides a first delay to the first data input signal coπesponding to the first delay signal, thereby forming a first delayed data input signal, and provides the first delay to the second data input signal coπesponding to the first delay signal, thereby forming a second delayed data input signal; and v. a second delay element coupled to the second driving circuit and configured to receive the differential data input signal including the first data input signal and the second data input signal and to receive a second delay signal, wherein the second delay element provides a second delay to the first data input signal coπesponding to the second delay signal, thereby forming a third delayed data input signal, and provides the second delay to the second data input signal coπesponding to the second delay signal, thereby forming a fourth delayed data input signal; and d. an interface coupled to the write amplifier circuit for providing a plurality of control signals and a plurality of delay signals to the write amplifier circuit.

29. The magnetic storage system according to claim 28 wherein the first and second delay signals are configured to reduce distortion in the write cuπent supplied to the head by the write amplifier circuit.

30. The magnetic storage system according to claim 28 wherein the first and second delay signals are selectively programmable.

31. The magnetic storage system according to claim 28 further including an overshoot control circuit coupled to the second driving circuit for controlling an overshoot of the write current.

32. The magnetic storage system according to claim 31 wherein the overshoot control circuit includes: a. a pulse generating circuit configured to receive the differential data input signal including a first data input signal and a second data input signal for generating a plurality of signals having a plurality of pulses that control a duration of overshoot of the write cuπent, wherein the pulse generating circuit is further configured to receive a duration delay signal for controlling the plurality of pulses; and b. an overshoot magnitude circuit coupled to the pulse generating circuit and to the cuπent amplifier of the second driving circuit for generating an overshoot cuπent through a differential overshoot output that controls a magnitude of the overshoot of the write current, wherein the overshoot magnitude circuit is configured to receive the plurality of signals from the pulse generating circuit and to receive a reference current control signal for controlling the overshoot cuπent, and further wherein the overshoot current provided to the second driving circuit causes formation of an amplified overshoot current at the switching circuit providing the write cuπent to the inductive element.

33. The magnetic storage system according to claim 32 wherein the pulse generating circuit includes: a. a delay element configured to receive the first data input signal and to receive the duration delay signal such that the delay element provides a delay to the first data input signal coπesponding to the duration delay signal, thereby forming a fifth delayed data input signal; b. a first NAND circuit coupled to the delay element for receiving the second data input signal and the fifth delayed data input signal and for generating a first differential output signal including a first output signal and a second output signal, wherein the first differential output signal includes one or more of the plurality of pulses; c. an inverting circuit coupled to the delay element for inverting the fifth delayed data input signal, thereby forming an inverted fifth delayed data input signal; and d. a second NAND circuit coupled to the inverting circuit for receiving the first data input signal and the inverted fifth delayed data input signal and for generating a second differential output signal including a third output signal and a fourth output signal, wherein the second differential output signal includes one or more of the plurality of pulses.

34. The magnetic storage system according to claim 32 wherein the overshoot magnitude circuit includes a plurality of input transistors, each coupled to one of the signals generated by the pulse generating circuit and to an overshoot reference current that is controlled by the reference cuπent control signal, wherein the overshoot cuπent is dependent on the overshoot reference cuπent, and wherein the plurality of input transistors are coupled in a cuπent switch aπangement.

35. The magnetic storage system according to claim 28 further including a damping circuit coupled to the switching circuit and to the second driving circuit for reducing an undershoot and a settling time of the write current.