WO2001022598A1 - Procede et dispositif de creation de donnees de decision ponderee - Google Patents

Procede et dispositif de creation de donnees de decision ponderee Download PDF

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Publication number
WO2001022598A1
WO2001022598A1 PCT/JP1999/005053 JP9905053W WO0122598A1 WO 2001022598 A1 WO2001022598 A1 WO 2001022598A1 JP 9905053 W JP9905053 W JP 9905053W WO 0122598 A1 WO0122598 A1 WO 0122598A1
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Prior art keywords
data
level
soft decision
soft
decision data
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PCT/JP1999/005053
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English (en)
Japanese (ja)
Inventor
Natsuhiko Nakayauchi
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Fujitsu Limited
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Priority to PCT/JP1999/005053 priority Critical patent/WO2001022598A1/fr
Publication of WO2001022598A1 publication Critical patent/WO2001022598A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45—Soft decoding, i.e. using symbol reliability information
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization

Definitions

  • the present invention relates to a method and an apparatus for generating soft decision data, and more particularly to a soft decision input data which is weighted by level and output as soft decision data with a small number of bits of the input data.
  • the present invention relates to a method and apparatus for generating judgment data.
  • the erroneous correction code is used to correct erroneous information contained in received information, reproduction information, and the like so that the original information can be correctly decoded, and is applied to various systems. For example, when transmitting data without error in mobile communications and other data communications
  • error correcting codes include convolutional codes and turbo codes.
  • Figure 9 shows an example of a convolutional encoder. It has a 2-bit shift register SFR and two exclusive OR circuits EX0R1 and EX0R2, where EX0R1 is the exclusive OR g of the input and R. Outputs, EX0R2 outputs an exclusive OR gi between the input and the R 0. Therefore, the input / output relationship of the convolutional encoder and the state of the shift register SFR when the input data is 01001 are as shown in FIG.
  • the contents of the shift register SFR of the convolutional encoder are defined as state. As shown in Fig. 11, four states of 00, 01, 10, and 11 are peri, where each is state a and state b. , State c, and state d. In the convolutional encoder shown in FIG. 9, it is determined whether the state of the shift register SFR is a to d and whether the next input data is "0" or "1". , And the output (g 0 , and the next state are uniquely determined.
  • Figure 12 shows the relationship between the state of the convolutional encoder and the input and output. The dotted line indicates the “0” input, and the solid line indicates the “1” input. That is,
  • the convolutional code of the convolutional encoder of FIG. 9 is represented in a lattice-like form (trellis diagram) as shown in FIG. 13 (A).
  • k means the input time of the k-th bit
  • the dotted line “0" input and the solid line “gamma indicates the input, two numbers on the line indicates the output (g 0, gl). Therefore, in the initial state a (00),” the input is 0 " Then, the output becomes 00 and the state becomes a, and when "1" is input, the output becomes 11 and the state becomes c.
  • the received data is determined first. There are two types of this decision, a hard decision and a soft decision.
  • the soft decision compensates for the disadvantages of the hard decision.As shown as an example at the left end of Fig. 14, the detection output is quantized at, for example, eight levels, and the certainty is weighted according to each level. The decision result is output to the decoder.
  • the Viterbi decoding method for decoding convolutional codes can output hard-decision input hard-decision output and soft-decision input hard-decision output.
  • the hard decision input and the hard decision output assuming that the hard decision received data (go, gi) is 11 ⁇ 10 ⁇ 10 ⁇ 11 ⁇ 11 and is in an ideal state without errors, Fig. 15 ( The path indicated by the two-dot chain line with the arrow in A) is obtained, and by setting the dotted line to "0" and the solid line to "1", the decoding result of 11001 can be obtained as shown in Fig. 17 (B). .
  • received data often contains errors. This opens the interface shown in FIG.
  • the decoding result 11001 having the minimum number of errors ERR is selected and output. In this way, the original data 11001 can be correctly restored even if there is an error in the received data.
  • FIG. 16 is an explanatory diagram of decoding in the case of soft-decision reception data.
  • the soft-decision reception data (g 0 , gi) power 1,1 ⁇ 1,0 ⁇ 1,0 ⁇ 2 Suppose that / 8,1 ⁇ 1,1.
  • ERR error count
  • the decoding result 11001 having the minimum number of errors ERR is selected and output. In this way, the original data 11001 can be correctly restored even if there is an error in the received data.
  • the soft decision has the same principle as the hard decision except that the number of errors ERR is no longer an integer, but improves the ability to determine the number of errors with high accuracy and improves the error correction capability.
  • each of the states a, b, c, d at the time of inputting the k-th data by using the data up to the k-th (k 1, 2,...) Of the coded data having the information length N Then, a path having a small number of errors is selected from the two paths leading to the state, and a path having a large number of errors is discarded. Thereafter, the state is similarly reached for each state at the time of the final N-th data input. The path with the least error is selected from the two paths, and decoding is performed using the path with the least error among the paths selected in each state.
  • the level of received data always fluctuates due to the communication environment, noise, etc.
  • weighting of demodulated data is performed based on the level to obtain soft decision data, and the soft decision data is input to an error correction decoder.
  • a configuration for performing decoding is adopted. In this case, the number of bits of the soft-decision data A obtained by weighting the demodulated data is larger than the number of bits of the soft-decision data B handled by the error correction decoder. That is, the weighted soft decision data A also finely represents the soft decision data input to the error correction decoder. Therefore, as shown in Fig.
  • an ALC (Automatic Level Contor 1) circuit 3 is provided between the demodulator 1 and the soft decision decoder (erroneous correction decoder) 2, and the bit of the soft decision data A is The number is reduced and converted into soft-decision data B having the number of bits that can be handled by soft-decision decoder 2.
  • soft decision data B is generated by reducing the number of bits as faithfully as It needs to be passed to the decoder 2, which is conventionally done as follows.
  • the soft decision data A (consisting of a sign bit and an amplitude bit) weighted by the separator 3a is separated into a sign bit and an amplitude bit, and the sign bit is stored in the sign bit memory 3b.
  • the amplitude bit is stored in the data holding memory as 3c and input to the maximum value detector 3d.
  • the maximum value detector 3d detects a maximum value for each error correction code length unit, and notifies the bit selector 3e of the maximum value.
  • the bit selector 3e retrieves the specific amplitude bit so as to make use of the maximum value notified in the data storage stored in the data holding memory 3c, and extracts the sign bit memory. 3 Retrieve and add the corresponding sign bit to b, and output it as soft decision data B.
  • da t a ⁇ 15..0 ⁇ xaaa aaaa aaaa aaaa x: Sign hit, a: 0orl (1) is input to ALC circuit 3. Also, the number n of data that constitutes one error correction code length is 300, and the maximum level of the amplitude represented by 15 bits is a binary number.
  • the ALC circuit 3 outputs the soft decision data as nan [4..0] to output the weighted data A and the 5-bit (one sign bit + 4 amplitude bits) soft decision data B. , Nan [4] data [15], nan [3..0] ⁇ da ta [13..10] (3)
  • the bit selection range is switched based on the maximum value obtained for each error correction code length.
  • the switching timing of the bit selection range in the conventional method has an advantage that control can be easily performed by switching at a low speed in units of one error correction code length.
  • the bit selection range is determined only by the maximum value.
  • the ALC circuit 3 cannot convert the weighted soft-decision data A into appropriate soft-decision data B, and the gain in subsequent error correction decoding is significantly reduced, and the original data cannot be decoded correctly.
  • the bit selection range according to the conventional method (4 bits from the first “1” at the maximum level) Is not appropriate, the upper 2 or 3 bits of the 4 bits of soft decision data B become 0, and only "1" appears in the lower 1 or 2 bits, and the amplitude bits are used effectively. And the gain in error-correction decoding decreases significantly.
  • the number of soft decision bits must be increased in order to generate optimal soft decision data.
  • such a method has a problem that the hardware scale of the erroneous correction decoder is significantly increased.
  • Another object of the present invention is to reduce the re-memory and shorten the overall processing time by mixing the soft decision data generation processing with the dinterleaving processing.
  • the soft decision data generator of the present invention converts input data weighted by level into soft decision data having a smaller number of bits than the input data and outputs the soft decision data. That is, the average value calculation unit calculates the level average value of the input data for each error correction code length, and the soft decision data determination unit determines that the soft decision data corresponding to the input data having the level average value is all " It is located at the center of all soft decision data from "0" to all "1", and the input data on both sides of the average value are converted to predetermined soft decision data corresponding to the level and output.
  • the variance calculating means calculates the variance of the input data level from the level average value
  • the soft decision data determination unit converts the variance of the input data level to the soft decision data of 0 (zero) based on the calculated variance.
  • the third level range sandwiched between is equally assigned to all soft decision data except for all "0" and all "1".
  • the soft-decision data determining unit converts the input data into soft-decision data corresponding to the level range including the level and outputs the soft-decision data.
  • the variance calculation means calculates the variance of the input data level from the level average value, and the soft decision data decision unit determines the two central variances based on the calculated variance.
  • the level range of the soft-decision data, the level range of the two soft-decision data on both sides, and so on, are set in the same way, and the input data is set according to the level range where the level is located. Output as soft decision data. In this case, each level range is made wider as it goes away from the average value.
  • the soft decision data corresponding to the input level is generated with the level average as the center, the amplitude bits can be used effectively, the gain in error correction decoding can be improved, and the original Can decrypt data.
  • the storage unit stores the input data
  • the soft decision data determination unit reads out the input data one by one from the storage unit after calculating the average value and the variance value, and softly reads the input data. Convert to judgment data and output.
  • the process of generating soft decision data is mixed with the deinterleaving process to reduce re-memory and shorten the overall processing time.
  • FIG. 1 is a schematic configuration diagram of a wireless device including a soft decision data generation unit (ALC circuit) of the present invention.
  • ALC circuit soft decision data generation unit
  • FIG. 2 is an explanatory diagram of the principle of generating soft decision data according to the first embodiment.
  • FIG. 3 is a flowchart for generating soft decision data according to the first embodiment.
  • FIG. 4 is an explanatory diagram of the principle of generating soft decision data according to the second embodiment.
  • FIG. 5 is a flowchart for generating soft decision data according to the second embodiment.
  • FIG. 6 is a configuration diagram of the soft decision data generator (ALC circuit) of the present invention.
  • FIG. 7 shows a modification of the soft decision data generator (ALC circuit) of FIG.
  • FIG. 8 is another configuration diagram of the soft decision data generator (ALC circuit) of the present invention.
  • FIG. 9 is an example of a convolutional encoder.
  • FIG. 10 is a diagram for explaining the input / output relationship of the convolutional encoder and the state of the shift register SFR.
  • FIG. 11 is an explanatory diagram of the state of the convolutional encoder.
  • FIG. 12 is a diagram showing the relationship between the state of the convolutional encoder and the input / output.
  • FIG. 13 is a diagram showing the convolutional codes of the convolutional encoder in a lattice form.
  • FIG. 14 is an explanatory diagram of hard decision and soft decision.
  • FIG. 15 is an explanatory diagram of a decoding method for hard decision input and hard decision output.
  • FIG. 16 is an explanatory diagram of a decoding method of a soft decision input and a hard decision output.
  • FIG. 17 is an explanatory diagram of a conventional ALC circuit.
  • A Radio equipment including soft decision data generator (ALC circuit)
  • FIG. 1 is a schematic configuration diagram of a wireless device including a soft decision data generation unit (ALC circuit) according to the present invention.
  • the wireless device for example, there are a mobile phone device and a transmitting device of a CDMA system, a PD system, or the like.
  • 21 is an upper layer processing unit
  • 22 is a channel codec
  • Reference numeral 3 denotes a modulation unit for modulating a carrier wave to code data
  • reference numeral 24 denotes a radio unit.
  • the baseband transmission frequency is up-converted to a high-frequency signal, amplified by a transmission power amplifier, transmitted to a transmission antenna 25, and transmitted.
  • the high-frequency signal received by the antenna 26 is down-converted into a baseband signal and output.
  • 27 is a demodulation unit that demodulates the received data and weights and outputs the received level, and 28 converts the weighted input data A to soft-decision data B that has a smaller number of rebits than the input data.
  • a soft decision data generator (ALC circuit) 29 is a channel codec, which is an error correction decoder such as a Viterbi decoder for error correction decoding of a convolutional code.
  • the level average value E and the root mean square value E 2 are obtained, and the variance V is obtained using these E and E 2 . If the number of input levels per unit of error correction code length is represented by n and each input level is represented by B bits, the input data D is
  • V E 2 — E 2 (8)
  • soft decision data C m or cm (K bits) corresponding to input data having an average value E from all bits “1” to all bits “0” so as to be positioned in the center of the 2 K-number of the entire soft-decision data, and the first level range R 1 for outputting soft decision data of all bits "1" (2 ⁇ _ 1 ) ⁇
  • the third level range R3 sandwiched between the first and second level ranges is equally allocated to the remaining 2 (m-1) soft decision data. Since the width of the third level range R 3 is 2 ⁇ f (V), the level width X of each soft decision data is
  • each soft decision data c 0 , ci, c 2 , ⁇ , c 2m -i can be assigned to each level range shown in Fig. 2.
  • the soft decision data can be determined and output depending on which level range the input data level falls within. That is, according to the first embodiment, the B-bit input data level can be converted into K-bit soft-decision data using the average value E and the truncation f (V).
  • the cutoff level E f (V) for outputting soft decision data of all bits “1” and all bits “0” is varied by the variance V.
  • the variance V will be large, and the truncation level will be far from the average E.
  • the dispersion of the input level from the average E is small, the variance V will be As it gets smaller, the cut-off level approaches the average value E. In this way, the width in which all soft-decision data other than all bits "1" and all bits "0” are represented by K bits is switched according to the variance of the input level. Data can be accurately converted to K-bit soft-decision data and output.
  • FIG. 3 is a flowchart of generating soft decision data.
  • j ++ means increment j.
  • the level width X of each (2m ⁇ 2) pieces of soft decision data included in the third level range R 3 is obtained (step 101).
  • 2 K 2 m.
  • d i is compared with the average value E (step 104). If d i ⁇ E, j is compared with (m ⁇ 2) (step 105).
  • the input data di is the region R ' 3 , in FIG. Check if it is included in.
  • soft decision data is output (step 107).
  • step 104 if d E, j is compared with (m ⁇ 2) (step 110). If j ⁇ m ⁇ 2, the following equation is obtained.
  • step 115 If the soft decision data is output in steps 107, 109, 111, 114, i is incremented (step 115), and it is checked whether i ⁇ n (step 116). ”, Reads the next data d; from the memory and repeats the subsequent processing. If“ YES ”, outputs soft-decision data of n input data in units of 1 error correction code length. To end.
  • the soft decision data C m or cm corresponding to the input data having the average value E is obtained from the soft decision data c 0 of all bits “0” to the soft decision of all bits “1”. It is located at the center of all soft decision data up to data C.
  • the outermost level range R If m -Rm-,,, is the (ml) level range (i m-1), the boundary level of the i-th level range RiQ RM is
  • V i is a cut-off function that determines the boundary of the i-th level range
  • each soft decision data CQ C 1 C 2 ⁇ ⁇ ⁇ (: can be assigned to each level range shown in Fig. 4. Therefore, the input data level is included in any level range. It is possible to determine and output soft decision data depending on whether or not it is rare.
  • the i-th level range is determined based on the average value E and the truncation function f (V, i), and the input data level is included in any level range. Since the soft decision data is determined, the B-bit input data can be faithfully converted to K-bit soft decision data according to the level. In particular, since each level range is varied by the variance V, and the level range is widened as it departs from the average value E, the number of input data included in each level range can be made uniform and the B-bit input data can be reduced. It can be faithfully converted to K-bit soft decision data.
  • FIG. 5 is a flowchart for generating soft decision data.
  • j ++ means to increment j
  • f (V, -1) 0.
  • d i is compared with the average value E (step 204). If d i d E, j is compared with (m ⁇ 2) (step 205). If j m m ⁇ 2, the following equation is obtained.
  • the input data di is the region R 0 in FIG. Check whether it is included.
  • step 204 if d i ⁇ E, j is compared with (m ⁇ 2) (step 2 10). If j ⁇ m ⁇ 2, the following equation is obtained.
  • step 215 If the soft decision data is output in steps 207, 209, 212, and 214, i is incremented (step 215), then it is checked whether it is in (step 216), and if "N0", the next data d is read from the memory, and the subsequent processing is repeated. If “YES”, the soft decision data output of n input data of one error correction code length unit is terminated.
  • k is a constant.
  • FIG. 6 is a block diagram of the soft decision data generator (ALC circuit) 28 of the present invention. It is assumed that input data is interleaved on the data transmitting side.
  • the average value calculation unit 51 calculates the average value ⁇ of ⁇ pieces of input data constituting one error correction code length according to equation (6), and the variance calculation unit 52 calculates the variance V as (7), (8 ) Equation is calculated.
  • the first and second memories 53a and 53b for ALC are composed of n error correction code lengths.
  • the input data is alternately stored, and when one is written, the other is read and input to the soft decision data determination unit 54.
  • the soft decision data decision unit 54 uses the average value E, the variance V, and n pieces of input data constituting one error correction code length stored in the first and second memories 53a and 53b. Then, the soft decision data is determined and output according to the processing flow of FIG. 3 or FIG.
  • the first and second dinterleave memories 55a and 55b alternately store n pieces of soft-decision data constituting one error correction code length output from the soft-decision data generator 28, and When the data is written to the other side, the soft decision data is read out in the order of the reinterleaving, rearranged in the order before interleaving, and input to the error correction decoder (soft decision Viterbi decoder, etc.) 56.
  • the error correction decoder 56 performs a decoding process on the input data and outputs the result.
  • the first memory 53 a stores n input data constituting the first one error correction code length
  • the average value calculation unit 51 calculates the average value E
  • the variance calculation unit 52 calculates the variance V.
  • the soft-decision data determining unit 54 sequentially uses the average value E and the variance V to sequentially input n pieces of input data constituting one error correction code length stored in the first memory 53 a.
  • the data is converted into soft decision data and written to the next stage memory 55a.
  • the second memory 53b stores n input data constituting the following one error correction code length
  • the average value calculation unit 51 calculates the average value E
  • the calculation unit 52 calculates the variance V.
  • the soft-decision data determination unit 54 configures the 1 error correction code length stored in the second memory 53 b using the average value E and the variance V of the second 1 error correction code length.
  • the n input data are sequentially converted to soft decision data and written to the next-stage ding leave memory 55b.
  • the first memory 53 a stores the n input data constituting the third 1 error correction code length
  • the average calculation unit 51 calculates the average E.
  • the variance calculation unit 52 calculates the variance V.
  • the interleave 55 a reads out the soft decision data in the order of the interleave, rearranges the data in the order before interleaving, inputs the data to the error correction decoder (soft decision decoder) 56, and outputs the error correction decoder 56.
  • the input data is decrypted and output.
  • the read / write of the memos 53a, 53b and the memos 55a, 55b are alternately switched for each error correction code length. And repeat the above operation.
  • the soft decision data generator 28 can be realized using a DSP (digital signal processor) or using a microcomputer.
  • Fig. 6 is applicable to the case where the input data is all positive, for example, but if the input data is positive or negative signed, as shown in Fig. 8, the separator 57 and the sign bit memories 58 a and 58 b are used. Provide.
  • Separator 57 separates the input data into code bits and amplitude bits, and code bit memories 58a and 58b store the code bits alternately for each error correction code length. It is read out and input to the soft decision data decision unit 54.
  • the average value calculation unit 51 calculates the average value E of n pieces of amplitude data constituting one error correction code length according to equation (6), and the variance calculation unit 52 calculates the variance V as (7), ( 8) Calculate using equation.
  • the first and second memories 53a and 53b for ALC alternately store n pieces of amplitude data constituting one error correction code length, and when writing to one, read from the other to make a soft decision data decision section. Enter 54.
  • the soft decision data determination unit 54 uses the average value E, the variance V, and n pieces of amplitude data constituting one error correction code length stored in the first and second memories 53a and 53b, The soft decision amplitude data is determined according to the processing flow of FIG. 3 or FIG. 5, and the corresponding sign bit is retrieved from the sign bit memories 58a and 58b and added to the amplitude data to produce soft decision data. Output.
  • FIG. 8 is another block diagram of the soft decision data generator (ALC circuit) 28 of the present invention, and the same parts as those of the soft decision data generator of FIG. The difference is
  • a deinterleave address controller 61 that generates addresses in deinterleave order is provided.
  • First and second memories 53a, 53b Read input data in the order of de-interleaving, rearrange the input data in the order before interleaving, and enter the soft-decision data determining unit 54. That is, the soft decision data is directly input to the error correction decoder 56.
  • the memory can be reduced, and the processing delay required for the ding leave can be reduced as compared with the embodiment of FIG.
  • FIG. 8 is applicable to the case where all the input data is positive. However, if the input data is positive or negative, a separator and a sign bit memory are provided as in FIG.
  • the soft decision data generator (ALC circuit) of the present invention By using the soft decision data generator (ALC circuit) of the present invention, even in an environment where the reception level fluctuates rapidly, the reception level can be established. It can be easily converted to statistical soft decision data, and error correction can be performed later. A high gain can be obtained in decoding, and communication quality can be improved.
  • the soft decision data generator (ALC circuit) of the present invention can output more optimal soft decision than before, so that the number of soft decision bits in error correction decoding can be reduced to obtain the same gain. And the hardware scale of the receiver can be reduced. In addition, since the soft decision data generation processing and the deinterleaving processing can be performed in a mixed manner, the overall processing time can be reduced.

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Abstract

L'invention concerne un dispositif de création de données de décision pondérée servant à convertir des données d'entrée pondérées, selon leurs niveaux, en données de décision pondérée dont le nombre de bits est inférieur à celui des données d'entrée, et à produire lesdites données de décision pondérée. Une section de calcul de moyenne calcule la moyenne de niveau E des données d'entrée pour chaque longueur de code de correction d'erreur. Une section de calcul de dispersion utilise ladite moyenne pour calculer la dispersion V représentant la diffusion des niveaux des données d'entrée. Sur la base de la moyenne E et de la dispersion V, une section de détermination de données de décision pondérée établit une première plage de niveau d'entrée pour convertir les données d'entrée en données de décision pondérée dont tous les bits sont '1', établit une seconde plage de niveau d'entrée pour convertir les données d'entrée en données de décision pondérée dont tous les bits sont '0', et, entre la première plage et la seconde plage, attribue une troisième plage de niveau d'entrée aux données de décision pondérée autres que celles dont les bits sont '0' ou '1', ce qui permet de convertir les données d'entrée en fonction de la plage de niveau contenant les données en données de décision pondérée, et de produire lesdites données.
PCT/JP1999/005053 1999-09-17 1999-09-17 Procede et dispositif de creation de donnees de decision ponderee WO2001022598A1 (fr)

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EP1383254A1 (fr) * 2001-04-27 2004-01-21 Mitsubishi Denki Kabushiki Kaisha Appareil de reception
EP1383254A4 (fr) * 2001-04-27 2006-10-04 Mitsubishi Electric Corp Appareil de reception
JP2003078506A (ja) * 2001-08-30 2003-03-14 Mitsubishi Electric Corp 軟判定処理ビット数削減装置、受信機および軟判定処理ビット数削減方法
JP4652632B2 (ja) * 2001-08-30 2011-03-16 三菱電機株式会社 軟判定処理ビット数削減装置、受信機および軟判定処理ビット数削減方法
WO2003026239A1 (fr) * 2001-09-13 2003-03-27 Mitsubishi Denki Kabushiki Kaisha Recepteur optique
US7239673B2 (en) 2001-09-13 2007-07-03 Mitsubishi Denki Kabashiki Kaisha Optical reception apparatus
JP2012151913A (ja) * 2012-05-18 2012-08-09 Sumitomo Electric Ind Ltd 軟判定復号装置および軟判定復号プログラム
WO2017175754A1 (fr) * 2016-04-06 2017-10-12 日本電信電話株式会社 Système de communication sans fil et procédé de communication
CN108886372A (zh) * 2016-04-06 2018-11-23 日本电信电话株式会社 无线通信***以及通信方法
US10404501B2 (en) 2016-04-06 2019-09-03 Nippon Telegraph And Telephone Corporation Wireless communication system and communication method
CN108886372B (zh) * 2016-04-06 2022-08-23 日本电信电话株式会社 无线通信***以及通信方法

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