WO2000070672A1 - Creation of a corner of an electric strip conductor, in particular, consisting of copper, which has been produced by damascene work on a substrate - Google Patents

Creation of a corner of an electric strip conductor, in particular, consisting of copper, which has been produced by damascene work on a substrate Download PDF

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Publication number
WO2000070672A1
WO2000070672A1 PCT/DE2000/001409 DE0001409W WO0070672A1 WO 2000070672 A1 WO2000070672 A1 WO 2000070672A1 DE 0001409 W DE0001409 W DE 0001409W WO 0070672 A1 WO0070672 A1 WO 0070672A1
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Prior art keywords
conductor track
deflection
conductor
substrate
bevel
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PCT/DE2000/001409
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German (de)
French (fr)
Inventor
Holger HÜBNER
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Infineon Technologies Ag
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Publication of WO2000070672A1 publication Critical patent/WO2000070672A1/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths

Definitions

  • the present invention relates to the configuration of the shape of an electrical conductor track on a substrate at a point on this conductor track at which the course thereof has an approximately or more than 60 °, in particular also a right-angled change in direction or deflection of its course.
  • This is a conductor track that is produced on the substrate using the so-called Damascene technology.
  • copper is preferably used because of its low specific electrical resistance and its high resistance to electrical migration.
  • the Damascus technology for structuring, in particular, copper conductor tracks consists in that first a layer of electrically insulating material, i.e. an insulator layer is applied. Silicon dioxide is preferably used as the material for this layer. The material of the layer is deposited on the substrate in a thickness which is essentially equal to the thickness which the subsequent conductor track is to have.
  • the pattern of the conductor track (s) to be produced is etched down into the insulator layer down to the substrate surface.
  • the groove or groove produced by the etching in accordance with the predetermined structure of the conductor track to be produced is now filled with the copper of the conductor track. This measure is based on the production of
  • Damascene iron workpieces With the Damascene technology used here, the metal of the conductor tracks is inserted into the Furrows or grooves of the insulator layer introduced by growing or separating. With a subsequent chemical / mechanical polishing process (CMP), metal protruding beyond the surface of the insulator layer is removed, so that finally the regions of the insulator layer and the metallic regions embedded therein, ie conductor tracks, ideally together form a completely planar surface.
  • CMP chemical / mechanical polishing process
  • the intended planar surface is generally not ideally flat, but the copper of the conductor tracks, which is much softer than the material of the insulator layer, is more strongly removed in the polishing process.
  • there is a large amount of metallization e.g. relatively wide conductor tracks, more or less heavy washing out (dishing) of the metal surface.
  • the second problem is that when provided very little
  • Layer thickness (e.g. less than 5 ⁇ m)
  • a rounding of the edges of the insulator layer originally produced by etching has a relatively strong effect. This also contributes to the fact that the conductor track to be produced is impermissibly reduced in thickness by the polishing in those places where the dishing and this edge erosion have a greater effect.
  • the object of the present invention is to provide a method for producing a conductor track according to the Damascus method and an integrated circuit structure with a conductor track produced according to this method, in which washouts or edge erosions are avoided in the region of a deflection.
  • an insulator layer is applied to the surface of the substrate and structured by etching so that it has a groove, the shape of which corresponds to the shape of the conductor track to be produced later.
  • the conductor track is completed by filling the groove with metal, in particular copper, and chemical-mechanical polishing.
  • a conductor track produced according to the Damascene method is thus arranged on the surface of a substrate, it is surrounded by an insulator layer, with which it essentially closes off in height.
  • the diagonal conductor track width by 2 larger in the corners of the deflection by chamfering the outer corner of the conductor track or the outer edge of the deflection thereof, so that the diagonal width is then reduced there.
  • hard material of the same is left in this (outer) corner, so that a polygonal edge with now preferably two corners is created and the resulting diagonally measured width of the conductor track produced is reduced in this deflection.
  • the diagonally measured width of the conductor track in the deflection, which is reduced by the bevel is preferably such, e.g. dimensioned to the size of the normal width of the conductor track, so that there is now no major washout of e.g. Copper of the conductor path occurs during polishing than it generally occurs along the respective conductor path and can be taken into account quantitatively for the design of the circuit.
  • Figure 1 shows the measure according to the invention in supervision
  • FIG. 2 shows a further development for conductor tracks, which run in parallel in particular adjacent multiple times and are deflected together.
  • Denoted by 1 in FIG. 1 is a conductor track with a right-angled deflection 3 on a substrate S. This is located here between adjacent electrically conductive regions 21 and 22, which can also be further conductor tracks (11, 12 in FIG. 2). In practice, such a conductor track 1 has a width of a few 10 ⁇ m.
  • the thin webs 2 shown are left in the etching process mentioned above. nes material of the insulator layer previously applied in the Damascus technology, for example of silicon dioxide. These webs 2 electrically isolate the conductor track 1 from the regions 21 and 22.
  • the normal width of the conductor track 1 is designated by b. With a a dimension is indicated, which relates to the bevel 4 according to the invention of the outer corner or the beveled outer edge 14 of the conductor track 1.
  • the diagonally oriented width of the conductor track as specified in the preceding description and visible in FIG. 1 and thus resulting there, is designated by d.
  • d «b is measured. It can be seen from the dimensional relationships shown that with such a dimensioning of the diagonal width d, i.e.
  • a bevel 5 (as shown) of the inner corner can also be provided or the inner edge 15 of the conductor track 1 may be provided.
  • This bevel 5 would increase the diagonal width d again.
  • Such a rectangular coil designed according to the invention differs very well from a known coil with an approximately octagonal shape of the windings, namely essential to the invention in that, with the invention, there is still only minimal space for the rectangular coil is required on the substrate surface.
  • a known octagonal coil has a comparatively larger space requirement.
  • the bevel 5 of the inner corner or the inner edge 15 of the respective conductor track 1, 11, 12 ..., e.g. of the individual turns of an otherwise rectangular coil, advantageously also reduces a disadvantageously increased current density in the conductor track that otherwise occurs in such a corner.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to the creation of the form of a strip conductor which has been produced by damascene work on a substrate (S), comprising diagonal corners (4, 5) at each deviation (3) of the strip conductor. The invention is used, in particular, for rectangular strip conductor coils.

Description

Beschreibungdescription
AUSGESTALTUNG EINER ECKE EINER IN DAMASZENER-TECHNOLOGIE AUF EINEM SUBSTRAT HERGESTELLTEN ELEKTRISCHEN LEITERBAHN AUS INSBESONDERE KUPFERDESIGNING A CORNER OF AN ELECTRICAL ELECTRICAL PATH MADE OF DAMASCENE TECHNOLOGY ON A SUBSTRATE, IN PARTICULAR COPPER
Die vorliegende Erfindung bezieht sich auf die Ausgestaltung der Form einer elektrischen Leiterbahn auf einem Substrat an einer Stelle dieser Leiterbahn, an der deren Verlauf eine etwa oder mehr als 60°, insbesondere auch rechtwinklige Richtungsänderung bzw. Umlenkung ihres Verlaufes aufweist. Dabei handelt es sich um eine Leiterbahn, die in der sogenannten Damaszener-Technologie auf dem Substrat hergestellt ist.The present invention relates to the configuration of the shape of an electrical conductor track on a substrate at a point on this conductor track at which the course thereof has an approximately or more than 60 °, in particular also a right-angled change in direction or deflection of its course. This is a conductor track that is produced on the substrate using the so-called Damascene technology.
Für Halbleiterschaltungen und auch sonstige „gedruckte,, Schaltungen, bei denen die elektrischen Leiterbahnen auf einem Substrat ausgeführte elektrisch leitende metallene Streifen sind, wird bevorzugt Kupfer wegen dessen geringen spezi- fischen elektrischen Widerstandes und seiner hohen Beständigkeit gegenüber Elektrornigration verwendet. Die Damaszener- Technologie zur Strukturierung von insbesondere Kupfer- Leiterbahnen besteht darin, daß auf dem schon erwähnten Substrat zunächst eine Schicht aus elektrisch isolierendem Mate- rial, d.h. eine Isolatorschicht, aufgebracht wird. Vorzugsweise wird als Material für diese Schicht Siliziumdioxid verwendet. Das Material der Schicht wird auf dem Substrat in einer Dicke abgeschieden, die im wesentlichen gleich der Dicke ist, die die spätere Leiterbahn haben soll. Zur Strukturie- rung wird in diese Isolatorschicht das Muster der zu erzeugenden Leiterbahn (en) bis auf die Substratoberfläche hinunter hineingeätzt. Die der vorgegebenen Struktur der herzustellenden Leiterbahn entsprechend durch das Ätzen erzeugte Furche bzw. Nut wird nunmehr mit dem Kupfer der Leiterbahn aufge- füllt. Diese Maßnahme ist angelehnt an die Herstellung vonFor semiconductor circuits and also other “printed” circuits, in which the electrical conductor tracks are electrically conductive metal strips carried out on a substrate, copper is preferably used because of its low specific electrical resistance and its high resistance to electrical migration. The Damascus technology for structuring, in particular, copper conductor tracks consists in that first a layer of electrically insulating material, i.e. an insulator layer is applied. Silicon dioxide is preferably used as the material for this layer. The material of the layer is deposited on the substrate in a thickness which is essentially equal to the thickness which the subsequent conductor track is to have. For structuring, the pattern of the conductor track (s) to be produced is etched down into the insulator layer down to the substrate surface. The groove or groove produced by the etching in accordance with the predetermined structure of the conductor track to be produced is now filled with the copper of the conductor track. This measure is based on the production of
Damaszener-Eisenwerkstücken. Bei der hier angewendeten Damaszener-Technologie wird das Metall der Leiterbahnen in den Furchen bzw. Nuten der Isolatorschicht durch Aufwachsen oder Abscheiden eingebracht. Mit einem anschließenden chemisch/mechanischen Polierprozeß (CMP) wird über die Oberfläche der Isolatorschicht hinausragendes Metall abgetragen, so daß schließlich die Bereiche der Isolatorschicht und die auf der Substratoberfläche darin eingelagerten metallischen Bereiche, d.h. Leiterbahnen, im Idealfall zusammen eine völlig planare Oberfläche bilden.Damascene iron workpieces. With the Damascene technology used here, the metal of the conductor tracks is inserted into the Furrows or grooves of the insulator layer introduced by growing or separating. With a subsequent chemical / mechanical polishing process (CMP), metal protruding beyond the surface of the insulator layer is removed, so that finally the regions of the insulator layer and the metallic regions embedded therein, ie conductor tracks, ideally together form a completely planar surface.
Bei diesem Verfahren gibt es zwei Probleme zu lösen. Die beabsichtigt planare Oberfläche ist in der Regel nicht ideal plan, sondern das gegenüber dem Material der Isolatorschicht wesentlich weichere Kupfer der Leiterbahnen wird im Polierprozeß stärker abgetragen. Dadurch gibt es insbesondere bei größerflächigen Metallisierungen, z.B. relativ breiten Leiterbahnen, mehr oder weniger starke Auswaschungen (dishing) der Metalloberfläche. Das führt unerwünschterweise dazu, daß die vorgesehene Dicke der Leiterbahn vor allem im mittleren Bereich derselben zwischen den Rändern nicht eingehalten ist. Das zweite Problem ist, daß bei vorgesehen sehr geringerThere are two problems to be solved with this method. The intended planar surface is generally not ideally flat, but the copper of the conductor tracks, which is much softer than the material of the insulator layer, is more strongly removed in the polishing process. As a result, there is a large amount of metallization, e.g. relatively wide conductor tracks, more or less heavy washing out (dishing) of the metal surface. This undesirably leads to the fact that the intended thickness of the conductor track is not adhered to, especially in the central region thereof between the edges. The second problem is that when provided very little
Schichtdicke (z.B. kleiner 5 um) sich eine Abrundung der ursprünglich durch Ätzen erzeugten Kanten der Isolatorschicht relativ stark auswirkt. Auch dies trägt dazu bei, daß die zu erzeugende Leiterbahn an solchen Stellen, an denen sich das Dishing und diese Kantenerosion stärker auswirken, durch das Polieren unzulässig stark hinsichtlich ihrer Dicke verringert wird.Layer thickness (e.g. less than 5 µm), a rounding of the edges of the insulator layer originally produced by etching has a relatively strong effect. This also contributes to the fact that the conductor track to be produced is impermissibly reduced in thickness by the polishing in those places where the dishing and this edge erosion have a greater effect.
Ganz besonders wirken sich die vorgenannten negativen Effekte an solchen Stellen einer Leiterbahn aus, bei der diese auf dem Substrat eine etwa mehr als 60° Umlenkung, insbesondere einen rechtwinkligen Verlauf, hat. In einer rechtwinkligen Ecke ist die Breite der Leiterbahn, dort diagonal gemessen, um rund 40% breiter als das Maß der Breite im Bereich des ge- radlinigen Verlaufs. Eine nach dem Stand der Technik mit dem Polierprozeß auftretende Verringerung der Leiterbahndicke im Bereich insbesondere der Mitte einer solchen Umlenkung ist unerwünscht. Dies deshalb, weil diese Verringerung auch schwierig quantitativ erfaßbar ist. Eine mit ihr verbundene Minderung des dann dort effektiv wirksamen Stromleiterquerschnitts könnte somit bei der Auslegung der Schaltung kaum berücksichtigt werden.The above-mentioned negative effects have a very particular effect at those points on a conductor track in which it has an approximately more than 60 ° deflection on the substrate, in particular a rectangular course. In a right-angled corner, the width of the conductor track, measured diagonally there, is around 40% wider than the dimension of the width in the area of the straight line. A reduction in the conductor track thickness in the region, in particular in the middle, of such a deflection, which occurs with the polishing process according to the prior art undesirable. This is because this reduction is also difficult to quantify. A reduction in the current conductor cross-section that is then effective there could hardly be taken into account when designing the circuit.
Eine Abhilfe wäre an sich, solche „eckigen" Umlenkungen einer Leiterbahn zu vermeiden. Diese Lösung ist jedoch in der Praxis unerwünscht, weil eine derartige Maßnahme in der Regel zu größerem Flächenbedarf für eine vorgegebene Schaltung führen würde, d.h. eine hohe Ausnutzung der Substratoberfläche behindert wird. Besonders fällt dies für die Realisierung von „gedruckten,, Spulen auf der Substratoberflache ins Gewicht. Zur Platzeinsparung werden solche Spulen mit solchen Leiter- bahnen bevorzugt mit jeweils rechteckigem Verlauf der Windungen ausgeführt. Eine solche Rechteckspule hat also eine Vielzahl von wie oben erwähnten Problemstellen, nämlich in/an den Ecken der Windungen.A remedy in itself would be to avoid such "angular" deflections of a conductor track. However, this solution is undesirable in practice, since such a measure would generally require a larger area for a given circuit, ie a high utilization of the substrate surface is hindered This is particularly important for the realization of “printed” coils on the substrate surface. To save space, such coils with such conductor tracks are preferably designed with a rectangular course of the turns. Such a rectangular coil therefore has a large number of problem areas as mentioned above , namely in / at the corners of the turns.
Aufgabe der vorliegenden Erfindung ist es, ein Verfahren zur Herstellung einer Leiterbahn nach dem Damaszener-Verfahren und eine integrierte Schaltungsstruktur mit einer nach diesem Verfahren hergestellten Leiterbahn anzugeben, bei dem/der im Bereich einer Umlenkung Auswaschungen oder Kantenerosionen vermieden werden.The object of the present invention is to provide a method for producing a conductor track according to the Damascus method and an integrated circuit structure with a conductor track produced according to this method, in which washouts or edge erosions are avoided in the region of a deflection.
Diese Aufgabe wird mit den Merkmalen des Patentanspruchs 1 sowie des Patentanspruchs 7 und in Weiterbildung mit den Maßnahmen der Unteransprüche gelöst.This object is achieved with the features of patent claim 1 and patent claim 7 and in a further development with the measures of the subclaims.
Bei der Herstellung der Leiterbahn nach dem Damaszener-Verfahren wird auf die Oberfläche des Substrats eine Isolatorschicht aufgebracht und durch Ätzen so strukturiert, daß sie eine Furche aufweist, deren Form der Form der später herzu- stellenden Leiterbahn entspricht. Die Leiterbahn wird durch Auffüllen der Furche mit Metall, insbesondere Kupfer, und chemisch-mechanisches Polieren fertiggestellt. Eine nach dem Damaszener-Verfahren hergestellte Leiterbahn ist somit auf der Oberfläche eines Substrats angeordnet, sie ist von einer Isolatorschicht umgeben, mit der sie in der Hö- he im wesentlichen abschließt.In the production of the conductor track using the Damascene method, an insulator layer is applied to the surface of the substrate and structured by etching so that it has a groove, the shape of which corresponds to the shape of the conductor track to be produced later. The conductor track is completed by filling the groove with metal, in particular copper, and chemical-mechanical polishing. A conductor track produced according to the Damascene method is thus arranged on the surface of a substrate, it is surrounded by an insulator layer, with which it essentially closes off in height.
Erfindungsgemäß ist vorgeschlagen, die in den Ecken der Umlenkung um 2 größere diagonale Leiterbahnbreite zu reduzieren, indem die äußere Ecke der Leiterbahn bzw. der außenlie- gende Rand der Umlenkung derselben abgeschrägt wird, so daß dort die diagonale Breite dann vermindert ist. Es wird also beim Ausätzen der Isolatorschicht hartes Material derselben in dieser (äußeren) Ecke stehengelassen, so daß ein polygonaler Rand mit nun vorzugsweise zwei Ecken entsteht und die sich ergebende diagonal gemessene Breite der hergestellten Leiterbahn in dieser Umlenkung verringert ist. Die durch die Abschrägung verringerte diagonal gemessene Breite der Leiterbahn in der Umlenkung wird vorzugsweise derart, z.B. auf das Maß der normalen Breite der Leiterbahn, vermindert bemessen, daß dort nunmehr keine größere Auswaschung des z.B. Kupfers der Leiterbahn beim Polieren auftritt, als sie generell entlang der jeweiligen Leiterbahn auftritt und für die Auslegung der Schaltung quantitativ berücksichtigt werden kann.According to the invention, it is proposed to reduce the diagonal conductor track width by 2 larger in the corners of the deflection by chamfering the outer corner of the conductor track or the outer edge of the deflection thereof, so that the diagonal width is then reduced there. When etching out the insulator layer, hard material of the same is left in this (outer) corner, so that a polygonal edge with now preferably two corners is created and the resulting diagonally measured width of the conductor track produced is reduced in this deflection. The diagonally measured width of the conductor track in the deflection, which is reduced by the bevel, is preferably such, e.g. dimensioned to the size of the normal width of the conductor track, so that there is now no major washout of e.g. Copper of the conductor path occurs during polishing than it generally occurs along the respective conductor path and can be taken into account quantitatively for the design of the circuit.
Figur 1 zeigt die erfindungsgemäße Maßnahme in Aufsicht undFigure 1 shows the measure according to the invention in supervision and
Figur 2 zeigt eine Weiterbildung für insbesondere benachbart mehrfach parallel verlaufende und gemeinsam umgelenkte Leiterbahnen.FIG. 2 shows a further development for conductor tracks, which run in parallel in particular adjacent multiple times and are deflected together.
Mit 1 bezeichnet ist in Figur 1 eine Leiterbahn mit einer hier rechtwinkligen Umlenkung 3 auf einem Substrat S. Diese befindet sich hier zwischen benachbarten elektrisch leitenden Bereichen 21 und 22, die auch weitere Leiterbahnen (11, 12 in Figur 2) sein können. In der Praxis hat eine solche Leiterbahn 1 eine Breite von einigen 10 μm. Die dargestellten dünnen Stege 2 sind beim obenerwähnten Ätzprozeß stehengelasse- nes Material der vorausgehend in der Damaszener-Technologie aufgebrachten Isolatorschicht aus z.B. Siliziumdioxid. Diese Stege 2 isolieren elektrisch die Leiterbahn 1 gegen die Bereiche 21 und 22.Denoted by 1 in FIG. 1 is a conductor track with a right-angled deflection 3 on a substrate S. This is located here between adjacent electrically conductive regions 21 and 22, which can also be further conductor tracks (11, 12 in FIG. 2). In practice, such a conductor track 1 has a width of a few 10 μm. The thin webs 2 shown are left in the etching process mentioned above. nes material of the insulator layer previously applied in the Damascus technology, for example of silicon dioxide. These webs 2 electrically isolate the conductor track 1 from the regions 21 and 22.
Mit b ist die normale Breite der Leiterbahn 1 bezeichnet. Mit a ist eine Abmessung angegeben, die sich auf die erfindungsgemäße Abschrägung 4 der äußeren Ecke bzw. des dort abgeschrägten äußeren Randes 14 der Leiterbahn 1 bezieht. Die wie in der voranstehenden Beschreibung angegebene und in der Figur 1 ersichtliche, sich dort damit ergebende erfindungsgemäß verringerte diagonal ausgerichtete Breite der Leiterbahn ist mit d bezeichnet. Insbesondere wird d « b bemessen. Aus den dargestellten Abmessungsrelationen ist zu erkennen, daß bei einer solche Bemessung der diagonalen Breite d, d.h. wie gezeigter Abschrägung des äußeren Randes 14 der Leiterbahn 1, keine relevant größere Auswaschung des Materials der Leiterbahn 1 bei der Ausführung des Polierprozesses eintreten kann, nämlich wie dies ohnehin für die Leiterbahn mit der Breite b hinzunehmen bzw. tolerierbar ist. Die in Figur 1 mit zwei Ek- ken gezeigte Abschrägung 4 kann im Rahmen der Erfindung auch mit mehr als diesen zwei Ecken ausgeführt sein. Damit könnte jedoch wieder eine vergrößerte Abmessung b vorliegen, die aber durch anzupassende Bemessung wenigstens weitgehend ver- mieden werden kann.The normal width of the conductor track 1 is designated by b. With a a dimension is indicated, which relates to the bevel 4 according to the invention of the outer corner or the beveled outer edge 14 of the conductor track 1. The diagonally oriented width of the conductor track, as specified in the preceding description and visible in FIG. 1 and thus resulting there, is designated by d. In particular, d «b is measured. It can be seen from the dimensional relationships shown that with such a dimensioning of the diagonal width d, i.e. as shown in the beveling of the outer edge 14 of the conductor track 1, no relevantly larger washout of the material of the conductor track 1 can occur during the execution of the polishing process, namely how this is tolerable for the conductor track with the width b anyway. The bevel 4 shown in FIG. 1 with two corners can also be designed with more than these two corners within the scope of the invention. This could, however, again result in an enlarged dimension b, which, however, can at least be largely avoided by adapting the dimensioning.
Vorzugsweise bei mehrfach parallel laufenden, umgelenkten Leiterbahnen 1, 11, 12 ..., wie in Figur 2 gezeigt und wie dies insbesondere bei Rechteckspulen der Fall ist, kann gemäß einer Weiterbildung der Erfindung zusätzlich auch eine (wie dargestellte) Abschrägung 5 der inneren Ecke bzw. des inneren Randes 15 der Leiterbahn 1 vorgesehen sein. Zwar würde mit dieser Abschrägung 5 die diagonale Breite d wieder vergrößert werden. Es kann aber durch, vergleichsweise zur Figur 1, stärkere Abschrägung 4 der äußeren Ecke bzw. des äußeren Randes 14 der Leiterbahn 1 die diagonale Breite d wieder auf die bevorzugte Bemessung d = b zumindest angenähert eingestellt werden. Diese der Weiterbildung entsprechende Maßnahme kann an der jeweiligen Umlenkung für alle benachbart laufenden, gemeinsam umgelenkten Leiterbahnen 1, 11, 12 ... ausgeführt sein. Diese Maßnahme kann bei z.B. einer Rechteckspule an sämtlichen Ecken derselben ausgeführt werden.Preferably, in the case of multiply parallel, deflected conductor tracks 1, 11, 12 ..., as shown in FIG. 2 and as is the case in particular with rectangular coils, according to a development of the invention, a bevel 5 (as shown) of the inner corner can also be provided or the inner edge 15 of the conductor track 1 may be provided. This bevel 5 would increase the diagonal width d again. However, in comparison to FIG. 1, a greater bevel 4 of the outer corner or the outer edge 14 of the conductor track 1 can at least approximate the diagonal width d to the preferred dimensioning d = b become. This measure corresponding to the further development can be carried out on the respective deflection for all adjacent, jointly deflected conductor tracks 1, 11, 12 .... This measure can be carried out at all corners of a rectangular coil, for example.
Durch die erfindungsgemäße Abschrägung 4 der äußeren Ecke der inneren Leiterbahn, z.B. der Leiterbahn 11, ergibt sich nämlich die Möglichkeit, von dem dort beim Ätzprozeß stehenge- lassenen Anteil der Isolatorschicht den für die Abschrägung 5 der inneren Ecke der Leiterbahn 1 notwendigen Platz abzutrennen bzw. zu gewinnen, wie dies aus Figur 2 ersichtlich ist. Das Gleiche gilt für die Abschrägung 5 der inneren Ecke der in Bezug auf die Leiterbahn 1 nächstliegend äußeren Leiter- bahn 12. Dieses Schema kann von der innersten bis zur äußersten Leiterbahn für die jeweils benachbarten Ecken der Umlen- kungen ausgeführt werden.Due to the bevel 4 according to the invention of the outer corner of the inner conductor track, e.g. of the conductor track 11, there is the possibility of separating or gaining from the portion of the insulator layer left there during the etching process the space required for the bevel 5 of the inner corner of the conductor track 1, as can be seen from FIG. The same applies to the bevel 5 of the inner corner of the outer conductor track 12 closest in relation to the conductor track 1. This scheme can be carried out from the innermost to the outermost conductor track for the respectively adjacent corners of the deflections.
Eine solche nach der Erfindung (Figur 2) ausgeführte Recht- eckspule mit erfindungsgemäß abgeschrägten Ecken unterscheidet sich sehr wohl von einer an sich bekannten Spule mit etwa oktogonaler Form der Windungen, nämlich erfindungswesentlich darin, daß auch mit der Erfindung für die Rechteckspule weiterhin nur minimaler Platz auf der Substratoberfläche benö- tigt wird. Eine bekannte oktogonale Spule hat dagegen einen vergleichsweise größeren Platzbedarf.Such a rectangular coil designed according to the invention (FIG. 2) with bevelled corners differs very well from a known coil with an approximately octagonal shape of the windings, namely essential to the invention in that, with the invention, there is still only minimal space for the rectangular coil is required on the substrate surface. A known octagonal coil, on the other hand, has a comparatively larger space requirement.
Die Abschrägung 5 der inneren Ecke bzw. des inneren Randes 15 der jeweiligen Leiterbahn 1, 11, 12 ..., z.B. der einzelnen Windungen einer ansonsten rechteckigen Spule, vermindert auch vorteilhafterweise eine ansonsten in einer solchen Ecke auftretende stellenweise nachteilig erhöhte Stromdichte in der Leiterbahn.The bevel 5 of the inner corner or the inner edge 15 of the respective conductor track 1, 11, 12 ..., e.g. of the individual turns of an otherwise rectangular coil, advantageously also reduces a disadvantageously increased current density in the conductor track that otherwise occurs in such a corner.
Bis zu welchem Maß eine solche Abschrägung von äußeren Rand 14 und ggf. auch inneren Rand 15 am Ort einer jeweiligen Umlenkung z.B. benachbarter Leiterbahnen vorzunehmen ist und wie hoch eine solche äußere (4) und ggf. auch innere (5) Abschrägung zu bemessen ist, hängt in der Regel vom Einzelfall ab und kann jedoch vom Fachmann ohne weiteres auf den jeweiligen Einzelfall angepaßt bestimmt werden. To what extent such a beveling of the outer edge 14 and possibly also the inner edge 15 is to be carried out at the location of a respective deflection, for example of adjacent conductor tracks, and How much such an outer (4) and possibly also inner (5) bevel is to be dimensioned generally depends on the individual case and can, however, be readily determined by the person skilled in the art to be adapted to the respective individual case.

Claims

Patentansprüche claims
I. Verfahren zur Herstellung einer Leiterbahn (1) mit einer Umlenkung (3) auf der Oberfläche eines Substrats (S) nach dem Damaszener-Verfahren, g e k e n n z e i c h n e t d a d u r c h , daß der äußere Rand (14) der Leiterbahn an der Stelle der Umlenkung (3) abgeschrägt (4) wird.I. Process for producing a conductor track (1) with a deflection (3) on the surface of a substrate (S) according to the Damascene method, characterized in that the outer edge (14) of the conductor track is chamfered at the point of the deflection (3) (4) will.
2. Verfahren nach Anspruch 1, g e k e n n z e i c h n e t d a d u r c h , daß die diagonal gemessene Breite (d) der Leiterbahn (1) am Ort der Umlenkung derselben etwa gleich groß der Breite (b) der Leiterbahn (1) bemessen wird.2. The method of claim 1, g e k e n n z e i c h n e t d a d u r c h that the diagonally measured width (d) of the conductor track (1) at the location of the deflection thereof is approximately the same size as the width (b) of the conductor track (1).
3. Verfahren nach Anspruch 1 oder 2, g e k e n n z e i c h n e t d a d u r c h , daß der äußere Rand (14) der Abschrägung (4) wenigstens angenähert die Form eines zwei- oder noch mehrfach eckigen Poly- gonalzuges hat.3. The method of claim 1 or 2, g e k e n n z e i c h n e t d a d u r c h that the outer edge (14) of the bevel (4) has at least approximately the shape of a polygonal train with two or more corners.
4. Verfahren nach Anspruch 1, 2 oder 3, g e k e n n z e i c h n e t d a d u r c h , daß zusätzlich zur Abschrägung (4) des äußeren Randes (14) der Leiterbahn (1) an der Stelle der Umlenkung auch der innere Rand (15) dieser Leiterbahn (1) eine nach außen gerichtete Abschrägung (5) aufweist.4. The method according to claim 1, 2 or 3, characterized in that in addition to the bevel (4) of the outer edge (14) of the conductor track (1) at the point of deflection, the inner edge (15) of this conductor track (1) one after has outside bevel (5).
5. Verfahren nach Anspruch 4, g e k e n n z e i c h n e t d a d u r c h , daß bei mehrfachen, benachbart verlaufenden Leiterbahnen (1,5. The method of claim 4, g e k e n n z e i c h n e t d a d u r c h that with multiple, adjacent conductor tracks (1,
II, 12) mit gemeinsam verlaufender Umlenkung solche Abschrägungen (4 und 5) der jeweiligen äußeren Ränder (14) und der jeweiligen inneren Ränder (15) dieser Leiterbahnen (1, 11, 12) vorgesehen sind.II, 12) with common deflection, such bevels (4 and 5) of the respective outer edges (14) and the respective inner edges (15) of these conductor tracks (1, 11, 12) are provided.
6. Anwendung des Verfahrens nach einem der Ansprüche 1 bis 5 zur Herstellung elektrischen Spule auf der Oberfläche des Substrats.6. Application of the method according to one of claims 1 to 5 for producing electrical coil on the surface of the substrate.
7. Integrierte Schaltungsstruktur mit einer Leiterbahn (1), die auf der Oberfläche eines Substrats angeordnet ist, die von einer Isolatorschicht umgeben ist, die in der Höhe im wesentlichen mit der Isolatorschicht abschließt und die eine Umlenkung (3) aufweist, g e k e n n z e i c h n e t d a d u r c h , daß der äußere Rand (14) der Leiterbahn an der Stelle der Umlenkung (3) abgeschrägt (4) ist.7. Integrated circuit structure with a conductor track (1), which is arranged on the surface of a substrate, which is surrounded by an insulator layer which is substantially flush with the insulator layer and which has a deflection (3), characterized in that the outer edge (14) of the conductor track is chamfered (4) at the point of the deflection (3).
8. Schaltungsstruktur nach Anspruch 7, g e k e n n z e i c h n e t d a d u r c h , daß die diagonal gemessene Breite (d) der Leiterbahn (1) am Ort der Umlenkung derselben etwa gleich groß der Breite (b) der Leiterbahn (1) bemessen ist.8. Circuit structure according to claim 7, g e k e n n z e i c h n e t d a d u r c h that the diagonally measured width (d) of the conductor track (1) at the location of the deflection thereof is approximately the same size as the width (b) of the conductor track (1).
9. Schaltungsstruktur nach Anspruch 7 oder 8, g e k e n n z e i c h n e t d a d u r c h , daß der äußere Rand (14) der Abschrägung (4) wenigstens angenähert die Form eines zwei- oder noch mehrfach eckigen Polygonalzuges hat.9. Circuit structure according to claim 7 or 8, g e k e n n z e i c h n e t d a d u r c h that the outer edge (14) of the bevel (4) has at least approximately the shape of a polygonal train with two or more corners.
10. Schaltungsstruktur nach Anspruch 7, 8 oder 9, g e k e n n z e i c h n e t d a d u r c h , daß zusätzlich zur Abschrägung (4) des äußeren Randes (14) der Leiterbahn (1) an der Stelle der Umlenkung auch der innere Rand (15) dieser Leiterbahn (1) eine nach außen gerichtete Abschrägung (5) aufweist.10. Circuit structure according to claim 7, 8 or 9, characterized in that in addition to the bevel (4) of the outer edge (14) of the conductor track (1) at the point of deflection, the inner edge (15) of this conductor track (1) one after has outside bevel (5).
11. Schaltungsstruktur nach Anspruch 10, g e k e n n z e i c h n e t d a d u r c h , daß bei mehrfachen, benachbart verlaufenden Leiterbahnen (1, 11, 12) mit gemeinsam verlaufender Umlenkung solche Abschrägungen (4 und 5) der jeweiligen äußeren Ränder (14) und der jeweiligen inneren Ränder (15) dieser Leiterbahnen (1, 11, 12) vorgesehen sind.11. Circuit structure according to claim 10, characterized in that, in the case of multiple, adjacent conductor tracks (1, 11, 12) with deflection running together, such bevels (4 and 5) of the respective outer edges (14) and the respective inner edges (15) of these conductor tracks (1, 11, 12) are provided.
12. Schaltungsstruktur nach einem der Ansprüche 7 bis 11, g e k e n n z e i c h n e t d a d u r c h , daß die Leiterbahn (1) als auf der Oberfläche des Substrats ausgeführte elektrische Spule ausgebildet ist. 12. Circuit structure according to one of claims 7 to 11, g e k e n n z e i c h n e t d a d u r c h that the conductor track (1) is designed as an electrical coil executed on the surface of the substrate.
PCT/DE2000/001409 1999-05-18 2000-05-04 Creation of a corner of an electric strip conductor, in particular, consisting of copper, which has been produced by damascene work on a substrate WO2000070672A1 (en)

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DE19922789.6 1999-05-18

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Publication number Priority date Publication date Assignee Title
US11244900B2 (en) * 2020-01-17 2022-02-08 Samsung Electronics Co., Ltd. Wiring structures having a metal pattern intersection portion
US12009300B2 (en) 2020-01-17 2024-06-11 Samsung Electronics Co., Ltd. Wiring structures having intersecting metal patterns

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JPH03278537A (en) * 1990-03-28 1991-12-10 Nec Corp Semiconductor device
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JPH0249429A (en) * 1988-08-10 1990-02-19 Nec Corp Semiconductor device
EP0442491A2 (en) * 1990-02-14 1991-08-21 Kabushiki Kaisha Toshiba Semiconductor device having a wiring pattern in which a plurality of lines are arranged in close proximity to one another
JPH03278537A (en) * 1990-03-28 1991-12-10 Nec Corp Semiconductor device
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11244900B2 (en) * 2020-01-17 2022-02-08 Samsung Electronics Co., Ltd. Wiring structures having a metal pattern intersection portion
US12009300B2 (en) 2020-01-17 2024-06-11 Samsung Electronics Co., Ltd. Wiring structures having intersecting metal patterns

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