WO2000065701A1

WO2000065701A1 - Voltage spike protection device

Info

Publication number: WO2000065701A1
Application number: PCT/SE2000/000567
Authority: WO
Inventors: Claes-Göran BERGE
Original assignee: Siemens Ab
Priority date: 1999-04-27
Filing date: 2000-03-23
Publication date: 2000-11-02
Also published as: SE9901513D0

Abstract

A voltage spike protection device for protecting electronic components in an electric circuit against ESD spikes. The device comprises a closed housing (3, 4, 5, 6) which is preferably formed as a surface mount package and which contains two electrodes (7; 8) each having a proximal region (13; 12) separately electrically connectable external of the housing (3, 4, 5, 6) to provide a shunt path for voltage spikes in the electric circuit away from the electronic components and a distal region (9; 10). The distal regions (9; 10) of each electrode are dimensioned and separated by a gap (11) to provide a flash-over voltage less than a component damaging voltage and a GHz response frequency for the device and are preferably formed as triangular conducting layers of constant thickness sandwiched between insulating material (5, 6).

Description

Voltage Spike Protection Device

The present invention relates to a voltage spike protection device for protecting electronic components against rapid rise-time, short duration, high voltage, spikes such as are caused in electrostatic discharge (ESD) events. In particular the invention relates to a surface mount protection device suitable for use in ESD protection circuitry of portable electronic equipment.

Various types of power surges which are capable of destroying sensitive electronic components can occur in electrical circuits containing such components. Electrostatic discharge (ESD) is a particularly problematical power surge especially in portable electronic equipment such as mobile telecom- munications equipment and laptop computers.

It is well known that the human body (which typically has a capacitance of 150 to 200 picofarads (pF) ) frequently stores electrostatic charge which may be accumulated by walking on carpets, etc. The human body is quite capable of capacitively storing charge so as to be at a potential difference of several tens of kilovolts (kV) with respect to ground. When this voltage is discharged by a person touching electronic equipment a transient voltage spike may be created within the circuitry of the equipment having a rise time of typically less than 1 nanosecond and a current of around 30 amperes. This fast rise-time, high power spike can destroy sensitive electronic components, causing unexpected equipment failures.

One known voltage spike protection device used to protect sensitive electronic components against ESD is the metal oxide varistor. This device basically comprises a number of zinc oxide based discs in which each disc is made up from sintered granular material. Conduction occurs mainly as a result of flash-over across the grain boundaries. The voltage required to achieve conduction depends on the total disc thickness, whereas the current handling capability depends on the disc area (so the volume of the varistor decides its power handling) . Such a device is usually connected to the electric circuit to provide a current shunt path for voltage spikes before they can damage the sensitive electronic components .

However, this type of varistor has a relatively large capacitance which makes it unsuitable for use in certain high frequency circuits, such as in high frequency signal input lines of telecommunications equipment, where its presence can degrade the operation of the circuit. Moreover, the shape, size and constituency of the individual grains that make up each disc have to be carefully controlled in order to reproducibly guarantee the voltage/current characteristics of the varistor and requires the use of complex processes and equipment to do this.

It is an aim of the present invention to provide a voltage spike protection device which alleviates some of the problems associated with the known ESD protection device.

Accordingly there is provided a device described in and characterised by the present Claim 1 which, because of its electrode configuration, can provide ESD protection, operate in the gigahertz (GHz) frequency range and which can be readily packaged as standard sized (e.g. 0201, 0402, 0603, 0805 and 1206) surface mount components. Moreover, the electrodes can be readily and reproducibly fabricated using standard wet or dry multilayer chip technology and dimensioned and separated to tailor the flash-over voltage at which protection commences.

By tapering each electrode from the proximal region to the distal region, preferably to provide a substantially flat distal region, such as is provided in a frusto-conical, a frusto-pyra idal or a truncated thick triangular (trapezium based prism) electrode shape, the inductance and capacitance of the device may be lowered to increase its operating frequency. This particular shape of the electrodes also increases the electric field strength at the distal end so that substantially all flash over events between the electrodes will occur in this region.

Moreover, by providing substantially planar distal ends for the electrodes flash over is likely from any point of a relatively large region, substantially the whole of the planar region. This prolongs the lifetime of the device.

Usefully, the device may also include an insulating material disposed in contact with and enclosing the electrodes so as to leave the gap between the distal regions filled with a gaseous, preferably air, medium. This prevents accumulation of dust or other conductive elements in the gap between the electrodes which may otherwise be electrostatically attracted by the high electric fields present during use of the device. Moreover, the insulating material may be selected to provide physical protection for the electrodes and be arranged as at least part of the housing. In this way the external dimensions of the device are reduced.

The device according to the present invention may be used in a voltage spike protection circuit where it is combined with one or more known devices that are adapted to provide protection at voltages below the flash-over voltage in order to provide protection over an extended voltage range.

An exemplary embodiment of the protection device according to the present invention will now be described with reference to the drawings of the accompanying figures of which:

Figure 1 shows an external view of the surface mount device package.

Figure 2 shows a cross-sectional view along A-A. Figure 3 shows a cross-sectional view along B-B .

Figure 4 shows a detail view of one electrode of the device of Figures 1 to 3.

Considering now Figure 1, the surface mount package 1 comprises a protective body 2 and electrically conductive end-caps 3,4 which together form a sealed housing. From Figure 2 it can be seen that the protective body 2 comprises electrically insulating ceramic layers 5, 6 respectively forming upper and lower body sections. Sandwiched between these layers 5,6 are a pair of electrodes 7,8 which are formed as thick metallised films deposited on one of the facing surfaces of the insulating ceramic layers 5,6. The distal ends 9,10 of the respective electrodes 7,8 are planar and separated by a gap 11 and their proximal ends 13,12 are in electrical contact with their respective conductive end- caps 4,3. With reference to Figure 3, each electrode 7,8 is tapered towards its respective distal end 9,10 to form a truncated triangular shape in a plane parallel to the facing surface of the insulating layer 6 (or 5) onto which it is deposited.

Figure 4 shows the general shape of the electrodes 7,8 of the device of Figures 1 to 3. For clarity all further references will be to only one electrode 7. It can be seen that the electrode 7 has rectangular cross-section distal 9 and proximal 13 ends. A pair of substantially parallel truncated- triangle shaped faces 14,15 are arranged opposing one another and spaced apart by side walls 16,17 of substantially constant thickness W of approximately 50xl0^"6m. The tapered electrode 7 so formed is of a trapezium based prism shape and has a proximal end 13 of length Lp of between approximately 2.5xl0^~'^sm and 1.25xl0^_3m, depending on the size of the final surface mount device shown in Figure 1. The distal end 9 of electrode 7 has a length Ld of between approximately Lp/3 and Lp/4 to provide the desired plate area (here, for example, chosen to be 2.5xl0^~8 m²) . This distal end 9 will, in use, form one plate of a parallel plate capacitor in which the other plate is formed by an identical electrode 8.

A device as shown in Figures 1 to 3 may be fabricated using known production techniques in which the ceramic layer 6 (or 5) has screen printed or sputtered thereon a suitably shaped metal layer (in this embodiment a bow-tie shape of two joined electrodes 7,8 will be suitable). The gap 11 between the electrodes 7,8 is then formed using a laser to remove the required amount of metal. The second ceramic layer 5 (or 6) is placed to cover the electrodes 7,8 and the sandwich so formed is pressed together under a high pressure to encapsulate the air gap electrode arrangement 7,8,11. This package is then cut to its final surface mount size (for example I.E.C. standard sizes from 0201 upwards) and dried in an oven. After drying the electrically conductive end-caps 3,4 are formed in a conventional manner by first dipping the ends of the package into a silver (Ag) bath and then chemically adding a nickel-tin (NiSn) layer.

It will be understood by those skilled in the art that the electrodes may be formed using other known techniques, such as etching using the photo-resist method common in printed circuit board fabrication, and that the protective housing may be formed in other ways.

The planar surfaces that form the distal faces 9,10 of the electrodes 7,8 have a surface area of typically between 1 and 10 xlO^"8 m² and are separated by a gap 11 of between lxlO^-5 m and 5x10^"4 m to provide a device capacitance which may be readily calculated using the equation:

C = (ε₀xε_rxA)/ (d) (1)

where C is the capacitance in farads ε_r is the relative dielectric constant = 1 for air ε₀ is the free space dielectric constant = 8.85xl0^~12 Frrf¹

A is the area of the distal ends of the electrodes d is the separation between the distal ends

and is 0.0074 pF for a device where A=2.5xl0^~8 m² and d=30xl0^"6m. In reality, because of stray capacitance effects, the actual capacitance of the device will be somewhat higher than that calculated theoretically from the equation (1) above and will typically be of the order of 0.1 pF for a device as dimensioned above.

A capacitance of 0.1 pF provides an operating frequency, f₀, for the device which may be calculated using the equation:

f₀ = 1/(2XITXV(LXC) (2)

where L is the inductance of the device and C is the capacitance calculated from (1) above

and will be approximately 7 GHz, assuming L=5xl0^"9H.

The break-down or flash-over voltage V_f may be calculated using the equation:

V_f = V_bxd (3)

where V_b is the break-down voltage for air and is approximately lkV per mm and d is the separation of the distal faces 9,10 of the electrodes 7,8.

This gives for the above dimensioned device a flash-over voltage of 30 volts.

It will be clear to a person skilled in the art that the operating characteristics may be readily tailored by varying the shape, dimensions and separation of the electrodes 7,8 and using the equations (1) to (3) above. These operating characteristics may also be readily tested and determined empirically using well known and standard test procedures and equipment . With each flash-over event an amount of metal may be lost from the electrodes 7,8, which amount increases as the electrode separation 11 decreases. If a too thin layer of metal is used a so-called "self-healing" phenomena will occur and metal evaporates from the electrode surfaces. To minimise or avoid these effects a preferable minimum separation between the electrodes 7,8 of between 3xl0^~5 m and lxl0^"4m is required. At these separation the amount of metal lost will not adversely effect the device operation for at least several hundred thousand (typically greater than 5,000,000) flash-over events.

Claims

1. A voltage spike protection device (1) for protecting electronic components in an electric circuit, the device comprising a closed housing (2,3,4) containing two electrodes (7; 8) each having a proximal region (13; 12) separately electrically connectable external of the housing (2,3,4) to provide a shunt path for voltage spikes in the electric circuit away from the electronic components and a distal region (9; 10) characterised in that the distal regions (9; 10) of each electrode are dimensioned and separated by a gap (11) to provide a flash-over voltage less than a component damaging voltage and a GHz response frequency for the device.

2. A voltage spike protection device as claimed in claim 1 characterised in that the distal regions (9;10) of the corresponding electrodes (7; 8) are substantially planar.

3. A voltage spike protection device as claimed in Claim 1 or Claim 2 characterised in that the distal regions (9; 10) of the electrodes (7; 8) are separated a gap (11) sufficient to inhibit significant loss of electrode material during flash-over.

4. A voltage spike protection device as claimed in Claim 3 characterised in that the distal regions (9; 10) are separated by no less than lxlO^-5 m and are dimensioned to provide a device capacitance of less than 1 pF.

5. A voltage spike protection device as claimed in Claim 3 or Claim 4 characterised in that the distal regions (9; 10) are separated by between lxlO^-5 and 5xl0^"4 m and dimensioned to provide a device capacitance of less than 0.1 pF.

6. A voltage spike protection device as claimed in any of the claims 2 to 4 characterised in that the distal regions (9; 10) are provided with an area of between lxl0^"8 m² and lxl0^"7 m².

7. A voltage spike protection device as claimed in any preceding Claim characterised in that each electrode (7; 8) is tapered to provide a cross-sectional area of the distal region (9; 10) less than that of the proximal region (13; 12) .

8. A voltage spike protection device as claimed in Claim 7 characterised in that each electrode is shaped with opposite sides that tend towards a common vertex and with the distal region of each electrode forming a frustum surface.

9. A voltage spike protection device as claimed in Claim 7 characterised in that each electrode (7; 8) is shaped as a substantially constant thickness trapezium based prism.

10. A voltage spike protection device as claimed any of the preceding claims characterised in that the electrodes (7; 8) are arranged with their distal regions (9; 10) separated by a gaseous medium and are sandwiched between contacting insulating layers (5; 6).

11. A voltage spike protection device as claimed in Claim 10 characterised in that each electrode (7; 8) is formed as a conductive layer deposited on a common insulating substrate (6) .

12. A voltage spike protection device as claimed in claim 10 or claim 11 characterised in that the housing (2,3,4) is fabricated into a surface mount package dimensioned according to I.E.C. standard sizes from 0201 upwards .