WO2000031809A1 - Element magnetoresistant et son utilisation comme element memoire dans un ensemble de cellules memoire - Google Patents

Element magnetoresistant et son utilisation comme element memoire dans un ensemble de cellules memoire Download PDF

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Publication number
WO2000031809A1
WO2000031809A1 PCT/DE1999/003696 DE9903696W WO0031809A1 WO 2000031809 A1 WO2000031809 A1 WO 2000031809A1 DE 9903696 W DE9903696 W DE 9903696W WO 0031809 A1 WO0031809 A1 WO 0031809A1
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WIPO (PCT)
Prior art keywords
ferromagnetic layer
layer
connection
ferromagnetic
magnetoresistive
Prior art date
Application number
PCT/DE1999/003696
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German (de)
English (en)
Inventor
Siegfried Schwarzl
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2000031809A1 publication Critical patent/WO2000031809A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices

Definitions

  • Magnetoresistive element and its use as a memory element in a memory cell arrangement.
  • Magnetoresistive elements also called magnetoresistive elements, are increasingly used as sensor elements or as memory elements for memory cell arrangements, so-called MRAMs (see S. Mengel, Technology Analysis Magnetism Volume 2, XMR Technologies, publisher VDI Technology Center Physical Technologies, August 1997).
  • MRAMs Magnetoresistive elements
  • a magnetoresistive element is understood to be a structure which has at least two ferromagnetic layers and a non-magnetic layer arranged between them.
  • GMR element magnetic resonance measurement resistive
  • TMR element Tunneling Magnetoresistive elements
  • GMR element is used in the technical field for layer structures which have at least two ferromagnetic layers and a non-magnetic, conductive layer arranged between them and which show the so-called GMR (giant magnetoresistance) effect.
  • GMR effect is understood to mean the fact that the electrical resistance of the GMR element is dependent on whether the magnetizations in the two ferromagnetic layers are aligned parallel or antiparallel.
  • the GMR effect is large compared to the so-called AMR (anisotropic magnetoresistance) effect.
  • AMR effect is understood to mean the fact that the resistance in magnetized conductors is different in parallel and perpendicular to the direction of magnetization.
  • the AMR effect is a volume effect that occurs in ferromagnetic single layers.
  • TMR element is used in the technical field for tunneling magnetoresistance layer structures which have at least two ferromagnetic layers and an insulating, non-magnetic layer arranged between them.
  • the insulating layer is so thin that there is a tunnel current between the two ferromagnetic layers.
  • These layer structures also show a magnetoresistive effect, which is brought about by a spin-polarized tunnel current through the insulating, non-magnetic layer arranged between the two ferromagnetic layers.
  • the electrical resistance of the TMR element depends on whether the magnetizations in the two ferromagnetic layers are aligned parallel or anti-parallel. The relative change in resistance is about 6 percent to about 40 percent.
  • GMR elements As memory elements in a memory cell array.
  • the memory elements are connected in series via read lines.
  • Word lines run at right angles to this and are insulated both from the read lines and from the memory elements. Due to the current flowing in the word line, signals applied to the word lines cause a magnetic field which, with sufficient strength, influences the memory elements located thereunder.
  • X / Y lines which cross at the memory cell to be written are used for writing in information. They are subjected to signals that cause a magnetic field sufficient for the magnetic reversal at the crossing point. The direction of magnetization in one of the two ferromagnetic layers is switched.
  • the direction of magnetization in the other of the two ferromagnetic layers remains unchanged.
  • the party- The direction of magnetization in the last-mentioned ferromagnetic layer is maintained by an adjacent anti-ferromagnetic layer, which holds the direction of magnetization, or by the switching threshold for this ferromagnetic layer being changed by another material or dimensioning, for example layer thickness in comparison to the first called ferromagnetic layer is enlarged.
  • a storage element comprises a stack which has at least two ring-shaped ferromagnetic layer elements and a non-magnetic conductive layer element which is arranged between them and which is connected between two lines.
  • the ferromagnetic layer elements differ in their material composition.
  • One of the ferromagnetic layer elements is magnetically hard, the other magnetically softer.
  • the magnetization direction in the magnetically softer layer element is switched over, while the magnetization direction is retained in the magnetically harder layer element.
  • magnetoresistive elements for example as an integrated magnetoresistive memory cell arrangement (so-called MRAM) or as an integrated sensor arrangement
  • MRAM magnetoresistive memory cell arrangement
  • the integration of magnetoresistive elements in a semiconductor process technology is required.
  • temperatures up to at least about 450 ° C. occur in particular in the completion of the semiconductor arrangements in the so-called back-end process at the wafer level, also called BEOL (back end of line) (see, for example, D. Widmann et al, Integrated Technology Heidelberg, Springer Verlag 1996, p. 58), to which the magnetoresistive elements and the associated lines are also exposed.
  • BEOL back end of line
  • Diffusion lengths of 600 nm to 27 ⁇ m are expected for one hour at a temperature load of 450 ° C for the diffusion of Co, Fe and Ni into connections or conductor tracks that contain AI.
  • diffusion lengths of 10 to 50 nm are expected for one hour at a temperature load of 450 °.
  • a thermal load of one hour at 450 ° diffusion lengths of about 1 nm is expected.
  • the diffusion lengths can be increased and accelerated by grain boundaries, phase boundaries and crystal defects (vacancies and dislocations), by electrical fields and mechanical stress.
  • the invention is based on the problem of specifying a magnetoresistive element which can be produced in the context of a semiconductor process technology.
  • the magnetoresistive element has a first ferromagnetic layer element, a non-magnetic layer element and a second ferromagnetic layer element, the non-magnetic layer element being arranged between the first ferromagnetic layer element and the second ferromagnetic layer element.
  • the first ferromagnetic layer element is electrically connected to a first connection and the second ferromagnetic layer element is electrically connected to a second connection.
  • a first barrier layer is arranged between the first ferromagnetic layer element and the first connection, and a second barrier layer is arranged between the second ferromagnetic layer element and the second connection. The first barrier layer suppresses diffusion between the first connection and the first ferromagnetic layer element, the second barrier layer suppresses diffusion between the second connection and the second ferromagnetic layer element.
  • first barrier layer and the second barrier layer ensures that the magnetoresistive element, even if it is produced as part of a semiconductor process technology, is functional and that, in particular, changes in the electrical and magnetic properties Shafts due to diffusion-induced material migration at the interfaces of the first ferromagnetic layer element and the second ferromagnetic layer element can be avoided.
  • the first connection and the second connection are suitable for contacting the first ferromagnetic layer element and the second ferromagnetic layer element, respectively.
  • the first connection and the second connection are designed as contacts, lines or the like.
  • the first barrier layer and the second barrier layer are preferably formed from a material which acts as a diffusion barrier at least in the temperature range between 20 ° C. and 450 ° C.
  • the magnetoresistive element is a stack of flat layer elements.
  • the first ferromagnetic layer element, the non-magnetic layer element and the second ferromagnetic layer element are designed as flat layer elements which are arranged one above the other as a stack. It is within the scope of the invention that the dimensions of the first ferromagnetic layer element and the second ferromagnetic layer element are between 50 nm x 80 nm and 250 nm x 400 nm and the thickness of the first ferromagnetic layer element and the second ferromagnetic layer element is between 2 nm and 20 nm.
  • the thickness of the non-magnetic layer element is between 1 and 4 n.
  • the cross section of the first ferromagnetic layer element and the second ferromagnetic layer element is preferably essentially rectangular. It can also be round, oval, polygonal or ring-shaped.
  • the ferromagnetic layer elements preferably each contain at least one of the elements Fe, Ni, Co, Cr, Mn, Gd, or Dy.
  • the non-magnetic layer element can be both conductive and non-conductive. If the non-magnetic layer element is made of a conductive material, for example Cu, Au or Al, it preferably has a dimension perpendicular to the interface with the ferromagnetic layer elements of 2 nm to 4 nm. In this case, the magnetoresistive element is a GMR element.
  • the non-magnetic layer element is made of a non-conductive material, for example Al 2 O 3, NiO, HfO 2, iO 2, NbO and / or SiO 2, then it preferably has a thickness of between 1 and 4 nm.
  • the magnetoresistive element is a TMR element which, compared to a GMR element, has a high electrical resistance perpendicular to the tunnel layer.
  • the first barrier layer and the second barrier layer preferably contain Ta, W, Mo, Nb, TaN, WN, MoN, NbN, Ti, TiN, TiW, Cr, WSiN and / or Pd2Si.
  • the barrier layers are effective for ferromagnetic layer elements which contain Fe, Ni, Co, Cr, Mn, Gd and / or Dy and connections which are made of Al, Al / Cu, Cu, Al / Si or Cu with alloy additives consist of Ti, Hf, Zr, Mg and / or Al.
  • first barrier layer and the second barrier layer which act as a diffusion barrier between the first and second connection and the first and second ferromagnetic layer element, respectively, a diffusion of Co, Fe and Ni into the first connection and the second connection is thereby prevents the diffusion lengths of the barrier layer from being less than 1 nm at 450 ° C. when subjected to temperature loads of one hour.
  • the thickness of the barrier layers is preferably 10 to 100 nm, so that this diffusion is effectively suppressed.
  • the magnetoresistive element can, among other things, advantageously be used as a memory element in a memory cell arrangement.
  • the first connection and the second connection are connected to lines or part of lines via which the magnetoresistive element is driven.
  • the magnetoresistive element can be used as a sensor element.
  • FIG. 1 shows a magnetoresistive element which is connected between a first connection and a second connection.
  • FIG. 2 shows a section of a memory cell arrangement which has magnetoresistive elements as memory elements.
  • a first ferromagnetic layer element 1, a non-magnetic layer element 2 and a second ferromagnetic layer element 3 are arranged one above the other as a stack (see FIG. 1). They have an essentially rectangular cross section with dimensions of 130 nm x 250 nm.
  • the first ferromagnetic layer element 1 and the second ferromagnetic layer element 2 have a thickness of 10 nm.
  • the non-magnetic layer element 2 has a thickness of 2 nm.
  • the first ferromagnetic layer element 1 contains Co.
  • the non-magnetic layer element contains Al2O 3 .
  • the second ferromagnetic layer element 3 contains NiFe.
  • the first ferromagnetic layer element 1 is electrically connected to a first terminal 5 via a first barrier layer 4.
  • the first barrier layer 4 likewise has a rectangular cross section corresponding to the dimensions of the most ferromagnetic layer element 1.
  • the thickness of the first barrier layer 4 is 10 to 100 nm.
  • the first barrier layer 4 consists of Ta, W, Mo, Nb, TaN, WN, MoN, NbN, Ti, TiN, TiW, Cr, WSiN and / or Pd2Si.
  • the first connection 5 consists of AlSi, AlCu, Cu or Cu with alloy additions of Ti, Hf, Zr, Mg and / or Al.
  • the second ferromagnetic layer element 3 is connected to a second connection 7 via a second barrier layer 6.
  • the second barrier layer 6 likewise has an essentially rectangular cross section with dimensions corresponding to the second ferromagnetic layer element 3 and a thickness of 10 to 100 nm.
  • the second barrier layer 6 contains Ta, W, Mo, Nb, TaN, WN, MoN, NbN, Ti, TiN, TiW, Cr, WSiN and / or Pd2Si.
  • the second connection 7 contains AlSi,
  • the first connection 5 and the second connection 7 can each be part of lines via which the magnetoresistive element 1, 2, 3 can be controlled.
  • each storage element S is connected between a first line L1 and a second line L2.
  • the first connection of each of the memory elements S is connected to the first line L 1 or is part of the first line L 1 and the second connection is connected to the second line L 2 or is part of the second line L 2.
  • the first lines L1 run parallel to one another and cross the second lines L2, which also run parallel to one another (see FIG. 2).
  • a sufficient magnetic field is created to switch the direction of magnetization of one of the ferromagnetic layer elements.
  • the magnetic field effective at the respective crossing point is a superposition of the magnetic field induced by the current flow in the first line L1 and the magnetic field induced by the current flow in the second line L2.
  • the resistance value of the magnetoresistive elements which corresponds to the parallel orientation of the magnetization direction in the first ferromagnetic layer element to that in the second ferromagnetic layer element, becomes a first logical value
  • the resistance value, which corresponds to the antiparallel orientation of the magnetization direction in the first ferromagnetic layer element Layer element corresponds to that of the second ferromagnetic layer element, assigned a second logical value.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Hall/Mr Elements (AREA)

Abstract

L'invention concerne un élément magnétorésistant constitué d'une première couche ferromagnétique (1), d'une couche non magnétique (2) et d'une seconde couche ferromagnétique (3), et connecté entre un premier conducteur (5) et un premier conducteur (7). Entre la première couche ferromagnétique (1) et le premier conducteur (5), ainsi qu'entre la seconde couche ferromagnétique (3) et le second conducteur (7) est disposée une couche barrière (4, 6), qui empêche la diffusion entre les conducteurs et les couches ferromagnétiques (1, 3). L'élément magnétorésistant peut être utilisé comme élément mémoire ou comme élément capteur.
PCT/DE1999/003696 1998-11-19 1999-11-19 Element magnetoresistant et son utilisation comme element memoire dans un ensemble de cellules memoire WO2000031809A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19853427 1998-11-19
DE19853427.2 1998-11-19

Publications (1)

Publication Number Publication Date
WO2000031809A1 true WO2000031809A1 (fr) 2000-06-02

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10043159A1 (de) * 2000-09-01 2002-03-21 Infineon Technologies Ag Speicherzellenanordnung und Verfahren zu deren Herstellung
EP1195820A2 (fr) * 2000-09-06 2002-04-10 Infineon Technologies AG Circuit intégré magnétorésistant
WO2003088253A1 (fr) * 2002-04-18 2003-10-23 Infineon Technologies Ag Combinaisons de materiau pour couche superieure de jonction a effet tunnel, masque dur de jonction a effet tunnel et couche germe empilee de jonction a effet tunnel dans le traitement de memoire vive magnetique
WO2003096354A1 (fr) * 2002-05-10 2003-11-20 Infineon Technologies Ag Couche conductrice de lissage de surface pour dispositifs a semi-conducteur pourvus de couches de materiau magnetique
WO2005043546A1 (fr) * 2003-10-28 2005-05-12 Infineon Technologies Ag Cellule de memoire magnetoresistante et son procede de fabrication

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63308394A (ja) * 1987-06-10 1988-12-15 Mitsubishi Electric Corp 磁気抵抗効果素子の製造方法
US5524092A (en) * 1995-02-17 1996-06-04 Park; Jea K. Multilayered ferroelectric-semiconductor memory-device
US5777542A (en) * 1995-08-28 1998-07-07 Kabushiki Kaisha Toshiba Magnetoresistance effect device and manufacturing method thereof
US5792569A (en) * 1996-03-19 1998-08-11 International Business Machines Corporation Magnetic devices and sensors based on perovskite manganese oxide materials

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63308394A (ja) * 1987-06-10 1988-12-15 Mitsubishi Electric Corp 磁気抵抗効果素子の製造方法
US5524092A (en) * 1995-02-17 1996-06-04 Park; Jea K. Multilayered ferroelectric-semiconductor memory-device
US5777542A (en) * 1995-08-28 1998-07-07 Kabushiki Kaisha Toshiba Magnetoresistance effect device and manufacturing method thereof
US5792569A (en) * 1996-03-19 1998-08-11 International Business Machines Corporation Magnetic devices and sensors based on perovskite manganese oxide materials

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 013, no. 147 (E - 741) 11 April 1989 (1989-04-11) *

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10043159A1 (de) * 2000-09-01 2002-03-21 Infineon Technologies Ag Speicherzellenanordnung und Verfahren zu deren Herstellung
US6943393B2 (en) 2000-09-01 2005-09-13 Infineon Technologies Ag Memory cell arrangement and method of fabricating it
EP1195820A2 (fr) * 2000-09-06 2002-04-10 Infineon Technologies AG Circuit intégré magnétorésistant
EP1195820A3 (fr) * 2000-09-06 2007-08-15 Infineon Technologies AG Circuit intégré magnétorésistant
WO2003088253A1 (fr) * 2002-04-18 2003-10-23 Infineon Technologies Ag Combinaisons de materiau pour couche superieure de jonction a effet tunnel, masque dur de jonction a effet tunnel et couche germe empilee de jonction a effet tunnel dans le traitement de memoire vive magnetique
JP2005523575A (ja) * 2002-04-18 2005-08-04 インフィネオン テクノロジーズ アクチエンゲゼルシャフト Ｍｒａｍ加工におけるトンネル接合部キャップ層、トンネル接合部ハードマスク、およびトンネル接合部スタック種膜の材質の組み合わせ
KR100727710B1 (ko) * 2002-04-18 2007-06-13 인피네온 테크놀로지스 아게 저항성 반도체 메모리 소자 및 그 제조 방법
CN100444280C (zh) * 2002-04-18 2008-12-17 因芬尼昂技术股份公司 Mram装置及其制造方法
WO2003096354A1 (fr) * 2002-05-10 2003-11-20 Infineon Technologies Ag Couche conductrice de lissage de surface pour dispositifs a semi-conducteur pourvus de couches de materiau magnetique
US6846683B2 (en) 2002-05-10 2005-01-25 Infineon Technologies Ag Method of forming surface-smoothing layer for semiconductor devices with magnetic material layers
WO2005043546A1 (fr) * 2003-10-28 2005-05-12 Infineon Technologies Ag Cellule de memoire magnetoresistante et son procede de fabrication
US7566941B2 (en) 2003-10-28 2009-07-28 Infineon Technologies Ag Magnetoresistive memory cell and process for producing the same

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Publication number Publication date
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