WO2000031784A1 - Method for forming transistors on a thin semiconductor wafer - Google Patents

Method for forming transistors on a thin semiconductor wafer Download PDF

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Publication number
WO2000031784A1
WO2000031784A1 PCT/US1999/021958 US9921958W WO0031784A1 WO 2000031784 A1 WO2000031784 A1 WO 2000031784A1 US 9921958 W US9921958 W US 9921958W WO 0031784 A1 WO0031784 A1 WO 0031784A1
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WO
WIPO (PCT)
Prior art keywords
layer
device layer
active device
wafer
support
Prior art date
Application number
PCT/US1999/021958
Other languages
French (fr)
Inventor
Stephen E. Bernacki
Steven R. Collins
Original Assignee
Raytheon Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Company filed Critical Raytheon Company
Priority to AU61581/99A priority Critical patent/AU6158199A/en
Publication of WO2000031784A1 publication Critical patent/WO2000031784A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

Definitions

  • This invention relates generally to transistors and more particularly to transistors adapted to operate at relative high power levels.
  • silicon transistors are used as amplifier in sources of microwave energy.
  • radar applications such as S-band operation at around a frequency of 3 GHz
  • heat dissipation in the transistor More particularly, heat is generated in the transistor junctions on the front surface (i.e., the active device layer) of a silicon substrate. This heat has to be conducted away from the front surface to the back surface of the substrate where it is removed with a heat sink. Further, the heat flow, H, in a silicon substrate of thickness x is given by the following equation:
  • the heat flow through the silicon substrate limits the amount of power generated in the transistor and the amount of heat which may be generated in the transistor during operation.
  • the hotter the transistor the lower the transistor's reliability and the shorter the mean time before failure (MTBF) .
  • MTBF mean time before failure
  • the heat in the transistor limits the power of the radar and hence the range and range discrimination of the radar .
  • a method for forming a transistor.
  • the method includes providing a wafer having a semiconductor active device layer in one surface of the wafer, a semiconductor support layer in a second surface of the wafer, and an insulating layer therebetween. Doped regions are formed in the transistor device layer.
  • a sacrificial support is disposed on, and bonded to, the first surface of the wafer. The semiconductor support and the insulating layer are selectively etched while the sacrificial support provides structural integrity to the transistor device layer.
  • a thin active device layer can be formed and processed using the sacrificial support as a mechanical handing means.
  • the sacrificial support is selectively removed .
  • the selective etching of the semiconductor support layer and the insulating layer exposes a surface of the active device layer and a heat conductive layer is formed on the exposed surface of the active device layer.
  • the sacrificial support is selectively removed after forming the heat conductive layer.
  • a plurality of transistors is formed in the active device layer and such transistors are separated into individual transistors subsequent to the forming of the heat conductive layer and removal of the sacrificial support .
  • FIGS. 1A and 1A' through IE' are diagrammatical sketches of a wafer fabricated in accordance with the invention to form transistors at various stages in the fabrication thereof, FIG. 1A' being a cross-sectional sketch taken along line 1A'-1A' of FIG. 1A; and
  • FIGS. ID'' and IE'' are diagrammatical sketches of a wafer fabricated in accordance with an alternative embodiment of the invention to form transistors at various stages in the fabrication thereof.
  • the wafer 10 includes a semiconductor, here silicon, active device layer 12, a buried silicon dioxide insulating layer 14, and a silicon support layer, or substrate 16.
  • a semiconductor here silicon
  • active device layer 12 a semiconductor
  • buried silicon dioxide insulating layer 14 a silicon support layer, or substrate 16.
  • the thickness of the silicon device layer 12 typically varies from 0.1 micrometers to ten micrometers.
  • the buried silicon dioxide layer 14 has a thickness which varies from 0.5 micrometers to 1.5 micrometers. It should be noted that the silicon dioxide layer 14 is typically provided on the wafer 10 for device (i.e., transistor) isolation.
  • the silicon dioxide layer 14 is used as etch stop layer because it etches to a given etch at a rate substantially different from the etch rate of silicon to such given etch.
  • the thickness of the silicon support layer 16 is the same as bulk silicon substrates, for example 200 microns thickness for a 150 millimeter diameter wafer.
  • the silicon active device layer 12 may, or may not, have epitaxial silicon grown on it to achieve desired doping profiles.
  • doped base (B) and emitter (E) regions for each of a plurality of transistors 18 are formed in the active device layer 12 (i.e., the collector) using conventional transistor processes including photolithography, ion implantation, diffusion and metal contact deposition and etching processes.
  • the collector region of each of the transistors 18 is here the active layer 12.
  • the transistors 18 may be bipolar npn or pnp transistors, or n-channel or p-channel metal oxide semiconductor (MOS) field effect transistors (FETs) or junction field effect transistor (JFETs) or static induction transistors (SITs) , for example.
  • MOS metal oxide semiconductor
  • FETs n-channel or p-channel metal oxide semiconductor
  • JFETs junction field effect transistor
  • SITs static induction transistors
  • complete integrated circuits may also be fabricated in the active device layer 12.
  • Lines 19, here shown dotted, are etched into the wafer to provide guide lines (i.e., typically referred to as scribe lines, or streets) when dicing the transistors into individual die, as will be described.
  • a sacrificial support 20 is deposited on the top surface of the silicon device layer 12 (and on the metal contacts, not shown, and over the passivation layers, not shown, formed over the device layer 12) .
  • the sacrificial support 20 serves as a mechanical support, or handle, in subsequent processing.
  • the sacrificial support 20 here has a thickness greater than 100 microns.
  • the sacrificial support 20 should have an etch rate to a silicon etch which is substantially lower than the etch rate to of such etch to silicon. Further, the sacrificial support 20 should be transparent to enable the guide lines to visible during the dicing operation.
  • One such material for the support 20 is a polyimide and another material is silicon having a layer of silicon dioxide formed over the other peripheral surface thereof, as shown in FIG. 1C. Glass with the same thermal expansion coefficient as silicon may also be used as the sacrificial support 20.
  • the support layer 20 is "glued" to the active device layer 12 by photoresist, wax, or some other material which can be dissolved away without harming the silicon active device layer 12.
  • the wafer 10, with the sacrificial support layer 20, is submerged in a beaker, not shown, having a silicon selective etch, (i.e., an etch which etches silicon at a substantially greater rate than the etch rate of the sacrificial support 20) .
  • a silicon selective etch i.e., an etch which etches silicon at a substantially greater rate than the etch rate of the sacrificial support 20.
  • the silicon support layer 18 is selectively etched away up to the bottom of the buried silicon dioxide layer 14.
  • Such selective silicon etch is here formed using a standard hydrofluoric acid and nitric acid solutions, or potassium hydroxide solutions. Plasma etching using appropriate etch gasses such as CF 4 or CC1F 3 may be used as well.
  • etching process is a timed process and thus because of etch rate of silicon is substantially higher than the etch rate of the silicon dioxide layer 14, the silicon dioxide acts as an etch stop layer and the etching process is substantially self- limiting.
  • the bottom surface of the active device layer 12 is exposed and the sacrificial support 20 provides mechanical support for mechanical handling of the wafer 10.
  • the buried silicon dioxide layer 14 is selectively etched away from the bottom surface of the active device layer 12. This can easily be done with standard buffered hydrofluoric acid etch solutions. Plasma etching with appropriate etch gasses such as C 2 F 6 may be used as well .
  • the selective etch should etch silicon dioxide at a significantly higher rate that the etch rate of silicon. Further, the selective etch should etch silicon at a significantly lower rate that the etch rate of the material of the sacrificial support 20.
  • a thermally conductive layer 26 is formed.
  • layer 26 is thin layer, or film of gold.
  • the gold film 26 is a one micron gold film deposited onto the bottom surface of the silicon active device layer 12. This deposition can be done with standard sputtering or evaporation processes.
  • the transistors 18 formed in the active layer 20 are separated into individual devices, or die 30, here by mechanical sawing, an exemplary one of the transistors 18 being shown in FIG. IE.
  • the die 30 are attached onto a base 32 of a package.
  • gold silicon eutectic die attach techniques are used for good thermal conductivity.
  • the sacrificial support layer 20 is removed, here using standard wet or dry etching techniques using oxygen, for example .
  • the sacrificial support layer 20 is removed, here using standard wet or dry etching techniques using oxygen, for example.
  • the devices 18 are mechanically supported by the thermally conductive layer 26' , here a composite layer made up of the thin gold film 26, described above, and a thicker gold layer 26" (FIG. ID'') .
  • the one micro thick gold film 26' is deposited onto the bottom surface of the silicon device layer 12 as described above, to serve as a plating base for gold layer 26".
  • the thickness of the gold film 26' can vary from 0.5 to 5.0 microns.
  • the gold layer 26" is electroplated onto the bottom surface of the thin gold film 26' .
  • the thickness of the gold layer 26" is here 75 micrometers or more and provide for mechanical support and heat conduction in the finished device.
  • Electroplating is used because it can be deposited with desired thickness in reasonable time and low stress, although other methods of deposition may be used.
  • the transistors 18 are then diced into individual die 30 and bonded to packages 32, as shown in FIG. IE''.
  • the sacrificial support layer 20 is removed, here using standard wet or dry etching techniques using oxygen, for example .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Weting (AREA)

Abstract

A method for forming a transistor. The method includes providing a wafer having a semiconductor active device layer in one surface of the wafer, a silicon support layer in a second surface of the wafer, and an insulating layer therebetween. Doped regions are formed in the transistor device layer. A sacrificial support is disposed on, and bonded to, the first surface of the wafer. The silicon support and the insulating layer are selectively etched while the sacrificial support provides structural integrity to the transistor device layer. The sacrificial support is selectively removed. The selective etching of the silicon support layer and the insulating layer exposes a surface of the active device layer and a heat conductive layer is formed on the exposed surface of the active device layer. The sacrificial support is selectively removed after forming the heat conductive layer. A plurality of transistors is formed in the active device layer and such transistors are separated into individual transistors subsequent to the forming of the heat conductive layer and removal of the sacrificial support. With such method, a thin active device layer can be formed and processed using the sacrificial support as a mechanical handing means.

Description

METHOD FOR FORMING TRANSISTORS ON A THIN SEMICONDUCTOR WAFER
Background of the Invention This invention relates generally to transistors and more particularly to transistors adapted to operate at relative high power levels.
As is known in the art, silicon transistors are used as amplifier in sources of microwave energy. In radar applications, such as S-band operation at around a frequency of 3 GHz, a major problem is heat dissipation in the transistor. More particularly, heat is generated in the transistor junctions on the front surface (i.e., the active device layer) of a silicon substrate. This heat has to be conducted away from the front surface to the back surface of the substrate where it is removed with a heat sink. Further, the heat flow, H, in a silicon substrate of thickness x is given by the following equation:
H=dQ/dt=- A{dT/dx) where :
H=heat flow
Q=heat energy t=time k=thermal conductivity
A=area
T=temperature x=silicon substrate thickness.
With silicon substrates in the range of 75 microns to 150 microns in thickness, the heat flow through the silicon substrate limits the amount of power generated in the transistor and the amount of heat which may be generated in the transistor during operation. The hotter the transistor, the lower the transistor's reliability and the shorter the mean time before failure (MTBF) . Thus, the heat in the transistor limits the power of the radar and hence the range and range discrimination of the radar .
Summary of the Invention In accordance with the present invention, a method is provided for forming a transistor. The method includes providing a wafer having a semiconductor active device layer in one surface of the wafer, a semiconductor support layer in a second surface of the wafer, and an insulating layer therebetween. Doped regions are formed in the transistor device layer. A sacrificial support is disposed on, and bonded to, the first surface of the wafer. The semiconductor support and the insulating layer are selectively etched while the sacrificial support provides structural integrity to the transistor device layer.
With such method, a thin active device layer can be formed and processed using the sacrificial support as a mechanical handing means. In accordance with another feature of the invention, the sacrificial support is selectively removed .
In accordance with another feature of the invention, the selective etching of the semiconductor support layer and the insulating layer exposes a surface of the active device layer and a heat conductive layer is formed on the exposed surface of the active device layer.
In accordance with another feature of the invention, the sacrificial support is selectively removed after forming the heat conductive layer.
In accordance with still another feature of the invention, a plurality of transistors is formed in the active device layer and such transistors are separated into individual transistors subsequent to the forming of the heat conductive layer and removal of the sacrificial support .
Brief Description of the Drawing Other features of the invention, as well as the invention itself, will become more readily understood from the following detailed description when read together with the accompanying drawings, in which;
FIGS. 1A and 1A' through IE' are diagrammatical sketches of a wafer fabricated in accordance with the invention to form transistors at various stages in the fabrication thereof, FIG. 1A' being a cross-sectional sketch taken along line 1A'-1A' of FIG. 1A; and
FIGS. ID'' and IE'' are diagrammatical sketches of a wafer fabricated in accordance with an alternative embodiment of the invention to form transistors at various stages in the fabrication thereof.
Description of the Preferred Embodiments Referring now to FIGS. 1A and 1A' , a commercially available silicon-on-insulator wafer 10 is provided. The wafer 10 includes a semiconductor, here silicon, active device layer 12, a buried silicon dioxide insulating layer 14, and a silicon support layer, or substrate 16. Such wafers 10 are available from Ibis Technology Corporation and SOITEC USA Incorporated. The thickness of the silicon device layer 12 typically varies from 0.1 micrometers to ten micrometers. The buried silicon dioxide layer 14 has a thickness which varies from 0.5 micrometers to 1.5 micrometers. It should be noted that the silicon dioxide layer 14 is typically provided on the wafer 10 for device (i.e., transistor) isolation. Here, however, as will be described, the silicon dioxide layer 14 is used as etch stop layer because it etches to a given etch at a rate substantially different from the etch rate of silicon to such given etch. The thickness of the silicon support layer 16 is the same as bulk silicon substrates, for example 200 microns thickness for a 150 millimeter diameter wafer. The silicon active device layer 12 may, or may not, have epitaxial silicon grown on it to achieve desired doping profiles.
It is noted that doped base (B) and emitter (E) regions for each of a plurality of transistors 18 are formed in the active device layer 12 (i.e., the collector) using conventional transistor processes including photolithography, ion implantation, diffusion and metal contact deposition and etching processes. The collector region of each of the transistors 18 is here the active layer 12. The transistors 18 may be bipolar npn or pnp transistors, or n-channel or p-channel metal oxide semiconductor (MOS) field effect transistors (FETs) or junction field effect transistor (JFETs) or static induction transistors (SITs) , for example. In addition to single transistors, complete integrated circuits may also be fabricated in the active device layer 12. It should be noted that, for simplicity, metal contact layers, although present, are not shown. Lines 19, here shown dotted, are etched into the wafer to provide guide lines (i.e., typically referred to as scribe lines, or streets) when dicing the transistors into individual die, as will be described.
A sacrificial support 20 is deposited on the top surface of the silicon device layer 12 (and on the metal contacts, not shown, and over the passivation layers, not shown, formed over the device layer 12) . As will become apparent, the sacrificial support 20 serves as a mechanical support, or handle, in subsequent processing. The sacrificial support 20 here has a thickness greater than 100 microns. The sacrificial support 20 should have an etch rate to a silicon etch which is substantially lower than the etch rate to of such etch to silicon. Further, the sacrificial support 20 should be transparent to enable the guide lines to visible during the dicing operation. One such material for the support 20 is a polyimide and another material is silicon having a layer of silicon dioxide formed over the other peripheral surface thereof, as shown in FIG. 1C. Glass with the same thermal expansion coefficient as silicon may also be used as the sacrificial support 20. The support layer 20 is "glued" to the active device layer 12 by photoresist, wax, or some other material which can be dissolved away without harming the silicon active device layer 12.
Referring now to FIG. IB', the wafer 10, with the sacrificial support layer 20, is submerged in a beaker, not shown, having a silicon selective etch, (i.e., an etch which etches silicon at a substantially greater rate than the etch rate of the sacrificial support 20) . Thus, the silicon support layer 18 is selectively etched away up to the bottom of the buried silicon dioxide layer 14. Such selective silicon etch is here formed using a standard hydrofluoric acid and nitric acid solutions, or potassium hydroxide solutions. Plasma etching using appropriate etch gasses such as CF4 or CC1F3 may be used as well. It is noted that while there is lateral (i.e., outer peripheral) etching of the silicon active device layer 12, such etching will remove about 200 micrometers of the outer periphery of the wafer 10 which here has a diameter of about 150 millimeters thereby resulting in a loss of an insignificant number of transistors formed on the wafer 10. Further, with any processing, peripheral devices are typically sacrificed anyway. It should also be noted that if the etch of the silicon support layer 18 were performed after each transistor were diced from the wafer, any lateral etching of the individual die would have significant effect on the individual, diced transistor device. The etching process is a timed process and thus because of etch rate of silicon is substantially higher than the etch rate of the silicon dioxide layer 14, the silicon dioxide acts as an etch stop layer and the etching process is substantially self- limiting.
At this point in the process, (i.e, after removal of the silicon support layer 18) , the bottom surface of the active device layer 12 is exposed and the sacrificial support 20 provides mechanical support for mechanical handling of the wafer 10.
Referring to FIG. 1C , the buried silicon dioxide layer 14 is selectively etched away from the bottom surface of the active device layer 12. This can easily be done with standard buffered hydrofluoric acid etch solutions. Plasma etching with appropriate etch gasses such as C2F6 may be used as well . Preferably, the selective etch should etch silicon dioxide at a significantly higher rate that the etch rate of silicon. Further, the selective etch should etch silicon at a significantly lower rate that the etch rate of the material of the sacrificial support 20.
Referring now to FIG. ID' , a thermally conductive layer 26 is formed. Here, layer 26 is thin layer, or film of gold. Here, the gold film 26 is a one micron gold film deposited onto the bottom surface of the silicon active device layer 12. This deposition can be done with standard sputtering or evaporation processes. Referring now to FIG. IE' , the transistors 18 formed in the active layer 20 are separated into individual devices, or die 30, here by mechanical sawing, an exemplary one of the transistors 18 being shown in FIG. IE. The die 30 are attached onto a base 32 of a package. Typically, gold silicon eutectic die attach techniques are used for good thermal conductivity. The sacrificial support layer 20 is removed, here using standard wet or dry etching techniques using oxygen, for example .
Alternatively, after formation of the thermally conductive layer 26 (FIG. ID'), the sacrificial support layer 20 is removed, here using standard wet or dry etching techniques using oxygen, for example. Once the sacrificial support 20 is removed the devices 18 are mechanically supported by the thermally conductive layer 26' , here a composite layer made up of the thin gold film 26, described above, and a thicker gold layer 26" (FIG. ID'') . Here, the one micro thick gold film 26' is deposited onto the bottom surface of the silicon device layer 12 as described above, to serve as a plating base for gold layer 26". The thickness of the gold film 26' can vary from 0.5 to 5.0 microns. The gold layer 26" is electroplated onto the bottom surface of the thin gold film 26' . The thickness of the gold layer 26" is here 75 micrometers or more and provide for mechanical support and heat conduction in the finished device.
Electroplating is used because it can be deposited with desired thickness in reasonable time and low stress, although other methods of deposition may be used. The transistors 18 are then diced into individual die 30 and bonded to packages 32, as shown in FIG. IE''. The sacrificial support layer 20 is removed, here using standard wet or dry etching techniques using oxygen, for example .
Other embodiments are within the spirit and scope of the appended claims. For example, while a transistor with single emitter and base contacts has been shown, multiple emitters and base contacts would be used for higher current capacity.
What is claimed is:

Claims

1. A method for forming a transistor, comprising: providing a wafer having a semiconductor active device layer in one surface of the wafer, a semiconductor support layer in a second surface of the wafer, and an etch stop layer therebetween; forming doped regions in the transistor device layer; forming a sacrificial support disposed on, and bonded to, the first surface of the wafer; selectively etching the semiconductor support layer and the etch stop layer while the sacrificial support provides structural integrity to the transistor device layer.
2. The method recited in claim 1 including selectively removing the sacrificial support.
3. The method recited in claim 1 wherein the selective etching of the semiconductor support layer and the etch stop layer exposes a surface of the active device layer and including forming a heat conductive layer on the exposed surface of the active device layer.
4. The method recited in claim 3 including selectively removing the sacrificial support after forming the heat conductive layer.
5. The method recited in claim 4 wherein a plurality of transistors is formed in the active device layer and including the step of separating the plurality of transistors into individual transistors subsequent to the forming of the heat conductive layer and removal of the sacrificial support.
6. A method for forming a transistor comprising: providing a semiconductor substrate with a transistor formed in an active device layer disposed on the substrate; removing the substrate to expose a surface of the active device layer; and forming a thermally conductive layer in contact with the exposed active device layer.
PCT/US1999/021958 1998-11-19 1999-09-21 Method for forming transistors on a thin semiconductor wafer WO2000031784A1 (en)

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US09/196,041 1998-11-19

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7541203B1 (en) 2008-05-13 2009-06-02 International Business Machines Corporation Conductive adhesive for thinned silicon wafers with through silicon vias

Citations (5)

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Publication number Priority date Publication date Assignee Title
EP0182218A2 (en) * 1984-11-07 1986-05-28 Kabushiki Kaisha Toshiba Method for dicing semiconductor wafer
US5071792A (en) * 1990-11-05 1991-12-10 Harris Corporation Process for forming extremely thin integrated circuit dice
WO1993011562A1 (en) * 1991-12-06 1993-06-10 Picogica S.A. Method of making semiconductor components with electrochemical recovery of the substrate
EP0573921A2 (en) * 1992-06-12 1993-12-15 Seiko Instruments Inc. Semiconductor device having a semiconductor film of low oxygen concentration
JPH076982A (en) * 1992-07-31 1995-01-10 Sharp Corp Method of splitting thin semiconductor substrate

Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
EP0182218A2 (en) * 1984-11-07 1986-05-28 Kabushiki Kaisha Toshiba Method for dicing semiconductor wafer
US5071792A (en) * 1990-11-05 1991-12-10 Harris Corporation Process for forming extremely thin integrated circuit dice
WO1993011562A1 (en) * 1991-12-06 1993-06-10 Picogica S.A. Method of making semiconductor components with electrochemical recovery of the substrate
EP0573921A2 (en) * 1992-06-12 1993-12-15 Seiko Instruments Inc. Semiconductor device having a semiconductor film of low oxygen concentration
JPH076982A (en) * 1992-07-31 1995-01-10 Sharp Corp Method of splitting thin semiconductor substrate

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Title
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 04 31 May 1995 (1995-05-31) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7541203B1 (en) 2008-05-13 2009-06-02 International Business Machines Corporation Conductive adhesive for thinned silicon wafers with through silicon vias

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