WO2000026955A1 - Fabrication of a transistor having an ultra-thin gate dielectric - Google Patents

Fabrication of a transistor having an ultra-thin gate dielectric Download PDF

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Publication number
WO2000026955A1
WO2000026955A1 PCT/US1999/014598 US9914598W WO0026955A1 WO 2000026955 A1 WO2000026955 A1 WO 2000026955A1 US 9914598 W US9914598 W US 9914598W WO 0026955 A1 WO0026955 A1 WO 0026955A1
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Prior art keywords
layer
dielectric layer
dielectric
gate
forming
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PCT/US1999/014598
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French (fr)
Inventor
Mark I. Gardner
H. Jim Fulford, Jr.
Jack C. Lee
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Advanced Micro Devices, Inc.
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Publication of WO2000026955A1 publication Critical patent/WO2000026955A1/en

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present invention relates generally to integrated circuit manufacture; and more particul-arly to the formation of transistors upon a semiconductive substrate having scaled dimensions.
  • MOS metal oxide semiconductor
  • a MOS transistor typically includes a substrate material onto which a gate insulator and a patterned gate conductor are formed.
  • the gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor.
  • the impurities placed into the substrate define a junction region, also known as source/drain regions.
  • the gate conductor is patterned from a layer of polysilicon using various lithography techniques.
  • a typical n-channel MOS transistor employs n-type junctions placed into a p-type substrate.
  • a typical p-channel MOS transistor comprises p-type junctions placed into an n-type substrate.
  • the substrate comprises an entire monolithic silicon wafer, in which, a portion of the substrate known as a well is formed.
  • the well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junction in the non-well areas. Accordingly, wells are often employed when both n-type and p-type transistors (i.e. Complementary MOS, are needed.
  • a pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible.
  • features such as the gate conductor, source/drain junctions, and interconnects to the junction must be made as small as possible.
  • Many modern day processes employ features, which have less than 0.15-micron critical dimensions.
  • feature size decreases, the resulting transistor as well as the interconnect between transistors also decreases.
  • Smaller transistors allow more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single and relatively small die area.
  • smaller tr ⁇ sistors typically have lower turn-on threshold voltages, faster switching speeds and consume less power in their operation.
  • Gate dielectrics are typically formed of silicon dioxide, which is grown on the surface of active regions of the substrate. When transistors are scaled, the gate dielectric thickness must be reduced accordingly. However, when the silicon dioxide gate dielectric is less than approximately 10 Angstroms thick, it fails to function properly. Thus, a limitation exists in the use of silicon dioxide, or other similar materials as gate dielectrics in scaled transistors. Thus, there exists a need in the art for an improved methodology of forming gate dielectrics that will better facilitate transistor scaling so that critical dimensions may be reduced to enhance performance of the formed transistors. Disclosure of the Invention
  • transistors formed according to the present invention that include a gate dielectric having a relatively high dielectric constant as compared to silicon dioxide. More specifically, the inventive method includes depositing a thin layer of tungsten upon the substrate and then converting the tungsten into tungsten trioxide to form the gate dielectric layer. To prevent diffusion of the tungsten into the silicon active regions of the substrate, another thin dielectric layer of a differing material is grown or deposited upon the substrate prior to the deposition of the tungsten.
  • the resultant gate dielectric is a sandwiched structure having a first dielectric layer that serves to prevent diffusion of metal into the silicon active regions and a second dielectric layer formed of tungsten trioxide.
  • the first dielectric may be formed of a nitride, or another suitable material, at a thickness of approximately 5 to 10 Angstroms.
  • a layer of tungsten is first deposited and is then converted to tungsten trioxide in a conversion process.
  • the second dielectric layer has a thickness of approximately 10 to 20 Angstroms.
  • the sandwiched gate dielectric has .an overall thickness of between 15 and 30 Angstroms, which is substantially thicker than a 10 Angstrom silicon dioxide gate dielectric.
  • the nitride dielectric layer has a dielectric constant of approximately 8 while silicon dioxide has a dielectric constant of approximately 4.
  • tungsten trioxide has a dielectric constant of approximately 500.
  • an integrated circuit manufactured according to the inventive methods may achieve levels of scaling that have, heretofore, been unachievable.
  • a gate conductor layer is deposed and patterned.
  • the gate conductor layer and the sandwiched gate dielectric are then etched back to form gate conductor/gate dielectric structures. Additional steps are then taken to complete formation of the transistors. Further, other steps, such as well formation and isolation region formation may be also be taken prior to formation of the sandwiched gate dielectric.
  • the formed transistors may then be interconnected to form an integrated circuit.
  • Figures 1 A through ID are partial cross-sectional views of a semiconductor substrate during the formation of transistors according to the present invention
  • Figures 2 A through 2D are additional partial cross- sectional views of the semiconductor substrate of Figures 1 A through ID during formation of transistors according to present invention
  • Figure 3 is a flow chart illustrating a first series of steps according to the present invention employed to form an integrated circuit including transistors with ultra-thin gate dielectrics having a high dielectric constant;
  • Figure 4 is a flow chart illustrating a second series of steps according to the present invention employed to form an integrated circuit including transistors with ultra-thin gate dielectrics having a high dielectric constant;
  • Figure 5 is a partial cross sectional diagram of a transistor that has been formed according to the present invention that illustrates the components of the transistor and how the transistor can be connected to other transistors to form an integrated circuit.
  • Figures 1A through ID are partial cross-sectional views of a semiconductor substrate during the formation of transistors according to the present invention.
  • a substrate 100 includes an active region 102 and a plurality of isolation regions 104.
  • Figure 1 A represents a substrate after a first step of integrated circuit fabrication process as described herein is performed.
  • the active region 102 is a semiconductive region in which an active device may be formed.
  • the isolation regions 104 are formed of an insulating material, which serves to isolate active devices or conductive components from other active devices or conductive components.
  • the isolation regions 104 are typically formed of silicon dioxide.
  • the isolation regions 104 may be formed using the well-known LOCOS growth process, trenching and filling steps or another isolation process. In general, the invention herein includes all forms of creating isolation regions.
  • substrate 100 includes a nitride layer 112 that has been formed upon active region 102 and isolation regions 104.
  • gate dielectrics are formed to define a channel within the active regions 102.
  • insulative layers are formed of an oxide as was discussed above.
  • a first thickness of the gate dielectric is formed of the nitride layer 112.
  • the nitride layer 112 is deposited or grown upon the substrate 100 using a known technique for depositing or growing such a layer upon a substrate.
  • the nitride is formed to a depth of 5 to 10 Angstroms.
  • Nitride is used in the embodiment because it has a dielectric constant of 8 and because it adequately serves to protect the substrate 100 surface during subsequent steps. Specifically, as will be discussed below, the nitride layer prevents metal migration during subsequent tungsten deposition and oxidation steps.
  • substrate 100 includes a tungsten layer 122 that has been formed upon nitride layer 112.
  • the tungsten layer 122 may be formed upon nitride layer 112 in a sputtering process or in a plasma deposition process.
  • the tungsten layer 122 is formed to have a thickness of between 10 and 20 Angstroms.
  • Titanium may be employed in lieu of Tungsten.
  • the tungsten layer 122 has been transformed into a tungsten trioxide layer 124.
  • the tungsten trioxide layer 124 has a dielectric constant of 500.
  • the combination of the nitride layer 112 and the tungsten trioxide layer 124 creates a relatively thin sandwiched dielectric layer that has superior operating characteristics.
  • the dielectric constants of the materials employed, nitride having a dielectric constant of 8 and tungsten trioxide having a dielectric constant of 500 are superior to other materials otherwise used in forming the gate dielectric, e.g., silicon dioxide.
  • Figures 2A through 2D are partial cross sectional views of a semiconductor substrate during formation of transistors according to present invention subsequent to the structure of Figure ID.
  • a polysilicon layer 202 is deposited upon the tungsten trioxide layer 124 as a gate conductor layer.
  • Figure 2 A also illustrates a portion of a photoresist mask 204 that has been patterned to define a desired location of a gate conductor/gate dielectric stack above the active region 102.
  • the patterned photoresist mask 204 is initially formed as a uniform photoresist layer over all portions of the polysilicon layer 202. Then, the photoresist layer is selectively exposed in a lithography step. After the selective exposure, exposed portions of the photoresist are removed so that the patterned photoresist mask 204 remains.
  • the structure is anisotropically etched to remove unprotected portions of the polysilicon layer 202, the tungsten trioxide layer 124 and the nitride layer 112 to expose those portions of the active regions 102 and isolation regions 104 unprotected by the patterned photoresist mask
  • Anisotropic etching steps are generally known to form vertical sidewalls. Thus, using anisotropic etching, uniform gate conduct conductor/gate dielectric structures are formed.
  • gate conductor/gate insulator structures are formed that include gate conductors 222 and gate insulators that include a nitride layer portion 212 and a tungsten trioxide portion 224. It may be seen that the only portions remaining above the isolation regions 104 and the active regions 102 of substrate 100 are those portions of layers 112, 124, and 202 that were protected by the patterned photo resist mask 204. Subsequent to the etch step, remaining portions of the patterned photo resist 204 are removed in an ashing step or another known step.
  • Thin spacers 240 are for isolating the gate conductors 222 and for preventing the introduction therein of impurities during subsequent doping and salicadation steps. These structures are added using steps known in the art, such as the well-known TEOS method, and will not be discussed herein in detail.
  • Figure 2D illustrates the substrate after LDD implants 244 and final spacers 250 have been formed and after the source 252 and drain regions 254 have been formed. These steps are performed using known techniques, which may also employ the TEOS method. Salicadation may be subsequently performed to enhance conductivity of the source 252 and drain 254 regions and the gate conductor 222. As is shown, formation of the source 252 and drain 254 regions defines a channel 260 there between.
  • Figure 3 is a flow chart illustrating a first series of steps according to the present invention employed to form an integrated circuit including transistors with ultra-thin gate dielectrics having a high dielectric constant.
  • the inventive method includes the initial steps of forming isolation regions 104 within the semiconductor substrate 100 (step 302). Any technique for forming isolation regions may be used such as locally growing oxides (LOCOS) and trenching/filling or depositing and etching the isolation regions upon the surface of the semiconductive substrate 100, among other processes.
  • LOC locally growing oxides
  • the active regions in or on the substrate are formed, if necessary (step 304). Whether the active regions 104 must be created at step 304 depends in large part upon how the isolation regions 104 are formed. For example, if the isolation regions 104 were deposited, the active regions 104 may be epitaxially grown or deposited to fill the voids created by the formation of the isolation regions 104.
  • a nitride layer 1 12 is deposited on the active regions 102 and isolation regions 104 (step 306).
  • the nitride may be deposited in a standard nitride deposition step, e.g., Chemical Vapor Deposition (CVD) of xylene or ammonia gas at 600 degrees Celsius to 800 degrees Celsius.
  • CVD Chemical Vapor Deposition
  • the nitride layer may be added in a sputtering process or in a plasma deposition process at 50 degrees Celsius to 350 degrees Celsius.
  • the nitride layer is formed to a depth of 5 to 10 Angstroms in the embodiment.
  • One particular reason for adding the nitride layer is to prevent metal migration into the surface of active regions 102 and isolation regions 104 in a subsequent tungsten deposition step.
  • a thin layer 122 of tungsten is deposited on top of the nitride layer 1 12 (step 308).
  • tungsten layer 122 may be deposited in sputtering steps or in a plasma deposition step.
  • plasma is generated remotely and generated plasma particles (tungsten) are subjected to acceleration by an acceleration grid and applied to the nitride layer 1 12.
  • the tungsten layer 122 has a thickness of 10 Angstroms to 20 Angstroms.
  • the tungsten layer 122 is subjected to an oxidation process to transform the tungsten layer 122 into a tungsten trioxide layer 124 (step 310).
  • the tungsten layer 122 is transformed into a tungsten trioxide layer 124 by subjecting the tungsten layer 122 to an oxygen bearing ambient.
  • Such transformation typically is performed in an oxygen furnace at 650 to 900 degrees Celsius for a time period of 10 seconds to 90 seconds in a
  • tungsten trioxide layer 124 therefore behaves similarly to a much thinner nitride or silicon dioxide layer. Due to this behavior, a relatively thicker tungsten trioxide layer 124 and nitride layer 1 12 stack may be employed to form a relatively smaller, scaled transistor. In other words, a gate dielectric formed of the tungsten trioxide layer 124 and the nitride layer 112 has superior performance, as compared to a thinner silicon dioxide gate dielectric.
  • a layer of polysilicon 202 or another material that is conductive or that may subsequently be rendered conductive is deposited above the tungsten trioxide layer 124 (step 312).
  • a standard deposition step may be used to depose the polysilicon layer 202 or another conductive material of choice.
  • the surface of the substrate is then patterned with a patterned photoresist mask 204 of Figure 2 (step 314).
  • Figure 4 is a flow chart illustrating a second series of steps according to the present invention employed to form an integrated circuit including transistors with ultra-thin gate dielectrics having a high dielectric constant.
  • the exposed portions of the polysilicon layer 202, the tungsten trioxide layer 124 and the nitride layer 112 are then removed in an etching process to form gate conductors 222 and gate dielectric stacks that include nitride portions 212 and tungsten trioxide portions 224 (step 402) as illustrated in Figure 2B.
  • the patterned photoresist mask 204 is then removed in an ashing or wet process. While the step of removing the patterned photoresist mask 204 is not explicitly described herein, such a step is common and is known in the art.
  • step 404 thin spacers 240 are formed (step 404).
  • FIG. 2C illustrates the substrate 100 after thin spacers 240 have been formed in step 404 and after extension implants 242 are formed (step 406). These extension implants, also known as LDD regions 242, serve to provide a lesser-doped region between the source 252 and the channel and the drain
  • final spacers 250 and additional LDD regions 244 are formed (step 408).
  • additional isolation between the source 252 and channel and drain 254 and channel may be established.
  • the LDD regions 244 regions, as compared to LDD regions 242, are deeper and longer, the shape of such corresponding to the dimensions of the final spacer 250.
  • wells may be formed (step 410) if they have not previously been formed, punch through regions are formed (step 412) and source 252 and drain 254 drain regions are doped (step 414). Finally, the various devices of the semiconductor substrate are coupled to form the integrated circuit (step 416). Wells may be formed earlier in the manufacturing process, such as immediately after formation of the isolation regions 104 (step 302) and active regions
  • FIG. 5 is a partial cross sectional diagram of a transistor that has been formed according to the present invention that illustrates the components of the transistor and interconnections of the transistor to other transistors and other active structures made to form an integrated circuit. Referring now to Figure 5, a well 502 has been formed (step 304).
  • FIG. 4 illustrates the LDD implants 244 that were formed as described in step 408 of Figure 4 as well as the source 252 and the drain 254 of the transistor after being formed as discussed in relation to step 414 of Figure
  • FIG. 5 also illustrates an insulation layer 508 which is formed to isolate active devices from a metallization layer 524 that is used to interconnect active devices. While only a single active device is shown, literally millions of active devices are typically formed in an integrated circuit, some or all of the active devices formed according to the present invention. As is known in the art, the insulation layer 508 may be formed in a plurality of different ways. In one embodiment of the invention, the insulation layer 508 is formed in a CVD process to thickness that is required to isolate the metallization layer 524 from the active devices of the integrated circuit. Typically, the insulation layer 508 is polished in a CMP process to form a planar upper surface. It is then masked and etched to form openings to the active regions (e.g., source 252, gate conductor 222 and drain 254) of the device.
  • the active regions e.g., source 252, gate conductor 222 and drain 254
  • a sputtering or evaporation process is used to fill the vias with a metal.
  • the resulting metallized vias 510, 512 and 514 result.
  • Metals that can be used in this process include Ti, TiN, W and Al.
  • the metallization layer 524 may also be deposited.
  • metallization layer 524 is added, it is masked to form a conductor pattern .and the surface is etched back to the insulation layer 508 to form the conductors 516, 518 and 520.
  • An insulator layer 522 may be formed to isolate conductive paths 516, 518 and 520 formed in the metallization layer 524, particularly if a subsequent metallization layer is formed upon the metallization layer 524. Subsequent metallization layers (not shown) can provide further interconnections among the devices and external to the formed integrated circuit.

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Abstract

A transistor of an integrated circuit includes a high K gate dielectric (224) that was converted from a metal. A first dielectric layer (112) consisting of a nitride is blanket deposited across active (102) and isolation (104) regions of a substrate (100). A metal layer (122) is then blanket deposited upon the first dielectic layer (112). The metal layer (122) is then transformed into a second dielectric layer (124). In a described embodiment, the metal layer (122) is formed of tungsten and the second dielectric layer (124) is formed of tungsten trioxide. The tungsten trioxide serves as a thin dielectric having a dielectric constant in the range of K=500. A gate conductor layer (202) is then deposed and the gate conductor layer (202), the first dielectric layer (112) and the second dielectric layer (124) are then patterned and etched to produce gate conductor/gate dielectric structures.

Description

Title: FABRICATION OF A TRANSISTOR HAVING AN ULTRA-THIN GATE DIELECTRIC
Technical Field
The present invention relates generally to integrated circuit manufacture; and more particul-arly to the formation of transistors upon a semiconductive substrate having scaled dimensions. Background Art
The structure and the vmous components, or features, of a metal oxide semiconductor (MOS) device are generally well known. A MOS transistor typically includes a substrate material onto which a gate insulator and a patterned gate conductor are formed. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source/drain regions. The gate conductor is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS transistor employs n-type junctions placed into a p-type substrate. Conversely, a typical p-channel MOS transistor comprises p-type junctions placed into an n-type substrate. The substrate comprises an entire monolithic silicon wafer, in which, a portion of the substrate known as a well is formed. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junction in the non-well areas. Accordingly, wells are often employed when both n-type and p-type transistors (i.e. Complementary MOS, are needed.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high-density integrated circuit, features such as the gate conductor, source/drain junctions, and interconnects to the junction must be made as small as possible. Many modern day processes employ features, which have less than 0.15-micron critical dimensions. As feature size decreases, the resulting transistor as well as the interconnect between transistors also decreases. Smaller transistors allow more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single and relatively small die area. Further, smaller trωsistors typically have lower turn-on threshold voltages, faster switching speeds and consume less power in their operation. These features in combination allow for higher speed integrated circuits to be constructed that have greater processing capabilities.
The benefits of high-density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the higher resolutions needed for submicron features. To some extent, wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, suicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
Many other techniques are often used to achieve a higher density circuit. However, these techniques must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot, in all instances, offset the problems associated with the use of small features or features arranged extremely close to one another. For example, as the ch. nnel length decreases, short channel effects (ASCE@) generally occur. SCE -cause threshold voltage skews at the channel edges as well as excessive sub-threshold currents (e.g., punch through and drain- induced barrier lowering). Related to SCE is the problem of hot C rrier injection (AHCI@). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric fields give rise to so called hot carriers and the injection of these carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since these carriers can become trapped and skew the turn-on threshold voltage of the ensuing transistor. A particular problem relating to the scaling of transistors is found in the formation of transistor gate dielectrics.
Gate dielectrics are typically formed of silicon dioxide, which is grown on the surface of active regions of the substrate. When transistors are scaled, the gate dielectric thickness must be reduced accordingly. However, when the silicon dioxide gate dielectric is less than approximately 10 Angstroms thick, it fails to function properly. Thus, a limitation exists in the use of silicon dioxide, or other similar materials as gate dielectrics in scaled transistors. Thus, there exists a need in the art for an improved methodology of forming gate dielectrics that will better facilitate transistor scaling so that critical dimensions may be reduced to enhance performance of the formed transistors. Disclosure of the Invention
The problems outlined above are in large part solved by transistors formed according to the present invention that include a gate dielectric having a relatively high dielectric constant as compared to silicon dioxide. More specifically, the inventive method includes depositing a thin layer of tungsten upon the substrate and then converting the tungsten into tungsten trioxide to form the gate dielectric layer. To prevent diffusion of the tungsten into the silicon active regions of the substrate, another thin dielectric layer of a differing material is grown or deposited upon the substrate prior to the deposition of the tungsten.
The resultant gate dielectric is a sandwiched structure having a first dielectric layer that serves to prevent diffusion of metal into the silicon active regions and a second dielectric layer formed of tungsten trioxide. The first dielectric may be formed of a nitride, or another suitable material, at a thickness of approximately 5 to 10 Angstroms.
In forming the second dielectric layer, a layer of tungsten is first deposited and is then converted to tungsten trioxide in a conversion process. The second dielectric layer has a thickness of approximately 10 to 20 Angstroms.
Thus, the sandwiched gate dielectric has .an overall thickness of between 15 and 30 Angstroms, which is substantially thicker than a 10 Angstrom silicon dioxide gate dielectric. However, the nitride dielectric layer has a dielectric constant of approximately 8 while silicon dioxide has a dielectric constant of approximately 4. Moreover, tungsten trioxide has a dielectric constant of approximately 500. Thus, as compared to a silicon dioxide gate dielectric having a thickness of 10 Angstroms, for example, even a 30 Angstrom sandwiched gate dielectric constructed according to the present invention has superior operating characteristics due to the superior dielectric properties. Thus, an integrated circuit manufactured according to the inventive methods may achieve levels of scaling that have, heretofore, been unachievable.
Once the sandwiched gate dielectric has been formed, a gate conductor layer is deposed and patterned. The gate conductor layer and the sandwiched gate dielectric are then etched back to form gate conductor/gate dielectric structures. Additional steps are then taken to complete formation of the transistors. Further, other steps, such as well formation and isolation region formation may be also be taken prior to formation of the sandwiched gate dielectric. The formed transistors may then be interconnected to form an integrated circuit.
Moreover, other aspects of the present invention will become apparent with further reference to the drawings and specification which follow. Brief Description of Drawings
A better understanding of the present invention can be obtained when the following detailed description is considered in conjunction with the following drawings, in which: Figures 1 A through ID are partial cross-sectional views of a semiconductor substrate during the formation of transistors according to the present invention;
Figures 2 A through 2D are additional partial cross- sectional views of the semiconductor substrate of Figures 1 A through ID during formation of transistors according to present invention;
Figure 3 is a flow chart illustrating a first series of steps according to the present invention employed to form an integrated circuit including transistors with ultra-thin gate dielectrics having a high dielectric constant;
Figure 4 is a flow chart illustrating a second series of steps according to the present invention employed to form an integrated circuit including transistors with ultra-thin gate dielectrics having a high dielectric constant; and
Figure 5 is a partial cross sectional diagram of a transistor that has been formed according to the present invention that illustrates the components of the transistor and how the transistor can be connected to other transistors to form an integrated circuit.
Modes for Carrying out the Invention
Figures 1A through ID are partial cross-sectional views of a semiconductor substrate during the formation of transistors according to the present invention. Referring now to Figure 1 A, a substrate 100 includes an active region 102 and a plurality of isolation regions 104. In general, Figure 1 A represents a substrate after a first step of integrated circuit fabrication process as described herein is performed. The active region 102 is a semiconductive region in which an active device may be formed. The isolation regions 104 are formed of an insulating material, which serves to isolate active devices or conductive components from other active devices or conductive components. For silicon based semiconductor circuits, the isolation regions 104 are typically formed of silicon dioxide. The isolation regions 104 may be formed using the well-known LOCOS growth process, trenching and filling steps or another isolation process. In general, the invention herein includes all forms of creating isolation regions.
At this point in the fabrication, wells and VT regions may also be formed. However, as will become evident of one skilled in the art, the wells and VT regions may also be formed later in the process. Such processes are known in the art and are not described further herein. Referring now to figure IB, it may be seen that substrate 100 includes a nitride layer 112 that has been formed upon active region 102 and isolation regions 104. As is known, in the formation of MOS devices, gate dielectrics are formed to define a channel within the active regions 102. Typically, such insulative layers are formed of an oxide as was discussed above. However, in the described embodiment, a first thickness of the gate dielectric is formed of the nitride layer 112. The nitride layer 112 is deposited or grown upon the substrate 100 using a known technique for depositing or growing such a layer upon a substrate.
In the described embodiment, the nitride is formed to a depth of 5 to 10 Angstroms. Nitride is used in the embodiment because it has a dielectric constant of 8 and because it adequately serves to protect the substrate 100 surface during subsequent steps. Specifically, as will be discussed below, the nitride layer prevents metal migration during subsequent tungsten deposition and oxidation steps.
Referring now to Figure IC, it may be seen that substrate 100 includes a tungsten layer 122 that has been formed upon nitride layer 112. The tungsten layer 122 may be formed upon nitride layer 112 in a sputtering process or in a plasma deposition process. In the described embodiment, the tungsten layer 122 is formed to have a thickness of between 10 and 20 Angstroms. In another embodiment of the present invention, Titanium may be employed in lieu of Tungsten.
Referring now to Figure ID, it may be seen that the tungsten layer 122 has been transformed into a tungsten trioxide layer 124. With the transformation, the tungsten trioxide layer 124 has a dielectric constant of 500. Thus, the combination of the nitride layer 112 and the tungsten trioxide layer 124 creates a relatively thin sandwiched dielectric layer that has superior operating characteristics. Such is the case because the dielectric constants of the materials employed, nitride having a dielectric constant of 8 and tungsten trioxide having a dielectric constant of 500 are superior to other materials otherwise used in forming the gate dielectric, e.g., silicon dioxide.
Figures 2A through 2D are partial cross sectional views of a semiconductor substrate during formation of transistors according to present invention subsequent to the structure of Figure ID. Referring now to Figure 2 A, a polysilicon layer 202 is deposited upon the tungsten trioxide layer 124 as a gate conductor layer. Figure 2 A also illustrates a portion of a photoresist mask 204 that has been patterned to define a desired location of a gate conductor/gate dielectric stack above the active region 102. The patterned photoresist mask 204 is initially formed as a uniform photoresist layer over all portions of the polysilicon layer 202. Then, the photoresist layer is selectively exposed in a lithography step. After the selective exposure, exposed portions of the photoresist are removed so that the patterned photoresist mask 204 remains.
Subsequent to the creation of the patterned photoresist mask 204, the structure is anisotropically etched to remove unprotected portions of the polysilicon layer 202, the tungsten trioxide layer 124 and the nitride layer 112 to expose those portions of the active regions 102 and isolation regions 104 unprotected by the patterned photoresist mask
204. Anisotropic etching steps are generally known to form vertical sidewalls. Thus, using anisotropic etching, uniform gate conduct conductor/gate dielectric structures are formed.
Referring now to Figure 2B, it may be seen that the etch step has been completed, thus removing unprotected portions of the polysilicon layer 202, the tungsten trioxide layer 124 and the nitride layer 112. Resultantly, gate conductor/gate insulator structures are formed that include gate conductors 222 and gate insulators that include a nitride layer portion 212 and a tungsten trioxide portion 224. It may be seen that the only portions remaining above the isolation regions 104 and the active regions 102 of substrate 100 are those portions of layers 112, 124, and 202 that were protected by the patterned photo resist mask 204. Subsequent to the etch step, remaining portions of the patterned photo resist 204 are removed in an ashing step or another known step.
Referring now to Figure 2C, it may be seen that the subsequent steps have been performed to form thin spacers 240 and extension implants 242. Thin spacers 240 are for isolating the gate conductors 222 and for preventing the introduction therein of impurities during subsequent doping and salicadation steps. These structures are added using steps known in the art, such as the well-known TEOS method, and will not be discussed herein in detail.
Figure 2D illustrates the substrate after LDD implants 244 and final spacers 250 have been formed and after the source 252 and drain regions 254 have been formed. These steps are performed using known techniques, which may also employ the TEOS method. Salicadation may be subsequently performed to enhance conductivity of the source 252 and drain 254 regions and the gate conductor 222. As is shown, formation of the source 252 and drain 254 regions defines a channel 260 there between.
Figure 3 is a flow chart illustrating a first series of steps according to the present invention employed to form an integrated circuit including transistors with ultra-thin gate dielectrics having a high dielectric constant. Referring now to Figure 3, the inventive method includes the initial steps of forming isolation regions 104 within the semiconductor substrate 100 (step 302). Any technique for forming isolation regions may be used such as locally growing oxides (LOCOS) and trenching/filling or depositing and etching the isolation regions upon the surface of the semiconductive substrate 100, among other processes. Once the isolation regions 104 have been created, the active regions in or on the substrate are formed, if necessary (step 304). Whether the active regions 104 must be created at step 304 depends in large part upon how the isolation regions 104 are formed. For example, if the isolation regions 104 were deposited, the active regions 104 may be epitaxially grown or deposited to fill the voids created by the formation of the isolation regions 104.
After step 302 and optional step 304 are complete, a nitride layer 1 12 is deposited on the active regions 102 and isolation regions 104 (step 306). The nitride may be deposited in a standard nitride deposition step, e.g., Chemical Vapor Deposition (CVD) of xylene or ammonia gas at 600 degrees Celsius to 800 degrees Celsius. Alternatively, the nitride layer may be added in a sputtering process or in a plasma deposition process at 50 degrees Celsius to 350 degrees Celsius. Regardless of the method utilized for adding the nitride layer 112, the nitride layer is formed to a depth of 5 to 10 Angstroms in the embodiment. One particular reason for adding the nitride layer is to prevent metal migration into the surface of active regions 102 and isolation regions 104 in a subsequent tungsten deposition step.
Next, a thin layer 122 of tungsten is deposited on top of the nitride layer 1 12 (step 308). The tungsten layer
122 may be deposited in sputtering steps or in a plasma deposition step. In a plasma deposition step, plasma is generated remotely and generated plasma particles (tungsten) are subjected to acceleration by an acceleration grid and applied to the nitride layer 1 12. After deposition, the tungsten layer 122 has a thickness of 10 Angstroms to 20 Angstroms. After the tungsten layer 122 has been deposited, it is subjected to an oxidation process to transform the tungsten layer 122 into a tungsten trioxide layer 124 (step 310). The tungsten layer 122 is transformed into a tungsten trioxide layer 124 by subjecting the tungsten layer 122 to an oxygen bearing ambient. Such transformation typically is performed in an oxygen furnace at 650 to 900 degrees Celsius for a time period of 10 seconds to 90 seconds in a
Rapid Thermal Annealing (RTA) process. After the transformation, the tungsten trioxide layer 124 has a dielectric constant of approximately K=500. As compared to nitride layers and silicon dioxide layers which having dielectric constants of K=8 and K=4, respectively, the tungsten trioxide layer 124 formed in step 310 has superior dielectric strength of K=500 (approximate) even though it only has a thickness of 10 to 20 Angstroms. The tungsten trioxide layer
124 therefore behaves similarly to a much thinner nitride or silicon dioxide layer. Due to this behavior, a relatively thicker tungsten trioxide layer 124 and nitride layer 1 12 stack may be employed to form a relatively smaller, scaled transistor. In other words, a gate dielectric formed of the tungsten trioxide layer 124 and the nitride layer 112 has superior performance, as compared to a thinner silicon dioxide gate dielectric.
After the tungsten layer 122 has been transformed into tungsten trioxide 124, a layer of polysilicon 202 or another material that is conductive or that may subsequently be rendered conductive is deposited above the tungsten trioxide layer 124 (step 312). A standard deposition step may be used to depose the polysilicon layer 202 or another conductive material of choice. The surface of the substrate is then patterned with a patterned photoresist mask 204 of Figure 2 (step 314).
Figure 4 is a flow chart illustrating a second series of steps according to the present invention employed to form an integrated circuit including transistors with ultra-thin gate dielectrics having a high dielectric constant. Referring now to Figure 4, and continuing the method described in Figure 3, the exposed portions of the polysilicon layer 202, the tungsten trioxide layer 124 and the nitride layer 112 are then removed in an etching process to form gate conductors 222 and gate dielectric stacks that include nitride portions 212 and tungsten trioxide portions 224 (step 402) as illustrated in Figure 2B. The patterned photoresist mask 204 is then removed in an ashing or wet process. While the step of removing the patterned photoresist mask 204 is not explicitly described herein, such a step is common and is known in the art.
After the gate conductors/gate insulators have been formed in step 402, thin spacers 240 are formed (step 404).
The thin spacers 240 will prevent the formation of conductive paths along the surface of the gate conductors/gate insulators during subsequent fabrication process steps. Figure 2C illustrates the substrate 100 after thin spacers 240 have been formed in step 404 and after extension implants 242 are formed (step 406). These extension implants, also known as LDD regions 242, serve to provide a lesser-doped region between the source 252 and the channel and the drain
254 and the channel.
Next, final spacers 250 and additional LDD regions 244 are formed (step 408). By forming the spacers in two separate steps, additional isolation between the source 252 and channel and drain 254 and channel may be established. The LDD regions 244 regions, as compared to LDD regions 242, are deeper and longer, the shape of such corresponding to the dimensions of the final spacer 250.
Then, wells may be formed (step 410) if they have not previously been formed, punch through regions are formed (step 412) and source 252 and drain 254 drain regions are doped (step 414). Finally, the various devices of the semiconductor substrate are coupled to form the integrated circuit (step 416). Wells may be formed earlier in the manufacturing process, such as immediately after formation of the isolation regions 104 (step 302) and active regions
102 (step 304). The final spacers 250 also protect the gate conductor/gate insulator stack during subsequent process steps and prevent surface current migration. The punch through regions work to minimize short channel effects and subthreshold currents at or near the substrate surface. Figure 2D illustrates the structure after the final spacers 250 have been formed and source and drain regions 252 have been doped. Figure 5 is a partial cross sectional diagram of a transistor that has been formed according to the present invention that illustrates the components of the transistor and interconnections of the transistor to other transistors and other active structures made to form an integrated circuit. Referring now to Figure 5, a well 502 has been formed (step
410) and a punch through region 504 has been formed (step 412). Further the transistor has been interconnected with other active devices to form an integrated circuit (step 416). Figure 5 also illustrates the LDD implants 244 that were formed as described in step 408 of Figure 4 as well as the source 252 and the drain 254 of the transistor after being formed as discussed in relation to step 414 of Figure
4. A channel region 506 formed between the source 252 and drain 254 may also be seen in Figure 5. Figure 5 also illustrates an insulation layer 508 which is formed to isolate active devices from a metallization layer 524 that is used to interconnect active devices. While only a single active device is shown, literally millions of active devices are typically formed in an integrated circuit, some or all of the active devices formed according to the present invention. As is known in the art, the insulation layer 508 may be formed in a plurality of different ways. In one embodiment of the invention, the insulation layer 508 is formed in a CVD process to thickness that is required to isolate the metallization layer 524 from the active devices of the integrated circuit. Typically, the insulation layer 508 is polished in a CMP process to form a planar upper surface. It is then masked and etched to form openings to the active regions (e.g., source 252, gate conductor 222 and drain 254) of the device.
Once the openings are formed, a sputtering or evaporation process, by way of example, is used to fill the vias with a metal. The resulting metallized vias 510, 512 and 514 result. Metals that can be used in this process include Ti, TiN, W and Al. Alternatively, the metallization layer 524 may also be deposited.
Once metallization layer 524 is added, it is masked to form a conductor pattern .and the surface is etched back to the insulation layer 508 to form the conductors 516, 518 and 520. An insulator layer 522 may be formed to isolate conductive paths 516, 518 and 520 formed in the metallization layer 524, particularly if a subsequent metallization layer is formed upon the metallization layer 524. Subsequent metallization layers (not shown) can provide further interconnections among the devices and external to the formed integrated circuit. Industrial Applicability
The teachings of the present invention may be employed in the manufacture of any various type of integrated circuit. For example, the teachings described herein may be employed in the construction of processors, memory, peripheral parts, and many other types of integrated circuits. While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and detailed description. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives falling within the scope of the present invention as defined by the claims.

Claims

Claims:
1. A method for forming a transistor in a semiconductive substrate, characterized by: forming isolation regions and an active region upon the semiconductive substrate (302, 304); forming a first dielectric layer upon the isolation regions and the active region (306); forming a metal layer upon the first dielectric layer (308); transforming the metal layer into a second dielectric layer (310); forming a gate conductor layer upon the second dielectric layer (312); and selectively removing portions of the gate conductor layer, the first dielectric layer and the second dielectric layer to form a gate conductor and a gate dielectric upon the active region, the gate dielectric including remaining portions of the first dielectric layer and the second dielectric layer (314, 402).
2. The method of claim 1 , wherein the metal layer comprises tungsten having a thickness of between 10 and 20 Angstroms.
3. The method of claim 2, wherein: the second dielectric layer comprises tungsten trioxide; and the first dielectric layer comprises a nitride.
4. The method of claim 1, further characterized by: forming spacers about the gate conductor and gate dielectric (404); forming a source and a drain (414); and forming lightly doped drain regions (408).
5. A method for forming an integrated circuit in a semiconductive substrate, characterized by: forming isolation regions and active regions upon a substrate (302, 304); forming a first dielectric layer upon the isolation regions and the active regions (306); forming a metal layer upon the first dielectric layer (308); transforming the metal layer into a second dielectric layer (310); forming a gate conductor layer upon the second dielectric layer (312); and selectively removing portions of the gate conductor layer, the first dielectric layer and the second dielectric layer to form a plurality of gate conductors and gate dielectrics upon the active regions, the gate dielectrics including remaining portions of the first dielectric layer and the second dielectric layer (314, 402).
6. The method of claim 5, wherein the metal layer comprises tungsten having a thickness of between 10 and 20 Angstroms.
7. The method of claim 6, wherein: the second dielectric layer comprises tungsten trioxide; and the first dielectric layer comprises a nitride.
8. A transistor formed on an active region of a substrate, the transistor comprising: a source (252); a drain (254); a channel (260); a gate dielectric comprising a first dielectric layer (212) residing upon the channel (260) and a second dielectric layer (224) residing upon the first dielectric layer (212), the second dielectric layer (224) comprising a portion of a metal layer (122) that has been transformed into an insulating metal oxide (124); and a gate conductor (222) residing upon the second dielectric layer (224).
9. The transistor of claim 8, wherein the metal layer (222) comprises tungsten having a thickness of between 10 and 20 Angstroms.
10. The transistor of claim 9, wherein the second dielectric layer (224) comprises tungsten trioxide.
PCT/US1999/014598 1998-10-30 1999-06-28 Fabrication of a transistor having an ultra-thin gate dielectric WO2000026955A1 (en)

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Citations (4)

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Publication number Priority date Publication date Assignee Title
US3731163A (en) * 1972-03-22 1973-05-01 United Aircraft Corp Low voltage charge storage memory element
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US5440174A (en) * 1992-10-20 1995-08-08 Matsushita Electric Industrial Co., Ltd. Plurality of passive elements in a semiconductor integrated circuit and semiconductor integrated circuit in which passive elements are arranged
EP0784347A2 (en) * 1992-06-18 1997-07-16 Matsushita Electronics Corporation Semiconductor device having capacitor

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Publication number Priority date Publication date Assignee Title
US3731163A (en) * 1972-03-22 1973-05-01 United Aircraft Corp Low voltage charge storage memory element
EP0784347A2 (en) * 1992-06-18 1997-07-16 Matsushita Electronics Corporation Semiconductor device having capacitor
US5440174A (en) * 1992-10-20 1995-08-08 Matsushita Electric Industrial Co., Ltd. Plurality of passive elements in a semiconductor integrated circuit and semiconductor integrated circuit in which passive elements are arranged
JPH07135202A (en) * 1993-11-09 1995-05-23 Miyagi Oki Denki Kk Manufacture of semiconductor device

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