WO2000014747A1 - Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices - Google Patents
Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices Download PDFInfo
- Publication number
- WO2000014747A1 WO2000014747A1 PCT/US1998/018548 US9818548W WO0014747A1 WO 2000014747 A1 WO2000014747 A1 WO 2000014747A1 US 9818548 W US9818548 W US 9818548W WO 0014747 A1 WO0014747 A1 WO 0014747A1
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- WIPO (PCT)
- Prior art keywords
- voltage
- source
- coupled
- circuit
- negative voltage
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
Definitions
- the present invention relates to floating gate memory devices, and more particularly to circuits for generating a negative voltage to be applied to a control gate and a positive voltage to be applied to a source, a drain or a channel, in such a way that a constant electric field is maintained across the memory cell for inducing Fowler-Nordheim tunneling.
- Flash memory devices are based on arrays of floating gate memory cells which are programmed in some cases by biasing the memory cells to induce hot electron injection into the floating gate increase the threshold of the memory cell. Also, in many examples the cells are erased by biasing the cells to induce Fowler- Nordheim tunneling of electrons out of the floating gate in order to establish a low threshold state.
- One common approach inducing Fowler-Nordheim tunneling for the erase operation is referred to as source side erase. According to this approach, a negative voltage is applied to the wordline of cells in the array to be erased, while a positive voltage or ground, is applied to the source. This biasing establishes an electric field between the floating gate and the source to induce Fowler-Nordheim tunneling.
- integrated circuits include a negative voltage charge pump or other source of negative voltage on the integrated circuit.
- the voltage on the source side is as high as possible to reduce the magnitude of the negative voltage needed on the gate to establish sufficient electric field for tunneling. Also, it is known that a higher source voltage will induce higher band-to-band current on the source side and improve the efficiency of the tunneling.
- a circuit for applying a negative voltage to the control gate of a floating gate memory cell and a positive voltage to a complementary node comprising the source, the drain or the channel, which comprises a positive voltage source that is responsive to a supply voltage to provide a positive voltage to the source (in a preferred embodiment) of the cell and a negative voltage source responsive to the supply voltage providing a negative voltage to the control gate.
- a voltage regulator is included that is coupled to the negative voltage source and to the positive voltage source to maintain the negative voltage at a level responsive to the positive voltage.
- the positive voltage and the negative voltage establish an electric field between the floating gate and the source (or other complementary node) of the memory cell to be erased.
- the regulator maintains the negative voltage in response to the positive voltage so that the electric field remains essentially constant over a range of values of the positive voltage, or alternatively maintains an essentially constant erase speed.
- the electric field established between the floating gate and the source (or other complementary node) can be modeled by a physical relationship.
- the regulator according to one aspect of the invention, comprises a circuit that has a transfer function modeling the physical relationship to compensate for variations in the electric field over a range of values of voltage.
- the regulator comprises an amplifier that has a first input coupled to the positive voltage, a second input coupled to a reference potential, and an output coupled to the negative voltage source. Feedback is connected between the output of the negative voltage source and the second input to induce the output of the negative voltage source to track changes in the source voltage.
- the regulator comprises a level shift circuit coupled to the negative voltage generator, including for example a zener diode.
- a voltage divider is coupled between the level shift circuit and a reference potential and supplies a feedback voltage indicating variations in the negative voltage supplied by the negative voltage generator.
- a n-channel MOS transistor has a drain coupled to the supply voltage, a gate coupled to the positive voltage, and a source.
- a p-channel MOS transistor has a source coupled to the source of the n-channel MOS transistor, a gate coupled to the feedback voltage from the voltage divider, and a drain coupled to the negative voltage generator, through for example a level shifting circuit.
- a clamp circuit is coupled to the source of the n-channel MOS transistor to prevent the source of the n- channel MOS transistor from dropping below a clamp level.
- the present invention can also be characterized as an integrated circuit memory comprising an array of floating gate memory cells, and circuits for reading, programming and erasing the memory cells in the array.
- the circuit for erasing the memory cells in the array includes resources to apply a negative voltage to wordlines in the array and a positive voltage across the conductive paths to sources (or other complementary nodes) of memory cells in the array, and to maintain an essentially constant electric field across the floating gates and sources of memory cells in the array over a range of source voltages.
- the constant electric field according to a preferred aspect of the invention is maintained utilizing the voltage regulating technique discussed above.
- the present invention thus provides a method for erasing floating gate memory cell based on applying a positive voltage to the source (or other complementary nodes) and applying a negative voltage to the control gate.
- the method involves regulating the negative voltage to maintain the negative voltage at a level responsive to the positive voltage on the source.
- the level responsive to the source voltage is regulated so that the electric field remains essentially constant between the floating gate and the source of the cell over a range of values of the source voltage.
- the regulating according to another aspect of the invention, the source voltage and a negative voltage establish an electric field between the floating gate and the source of the memory cell to be erased according to a physical relationship.
- the regulating of the negative voltage is accomplished by a circuit having a transfer function modeling the physical relationship. In this manner, integrated circuit memory device having a constant erase speed can be provided. With a constant erase speed, the control circuitry for erasing the array of cells, can be improved.
- Fig. 1 is a simplified diagram illustrating the source side Fowler- Nordheim Tunneling erase operation according to the present invention with a negative voltage regulator which is responsive to the source voltage.
- Fig. 2 is a circuit diagram of a preferred embodiment of the negative voltage regulator of Fig. 1.
- Fig. 3 illustrates an alternative view of a regulator according to the present invention.
- Fig. 4 is a graph of the output of the negative voltage generator versus source voltage according to a simulation of the circuit of Fig. 2.
- Fig. 5 is a graph of the magnitude of the electric field between the floating gate and source of the memory cell for a range of source voltages based on simulation of the circuit of Fig. 2.
- Fig. 6 illustrates the measured results of operation of an integrated circuit implementing the regulator of Fig. 2 for a supply potential of 4.4 volts.
- Fig. 7 illustrates the measured results of operation of an integrated circuit implementing the regulator of Fig. 2 for a supply potential of 5 volts.
- Fig. 8 illustrates the measured results of operation of an integrated circuit implementing the regulator of Fig. 2 for a supply potential of 5.6 volts.
- Fig. 9 is a simplified diagram of an integrated circuit memory implementing the regulated negative voltage generator of the present invention.
- Fig. 1 a simplified diagram of a circuit according to the present invention is provided.
- a flash memory cell 10 having a control gate on line 11, a drain on line 12, and a source on line 13 is provided.
- the floating gate cell 10 includes a floating gate 14.
- the cell 10 is coupled in this simplified example to a substrate represented by line 15 which is grounded for the erase operation.
- a source potential is applied to line 13 through transistor 16.
- the drain of transistor 16 is coupled to the supply potential VDD.
- the gate is coupled to a reference voltage which is used to establish the positive voltage on the source 13. Due to variations in VDD and other factors, the positive voltage on the source 13 can vary over a range of values.
- the drain terminal 12 is left floating, by disconnecting bitlines coupled to the drain.
- a negative voltage NVPP is applied to line 11.
- the negative voltage NVPP is generated by a charge pump 20 having a negative voltage regulator 21 coupled to it.
- the negative voltage charge pump 20 for one embodiment, is described in United States Patent No. 5,532,906 entitled NEGATIVE VOLTAGE GENERATOR FOR FLASH EEPROM, issued 2 July 1996.
- the source voltage 13 is coupled to the negative voltage regulator 21 as indicated by line 22.
- the negative voltage regulator is responsive to the source voltage to control the output of the negative voltage generator 20 so as to maintain a constant erase speed, or alternatively, to maintain a constant electric field between the floating gate 14 and the source 13.
- E-Field [V(source) - V(floating gate)] / oxide thickness
- Equation 2 shows the relationship.
- Vg ((1-Cs) / Cg)*Vs - (E-field*oxide thickness) / Cg + V ⁇ /Cg (equation 2)
- Fig. 2 is a circuit diagram of a preferred negative voltage regulator 21 according to the present invention.
- the negative voltage regulator is coupled to the output NVPP of the negative pump on line 50.
- the source voltage generated by the source voltage source is supplied on line 51.
- a level shift circuit which induces a voltage shift V SHr T is coupled from line 50 to node 52 at which a voltage V D is created.
- the level shift circuit comprises a zener diode 53, a first p-channel MOS transistor 54 and a second p-channel MOS transistor 55 in series.
- the transistors 54 and 55 have their respective gates coupled to their respective drains in diode configurations.
- the n-wells in which the transistors 54 and 55 are implemented are each coupled to the source of transistor 55 at node 52.
- transistor 54 is a native mode device in which the channel is doped with a lesser doping concentration to induce a lower threshold voltage. Both transistors 54 and 55 having channels that are 30 microns wide and 1 micron long in this example.
- Node 52 is coupled to a voltage divider including resistor 56 and resistor 57.
- resistor 56 has 38 kilohms of resistance
- resistor 57 has 42 kilohms.
- Resistor 57 is coupled to the source of n-channel transistor 58.
- the gate of transistor 58 is coupled to a reference voltage 59.
- the drain of transistor 58 is coupled to the supply potential VDD.
- the reference voltage 59 is about 4.2 volts causing the voltage V ⁇ at the source of transistor 58 to be about 4.2 volts less the threshold of transistor 58 of about 0.7 volts, or about 3.5 volts in this example.
- transistor 58 is quite large (the channel is 30 microns wide by 0.6 microns long in this example), and the current through transistor 58 is relatively small (20 to 60 microamps in this example), the gate to source voltage threshold can be kept relatively constant. At node 60 between resistors 56 and 57, a feedback potential Y mv is generated.
- the feedback potential V ffiF is applied to the gate of p-channel transistor 61.
- the source of p-channel transistor 61 is coupled to the node 62.
- Node 62 is coupled to the source of n-channel transistor 63.
- the source voltage 51 is coupled to the gate of transistor 63, and the drain of transistor 63 is coupled to the supply potential VDD.
- the drain of transistor 61 is coupled to the output of the negative voltage generator on line 50 through the diode connected transistors 64 and 65.
- Transistors 64 and 65 each have their gates coupled to their drains. They are connected in series as illustrated in the figure.
- the n-wells are each coupled to the node 62. Likewise, the n-well of transistor 61 is coupled to node
- a clamping transistor 66 has its source coupled to node 62, its drain coupled to the supply potential VDD and its gate coupled to a reference voltage on line 67, which in this example is about 4.0 volts.
- the zener diode 53 and the transistors 54 and 55 constitute a level shifter which reflects the magnitude of the negative voltage at line 50 by a voltage closer to, or above, the ground potential on node 52.
- Transistor 58 provides a constant voltage at its source as a power supply for the level shifter.
- Voltage divider implemented by resistors 56 and 57 is used to model the coefficient of equation 2 set forth above.
- the transfer function of the circuit of Fig. 2 can be expressed as follows:
- N D V NVPP + V SHIFT (equation 4)
- V REF (V U -V D )*R 2 / (R 1 +R 2 )+V D (equation 5)
- Nsou RCE V REF + V GS (trans. 63) - V GS (trans. 61) (equation 6)
- R j resistance of resistor 57
- R 2 resistance of resistor 56
- V NVPP - [(R,+R 2 )/R,*V GS (trans. 63) - (R,+R 2 )/R,*V GS (trans. 61) + R 2 /U,*V u +V SHIFT )j (equation 7).
- the gate to source voltage V GS for both transistors 61 and 63 is relatively constant by implementing them with relatively large devices (200 microns wide by 1 micron long for each in this example). Also, voltage V ⁇ at the source of transistor 58 is relatively constant. Thus, equation 7 can be made to match equation 2 quite well with the proper choice of the ratio of the resistances in the voltage divider implemented by resistors 56 and 57. Thus, as the voltage at the source of the transistors falls, the gate voltage can be increased in magnitude to compensate. This maintains erase speed essentially constant for a preferred system. Other relations to maintain constant erase speed may be implemented on a particular flash memory system. Transistor 66 provides additional protection. If the source voltage drops too much, transistor 66 will prevent node 50 from going below a limit which would cause stress on a circuitry in the device.
- Fig. 3 provides another point-of-view of the regulator 21.
- the regulator includes an amplifier 100 having a positive input coupled to the source voltage on line 101, and a negative input 102 provided at the output of an offset generator 103.
- the input to the offset generator 103 is provided by the reference voltage Vu across resistor 104, and by feedback provided through resistor 105 and level shifter 106 from the output on line 107, which is coupled to the output of the negative voltage generator.
- the diagram of Fig. 3 is implemented in the circuit of Fig. 2 when the offset 103 is characterized as the threshold voltage of transistor 63 plus the absolute value of the threshold of the transistor 61.
- the resistors 104 and 105 adjust the feedback ratio.
- the voltage Vu is utilized to adjust the output DC offset.
- Other circuit designs may also be employed to model the physical relationship expressed in equation 2, or other physical relationship based on erase speed or electric field magnitude.
- Figs. 4 and 5 illustrate the results of simulation of the circuit of Fig. 2.
- Trace 200 corresponds to a supply potential of 4.4 volts at 85 °C
- trace 201 corresponds to a supply potential of 5 volts at
- trace 202 corresponds to a supply potential of 5.6 volts at 0°C.
- the ideal curve is illustrated at line 203. As can be seen, the simulated results track the ideal curve quite well.
- Fig. 5 illustrates simulation of the magnitude of the electric field over a range of source voltages for each of the three cases identified above.
- trace 210 corresponds to a supply potential of 4.4 volts at 85°C
- case 211 corresponds to a supply potential of 5 volts at 25 °C
- case 212 corresponds to a supply potential of 5.6 volts at 0°C.
- the electric field is essentially constant for a source voltage above 4 volts.
- Figs. 6, 7 and 8 illustrate measurement data for a circuit implemented according to Fig. 2.
- the negative voltage potential is graphed along trace 600 in Fig. 6, and the source voltage potential is graphed along trace 601.
- Fig. 7 the negative voltage is shown on trace 700 and the source potential is shown on trace 701.
- Fig. 8 the negative voltage is shown on trace 800, and the source potential is shown on trace 801.
- horizontal axis represents time in 10 milliseconds per scale.
- the vertical axis represents the potential at the source and the output of the negative voltage generator.
- the line at point 605 represents an offset of 4 volts for the source potential.
- Line 606 represents an offset of about -8 volts for the negative voltage generator.
- line 705 represents 4.5 volts for the source potential and -8 volts for the negative voltage.
- line 805 represents 4.5 volts for the source voltage and line 806 represents -8 volts for the negative voltage.
- Table 1 illustrates the results for Figs. 6, 7 and 8 at the various supply potentials.
- the non-constant tracking ratio reflected in the measurement data are believed to be due to the non-constant shifting voltage of the voltage shifter and poor regulation of the reference potentials in the tested circuit.
- the electric field can be maintained essentially constant and the erasing speed controlled using a circuit that manages the magnitude of the negative voltage applied to the control gate in response to variations in the source potential.
- Fig. 9 is a simplified diagram of an integrated circuit 900 including a flash memory array 901.
- a negative voltage generator 902 which is regulated in response to the voltage generated by a source voltage generator 903 is included for use during erasing of the array as described above.
- the integrated circuit 900 includes address input circuits 905, data input/output circuits 906, a supply potential input 907, and a ground input 908.
- a control state machine 909 is coupled to the data input/output circuits 906 and the address input circuits 905 for managing the operation of the device for read, program and erase operations as known in the art.
- a data in voltage source 910 is coupled to a column decoder 911 and to the data input/output circuits 906 for applying voltages necessary for programming the array.
- the source voltage source 903 applies a voltage utilized for connection across source conductors to the sources of transistors in the array during the erase, program and read operations.
- the column decoder drives a set of bitlines 912 which are used to access memory cells in the array.
- a wordline decoder 913 is coupled to the array.
- the wordline decoder drives wordlines 914 which are used to access memory cells in the array.
- the terminal 907 is coupled to a supply voltage VDD provided by a power supply (not shown) external to the circuit.
- This power supply voltage is specified typically to be about 5 volts +/- 10%. In alternative systems, the supply voltage VDD may be specified at lower voltages, for example from 2.6 to about 3.2 volts, depending on the particular implementation.
- the data-in voltage generator 910, the source voltage generator 903, and the negative voltage generator 902 are all responsive to the supply voltage VDD to generate the potentials used during the read, program and erase operations.
- the erasing operations executed by the control state machine 909 are implemented for example as described in United States Patent No. 5,414,664 entitled FLASH
- a negative voltage is applied from the negative voltage generator 902 to wordlines of cells to be erased.
- a positive voltage is applied from the source voltage source 903 to sources of transistors in the array as indicated by line 915.
- the negative voltage generator 902 includes a voltage regulator, as described above which maintains a constant erase speed, and supports a constant erasing time for memory cells in the array. This simplifies the control state machine 909, the algorithms which must be executed to erase the array, and in general allows for a faster, more reliable erasing algorithm.
- the present invention provides an improved technique for erasing memory cells in a floating gate memory device based on a source side erase operation.
- a voltage regulator having a transfer function that models the physical relationship between source and wordline voltages, and the electric field between the floating gate and the source is provided.
- the output of the negative voltage generator driving the wordline is regulated in response to the source voltage to maintain such electric field in a manner that maintains the erasing speed constant during the erase operation. This provides for easier control of the erasing algorithms, and more efficient operation of the integrated circuitry.
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Abstract
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Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98943549A EP1125298A4 (en) | 1998-09-03 | 1998-09-03 | Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices |
CN98814235.XA CN1255813C (en) | 1998-09-03 | 1998-09-03 | Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices |
PCT/US1998/018548 WO2000014747A1 (en) | 1998-09-03 | 1998-09-03 | Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices |
JP2000569405A JP4074748B2 (en) | 1998-09-03 | 1998-09-03 | Voltage source regulated to introduce tunneling current into floating gate memory device |
US09/380,873 US6229732B1 (en) | 1998-09-03 | 1998-09-03 | Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US1998/018548 WO2000014747A1 (en) | 1998-09-03 | 1998-09-03 | Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices |
Publications (1)
Publication Number | Publication Date |
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WO2000014747A1 true WO2000014747A1 (en) | 2000-03-16 |
Family
ID=22267835
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/018548 WO2000014747A1 (en) | 1998-09-03 | 1998-09-03 | Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1125298A4 (en) |
JP (1) | JP4074748B2 (en) |
CN (1) | CN1255813C (en) |
WO (1) | WO2000014747A1 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100358049C (en) * | 2003-12-08 | 2007-12-26 | 联华电子股份有限公司 | Method for programming P channel electrically erasable programmable read only memory |
IL266125B (en) * | 2014-03-03 | 2022-07-01 | Solarlytics Inc | Method and system for applying electric fields to multiple solar panels |
US9472247B2 (en) * | 2015-02-13 | 2016-10-18 | Taiwan Semiconductor Manufacturing Company Limited | Memory, semiconductor device including the same, and method for testing the same |
CN114553216A (en) * | 2020-11-25 | 2022-05-27 | 长鑫存储技术有限公司 | Potential generating circuit, inverter, delay circuit and logic gate circuit |
EP4033661B1 (en) | 2020-11-25 | 2024-01-24 | Changxin Memory Technologies, Inc. | Control circuit and delay circuit |
EP4033312A4 (en) | 2020-11-25 | 2022-10-12 | Changxin Memory Technologies, Inc. | Control circuit and delay circuit |
US11681313B2 (en) | 2020-11-25 | 2023-06-20 | Changxin Memory Technologies, Inc. | Voltage generating circuit, inverter, delay circuit, and logic gate circuit |
EP4033664B1 (en) | 2020-11-25 | 2024-01-10 | Changxin Memory Technologies, Inc. | Potential generation circuit, inverter, delay circuit, and logic gate circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5282170A (en) * | 1992-10-22 | 1994-01-25 | Advanced Micro Devices, Inc. | Negative power supply |
US5687117A (en) * | 1996-02-23 | 1997-11-11 | Micron Quantum Devices, Inc. | Segmented non-volatile memory array with multiple sources having improved source line decode circuitry |
US5721707A (en) * | 1996-01-24 | 1998-02-24 | Sgs-Thomson Microelectronics S.R.L. | Erase voltage control circuit for an electrically erasable non-volatile memory cell |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5532915A (en) * | 1994-03-23 | 1996-07-02 | Intel Corporation | Method and apparatus for providing an ultra low power regulated negative charge pump |
-
1998
- 1998-09-03 JP JP2000569405A patent/JP4074748B2/en not_active Expired - Lifetime
- 1998-09-03 CN CN98814235.XA patent/CN1255813C/en not_active Expired - Lifetime
- 1998-09-03 WO PCT/US1998/018548 patent/WO2000014747A1/en not_active Application Discontinuation
- 1998-09-03 EP EP98943549A patent/EP1125298A4/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5282170A (en) * | 1992-10-22 | 1994-01-25 | Advanced Micro Devices, Inc. | Negative power supply |
US5721707A (en) * | 1996-01-24 | 1998-02-24 | Sgs-Thomson Microelectronics S.R.L. | Erase voltage control circuit for an electrically erasable non-volatile memory cell |
US5687117A (en) * | 1996-02-23 | 1997-11-11 | Micron Quantum Devices, Inc. | Segmented non-volatile memory array with multiple sources having improved source line decode circuitry |
Non-Patent Citations (1)
Title |
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See also references of EP1125298A4 * |
Also Published As
Publication number | Publication date |
---|---|
JP2003522363A (en) | 2003-07-22 |
CN1255813C (en) | 2006-05-10 |
JP4074748B2 (en) | 2008-04-09 |
EP1125298A1 (en) | 2001-08-22 |
CN1367927A (en) | 2002-09-04 |
EP1125298A4 (en) | 2003-05-07 |
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