WO1999044295A1 - Full and half-rate signal space detection for channels with a time-varying mtr - Google Patents
Full and half-rate signal space detection for channels with a time-varying mtr Download PDFInfo
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- WO1999044295A1 WO1999044295A1 PCT/US1998/018851 US9818851W WO9944295A1 WO 1999044295 A1 WO1999044295 A1 WO 1999044295A1 US 9818851 W US9818851 W US 9818851W WO 9944295 A1 WO9944295 A1 WO 9944295A1
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- sample vector
- data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/31—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
- H03M5/145—Conversion to or from block codes or representations thereof
Definitions
- the present invention relates to disc drives. More particularly, the present invention relates to a data detector in a disc drive wherein the data detector detects data encoded according to a code having time varying constraints .
- a typical disc drive includes one or more discs mounted for rotation on a hub or spindle.
- a typical disc drive also includes a transducer supported by a hydrodynamic air bearing which flies above each disc .
- the transducer and the hydrodynamic air bearing are collectively referred to as a data head.
- a drive controller is conventionally used for controlling the disc drive based on commands received from a host system. The drive controller controls the disc drive to retrieve information from the discs and to store information on the discs.
- an electromechanical actuator operates within a negative feedback, closed-loop servo system.
- the actuator moves the data head radially over the disc surface for track seek operations and holds the transducer directly over a track on the disc surface for track following operations .
- Information is typically stored in concentric tracks on the surface of the discs by providing a write signal to the data head to write information on the surface of the disc representing the data to be stored.
- the drive controller controls the electromechanical actuator so that the data head flies above the disc and generates a read signal
- the read signal is typically conditioned and then decoded by the drive controller to recover the data.
- a typical read channel includes the data head, preconditioning logic (such as preamplification circuitry and filtering circuitry) , a data detector and recovery circuit, and error detection and correction circuitry.
- the read channel is typically implemented in a drive controller associated with the disc drive.
- a drive controller associated with the disc drive.
- the error rate per number of bits recorded (the bit error rate) be maintained at a relatively low level.
- maximum likelihood sequence detection (MLSD) methods are desired.
- Such methods can be implemented using the well known Viterbi algorithm.
- a direct implementation of an MLSD method is very costly. For example, the channel response after forward filtering is typically quite long, and may contain ten or more terms. Thus, a Viterbi detector would require 2 10 " 1 sates, which is impractically complex. Therefore, other techniques have been investigated which tend to reduce complexity yet still provide results which approach those of direct MLSD methods .
- One such technique is to apply the Viterbi algorithm to a reduced number of terms by cancelling some of the terms with feedback. For example, by cancelling all but two terms (and including the main cursor) allows the Viterbi detector to have only four states. Such detectors are referred to as reduced state sequence estimators (RSSE) .
- RSSE reduced state sequence estimators
- E 2 PRML enhanced extended partial response maximum likelihood
- the present invention addresses these and other problems, and offers other advantages over the prior art .
- MTR codes act to increase the minimum Euclidean distance between data samples in a magnetic recording channel .
- the 3D-110 detector whose performance is comparable to a fixed delay tree search with decision feedback of depth 2 (FDTS/DF(2) ) at high symbol densities .
- the detector is constructed by considering vectors of three received samples in a three dimensional space . Three planar boundaries are calculated and are used to divide the signal space into two regions, each of which correspond to a decision of +1 or -1 for the bit currently being processed.
- the 3D- 110 detector also includes a forward filter which removes precursor intersymbol interference (ISI) terms and forces the two post cursor ISI terms to be 1 and 0, respectively, where the cursor is also normalized to 1.
- ISI precursor intersymbol interference
- a feedback filter is implemented which removes all but the two post cursor ISI terms. Therefore, with no error propagation through the detector, the equivalent discrete-time channel pulse response can be denoted as 110. Such a constraint on the channel response is used to simplify the detector structure.
- FIR constrained length finite impulse response
- the 3D-110 channel provides significant advantages in performance and/or simplicity over other detectors (such as the more complicated FTDS/DF(2) detector) it does contain the above-described disadvantages .
- the present invention is directed to a system that addresses these and other problems, and offers other advantages .
- a detector of the present invention is provided to detect data values within a data signal that is sampled to provide temporally separated data samples.
- a first detector portion is configured to determine the location of a first sample vector in a first signal space.
- a second detector portion is configured to determine the' location of a second sample vector in a second signal space.
- the second detector portion determines the location by using a logic statement to combine a plurality of location indicators. Each location indicator provides the location of the second sample vector relative to a respective boundary surface.
- the form of the logic statement is independent of the values of the location indicators.
- each location indicator is independent of all other location indicators .
- FIG. 1 is a top view of a disc drive with its upper casing removed and embodying features of the present invention.
- FIG. 2 is a high level block diagram of the disc drive shown in FIG. 1.
- FIG. 3 is a schematic diagram illustrating a magnetic channel and associated reading circuitry to better illustrate notation used herein.
- FIGS. 4-1 and 4-2 illustrate symbol constellations corresponding to a detector in accordance with one aspect of the present invention.
- FIGS. 5-1 and 5-2 show waveforms illustrating dominant error events for MLSD of high densities .
- FIG. 6 is a block diagram illustrating a detector architecture of a detector in accordance with one aspect of the present invention.
- FIGS. 7-1 and 7-2 illustrate a FTDS/DF tree used to illustrate operation of a detector in accordance with one aspect of the present invention.
- FIG. 8 is a block diagram showing the architecture of an embodiment of a 3D/4D signal space detector of the present invention.
- FIG. 9 is a block diagram showing the architecture of one embodiment of a half-rate 3D/4D signal space detector of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
- a rotary disc drive system suitable for incorporating the teachings of the present invention is shown in diagrammatic form and is referred to generally at 110.
- a plurality of information storage discs 112 are journaled about a spindle motor assembly 114 within a housing 116.
- Each disc 112 has a multiplicity of concentric circular recording tracks, indicated schematically at 118 for recording information.
- Each track 118 is subdivided into a plurality of sectors, indicated schematically at 120.
- Data can be stored on or retrieved from the discs 112 by referencing a specific track 118 and sector 120.
- An actuator arm assembly 122 is rotatably mounted preferably in one corner of the housing 116.
- the actuator arm assembly 122 carries a plurality of head gi bal assemblies 124 that each carry a slider 125 having a read/write head, or transducer 126, for reading information from and writing information onto the discs 112.
- a voice coil motor 128 is adapted to precisely rotate the actuator arm assembly 122 back and forth such that the transducers 126 move across the discs 112 along arc 130.
- Control circuitry 132 controls the position of the transducers 126 and processes information to be written to or received from discs 112.
- FIG. 2 shows a high level block diagram of the control circuitry 132 of disc drive system 110.
- a microcontroller 134 directly implements all of the primary functions of the disc drive system 110.
- a read/write support and interface control circuit, indicated generally at 136, and a motor and actuator controller 138 are connected to the microcontroller 134 by a general purpose data, address, and control bus 140.
- Circuit 136 in general provides a hardware interface between the disc drive system 110 and a host computer system (not shown) via a communications bus 142.
- circuit 136 in general provides an interface between the motor and actuator controller 138 and a read/write channel 144.
- the read/write channel 144 receives a signal from preamplifier 143 which, in turn, receives a signal from transducers 126.
- Read/write channel 144 acts as an interface between the microcontroller 134 and the transducers 126 over lines 145.
- the read/write channel 144 also provides signals over line 146 to the motor and actuator controller 138.
- Controller 138 is provided as an interface between the microcontroller 134 and the motor assembly 114 over lines 148, and an interface between the microcontroller 134 and the actuator arm assembly 122 over lines 150.
- FIG. 3 is a schematic diagram of a magnetic channel 160 and read channel blocks 162 and is provided for purposes of better understanding the notation used herein.
- Channel 160 includes the recording medium, such as disc 112 and transducers 126.
- Read channel blocks 162 includes adder 164, front filter 166, sampler 186, forward filter 168, adder 170, detector 172 and feedback filter 174.
- Read channel blocks 162 are generally implemented in read/write channel 144 shown in FIG. 2.
- the input 176 to magnetic channel 166 is preferably a sequence of data bits, the data bit for a current time period k is represented by a k .
- NRZI non-return- to-zero inverse
- the data bits are read from the magnetic channel, they are provided as a readback signal 178.
- the readback signal 178 is typically corrupted by noise 180 which is represented by n(t) being added to the readback signal 178 by adder 164.
- noise n(t) and adder 164 are shown as only representations of the noise which corrupts readback signal 178 and are thus not part of the actual hardware implementation. In any case, the noise n(t) is present and corrupts readback signal 178 to form corrupted read signal 182.
- Corrupted read signal 182 is provided to front filter 156.
- Front filter 156 is, by way of example, implemented as an analog low-pass filter which prevents aliasing and filters out high frequency noise and provides a filtered output 184 to sampler 186.
- Sampler 186 samples filtered output 184 and can be embodied as an analog-to-digital converter.
- the sampled signals produced by sampler 186 are provided to forward filter
- Forward filter 168 preferably operates alone or in combination with other filtering to whiten the noise in the readback signal and provide a modified readback signal 188 (also designated r k ) to adder 170.
- An example of forward filter 168 is a finite impulse response (FIR) filter which includes a plurality of taps.
- FIR finite impulse response
- Forward filter 168 removes all precursor inter- symbol interference (ISI) terms. Post-cursor ISI terms are permitted to assume their natural values, because no constraints are enforced on the channel coefficients.
- Detector 172 provides a sequence 190 (also designated a k ) at its output.
- the output a k is an estimate of the input data sequence a k .
- the output a k is also provided to feedback filter 174 which is used to provide feedback signal 192 to adder 170.
- Feedback signal 192 is added to the output r k of forward filter 168.
- the combination of these signals is provided at the output 194 (also designated y k ) of adder 170 to decision device 172.
- feedback filter 174 is intended to remove all but two post-cursor ISI terms. In another embodiment, it is intended to remove all but three post-cursor ISI terms
- an equivalent discrete-time channel response includes three terms and is denoted as (1, f x , f 2 ) .
- the noiseless input y k to decision device 172 can be written as follows:
- a three-dimensional signal space detector can be implemented by first considering a symbol constellation in three-dimensional space. As described in greater detail below, such a detector maps all possible symbols which could represent the input data sequence to the three-dimensional space. The detector then obtains a sample vector that includes contributions from a plurality of input samples that are each formed from a plurality of terms indicative of input data samples in the input sample sequence. The sample vector is then mapped to the same three-dimensional space in the constellation. The detector then determines which of the possible data symbols is closest in the three- dimensional space to the sample vector at each time interval.
- Each pair of possible symbols which point to different detector decisions should be separated by a boundary plane .
- the planar boundaries are combined by logic rules so that the signal space is partitioned into two regions, one corresponding to a detector decision of +1 and the other corresponding to a detector decision of -1.
- a binary decision is released by detector 172 as -lithe detector output a k .
- the detector structure is simplified by eliminating planes which are redundant, and also by eliminating separate symbols which are much further apart than the minimum Euclidean distance associated with the code .
- FIGS. 4-1 and 4-2 illustrate a vector space for a detector which analyzes an input sequence having three terms which constitute a sample vector, also known as an observation vector. More specifically, FIGS. 4-1 and 4-2 illustrate symbol constellations of a Lorentzian channel at symbol density of 2.25.
- the constellations have axes y k (also designated by numeral 200) and y' ) ._- . (also designated by numeral 202) .
- the constellations shown in FIGS. 4-1 and 4-2 also include a third axis y'' k - 2 (which is also designated by the number 204) .
- Axis y'' k _ 2 extends into and out of the plane of the paper containing FIGS. 4-1 and 4-2.
- y' k _ ⁇ and y' ' k _ 2 generically denote the detector inputs at times k-l and k-2 with the intersymbol interference due to the available past decisions (i.e., the decisions for a k _ 3 and a k _ 4 at time k) cancelled.
- the detector must make a decision on the input bit a k _ 2 (i.e., the input bit which was received two time intervals previously) at each time k in the detection process because the detector is processing three input samples as an observation vector.
- Table 1 illustrates all possible input sequences which could be represented by the observation vector.
- Table 1 also includes the possible symbols written out in terms of a k _ 2 , a k _ ⁇ and a k , and
- SUB8TnUTESHEET(R JE26) also provides an evaluation of the axis y k , y' k _ ⁇ and Y'' k - 2 written in terms of the channel response.
- FIGS. 5-1 and 5-2 illustrate waveforms 206, 208, 210 and 212 which represent dominant error events observed for MLSD detectors at high densities and high order partial response targets.
- the error event is generated when a tribit waveform 206 is shifted one time interval to produce a shifted tribit 208.
- the error event is generated when a quadbit waveform 210 is detected as a dibit waveform 212 or vice versa.
- symbol 5 corresponds to a sequence of input bits of the form (+1, -1, +1, -1) which contains three consecutive transitions and must be eliminated.
- FIGS. 4-1 and 4-2 also illustrate slicer planes A, B, C and D which are used to divide the various symbols mapped to the constellations.
- Plane A is provided to separate symbols 0 and 4 (and also symbols 1 and 5 in FIG. 4-1) .
- the decision boundaries are planes which bisect a line which connects the pairs of symbols being separated.
- the system is constrained to locate the plane not to separate the two symbols in three-dimensional space, but to separate their projections on a surface. This constraint is implemented by picking the two coordinates which contribute most heavily to the distance between the two symbols. It can be seen that the y'' k _ 2 coordinate should be retained since the two symbols which correspond to different decisions on the input bit a k _ 2 are easily separated on this axis.
- the y' k _ ⁇ coordinate contributes more heavily to the distance between symbols 0 and 4 than the y k coordinate.
- the symbols are projected to the ⁇ ' k _ ⁇ y'' k _ 2 surface.
- Slicer plane A is thus constrained to only rotate perpendicular to the y' k _ ⁇ y'' k _ 2 surface.
- the projection of plane A onto the chosen surface is thus represented as a line whose direction changes as the slicer plane is allowed to rotate. All points on the line have the same distance from the projected pair of symbols.
- plane C separates symbols 3 and 5.
- Plane C is constrained to only rotate perpendicular to the y k y'' k _ 2 surface since the coordinates which contribute most heavily to the distance between the symbols are the coordinates corresponding to the y k and y'' k _ 2 axes.
- Equation 8 A sgn (y" k _ 2 + l y' k _ ⁇ - fx)
- Equation 12 E sgn (y" k _ 2 - (f x - f 2 ) y k + (f x - f 2 ) a k _ 3 )
- Equation 12 can be simplified as follows :
- Equation 13 E sgn (y' ' k _ 2 - y k + a k _ 3 )
- Equation 14 A: sgn (y k-2 + f- . y k . ⁇ + ⁇ A) Equation 15
- Equation 17 ⁇ A (-f. - f.f 2 ) a k _ 3 - f 2 a k _ 4 - f-
- the offset values in general, are implemented as short FIR filters with binary inputs, two input multiplexers, or look up tables.
- Decision logic can be implemented by moving a test point through the three-dimensional signal space and recording the relative position of the point with respect to the planes.
- the corresponding detector output is obtained by finding the closest symbol in the constellation to the test point.
- a logic rule or statement is then obtained by combining the cases which result in the same output decision from the detector.
- the logic rule can simply be obtained by inspection. Mapping the boundary decisions -1 to 0, the logic rule can be written as follows: Equation 20
- FIG. 6 is an architectural block diagram illustrating a 3D-SSD detector 214 in accordance with one aspect of the present invention.
- Detector 214 includes delay operators 216 and 218, multiplier 220, summing circuits 222, 224, and 226, slicers 228, 230,
- y k is provided to delay operator 216 which provides, at its output 240, y k _ ⁇ . That term is also provided to delay operator 218 which provides at its output 242, y k _ 2 .
- Multiplier 220 receives at its input 244, f j _.
- Summing circuit 222 receives at one input 246 thereof the offset value ⁇ E and at the other two inputs thereof y k and y k _ 2 .
- Summing circuit 224 receives at one input 248 thereof offset value ⁇ B and at the other two inputs thereof the output 250 of multiplier 220 and also y k nourish 2 .
- Summing circuit 226 receives, at a first input 252 thereof the offset value ⁇ A and at its other inputs the output 250 from multiplier 220 and y k _ 2 from delay operator 218.
- the output of summing circuits 222, 224 and 226 are provided to slicers 228, 230 and 234, respectively.
- the outputs 229, 231 and 235 of slicers 228, 230 and 234 are to circuits 236 and 238 as shown.
- the output 256 of circuit 238 provides a k _ 2 .
- detector 214 uses one multiplier, there slicers, three adders and three two-input multiplexers.
- a similar 3D- 110 detector can be implemented using three slicers, three adders and two-input multiplexers.
- the dominant error events mentioned with respect to FIGS. 5-1 and 5-2 can also be removed using a time-variant transition run constraint.
- a time-variant transition run constraint allows tribits, but only allows them to start at predetermined intervals.
- the time-variant transition run constraint allows tribits to
- SUBSTITUTESHEET(RULE2?) start only at every other (i.e., even or odd) numbered time intervals.
- This type of relaxed constraint allows the development of codes with higher rates.
- the time variant MTR code it is possible to have both symbols 2 and 5 present in the signal constellation at every other time interval.
- modifications must be made in order to accommodate the change in the code constraint .
- a signal space detector in accordance with the present invention can be understood with reference to an FDTS/DF tree of depth 2.
- FIG. 7-1 illustrates such a tree 280 where the tree has a root beginning at an odd time interval k-3 (also designated by numeral 282) .
- FIG. 7-2 illustrates such a tree 284 having a root which begins at an even time interval k-3 (also designated 286) .
- path 5 can be pruned from the tree since it
- branches 2 and 5 are extended one step further in time (beyond time interval k) .
- Such extensions are labeled 2A, 2B, 5A and 5B in FIGS. 7-1 and 7-2 and are also indicated by designation numerals 304, 306, 308, 310, 312, 314, 316 and 318.
- Extension of paths 2 and 5 does not affect pruning of the branches as illustrated in FIG. 7-1. Path 2 is still allowed and path 5 is still disallowed.
- extension of the paths one extra time interval allows the pruning of branch 2B.
- branch 2A is still allowed in FIG. 7-2 because it does not violate the time-variant MTR code constraint.
- branch 2B does violate the code constraint because it represents a tribit beginning at an odd time interval.
- branch 5B in FIG. 7-2 is allowed, while branch 5A can be eliminated.
- the remaining symbols, after pruning, in FIG. 7-2 which are represented by path 2A and path 5B correspond to an error event of the form +/- (2, -2, 2, 2) .
- the distance between these two symbols should be considerably greater than the minimum Euclidean distance for the code.
- a three-dimensional/four-dimensional signal space detector (3D/4D SSD) is implemented that accepts samples having three post-cursor ISI terms.
- the detector provides three-dimensional detection and four-dimensional detection.
- three-dimensional detection the detector selects a data value by determining the location of a sample vector in a three-coordinate signal space.
- four-dimensional detection the detector uses the location of a sample vector in a four-coordinate signal space to determine a data value .
- the 3D/4D SSD works well with data that has been encoded using a time-varying MTR code.
- MTR code that has an MTR constraint of 2 for odd time intervals and an MTR constraint of 3 for even time intervals
- the three-dimensional detection system is used at odd time intervals and the four-dimensional detection system is used at even time intervals.
- the sample vectors used in the 3D/4D SSD are preferably constructed from combinations of samples that are defined by the following generic sample equations:
- Yk-l a k-l + f- a k-2 + ⁇ 2 k-3 + £-3 a k-4
- Yk-2 a k-2 + fl a k-3 + f 2 a k-4 + f 3 a k-5
- Yk-3 a k-3 + f_ a k-4 + f 2 a k-5 + ⁇ 3 a k-6
- y k is the current sample provided to the detector
- a k-x is the (k-x) th detected data value
- x is the (k-x)th input value with the current input value that is being detected being the a k _ 3 input value.
- the sample vector is based on the combination
- the sample vector is based on the combination of Yk Yk-i/ Yk- 2 nd y k _ 3 .
- the location of the three-dimensional sample vector is determined in a three-dimensional space defined by the following three axis:
- each of the three axes are formed by cancelling the contribution of at least one input value that contributes to a respective generic sample. This can be seen by defining the axes in terms of the samples using generic sample equations 30 - 33 above. The definitions of the axes then become as follows:
- the 3D/4D SSD determines an odd time interval data value using boundary planes in the three dimensional signal space .
- the boundary planes are determined in a manner similar to that described above in connection with equations 5 - 19 yielding the following four location identifiers :
- Equation 40 sgn (y k _ 3 + f x y k _ 2 + ⁇ A) Equation 41
- Equation 43 D sgn (y k _ 3 - y k _ 2 + ⁇ D)
- sgn (expression) provides the sign of the expression and values ⁇ A, ⁇ B, ⁇ C, and ⁇ D are offset values given by:
- ⁇ D ⁇ (f ⁇ - f 3 ) a k . 4 - f 2 a k _ 5 - f 3 a k _ 6 + 1
- the 3D/4D SSD determines the location of a four-dimensional sample vector in a four- coordinate signal space.
- the four- dimensional sample vector used during four-dimensional detection is based on the combination of y k , y k _ ⁇ , y k _ 2 , and y k _ 3 , which are described by equations 30 - 33 above.
- the location of this four-dimensional sample vector is determined in a four- coordinate space defined by the following four axes:
- the location of the four-dimensional sample vector is compared to the location of a boundary plane that separates two symbols corresponding to paths 2A and 5B of FIG. 7-2.
- samples 2A and 5B are located at (1, -1 + f 1# 1 - f x + f 2 , 1 + f - f 2 + f 3 ) and (-1, 1 - fx, -1 + fx - f 2 , -1 - f x + f 2 - f 3 ) , respectively.
- coordinates y''' k _ 3 and y k contribute the most to the distance between samples 2A and 5B.
- the plane P between 2A and 5B is described by the following:
- location identifier P is then defined as: Equation 57
- ⁇ P is defined by:
- equation 57 can be further simplified without a significant impact on the detector performance, resulting in:
- location identifiers A, B, C, and D of equations 40-43 that were used in the three-dimensional detection continue to be valid. Using these location identifiers and location
- the 3D/4D SSD is implemented using a full-rate detector 400 of FIG. 8.
- Detector 400 includes delay operators 402, 404, and 406, multiplier 408, summing circuits 410, 412, 414, 416, and 418, slicers 420, 422, 424, 426, and 428, AND circuits 452, 454, and 456, OR circuits 458 and 460, and muliplexers 462 and 464.
- Delay operators 402, 404, and 406 are connected together in series and provide outputs 403, 405, and 407, respectively.
- Delay operator 402 receives y k at its input, so the series of delay operators 402, 404, and 406 provide y k _ ⁇ , y k - 2 / and y k _ 3 at their respective outputs 403, 405, and 407.
- Multiplier 408 receives f ⁇ and y k _ 2 at its inputs and produces the product of those two values at its output, which is connected to summing circuits 416 and 418.
- summing circuit 418 In addition to receiving the output of multiplier 408, summing circuit 418 also receives y k _ 3 and ⁇ A. Summing circuit 418 adds its inputs together to produce an output that is provided to slicer 428, which produces a 1 if the sum is 0 or greater and 0 if the sum is less than 0. Together, summing circuit 418 and slicer 428 perform the function described by equation 40.
- Summing circuit 416 receives the output of multiplier 408 along with y k _ 3 and ⁇ B . Summing circuit 416 provides the sum of its input values to slicer 426, which operates in a manner similar to slicer 428. Together, summing circuit 416 and slicer 426 perform the function described by equation 41.
- Summing circuits 410 and 412 each receive y ⁇ . ⁇ and y k _ 3 . In addition, summing circuits 410 and 412 receive ⁇ C and ⁇ D, respectively. Summing circuit 410 subtracts y k-1 from y k _ 3 plus ⁇ C to produce an output that is provided to slicer 420, which operates in a similar manner to slicers 426 and 428. Together, summing circuit 410 and slicer 420 perform the functions of equation 42. Summing circuit 412 subtracts y k _ x from y k _ 3 plus ⁇ D to produce an output that is provided to slicer 422, which operates in a manner similar to slicers 426 and 428. Together, summing circuit 412 and slicer 422 perform the functions of equation 43.
- Summing circuit 414 receives y k , y k _ 3 and ⁇ P, and provides their sum to slicer 424, which operates in a manner similar to slicer 426. Together, summing circuit 414 and slicer 424 perform the functions of equation 59.
- Multiplexer 462 passes either the output of slicer 420, representing location identifier C, or the output of slicer 422, representing location identifier D, based on the value of a k _ 4 .
- the output of multiplexer 462 is provided to AND circuit 452 along with the output of slicer 426, representing location identifier B.
- AND circuit 452 performs a logical AND operation on these input values and provides an output to OR circuit 458, which also receives the output of slicer 428, representing location identifier A.
- OR circuit 458 performs a logical OR operation on its two input values and provides its output to multiplexer 464, which passes the output value if the current value being detected is at a time interval that does not permit tribits.
- AND circuits 454 and 456, OR circuit 460 and multiplexer 464 provide the detection logic needed during time intervals when tribits are allowed. Specifically, these components implement the function of Equation 60.
- AND circuit 454 receives the output of slicers
- AND circuit 456 receives the output of slicers 420 and 426, representing location identifiers C and D, respectively, and provides a logic AND output based on those inputs.
- the outputs of AND circuits 454 and 456 are received by OR circuit 460 along with the output from slicer 428, representing location identifier A.
- OR circuit 460 performs a logical OR operation on its inputs to produce an output that is passed by multiplexer 464 as the detected value if tribits are allowed.
- the detector is implemented as a half-rate detector, capable of operating at twice the frequency of the input symbols .
- the block diagram architecture of such a detector is shown as detector 498 in FIG. 9.
- Detector 498 has two inputs 500 and 502 that receive y k and y k _- respectively.
- Two delay circuits 504 and 506 delay the signals on inputs 500 and 502 for two time periods resulting in y k _ 2 and y k-1 on lines 508 and
- Lines 508 and 510 are connected to even-time period circuit 512, which includes multiplier 540, summing circuits 514, 516, 518, 520, and 522, slicers 524, 526, 528, 530, and 532, AND circuits 534 and 536, and OR circuit 538.
- Even-time period circuit 512 operates in a manner similar to the portions of detector 400 of FIG. 8 associated with the detection of even time period data values.
- AND circuits 534 and 536 and OR circuit 538 perform the same logical operation as AND circuits 454 and 456, and OR circuit 460 of detector 400.
- the output of even-time period circuit 512 is detected value a k _ 4 .
- Detector 498 of FIG. 9 also includes two odd- time period circuits 550 and 552, which perform the functions of Equations 49 and 48, respectively.
- odd-time period circuit 550 includes summing circuits 554, 556, and 558, slicers 560, 562, and 564, AND circuit 566, and OR circuit 568 while odd- time period circuit 552 includes summing circuits 570, 572, and 574, slicers 576, 578, and 580, AND circuit 582, and OR circuit 584.
- Summing circuits 570, 572, 554, and 556 add y k _ 2 to the product of y k _ ⁇ and fx produced by multiplier 590 and to ⁇ A 0 , ⁇ B 0 , ⁇ A 1( and ⁇ B 1; respectively.
- Summing circuits 574 and 558 subtract y k from the sum of y k _ 2 and ⁇ C 0 and ⁇ D-, respectively.
- ⁇ A 0 , ⁇ B 0 , and ⁇ C 0 are equal
- slicers 576, 578, 580, 560, 562 and 564 are provided to slicers 576, 578, 580, 560, 562 and 564, respectively.
- Each of the slicers produces a +1 if the value at their respective input is 0 or greater, and 0 if the value at their respective input is less than 0.
- the output of slicers 578 and 580 are provided to AND circuit 582, which performs a logical AND function on the two inputs.
- the output of AND circuit 582 is provided to OR circuit 584 along with the output of slicer 576.
- Or circuit 584 performs a logical OR operation on the two inputs to produce a possible detection output corresponding to equation 48.
- slicers 562 and 564 are provided to AND circuit 566, which performs a logical AND function on the two inputs.
- the output of AND circuit 566 is provided to OR circuit 568 along with the output of slicer 560.
- Or circuit 568 performs a logical OR operation on the two inputs to produce a possible detection output corresponding to equation 49.
- odd-time period circuits 552 and 550 assume that a k _ 4 is equal to 0 and 1, respectively, and calculate a possible detected value based on that assumption. This assumption is necessary in detector 498 because a k _ 3 is being calculated before a k _ 4 has been determined. Once a. k _ 4 has been determined by even-time period circuit 512, the value of a.
- k _ 4 is used to select the a k _ 3 value that was calculated using the correct assumption for k _ 4 . This selection is performed by multiplexer 592, which passes the a k-3 value from odd- time period circuit 552 when a k _ 4 is 0 and passes the a k _ 3 value from odd-time period circuit 550 when a k _ 4 is 1.
- the present invention provides a detector 400 in a disc drive 110 that includes a first detector portion 462, 452, 458 configured to determine the location of a sample vector, y k _ 3 , y k _ 2 , y k _ ⁇ / in a first signal space y''' k-3 , y' ' k _ 2 , y' k - ⁇ - Tne detector 400 also includes a second detector portion 454, 456, 460, 464 configured to determine the location of a second sample vector y k _ 3 , y k _ 2 , Y-i/ Y k ' n a second signal space y''' k _ 3 ' Y'' k - 2 / Y' k -i' Yk- Tne determination is made using a logic statement, equation 60, to combine a plurality of location indicators A, B, C, D and P. Each location indicator provides a location, 0 or
- the present invention is also implemented as a method.
- the method includes determining at least two location identifiers A, B, C, and D that indicate the location of a sample vector a location of a sample
- a first data value a k _ 3 is then determined based on the location identifiers.
- At least two additional location identifiers A, B, C, D, and P are determined where each additional location identifier indicates the location of a second sample vector y k _ 3 , y k _ 2 , Y k -i Y k ' relative to respective boundary surfaces A, B, C, D, and P, in a second signal space y''' k - 3 , Y' . 2 ⁇ Y - ⁇ > Y k -
- a second data value a k _ 3 is then determined by combining the additional location identifiers using a decision equation, Equation 60.
- the format of decision equation 60 is independent of the values of the additional location identifiers.
- the present invention can also be implemented as a signal space detector configured to perform the above-mentioned steps.
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Abstract
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000533946A JP2002505540A (en) | 1998-02-24 | 1998-09-09 | Full and half rate signal space detection for channels with time varying MTR |
DE19882980T DE19882980T1 (en) | 1998-02-24 | 1998-09-09 | Full and half rate signal space acquisition for channels using a time variable MTR |
GB0017526A GB2349251B (en) | 1998-02-24 | 1998-09-09 | A detector for, and method of, detecting data values using sample vectors |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US7571198P | 1998-02-24 | 1998-02-24 | |
US09/076,961 US5936558A (en) | 1997-05-14 | 1998-05-13 | Signal space detector for channels utilizing a code having time varying constraints |
US09/076,961 | 1998-05-13 | ||
US60/075,711 | 1998-05-13 |
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WO1999044295A1 true WO1999044295A1 (en) | 1999-09-02 |
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PCT/US1998/018851 WO1999044295A1 (en) | 1998-02-24 | 1998-09-09 | Full and half-rate signal space detection for channels with a time-varying mtr |
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JP (1) | JP2002505540A (en) |
CN (1) | CN1158776C (en) |
DE (1) | DE19882980T1 (en) |
GB (1) | GB2349251B (en) |
WO (1) | WO1999044295A1 (en) |
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CA2392640A1 (en) * | 2002-07-05 | 2004-01-05 | Voiceage Corporation | A method and device for efficient in-based dim-and-burst signaling and half-rate max operation in variable bit-rate wideband speech coding for cdma wireless systems |
CN101562372B (en) * | 2009-04-10 | 2012-11-14 | 北京新宇航世纪科技有限公司 | Self-control energy-saving motor |
CN111101892B (en) * | 2020-02-05 | 2021-11-09 | 电子科技大学 | Shale gas horizontal well shaft pressure test and toe end sliding sleeve starting combined method |
Citations (1)
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US5731768A (en) * | 1996-01-31 | 1998-03-24 | Seagate Technology, Inc. | Method and apparatus for implementing codes with maximum transition run length |
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1998
- 1998-09-09 GB GB0017526A patent/GB2349251B/en not_active Expired - Fee Related
- 1998-09-09 JP JP2000533946A patent/JP2002505540A/en active Pending
- 1998-09-09 WO PCT/US1998/018851 patent/WO1999044295A1/en active IP Right Grant
- 1998-09-09 CN CNB988137852A patent/CN1158776C/en not_active Expired - Fee Related
- 1998-09-09 DE DE19882980T patent/DE19882980T1/en not_active Withdrawn
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US5731768A (en) * | 1996-01-31 | 1998-03-24 | Seagate Technology, Inc. | Method and apparatus for implementing codes with maximum transition run length |
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GB2349251A (en) | 2000-10-25 |
GB2349251B (en) | 2003-01-08 |
DE19882980T1 (en) | 2001-03-29 |
GB0017526D0 (en) | 2000-09-06 |
CN1158776C (en) | 2004-07-21 |
CN1301432A (en) | 2001-06-27 |
JP2002505540A (en) | 2002-02-19 |
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