WO1999017363A1 - Method for producing a multilevel cable carrier (substrate), especially for multichip modules - Google Patents

Method for producing a multilevel cable carrier (substrate), especially for multichip modules Download PDF

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Publication number
WO1999017363A1
WO1999017363A1 PCT/DE1998/002742 DE9802742W WO9917363A1 WO 1999017363 A1 WO1999017363 A1 WO 1999017363A1 DE 9802742 W DE9802742 W DE 9802742W WO 9917363 A1 WO9917363 A1 WO 9917363A1
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Prior art keywords
substrate
substrates
producing
individual
multichip modules
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PCT/DE1998/002742
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German (de)
French (fr)
Inventor
Harry Hedler
Norbert Ammann
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Tyco Electronics Logistics Ag
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Filing date
Publication date
Application filed by Tyco Electronics Logistics Ag filed Critical Tyco Electronics Logistics Ag
Priority to JP2000514330A priority Critical patent/JP2001518713A/en
Priority to EP98955336A priority patent/EP1019961A1/en
Publication of WO1999017363A1 publication Critical patent/WO1999017363A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0317—Thin film conductor layer; Thin film passive component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists

Definitions

  • the invention relates to a method for producing a multilevel wiring carrier (substrate), in particular for multichip modules, in which the conductor track system is applied in several coating and microstructuring steps simultaneously to several individual substrates, which are connected in one piece and are only separated after the structuring.
  • Integrated circuits face the challenge of their assembly and connection technology. So far, individual chips have often been packed into individual packages and processed further. However, several technical reasons make a further development of these housing processes appear desirable. For example, the connections of the various chip components of a system (processors, memory, ...) via pin / pin wiring outside the individual single-chip housings must currently be implemented in a higher architecture level of the system structure. The often very high number of pins per chip (up to a few hundred) stands in the way of further integration. Lowering energy consumption and increasing the clock rate (signal propagation times) also lead to shorter cable routes and thus to closer placement of the different chips. As a consequence of these requirements, multichip modules have been known for some time and are available on the market.
  • modules introduce an intermediate carrier substrate with a high wiring density as an additional level in the hierarchy of the system structure. Typical of this are the use of several unhoused chips and a high one Area coverage of the multichip substrate.
  • a similar known new development relates to the chip size package (CSP), in which a single unhoused chip is applied to an intermediate substrate that is hardly larger than the chip area, and in which the space-saving one
  • the insulation layers of the multilevel wiring carrier are typically produced from photostructurable polymers which are resistant to the temperature loads during the subsequent housing process (for example
  • a typical flat housing shape such as the Quad Fiat Pack (QFP) housing, has a standard thickness of the plastic body of 1.4 mm, which should be reduced in the future.
  • QFP Quad Fiat Pack
  • the present invention is therefore based on the object of developing the method of the type mentioned at the outset in such a way that very thin multichip modules, in particular based on lead frames, are made possible.
  • Individual substrates are processed at least during the structuring in the form of a strip substrate.
  • the invention is based on the idea of departing from the previous manufacture of the circuits on individual wafers in favor of an essentially continuous one
  • Ceramic tapes organic materials such as epoxy films and, above all, thin metal tapes are suitable as substrate material.
  • the latter are particularly suitable because they have a very good thermal conductivity, which leads to
  • Removing the power loss of the chips is advantageous and also have very good electrical conductivities, which enables their use as a global ground and shielding level.
  • the thin strip substrates are preferably manufactured with a thickness of less than 100 ⁇ m.
  • the structure of the different layers of the interconnect system takes a total of about 20 ⁇ m.
  • the structured metal substrates On the one hand, it is possible to place the structured metal substrates on an additional, common lead frame.
  • the metallic strip substrate itself can also be further processed into the lead frame below. It makes sense to use the basic materials of the wiring carrier in the typical alloys of
  • Leadframes used so choose copper or iron.
  • a "leadframe substrate” as a wiring carrier, the material advantages (moldability, compatibility with the silicon chip) of the leadframe have been used as a substrate carrier and, on the other hand, this has advantageously been combined with a very thin wiring carrier.
  • a leadframe substrate is used, instead of a chip on a conventional leadframe, a large number of chips are placed on the leadframe substrate, which means that ultra-thin modules are possible.
  • the metal / line levels are deposited by metallizing strips, for example using sputtering technology, if necessary with subsequent galvanic reinforcement.
  • the deposition of insulation levels is achieved by applying insulation material to the strip substrate, for example by roller coating, spray coating or by extrusion coating.
  • the photolithography of the conductor and insulation levels can be carried out by coating tape substrates, for example by roller coating, spray coating or extrusion coating, then exposing and developing tape substrates.
  • the previous wet Etching processes of the line / insulation levels can be carried out as bath etching processes of tapes. Individual experiences with deposition and structuring processes in connection with band production are already known from the production of lead frames with fine structures (approx. 65 ⁇ m).
  • handling systems are extremely simplified, since production is now essentially carried out by transporting the strip substrate from roll to roll through one or more production stations.
  • the conductor track and contact system on the top of the substrates can be produced using thin-film technology, thick-film technology or a combination of both.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

The conductor track system is applied simultaneously to several individual substrates in several coating and microstructuring steps. Said substrates form a single piece and are separated only after structuring has occurred. In order to produce ready-made thin substrates, the individual substrates are processed at least during structuring in the form of a strip.

Description

Be s ehre ibungBe honored
Verfahren zur Herstellung eines Mehrebenen- Verdrahtungsträgers (Substrat) , insbesondere für MultichipmoduleMethod for producing a multilevel wiring carrier (substrate), in particular for multichip modules
Der Erfindung betrifft ein Verfahren zur Herstellung eines Mehrebenen- Verdrahtungsträgers ( Substrat) , insbesondere für Multichipmodule, bei dem das Leiterbahnsystem in mehreren Beschichtungs- und Mikrostrukturierungsschritten gleichzeitig auf mehrere EinzelSubstrate aufgebracht wird, die dabei einstückig zusammenhängen und erst nach der Strukturierung vereinzelt werden.The invention relates to a method for producing a multilevel wiring carrier (substrate), in particular for multichip modules, in which the conductor track system is applied in several coating and microstructuring steps simultaneously to several individual substrates, which are connected in one piece and are only separated after the structuring.
Mit den zunehmend kleiner und schneller werdendenWith the increasingly smaller and faster
Integrierten Schaltungen wächst die Herausforderung an ihre Aufbau- und Verbindungstechnik. Bisher werden noch vielfach einzelne Chips in einzelne Gehäuse gepackt und weiterverarbeitet. Mehrere technische Gründe lassen jedoch eine Weiterentwicklung dieser Häusungsverfahren wünschenswert erscheinen. So müssen derzeit die Verbindungen der verschiedenen Chip- Bausteine eines Systems (Prozessoren, Speicher, ....) über Pin / Pin Verdrahtungen außerhalb der einzelnen Singlechip- Gehäuse in einer höheren Architekturebene des Systemaufbaus realisiert werden. Die häufig sehr hohe Zahl von Pins pro Chip ( bis einige Hundert) steht einer weiteren Integration im Wege. Auch zwingen die Senkung des Energieverbrauches und Erhöhung der Taktrate (Signallaufzeiten) zu kürzeren Leitungswegen und damit zur dichteren Plazierung der unterschiedlichen Chips. Als Konsequenz dieser Forderungen sind seit einiger Zeit Multichipmodule bekannt und auf dem Markt erhältlich.Integrated circuits face the challenge of their assembly and connection technology. So far, individual chips have often been packed into individual packages and processed further. However, several technical reasons make a further development of these housing processes appear desirable. For example, the connections of the various chip components of a system (processors, memory, ...) via pin / pin wiring outside the individual single-chip housings must currently be implemented in a higher architecture level of the system structure. The often very high number of pins per chip (up to a few hundred) stands in the way of further integration. Lowering energy consumption and increasing the clock rate (signal propagation times) also lead to shorter cable routes and thus to closer placement of the different chips. As a consequence of these requirements, multichip modules have been known for some time and are available on the market.
Durch diese Module wird ein Zwischenträgersubstrat mit hoher Verdrahtungsdichte als zusätzliche Ebene in die Hierarchie des Systemaufbaus eingeführt. Typisch dabei sind die Verwendung mehrerer ungehäuster Chips und eine hohe Flächenbelegung des Multichip- Substrats. Eine ähnliche bekannte Neuentwicklung betrifft das Chip- Size Package (CSP) , bei dem ein einzelner ungehäuster Chip auf ein Zwischensubstrat aufgebracht wird, das kaum größer als die Chipfläche ist, und bei dem dann die platzsparendeThese modules introduce an intermediate carrier substrate with a high wiring density as an additional level in the hierarchy of the system structure. Typical of this are the use of several unhoused chips and a high one Area coverage of the multichip substrate. A similar known new development relates to the chip size package (CSP), in which a single unhoused chip is applied to an intermediate substrate that is hardly larger than the chip area, and in which the space-saving one
Kontaktierung zur nächsten Architekturebene direkt unter der Chipfläche genutzt wird.Contacting to the next architecture level directly below the chip area is used.
Diese neuartigen Integrationstechniken bedürfen eines Trägersubstrats, auf dem sowohl die Chips montiert als auch, für Multichip- Module, durch extrem kurze Verdrahtungen untereinander elektrisch verbunden sind. Aufgrund der in Dünnfilmtechnik (bisher auf Keramiksubstraten) erreichbaren hohen Verdrahtungsdichte (typische Leiterbahnbreiten 5-50μm) sind normalerweise zwei bis vier Metallisierungsebenen ausreichend. Die wesentlichen Technologieschritte bei der Herstellung eines Dünnfilm- Mehrebenen- Verdrahtungsträgers sind:These new integration technologies require a carrier substrate on which the chips are mounted and, for multichip modules, are electrically connected to each other by extremely short wiring. Due to the high wiring density that can be achieved in thin-film technology (previously on ceramic substrates) (typical conductor track widths 5-50μm), two to four metallization levels are normally sufficient. The main technological steps in the production of a thin-film multi-level wiring carrier are:
-Aufbringen von Metallisierungen durch Sputtertechnik oder durch Aufdampfen, -die nachfolgende Fotolithographie, -und naßchemische oder trockene Ätzprozesse zur Strukturerzeugung .-Application of metallizations by sputtering or by vapor deposition, -the subsequent photolithography, -and wet chemical or dry etching processes for the production of structure.
Die Isolationsschichten des Mehrebenen- Verdrahtungsträgers werden dabei typischerweise aus fotostrukturierbaren Polymeren hergestellt, die gegenüber den Temperaturbelastungen beim anschließenden Häusungsverfahren (beispielsweiseThe insulation layers of the multilevel wiring carrier are typically produced from photostructurable polymers which are resistant to the temperature loads during the subsequent housing process (for example
Plastumspritzprozesse) unempfindlich sind.Plastic extrusion processes) are insensitive.
Die bisherigen Techniken, insbesondere die Dünnfilmtechnik, zur Herstellung von Multichipsubstraten nutzen das auch aus der Halbleiterherstellung bekannte Prinzip der Fertigung der Einzelsubstrate in Wafern (Panels oder Nutzen) . Dabei wird eine Anzahl gleicher, noch nicht zerteilter Einzelsubstrate gleichzeitig prozessiert. In der Dünnfilmtechnik werden typische, rechteckige Wafer mit einer Größe von (4-8 Zoll) einzeln (beispielsweise bei Spin- Coating- Prozessen oder bei Fotolithographie) oder in Gruppen (beispielsweise bei Sputter- Metallisierung oder bei galvanischer Verstärkung) den Herstellungsprozessen unterzogen.The previous techniques, in particular thin-film technology, for producing multichip substrates use the principle of manufacturing individual substrates in wafers (panels or panels), which is also known from semiconductor production. A number of identical, not yet divided individual substrates are used processed at the same time. In thin film technology, typical rectangular wafers with a size of (4-8 inches) are subjected to the manufacturing processes individually (for example in spin coating processes or in photolithography) or in groups (for example in sputter metallization or in the case of galvanic amplification).
Entscheidend ist nun, daß Waferdicken von 400 μm und mehr erforderlich sind, um ein sicheres Handling (maschinell oder manuell) , beispielsweise den Transport eines Wafers von einer Fertigungsstation zur nächsten, zu realisieren. Für eine rationelle Fertigung möchte man natürlich gleichzeitig möglichst viele Einzelsubstrate, das heißt einen großen Wafer, bearbeiten, womit jedoch wiederum die erforderliche Waferdicke wächst. Dies ist insofern problematisch, als andererseits die Forderung von Anwenderseite her besteht, auch für Multichipmodule die standardisierten Halbleitergehäuse verwenden zu können. Eine typische flache Gehäuseform, wie das Quad-Fiat-Pack (QFP) -Gehäuse hat eine Standarddicke des Plastikkörpers von 1,4 mm, die in Zukunft eher noch reduziert werden soll . Bei den mit den bekannten Verfahren hergestellten bisherigen Substraten kämen bei derartigen flachen Gehäuseformen zur Dicke des Leadframes, der Chips und des Plastikmaterials wie oben erwähnt noch mal 0,4mm (Zwischenträgersubstratdicke) in der Höhe hinzu, so daß sich das Standardmaß von 1,4mm oder weniger nicht halten ließe. Prinzipiell könnten zur Abhilfe zwar aus der Siliziumtechnologie bekannte Abdünnprozesse eingesetzt werden, die jedoch für die Anwendung bei der Herstellung von MultiChipmodulen zu aufwendig erscheinen.The decisive factor now is that wafer thicknesses of 400 μm and more are required in order to implement safe handling (mechanically or manually), for example the transport of a wafer from one production station to the next. For efficient production, one naturally wants to process as many individual substrates as possible, i.e. a large wafer, at the same time, but this in turn increases the required wafer thickness. This is problematic in that, on the other hand, there is a demand from the user side that the standardized semiconductor packages can also be used for multichip modules. A typical flat housing shape, such as the Quad Fiat Pack (QFP) housing, has a standard thickness of the plastic body of 1.4 mm, which should be reduced in the future. In the previous substrates produced with the known methods, such flat housing shapes would add another 0.4 mm (subcarrier substrate thickness) to the thickness of the lead frame, the chips and the plastic material, as mentioned above, so that the standard dimension of 1.4 mm or less could not be held. In principle, thinning processes known from silicon technology could be used to remedy this, but these seem too complex for use in the manufacture of multi-chip modules.
Der vorliegenden Erfindung liegt daher die Aufgabe zugrunde, das Verfahren der eingangs genannten Art so weiterzubilden, daß der Aufbau von sehr dünnen, insbesondere auf Leadframes basierenden Multichipmodulen ermöglicht wird. Insbesondere soll ein Substrat auf Dünnschichtbasis herstellbar werden, welches in seiner technologischen Verarbeitbarkeit und in seiner äußeren Geometrie keinerlei Einschränkungen an die bisherigen Häusungstechniken erfordert.The present invention is therefore based on the object of developing the method of the type mentioned at the outset in such a way that very thin multichip modules, in particular based on lead frames, are made possible. In particular, it should be possible to produce a substrate based on thin layers, which in terms of its technological processability and in its outer geometry does not require any restrictions on the previous housing techniques.
Erfindungsgemäß wird diese Aufgabe bei einem Verfahren der eingangs genannten Art dadurch gelöst, daß dieAccording to the invention this object is achieved in a method of the type mentioned in that the
Einzelsubstrate zumindest während der Strukturierung in Form eines Bandsubstrats prozessiert werden.Individual substrates are processed at least during the structuring in the form of a strip substrate.
Weiterbildungen der Erfindung sind Gegenstand der Unteransprüche. Die Erfindung und ihre Weiterbildungen werden nachfolgend noch näher erläutert .Developments of the invention are the subject of the dependent claims. The invention and its developments are explained in more detail below.
Der Erfindung liegt die Idee zugrunde, von der bisherigen Fertigung der Schaltungen auf Einzelwafern abzugehen zu Gunsten einer -im wesentlichen- kontinuierlichenThe invention is based on the idea of departing from the previous manufacture of the circuits on individual wafers in favor of an essentially continuous one
Substratfertigung in Form von Bändern. Bandfertigung erlaubt die Nutzung von extrem dünnen Trägermaterialien ohne zusätzliche Handlingprobleme. Sie sichert einen enormen Produktivitätsgewinn durch kontinuierliche Fertigung bei Metallisierung und Mikrostrukturierung.Production of substrates in the form of tapes. Belt production allows the use of extremely thin carrier materials without additional handling problems. It ensures enormous productivity gains through continuous production in metallization and microstructuring.
Als Substratmaterial kommen Keramikbänder, organische Materialien wie Epoxid- Filme und, vor allem, dünne Metallbänder in Frage. Letzere eignen sich besonders gut, da sie eine sehr gute Wärmeleitfähigkeit besitzen, was zumCeramic tapes, organic materials such as epoxy films and, above all, thin metal tapes are suitable as substrate material. The latter are particularly suitable because they have a very good thermal conductivity, which leads to
Abtransport der Verlustleistung der Chips vorteilhaft ist und außerdem sehr gute elektrische Leitfähigkeiten besitzen, was ihren Einsatz als globale Ground- und Abschirmungsebene ermöglicht.Removing the power loss of the chips is advantageous and also have very good electrical conductivities, which enables their use as a global ground and shielding level.
Die dünnen Bandsubstrate werden erfindungsgemäß vorzugsweise mit einer Dicke von weniger als 100 μm gefertigt. Der Aufbau der verschieden Schichten des Leiterbahnsystems nimmt insgesamt etwa 20μm in Anspruch. Bei einem Bandsubstrat aus Metall bestehen grundsätzlich zwei Mögichkeiten der Weiterverarbeitung hinsichtlich eines Leadframes :According to the invention, the thin strip substrates are preferably manufactured with a thickness of less than 100 μm. The structure of the different layers of the interconnect system takes a total of about 20 μm. With a strip substrate made of metal, there are basically two options for further processing with regard to a lead frame:
Einerseits ist es möglich, die strukturierten Metallsubstrate auf ein zusätzliches, übliches Leadframe zu setzen. Andererseits kann im folgenden auch das metallische Bandsubstrat selbst zum Leadframe weiterverarbeitet werden. Dabei bietet es sich an, als Grundmaterialien des Verdrahtungsträgers die in typischen Legierungen vonOn the one hand, it is possible to place the structured metal substrates on an additional, common lead frame. On the other hand, the metallic strip substrate itself can also be further processed into the lead frame below. It makes sense to use the basic materials of the wiring carrier in the typical alloys of
Leadframes verwendeten, also Kupfer oder Eisen zu wählen. Mit einem derartigen „Leadframe- Substrat" als Verdrahtungsträger hat man einerseits die MaterialVorzüge (Moldbarkeit, Verträglichkeit mit dem Silizium- Chip) des Leadframes als Substratträger benutzt und dies andererseits vorteilhaft mit einem sehr dünnen Verdrahtungsträger verbunden. Der bisherige Technologieablauf der Häusungsprozesse wird vollständig beibehalten. Anstelle eines konventionellen Leadframes wird ein Leadframe- Substrat genutzt, anstelle eines Chips auf einem konventionellen Leadframe wird eine Vielzahl von Chips auf dem Leadframe- Substrat plaziert. Ultradünne Module sind folglich möglich.Leadframes used, so choose copper or iron. With such a "leadframe substrate" as a wiring carrier, the material advantages (moldability, compatibility with the silicon chip) of the leadframe have been used as a substrate carrier and, on the other hand, this has advantageously been combined with a very thin wiring carrier. Instead of a conventional leadframe, a leadframe substrate is used, instead of a chip on a conventional leadframe, a large number of chips are placed on the leadframe substrate, which means that ultra-thin modules are possible.
Der bisherige technologische Ablauf ist analog auf die erfindungsgemäße Bandfertigung übertragbar:The previous technological process can be transferred analogously to the strip production according to the invention:
Die Abscheidung der Metall- /Leitungsebenen erfolgt durch Metallisierung von Bändern z.B. mittels Sputtertechnik, gegebenenfalls mit anschließender galvanischer Verstärkung. Die Abscheidung von Isolationsebenen wird realisiert durch den Auftrag von Isolationsmaterial auf das Bandsubstrat, beispielsweise durch Roller Coating, Spray Coating oder durch Extrusion Coating. Die Fotolithographie der Leiter- und Isolationsebenen ist durchführbar durch Belackung von Bandsubstraten, beispielsweise durch Roller Coating, Spray Coating oder Extrusion Coating, anschließendes Belichten und Entwickeln von Bandsubstraten. Auch die bisherigen Naß- Ätzprozesse der Leitungs/Isolationsebenen sind als Bad- Ätzprozesse von Bändern durchführbar. Einzelne Erfahrungen mit Abscheidungs- und Strukturierungsprozessen im Zusammenhang mit Bandfertigung sind bereits aus der Herstellung von Leadframes mit feinen Strukturen ( ca. 65μm) bekannt .The metal / line levels are deposited by metallizing strips, for example using sputtering technology, if necessary with subsequent galvanic reinforcement. The deposition of insulation levels is achieved by applying insulation material to the strip substrate, for example by roller coating, spray coating or by extrusion coating. The photolithography of the conductor and insulation levels can be carried out by coating tape substrates, for example by roller coating, spray coating or extrusion coating, then exposing and developing tape substrates. The previous wet Etching processes of the line / insulation levels can be carried out as bath etching processes of tapes. Individual experiences with deposition and structuring processes in connection with band production are already known from the production of lead frames with fine structures (approx. 65μm).
Erfindungsgemäß resultieren nicht nur qualitativ verbesserte, nämlich extrem dünne Multichipmodule, sondern es wird auch quantitativ ein erheblich verringerter Aufwand in der Substratherstellung erzielt. Durch die Ablösung der Bearbeitung von Einzelscheiben kann sehr leicht und mit viel Kosteneinsparung auf sehr große Wafergrößen mit dementsprechend größerer Anzahl gleichzeitig prozessierbarer Substratträger für ein Multichipmodul übergegangen werden.According to the invention, not only do qualitatively improved, namely extremely thin, multi-chip modules result, but also a significantly reduced outlay in substrate production is achieved quantitatively. By replacing the processing of individual wafers, it is very easy and cost-saving to switch to very large wafer sizes with a correspondingly larger number of simultaneously processable substrate carriers for a multichip module.
Zusätzlich vereinfachen sich die Handling- Systeme extrem, da die Fertigung nunmehr im wesentlichen durch den Transport des Bandsubstrats von Rolle zu Rolle durch eine oder mehrere Fertigungstationen erfolgt.In addition, the handling systems are extremely simplified, since production is now essentially carried out by transporting the strip substrate from roll to roll through one or more production stations.
Das Leiterbahn- und Kontaktsystem auf der Oberseite der Substrate kann in Dünnschichttechnik, Dickschichttechnik oder einer Kombination aus beiden hergestellt werden. The conductor track and contact system on the top of the substrates can be produced using thin-film technology, thick-film technology or a combination of both.

Claims

Patentansprüche claims
1. Verfahren zur Herstellung eines Mehrebenen- Verdrahtungsträgers (Substrat) , insbesondere für Multichipmodule, bei dem das Leiterbahnsystem in mehreren1. A method for producing a multi-level wiring carrier (substrate), in particular for multichip modules, in which the conductor track system in several
Beschichtungs- und Mikrostrukturierungsschritten gleichzeitig auf mehrere EinzelSubstrate aufgebracht wird, die dabei einstückig zusammenhängen und erst nach der Strukturierung vereinzelt werden, dadurch gekennzeichnet, daß die Einzelsubstrate zumindest während der Strukturierung in Form eines Bandsubstrates prozessiert werden.Coating and microstructuring steps are applied simultaneously to several individual substrates, which are connected in one piece and are only separated after the structuring, characterized in that the individual substrates are processed in the form of a tape substrate at least during the structuring.
2. Verfahren nach Anspruch 1 , dadurch gekennzeichnet, daß ein Bandsubstrat aus Metall verwendet wird.2. The method according to claim 1, characterized in that a strip substrate made of metal is used.
3. Verfahren nach Anspruch 2 , dadurch gekennzeichnet , daß aus dem strukturierten Einzelsubstrat selbst anschließend der Leadframe des Multichipmoduls hergestellt wird. 3. The method according to claim 2, characterized in that the lead frame of the multichip module is then produced from the structured individual substrate itself.
PCT/DE1998/002742 1997-09-30 1998-09-16 Method for producing a multilevel cable carrier (substrate), especially for multichip modules WO1999017363A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000514330A JP2001518713A (en) 1997-09-30 1998-09-16 Particularly, a method of manufacturing a multilayer wiring carrier (substrate) for a multichip module
EP98955336A EP1019961A1 (en) 1997-09-30 1998-09-16 Method for producing a multilevel cable carrier (substrate), especially for multichip modules

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19743365.0 1997-09-30
DE1997143365 DE19743365A1 (en) 1997-09-30 1997-09-30 Method for producing a multi-level wiring carrier (substrate), in particular for multichip modules

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WO1999017363A1 true WO1999017363A1 (en) 1999-04-08

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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
DE19830158C2 (en) * 1997-09-30 2001-05-10 Tyco Electronics Logistics Ag Intermediate carrier substrate with high wiring density for electronic components
CN1211723C (en) * 2000-04-04 2005-07-20 胜开科技股份有限公司 Computer card and its making method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621278A (en) * 1981-12-30 1986-11-04 Sanyo Electric Co., Ltd. Composite film, semiconductor device employing the same and method of manufacturing
US4997517A (en) * 1990-01-09 1991-03-05 Olin Corporation Multi-metal layer interconnect tape for tape automated bonding
JPH03270026A (en) * 1990-03-20 1991-12-02 Fujitsu Ltd Manufacture of ic package
EP0469920A1 (en) * 1990-08-03 1992-02-05 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing insulated substrate for semiconductor devices and patterned metal plate used therefor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3619636A1 (en) * 1986-06-11 1987-12-17 Bosch Gmbh Robert Housing for integrated circuits
DE4237080A1 (en) * 1992-11-03 1994-05-11 Hauck Martin Multilayer film integrated circuit for microprocessor chip - has vapour-deposited thin film circuits laid out on flexible strip for rolling with interlayer of insulating material
US5510650A (en) * 1994-09-02 1996-04-23 General Motors Corporation Low mechanical stress, high electrical and thermal conductance semiconductor die mount

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621278A (en) * 1981-12-30 1986-11-04 Sanyo Electric Co., Ltd. Composite film, semiconductor device employing the same and method of manufacturing
US4997517A (en) * 1990-01-09 1991-03-05 Olin Corporation Multi-metal layer interconnect tape for tape automated bonding
JPH03270026A (en) * 1990-03-20 1991-12-02 Fujitsu Ltd Manufacture of ic package
EP0469920A1 (en) * 1990-08-03 1992-02-05 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing insulated substrate for semiconductor devices and patterned metal plate used therefor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 016, no. 084 (E - 1172) 28 February 1992 (1992-02-28) *

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EP1019961A1 (en) 2000-07-19
JP2001518713A (en) 2001-10-16
DE19743365A1 (en) 1999-04-08

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