WO1999016175A1 - Semiconductor integrated circuit and data processing system - Google Patents
Semiconductor integrated circuit and data processing system Download PDFInfo
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- WO1999016175A1 WO1999016175A1 PCT/JP1997/003367 JP9703367W WO9916175A1 WO 1999016175 A1 WO1999016175 A1 WO 1999016175A1 JP 9703367 W JP9703367 W JP 9703367W WO 9916175 A1 WO9916175 A1 WO 9916175A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/47—Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
Definitions
- the present invention relates to a semiconductor integrated circuit including a Galois multiplier used for multiplication on a Galois field, for example, encoding or decoding for error correction using a Read-Solomon code defined using the number of Galois fields. Multiplier used for multiplexing, and recording of CD-R0M (Compact Disc-Read Only Memory), DVD (Digital Video Desc), M0 (Magnet Optics), etc.
- the present invention relates to a technology effective when applied to error correction processing in a data processing system such as a recorded information reproducing apparatus or information recording / reproducing apparatus for a medium, and a satellite communication terminal apparatus. Background art
- a code word capable of correcting a reading error occurring in a recording medium is used in the recording information reproducing device or the information recording / reproducing device.
- a codeword can be defined by a special set of numbers called the Galois field and special operations defined with it. Code error correction is performed by data processing using the number of Galois fields and the above operation.
- the most frequently used codeword is a lead-Solomon code, which is particularly used for an error correction code in a data storage system (data recording system) or a communication system in which errors are easily concentrated in a part.
- Lead-Solomon codes are defined using the number of Galois fields, and encoding or decoding is performed by operations on the Galois field. For this encoding or decoding processing, addition and multiplication on Galois fields are frequently used.
- the set of numbers in the Galois field is defined by a primitive polynomial, and the set of numbers is defined. Multiple types of definitions are possible depending on the underlying polynomial to be defined. At the same time, operations on Galois fields are defined differently depending on the primitive polynomial. At present, different standards are defined for primitive polynomials that define Galois fields used in lead Solomon codes for each medium such as M0 and DVD. Further, in the storage system and communication system, codewords are continuously read or received, and there is a limit to the time allowed for reading or processing of received data including error correction. In other words, processing such as error correction must be performed at high speed without impairing the real-time performance.
- multipliers on Galois fields used for error correction and the like have been composed of hardware dedicated to primitive polynomials conforming to the standard of the system to which the multipliers are applied.
- Galois multiplier dedicated to a particular primitive polynomial cannot be applied to systems using different primitive polynomials. Therefore, in an information recording / reproducing apparatus that can support both MO and DV with different primitive polynomial standards, Galois multipliers must be separately mounted for each of MO and DVD.
- a Galois field is a Galois field in which a finite number of element sets are free to perform the four arithmetic operations and are in a closed configuration.
- the field means a set of elements that can freely perform the four arithmetic operations and its calculation rules.
- a primitive polynomial is defined in the Galois field.
- the Galois number is defined. In other words, a set of numbers that satisfies that the primitive polynomial is zero is a Galois field.
- Error correction is performed by performing arithmetic operations on Galois numbers.
- the error correction process uses the error correction code on the transmitting side (recording side) and the receiving side (reproducing side; Error correction decoding. Error correction is achieved by combining code and decoding.
- the four basic arithmetic operations of the most basic Galois field GF (p) will be described.
- mod p is used for the elements of 0, 1, 2,.
- mod is an abbreviation for modulo (remainder)
- p is a prime number.
- addition and multiplication by the mod p algorithm are performed as usual, and if the result is greater than or equal to P, the remainder can be obtained by dividing by P.
- the X means X 2 1 / a: a- 1 mod p. This X is called the multiplicative inverse of a, and is expressed as a- 1 . Division by a is the multiplication of a by the multiplicative inverse a- 1 .
- the Galois field GF (p) is a further development of the Galois field GF (2 m ).
- the Galois field GF (2) there are two types of elements, 0 and 1, between which the four arithmetic operations are performed. I did it.
- the Galois field GF (2 m ) In the Galois field GF (2 m ), on the other hand, there are 2 m elements, and the four arithmetic operations can be performed freely between those elements.
- the 2 m elements can be represented by m-dimensional vectors on GF (2) or polynomials of degree m ⁇ 1 or less on GF (2). The former is called vector display, and the latter is called polynomial display.
- the vector representation can be considered as a coefficient of each order in a polynomial.
- the addition between the elements of the Galois field GF (2 m ) is defined by the addition of vectors (addition of polynomials). That is, the addition of the vector elements (coefficients of the same order of the polynomial). However, the elements or coefficients are elements of GF (2). The addition may be performed by mod 2 calculation. The same applies to subtraction.
- the multiplication between the elements of the Galois field GF (2 m ) is usually performed by polynomial multiplication, and when the result is equal to or higher than the highest degree of the primitive polynomial, the result is divided by the primitive polynomial, and the remainder is the result.
- the result can be obtained by multiplying by a * x.
- the addition between the elements of the Galois field GF (2 m ) is the addition of the coefficients of the same order of the polynomial, and the coefficients are elements of GF (2).
- the calculation of mod 2 may be performed.
- the multiplication between the elements of the Galois field GF (2 m ) after performing a polynomial multiplication as usual, if the result exceeds the highest order of the primitive polynomial, divide by the primitive polynomial, and the remainder is the result. I just need.
- the addition of coefficients of the same order in multiplication may be performed by the calculation of mod 2 as described above.
- error correction uses a numerical system called the Galois field, and frequently performs operations mainly on multiplication and addition.
- this numerical system four arithmetic operations are defined for a set of numbers, and the number of results of the four arithmetic operations is included in the original set of numbers.
- moths lower number of defined operations 4 bits Bok Galois field GF (2 4).
- a primitive polynomial is defined, and the Galois number is defined as the root of the primitive polynomial.
- 4 bits Bok moth lower body GF (2 4) In the following two primitive polynomials exist.
- Equation 1 primitive polynomial 1: x 4 + x 1 ⁇ 1
- Equation 2 the primitive polynomial 2: x + x 3 + 1
- a set of numbers that satisfies that the above primitive polynomial is a Zeguchi is a Gaguchi field.
- the number of Galois fields can be represented by a polynomial as described above, and in the 4-bit Galois field GF (2 4 )
- multiplication differs from ordinary multiplication in that the result of multiplication differs depending on the primitive polynomial of the Galois field GF (2 4 ).
- Fig. 37 shows a Galois field for the primitive polynomial 1
- Fig. 38 shows a Galois field for the primitive polynomial 2.
- the Galois field GF (2 4 ) is expressed by showing the coefficients of x 3 , X 2 , X 1 , and x ° for each element.
- the conventional hardwired Galois multiplier employs, for example, a method in which the above equation is directly constituted by a logic circuit.
- the dedicated hardware multiplier forms the logic shown in FIG. 31 by the dedicated logic circuit shown in FIG.
- the multiplication of the element X 2 of GF (2 3 ) in the above polynomial expression and x + 1 is performed by a power expression.
- FIG. 33 shows an example of a Galois multiplier, which is not publicly known, for performing multiplication in a power expression using a ROM.
- the vector representation data corresponding to the Galois numbers ⁇ ⁇ and m is decoded by the first and second Galois number decoding logic.
- exponents (power numbers) n and m of Galois numbers according to the decoding result by the first and second Galois number decoding logic are stored in advance. The exponent is read from the first and second R ⁇ M according to the decoding result.
- the exponents n and m read from both ROMs are added, and the addition result is encoded by the encoder.
- the third R receiving the output of the encoder stores the Galois number according to the value of the exponent + n and the vector representation data of m + n in advance, and the Galois number according to the result of the encoding.
- the vector representation of am + n is output.
- the Galois multiplier shown in Fig. 33 which employs the power multiplication method, must have several types of ROMs, so the circuit size of the Galois multiplier becomes large.
- the OM when used, if the primitive polynomial changes, the stored data of R0M may be rewritten accordingly, but as the number of bits N in the Galois field increases, the R ⁇ M capacity becomes 2 N times increase, circuit rule There are more and more models.
- the primitive polynomials when applied to different primitive polynomials,
- the present invention has been made in view of the above circumstances, and has a semiconductor integrated circuit including a Galois multiplier that has a smaller circuit size than that using a ROM and enables multiplication using a plurality of different primitive polynomials.
- Another object of the present invention is applied to an information recording system, an information communication system, and the like, which can reduce a circuit scale for performing error correction on a plurality of types of information using codewords related to a plurality of different primitive polynomials.
- a data processing system To provide a data processing system.
- a semiconductor integrated circuit includes a Galois multiplier used for Galois multiplication between elements of a Galois field GF ( 2n ), wherein the Galois multiplier is a Galois field GF (2 n ), the original coefficient of the Galois field GF (2 n ), which is the multiplicand, and the coefficient of a primitive polynomial.
- the same hardware is used for primitive polynomials.
- the Galois multiplier is provided with coefficient setting means for giving a primitive polynomial coefficient of the Galois field GF ( 2n ).
- the Galois multiplier can perform multiplication on the Galois field in accordance with the primitive polynomial given from the coefficient setting means. Therefore, the semiconductor integrated circuit can be generally used for encoding or decoding of an error correction code or the like based on different Galois fields defined for each primitive polynomial.
- the coefficient setting means stores the coefficients of the primitive polynomial in a rewritable manner, and It may be storage means such as a register for outputting the stored coefficients of the primitive polynomial to the Galois multiplier. Further, the coefficient setting unit may be a unit such as a ROM that stores a plurality of types of primitive polynomial coefficients and outputs a coefficient selected from the stored coefficients to the Galois multiplier.
- the Galois multiplier includes a partial product adder and a correction term adder, and the partial product adder performs partial product addition of a multiplier coefficient and a multiplicand coefficient for each partial product of the multiplier and the multiplicand.
- the correction term adding unit can be configured to perform an operation of correcting the coefficient of the partial product of order n + 1 or more obtained by the partial product adding unit to the coefficient of the partial product of order n or less.
- the coefficients of the primitive polynomial are set in advance by the coefficient setting means.
- the correction term addition unit has previously input the coefficients of the primitive polynomial set in advance in such a manner, and can immediately perform the correction operation by inputting the partial product addition result by the partial product addition unit.
- the correction term addition unit calculates correction information for correcting the coefficient of the partial product of n + 1 or higher order obtained by the partial product addition unit to the coefficient of the partial product of nth or lower order by using a primitive polynomial.
- a first logical operation circuit that calculates in advance based on the coefficient; and a second logic operation circuit that obtains, for each coefficient of the n + 1 or higher order partial product obtained by the partial product addition unit, a product of the coefficient and the corresponding correction information. It can be composed of two logical operation circuits and a third logical operation circuit that adds the outputs of the respective second logical operation circuits.
- the correction term adder uses a method to reduce the order of the higher-order terms, performing partial product operations of the coefficients of the primitive polynomial and the coefficients of the multiplier and the multiplicand. A configuration in which the order is reduced every time can be adopted.
- the correction term adder that realizes this is provided with an array of n unit circuits of n-1 columns, the order of the unit circuits in the column direction is from 1 to 2 n-2, and the array of the first column is n The order is 2 n-2, the n-th array in the second column is the order 2 n— 3, and the order is reduced sequentially.
- the n-th array in the n-th column is the n-th order. .
- the unit circuit of each column of the array receives, as a common input for each column, a first Galois sum of the output of the uppermost unit circuit of the array of the preceding column and the value of the partial product addition corresponding thereto, and A logical product is generated by receiving the input and a coefficient of a primitive polynomial commonly input to the unit circuits of each column, and a second logical product of the value of the logical product and the output of the unit circuit at the same order position in the preceding column is obtained. It has a function to generate Galois sums and output them.
- Each of the unit circuits in the first column is supplied with the value of the order 2 n ⁇ 1, which is the highest order of partial product addition, as the common input, and generates an output without generating the second Galois sum. I do.
- the unit circuits of the second column and the lower array are used as the common input as the first Galois sum of the output of the uppermost unit circuit of the immediately preceding array and the corresponding partial product addition value. Receives and produces output. Then, the outputs of the n unit circuits in the n_1st column are output as the correction term additions.
- the Galois sum of the output of the correction term addition and the lower n bits of the partial product addition is used as the multiplication result.
- the correction term adder which further speeds up the arithmetic processing by the correction term adder, includes an array of n unit circuits in n-1 columns, and the order of the unit circuits in the column direction is 1 to 2 n ⁇ 2.
- the n-th array has the order 2 n—2
- the n-th array has the order 2 n— 3.
- the n-th array has the degree n.
- Unit circuits of order n + 1 or higher in each column of the array receive the value of the partial product addition at the corresponding bit position as a common input for each array, and are input to this common input and the unit circuit in each column.
- Generates a product by receiving the signal obtained by decoding the coefficients of the n-bit primitive polynomial And a function of generating and outputting the first Galois sum of the output from the unit circuit at the same order position in the front row and the product, and among the unit circuits of the order n + 1 or more in each column, the array
- the output of the unit circuit at the uppermost position generates a second Galois sum with the corresponding partial product addition value.
- a unit circuit of order n or less in each column of the array receives the second Galois sum as a common input, and calculates the common input and a corresponding coefficient of a primitive polynomial input to the unit circuit of each column.
- a third Galois sum of the output from the unit circuit at the same order position in the front row and the product is output.
- the unit circuit in the first column receives the value of the highest order 2 n-1 1 of partial product addition as a common input for the order n + 1 or more and the order n or less and generates an output.
- the unit circuit in the second column or less In this case, the input common to the order n + 1 or more is the corresponding partial product addition value, and the input common to the order n or less is the corresponding value of the second Galois sum in the unit circuits in the second column and below.
- You. n — The output of the n unit circuits in the first column is the output of the correction term addition.
- the Galois sum of the output of the correction term addition and the lower n bits of the partial product addition is used as the multiplication result.
- Decoding logic that decodes the coefficients of n-bit primitive polynomials simplifies the logic of generating correction information based on partial product addition results of degree n + 1 or more and coefficients of primitive polynomials, and reduces the number of gate series stages. Less.
- the correction term adder can be configured by omitting hardware relating to an order whose coefficient is commonly set to zero among a plurality of primitive polynomials.
- the primitive polynomials corresponding to it are limited to several types.At this time, in the order where the coefficient is always zero in all primitive polynomials, Hardware can be omitted. This promotes faster arithmetic processing by reducing the number of gate series stages.
- the partial product adder calculates the Galois sum of adjacent two bits of the multiplier as n ⁇ 1 bits. , And further decodes every two consecutive bits of the multiplicand to generate four outputs for every two bits.
- the number of columns of the partial product is set to 1/2, and each column of the partial product is output.
- the input of the bit position has four inputs: a bit value of an adjacent multiplier, a Galois sum of two adjacent bits of the multiplier, and zero, and selects an input based on the four outputs decoded as described above.
- the Galois sum of the selected input and the partial product of the front row can be output to the back row as an output. Even with such a configuration in which partial product addition is performed by the selector method, the number of gate series stages in the signal path can be reduced, and high-speed arithmetic processing is realized.
- the data processing system includes a Galois multiplier used for Galois multiplication between elements of a Galois field GF ( 2n ), and setting means for enabling a primitive polynomial of the Galois multiplier to be reset.
- the Galois multiplier, and the original coefficients of the Galois field GF (2 n) which is the number of multiplication, and the original coefficients of the Galois field GF (2 n) which is the multiplicand, and a coefficient of a primitive polynomial The input and the calculation of the coefficients for obtaining the Galois multiplication result are performed on the same hardware for a plurality of different primitive polynomials.
- the coefficients of the primitive polynomial may be provided from the setting means.
- the setting means may be configured to determine a primitive polynomial to be set in accordance with an operation state of a selection switch.
- Another data processing system includes a recognizing unit that recognizes the type of the information recording medium, an access unit that can access a plurality of types of information recording media, and a recording unit that reads the recording information read from the information recording medium by the access unit.
- Error correction circuit used for error correction.
- the Galois multiplier is used for Galois multiplication between the original and the original Galois field GF (2 n), and the original coefficients of the Galois field GF (2 n) which is a multiplier, is the multiplicand
- the original coefficients of the Galois field GF (2 n ) and the coefficients of the primitive polynomial are input, and the calculation of the coefficients for obtaining the result of the Galois multiplication is the same for a plurality of different primitive polynomials. This is done with one hardware.
- the primitive polynomial coefficient may be determined according to the result of recognition of the type of the information recording medium by the recognition means.
- either of the recording media is used for reproducing the recorded information and for recording the information.
- the Galois multiplier can also be used in common for the body, which contributes to the miniaturization of the system.
- Still another data processing system includes control means for decoding a fetched instruction to generate a control signal, arithmetic means controlled by the control signal, and interface means for interfacing the arithmetic means with the outside.
- the arithmetic means includes a Galois multiplier used for Galois multiplication between elements of the Galois field GF (2 n ), and the Galois multiplier is a Galois field GF (2 n ), The original coefficient of the Galois field GF (2 n ), which is the multiplicand, and the coefficient of the primitive polynomial, and the calculation of the coefficient to obtain the Galois multiplication result is performed by a plurality of different primitives.
- a Galois multiplier that performs the same hardware with respect to the polynomial may be included, and a coefficient of the primitive polynomial may be determined by control of the control unit.
- This data processing system can be configured as a microprocessor formed on a single semiconductor substrate.
- Fig. 1 is an explanatory diagram conceptually showing a Galois multiplier that enables multiplication of multiple types of primitive polynomials with the same hardware.
- Fig. 2 is an explanatory diagram showing the first calculation example of partial product addition and correction term addition
- Fig. 3 is a Galois multiplier realized by dividing the logic shown in the calculation example of Fig. 2 into a partial product and a correction term.
- Example logic circuit diagram Fig. 4 is an explanatory diagram showing a second calculation example of partial product addition and correction term addition
- Fig. 5 is a Galois multiplier that realizes the logic shown in the calculation example of Fig. 4 by dividing it into a partial product and a correction term.
- Fig. 6 is an explanatory diagram showing a third calculation example of partial product addition and correction term addition
- Fig. 7 is a Galois multiplier that implements the logic shown in the calculation example of Fig. 6 by dividing it into a partial product and a correction term.
- FIG. 8 is an explanatory diagram showing a calculation example of a partial product adding a complement Seiko addition in the case of considering that the coefficients C 2 both primitive polynomial in X 2 is zero at the primitive polynomial of the two there quartic ,
- Fig. 9 is an example logic circuit diagram of a Galois multiplier realized by dividing the logic shown in the calculation example of Fig. 8 into partial products and correction terms,
- FIG. 10 is an example logic circuit diagram of a Galois multiplier when the logic of FIGS. 6 and 7 is applied to an 8-bit Galois field
- FIG. 11 is a logic circuit diagram of an example of a Galois multiplier which is further speeded up from the configuration of FIG. 10,
- Fig. 12 is an explanatory diagram that functionally shows the configuration of a Galois multiplier that performs Galois multiplication by dividing into the partial product addition and the correction term addition specifically shown in Fig. 3, etc.
- Fig. 13 is the correction term.
- Explanatory diagram functionally showing the configuration of a Galois multiplier that decodes the coefficients of a primitive polynomial in an adder in advance and supplies the decoded data to a correction term adder.
- FIG. 14 is an explanatory diagram specifically showing the configurations of the correction term adder and the decoder when the 4-bit circuit configuration of FIG. 7 is expanded to the decoding system of FIG.
- FIG. 15 is an explanatory diagram showing an example of expansion of a correction term using the decoder of FIG. 14,
- Fig. 16 shows the case where the decoding method is applied to an 8-bit Galois multiplier.
- FIG. 17 is an explanatory diagram showing an example of expansion of a correction term using the decoder of FIG. 16,
- FIG. 18 is an explanatory diagram functionally showing a Galois multiplier in which a decoder is provided for both the input of the partial product addition unit and the input of the correction term addition unit to further speed up the processing;
- FIG. 19 is an explanatory diagram logically showing a configuration based on a selector system for further accelerating the arithmetic processing in the partial product addition unit.
- FIG. 20 is a logic circuit diagram of a partial product adder when the selector method shown in FIG. 19 is applied to a 4-bit Galois multiplier.
- FIG. 21 is a circuit diagram of an example of a first selector applied to the partial product adder of FIG. 20,
- FIG. 22 is a circuit diagram of an example of a second selector applied to the partial product adder of FIG. 20,
- FIG. 23 is a logic circuit diagram of the partial product adder when the selector system of FIGS. 19 and 20 is extended to an 8-bit Galois multiplier,
- FIG. 24 is a flow chart showing an example of the read'Solomon error correction decoding process
- FIG. 25 is a schematic diagram showing the internal configuration of each of the circuits for the Sindom operation, the leak operation and the Chien search. Block diagram shown,
- FIG. 26 is a block diagram of a processor for performing the read 'Solomon error correction decoding process shown in FIG. 24,
- Fig. 27 is a block diagram of an example of a data processing system that records or reproduces information on storage media such as DVDs.
- Figure 28 is an example block diagram of a data processing system used for communication systems such as satellite broadcasting.
- FIG. 29 is an explanatory diagram showing an example of multiplication calculation of a Galois number represented by a polynomial expression.
- FIG. 30 is an explanatory diagram showing a calculation example when a numerical value is inserted in the coefficient of each order of the multiplier and the multiplicand and the Galois number is multiplied,
- FIG. 33 is a block diagram showing an example of a Galois multiplier circuit based on the R0M method.
- Fig. 34 is an explanatory diagram of a communication system model that employs Galois field error correction.
- Fig. 35 is an explanatory diagram of a storage model that adopts error correction by Galois field
- FIG. 36 is an explanatory diagram showing elements of the Galois field GF (2 3 ),
- Fig. 37 is an explanatory diagram showing the elements of the Galois field GF (2 4 ) in the case of the primitive polynomial X 4 + X 1 + 1,
- Fig. 38 is an explanatory diagram showing the elements of the Galois field GF (2 4 ) in the case of the primitive polynomial X 4 + X 3 + 1,
- FIG Galois field GF explanatory view showing an example of a base click Bokuru representation and polynomial representation of the original, (2 4)
- 4 0 is an explanatory diagram showing an example of a polynomial representation preparative base key representation of the original Galois field GF (2 4).
- FIG. 1 shows an example of a semiconductor integrated circuit according to the present invention.
- the semiconductor integrated circuit 1 shown in FIG. 1 includes a Galois multiplier 2 and a coefficient It includes the setting means 3 and is formed on one semiconductor substrate such as single crystal silicon, for example, by a known CMOS integrated circuit manufacturing technique.
- the Galois multiplier 2 and the coefficient setting means 3 are used for Galois multiplication between elements of the Galois field GF ( 2n ).
- the Galois multiplier 2, and the original coefficients of the Galois field GF that is a multiplier (2 n) (n bits) 4, the original coefficients of the multiplicand and is Ru Galois field GF (2 n) (n bits) 5 and the coefficient (n bits) 6 of the primitive polynomial are input, and the operation of the coefficient for obtaining the Galois multiplication result is performed for a plurality of different primitive polynomials with the same hardware.
- the coefficient setting means 3 is a circuit that provides the Galois multiplier 2 with the coefficients of the primitive polynomial of the Galois field GF (2 ".
- the coefficient setting unit 3 may be a storage unit such as a register that stores the coefficients of the primitive polynomial in a rewritable manner and outputs the stored coefficients of the primitive polynomial to the Galois multiplier 2. Further, the coefficient setting means 3 may be a means such as a ROM which stores a plurality of types of primitive polynomial coefficients and outputs a coefficient selected from the stored coefficients to the Galois multiplier 2.
- the coefficient setting of the primitive polynomial or the coefficient selection of the primitive polynomial for the coefficient setting means 3 can be given from inside the semiconductor integrated circuit 1 via a signal line 7 or from outside the semiconductor integrated circuit via a signal line 8.
- the Galois multiplier 2 can perform multiplication on the Galois field according to the coefficients of the primitive polynomial given from the coefficient setting means 3. Therefore, the semiconductor integrated circuit 1 can be generally used for encoding or decoding of an error correction code or the like using a different Galois field defined for each primitive polynomial. Even when the semiconductor integrated circuit 1 is applied to a system for, for example, MO or DVD, it is not necessary to redesign the Galois multiplier.
- the single semiconductor integrated circuit 1 can be used for encoding and decoding error correction codes for both M0 and DVD.
- the circuit size of the Galois multiplier required for the entire system is about 1 unit for the former. / N, and the more primitive polynomials that need to be supported, the greater the effect of circuit scale reduction.
- Equation 21 The meaning of the above (Equation 21) will be clear from the above, but it is further added that Using the general form of the primitive polynomial of (Equation 17), the higher-order terms x 6 , X 5 , and X 4 of the partial product obtained by the equation multiplication are calculated using the lower-order terms X 3 , X 2 , It is replaced with X 1 and X 0 .
- the calculation formula shown in the column of correction term addition in FIG. 2 is a formula in which the higher-order terms X 6 , x 5 , and X 4 are replaced with lower-order terms X 3 , x 2 , x 1 , and x °. is there.
- correction term added to operations for such replacement the correction term was collected using cowpea in addition low-order sections x 3, x 2, X 1 , x ° is referred to as a correction term.
- a polynomial multiplication of two Galois numbers is called partial product addition, and each term obtained by that is called a partial product.
- Equation 21 in order to multiply the Galois number for general purpose, the coefficient c of the primitive polynomial of (Equation 21) is used.
- ⁇ c 3 by setting the coefficient of the necessary primitive polynomial multiplication result for any primitive polynomial is obtained, et al.
- a value that is a coefficient of each order of (Equation 21) is set in advance c. Leave obtained by logical operation between ⁇ c 3, Ri by the setting these values, the multiplication result for any primitive polynomial is obtained.
- FIG. 3 shows a specific example of the Galois multiplier 2 having the logic according to the above method.
- the Galois multiplier 2 includes a partial product adder 11, a correction term adder 12, and an output adder 13.
- the partial product adder 11 performs partial product addition of a multiplier coefficient and a multiplicand coefficient for each partial product of the Galois field GF (2 n ) and the multiplicand.
- the logic shown in the column of partial product addition in FIG. 2 is realized as it is.
- the correction term addition unit 12 performs an operation of correcting the coefficient of the ⁇ + 1 or higher order partial product obtained by the partial product addition unit 11 into the coefficient of the nth order or lower partial product.
- the logic shown in the column of correction term addition in FIG. 2 is realized as it is.
- the output adder 13 is a Galois sum of the output of the correction term adder 12 and the lower n-bit partial product coefficient of the partial product adder 11 (similar to the addition process for a 2-bit Galois field) To Calculate. Specifically, the outputs ⁇ 0 to ⁇ 3 are obtained by adding the coefficients of the corresponding orders by exclusive OR.
- the multiplication between the elements of the Galois field GF (2 n ) is defined by addition of a polynomial, and the coefficients of the polynomial are elements of GF (2). Since the calculation can be performed, the partial product addition unit 11, the correction term addition unit 12, and the addition output unit 13 are configured by using an AND gate and an exclusive OR gate (ex OR). ing.
- the correction term adding section 12 can be classified into first to third logical operation circuits.
- the first logical operation circuit converts the correction information for correcting the coefficient of the partial product of order n + 1 or higher obtained by the partial product adder 11 into the coefficient of the partial product of order n or less into the coefficient c of the primitive polynomial. 3 to c.
- This is a logic circuit that calculates in advance on the basis of, and is composed of gate rows 12G and 12E.
- the second logic operation circuit is a logic circuit that takes, for each coefficient of the n + 1 or higher-order partial product obtained by the partial product addition unit 11, a product of the coefficient and the corresponding correction information, It is composed of gate rows 12B, 12D, and 12F.
- the third logical operation circuit is a logical circuit for adding the outputs of the respective second logical operation circuits, and is constituted by gate arrays 12A and 12C.
- the output of the first logical operation circuit constituted by the gate trains 12 G and 12 E has the coefficients C 3 to C of the primitive polynomial.
- the result of the correction term addition operation can be immediately obtained by inputting the result of the partial product addition by the partial product addition unit.
- the number of gates used in the configuration of Fig. 3 is 25 for the partial product adder 11, 11 for the correction term adder 12, and 4 for the output adder 13. 64 AND elements and exOR are required.
- the circled numbers indicate the signal transmission of each of eXOR and the AND element.
- the critical path is a path for obtaining the output bit Bok o 3.
- the outputs of the first logical operation circuit composed of the gate arrays 12 G and 12 E are the primitive polynomial coefficients C 3 to C 3 .
- the transmission time until the output of the gate train 12F is determined is set to 2.
- FIG. 5 shows a correction term adder 14 that realizes the logic described in the column of correction term addition in FIG.
- the arrangement of the exclusive OR gate and the AND gate is more regular than that in FIG. Therefore, the layout design of the semiconductor integrated circuit in FIG. 5 can be easier than that in FIG.
- the first logic circuit is constituted by gate rows 14G and 14E.
- the second logical operation circuit is constituted by gate rows 14B, 14D, and 14F.
- the third logical operation circuit is constituted by gate rows 14A and 14C.
- the number of gates used in the configuration of FIG. 5 is the same as that of FIG. 3 for the partial product adder 11 and the output adder 13, but the correction term adder 12 has 39 In this case, 68 AND elements and exOR are required as a whole.
- the circled numbers indicate the required transmission time from the input to the point where the number is given, assuming that the signal transmission time of each of eXOR and the AD element is 1. means.
- Critical paths are the paths for output bit Bok o 3. Therefore, the Galois multiplier shown in FIG. 5 is not substantially different from the configuration in FIG. 3 in terms of the operation speed, but is superior in the layout of the correction term adder 14 as described above. I have.
- the two examples of the Galois multiplier are based on a method of replacing the higher-order terms X 6 , ⁇ 5 , and X 4 with lower-order terms x 3 , x 2 , x 1 , and x ° as coefficients of a primitive polynomial c n
- the calculation of the multiplier and the multiplicand coefficients an and b n I did it.
- the coefficients c n and the multiplier of the primitive polynomial and the coefficients a n and b n of the multiplicand are calculated successively.
- the unit circuit in each column of the array is an exclusive OR gate (e X) of the output of the uppermost unit circuit of the array in the preceding column and the corresponding partial product addition value as a common input for each column.
- e X exclusive OR gate
- an AND gate is generated by the AND gate 15 C, and an exclusive OR gate (eXOR) 1 of the value of the AND and the output of the unit circuit at the same order position in the front row is generated. It has a function to generate Galois sum by 5D and output it.
- the unit circuits in the first column have the common input
- the unit circuits of the second column and lower arrays are the exclusive OR of the output of the uppermost unit circuit of the immediately preceding array and the corresponding partial product addition value as the common input.
- Gate (ex OR) Generates output by receiving Galois sum by 15B. The lowest unit circuit of each array does not have the exclusive OR gate 15D.
- the force correction term adder 15 is composed of 20 gates. This is realized by 49 AND elements and exOR. Also, in FIG. 7, the numbers enclosed by circles are, as described above, the distance from the input to the point where the number is attached when the signal transmission time of each of the eXOR and the AND element is set to 1. Means the required transmission time.
- the critical path is a path for obtaining the output bit Bok o 3, that time has become ⁇ length than the fifth FIG. Therefore, the Galois multiplier shown in FIG. 7 is inferior to the configuration of FIG. 5 in terms of operation speed, but is much better in terms of the layout of the correction term adder 15.
- the Galois multipliers described so far are based on the number of bits in the multiplier and multiplicand.
- the logic was constructed using the general formula as shown in the above (Equation 17) which does not limit the primitive polynomial at all.
- Bok Gallo ⁇ body GF (2 4) are known to be two types, there is a waste in the logical structure of the primitive polynomial and complete formula. Therefore, if the primitive polynomial is limited to the extent that it can be used, some order coefficients may always be zero, which may make the hardware of the correction term adder for those coefficients inefficient. It can be partially omitted, and it becomes possible to configure a Gaa multiplier with a small logical scale.
- FIG. 8 in the general form of the primitive polynomial (Equation 17), when assuming a case coefficients c 2 of degree X 2 is zero, the logic of the correction term addition portion of the auxiliary Seiko addition field Is shown in FIG. 9 shows a configuration of the correction term adder 16 that realizes the logic.
- FIG. 9 shows, as an example, a structure obtained by further developing the configuration of FIG. 7, but also for the configurations of FIGS. 2 and 3, and FIGS. 4 and 5, c It is possible to omit the logic related to 2 and make the same improvement as above.
- FIG. 10 shows an example of a Galois multiplier in which the logical configuration of FIGS. 6 and 7 is extended to multiplication of an 8-bit Galois number.
- the partial product adder 11X and the correction term adder 15X both use the same unit circuit 19.
- the unit circuit 19 is an AND gate 17 which takes a logical product of the inputs P and A, and an exclusive logic is provided for the output of the AND gate and the input B.
- GD is the ground potential of the circuit and supplies a signal with a logical value of "0".
- a Galois multiplier can be realized by a very regular gate arrangement.
- the circled numbers mean the required transmission time from the input to the point marked with the number, assuming that the signal transmission time of each of eXOR and the AND element is 1. I do.
- Critical path is a path for obtaining the output bit o 7.
- FIG. 11 shows an embodiment for increasing the speed of the embodiment of FIG.
- the delay time until the multiplication output is obtained is relatively long.
- the correction term adder 15 X employs a configuration in which the order is reduced successively and linearly while calculating the coefficient c n of the primitive polynomial and the multipliers a n and b n of the multiplicand.
- a signal which is commonly applied to the output of the uppermost unit circuit 19 of the array via the exclusive OR gate 15B is provided to the next unit circuit 19.
- the speed of the drive input signal D k (k 2 2 to 8) of each column in the correction term adder 15 Y is increased.o
- the drive input signal Dk of each column is obtained by exclusive-ORing the drive input signal Dk-1 of the previous array with the AND gate 17 of the unit circuit 1.9. — Formed through gate 18 and exclusive OR gate 15B. In Fig. 11, such an exclusive OR gate 15B has been abolished. Assuming that the signal transmission time in each of the AND gate 17 and the exclusive OR gate 18 is 1 as shown in FIG.
- FIG. 10 the delay time between the signal Dk and the signal Dk-1 is 2 Becomes To shorten this, Figure 11 shows that the C7 signal in each column is Receiving unit circuit 19 A, 19 B and unit circuit 19 B, 19 A in the final array of correction term addition Combining exclusive OR circuit 18 A, 18 C with selector circuit 18 B
- the exclusive OR circuit 13A for receiving the Kn and Zn signals in FIG. 10 and the exclusive OR circuit 15B in FIG. 10 are omitted.
- the selection signal of the selector circuit 18B is a drive input signal Dk of each column.
- the unit circuit 19 A receiving the signals C 7 and D 8 and the unit circuit 19 A receiving the signals C 0 and D 2 select the exclusive OR circuit 18 A and its one input and output It is composed of a selector circuit 18B.
- a unit circuit 18B that receives the signal C7 and other Dk signals and outputs Z2 to Z8 in the last column is a unit circuit 19B, which is an exclusive OR circuit 18A and one of its inputs.
- the signal is output through an exclusive OR circuit 18C that takes the exclusive OR of the output of the selector circuit 18B and the output from the front row. .
- the transmission time of the selector circuit 18B is faster than that of an AND gate or an exclusive OR circuit, and the transmission time is about 0.5, so that signal transmission can be performed. Therefore, the delay time between the signal Dk and the signal Dk-1 in this embodiment is 0.5, C7 and other Dk signals in the unit circuit 19A receiving the signals C7 and D8.
- the receiving unit circuit 19 B is 1.5.
- the total delay time until obtaining the multiplication output is 13 and it is possible to speed up by 38% compared to the delay time 2 1 in Fig. 10.
- the Galois multipliers described so far have a small number of ⁇ and a partial product adder 1 1 (1 1 X) and a correction term adder 1 2 (1 4, 15, 1). 6, 15X, 15Y), and when the correction term adding section does not have an output adding function, an output adding section 13 (13X) is further provided.
- FIG. 13 shows an example of a Galois multiplier that can supply the coefficients of a primitive polynomial via a decoder. That is, a decoder 20 that decodes the primitive polynomial and supplies the decoded result to the correction term adder 21 is added.
- FIG. 14 shows an example of the decoder 20 and the correction term adder 21 shown in FIG. FIG. 14 shows the configuration when a decoder is added to the configuration of FIG.
- an example is shown in which the correction term adder 21 is applied to Galois multiplication of a Galois field GF (2 n ), in particular, a 4-bit Galois number in the case of n24.
- the n-th order is the order n (2 4).
- the exclusive OR circuit 21D receives the output from the unit circuit 21B at the position and the product and generates and outputs a first Galois sum, and the order n of each column is provided.
- the output of the unit circuit 2 1 B at the highest position in the array is exclusive with the corresponding partial product addition values G 3 and G 2
- the second Galois sum is generated by the OR circuit 21E.
- the unit circuit 21A having an order n or less of each column of the array receives the second Galois sum as a common input, and receives the common input and the unit circuit 21A of each column.
- a product is generated by an AND gate 21F, and an exclusive logic is generated by receiving the output from the unit circuit 21A at the same order position in the front row and the product. It has the function of generating and outputting the third Galois sum by the sum circuit 21G.
- the value (G 4 ) of the highest order 2 n ⁇ 1 of partial product addition is input as a common input for the order n + 1 or more and the order n or less, and an output is generated.
- the input common to the order n + 1 or more is the corresponding partial product addition value (G 3 ).
- the input common to the order n or less is Is the third Galois sum output from the corresponding exclusive OR circuit 21E.
- the Galois sum with the bit is the result of the multiplication.
- FIG. 15 shows the differences between the signal logic of nodes D 2 , D 3 and D 4 in FIG. 7 and the signal logic of the same nodes D 2 , D 3 and D 4 in FIG. .
- the value of the node D 3 depends on the value of the node D 4 in the preceding stage, and the value of the node D 2 is in the preceding stage. It depends on the values of the nodes D 3 and D 4 .
- the value of the node D 3 does not depend on the value of the preceding node D 4 but the value of the node D 2 Is a logical configuration that does not depend on the values of the preceding nodes D 3 and D 4 .
- Relationship after deployment of the first 5 diagrams are those from the right side expression of more substitution method was erased D 3, D 4.
- the values of the nodes D 2 and D 3 of the correction term adder 21 are theoretically the values of the nodes at the subsequent stage. It will be appreciated that it has no time effect on the confirmation. Therefore, the Galois multiplier employing the correction term adder 21 and the decoder 20 shown in FIG. The calculation processing can be performed at a higher speed than in the figure. That is, the critical path output Z 4 signal transmission time of the correction term addition unit 2 1 is a 7, are shorter than 8 in the case of Figure 7.
- the numbers with circles have the same meaning as described above.
- FIG. 16 shows an example in which a decoder 22 is employed for the configuration of the correction term adder of FIG.
- the first 7 Figure differs from the signal logic of the same node D 2 ⁇ D 8 of the signal logic and the first 4 view of nodes D 2 to D 8 of the first 0 diagram is shown.
- the Gaa multiplier employing the correction term adder 23 and the decoder 22 shown in FIG. 16 can realize a higher speed of the arithmetic processing as compared with FIG. That is, during the time of signal transmission of the output Z 8 of the critical path in the correction term addition unit 2 3 is a 11, is reduced to about half of the 20 in the case of the first 0 FIG.
- the circled numbers have the same meaning as described above.
- FIG. 18 shows a block diagram of a Galois multiplier in which the partial product adder and the correction term adder are further speeded up.
- the n-bit multiplicand is decoded by the decoder 30 and supplied to the partial product adder 31.
- the output of the partial product adder 31 is decoded by the decoder 26.
- To the correction term adder 25 To the correction term adder 25.
- FIG. 19 shows the logical configuration of the partial product adder 31 corresponding to the configuration of FIG.
- the coefficient of the partial product of Xa * Xb is calculated for each degree by b. , T ⁇ , organized in b 2 J b 3.
- the coefficients in column (2) are selected according to the decoding results of the coefficients b 3 and b 2 of the multiplicand x 3 and X 2 , and the coefficients in column (1) are similarly calculated by the multiplicand X 1 , x ° coefficient bb. Select according to the decoding result of. Before that, the manner of selection in each of columns (1) and (2) is shown in column (3) of FIG.
- FIG. 20 shows an example of the decoder 30 and the partial product adder 31 that specifically realize the logic of FIG. Decoder 30 is multiplicand b. , B 1 , b 2) Convert each bit of b 3 into inverted and non-inverted signals.
- the partial product adder 31 has two arrays of selectors 32, 33, 33, 33, 33, 32, and the selector of each array is in accordance with the logic in the column (3) in FIG. Select input.
- FIG. 21 An example of the selector 32 is shown in FIG. 21 and an example of the selector 33 is shown in FIG.
- the circled numbers shown in Fig. 20 indicate that the signal transmission time of each of the exclusive OR gate and AND gate is 1 and that the signal transmission time of Imba overnight is 0.5, from the input to that point. This shows the signal transmission delay time.
- the transmission time to the output K 4 in the partial product addition unit 11 in FIG. 7 is 4, and the signal transmission time to the output ⁇ 4 can be reduced to 3 in the configuration of FIG. This reduction rate of the transmission time becomes more remarkable when the number of bits of the multiplier and the multiplicand (the number of bits of the Galois number) is increased.
- the second 3 when applying 8 to the partial-product addition unit 3 first Galois multiplier which candidate operation Galois number of bits Bok FIG. 20 of the configuration shown in FIG.,
- the first 0 in the structure of kappa 8 The delay time until the output is obtained is 8, but it can be reduced to ((about half (5/8)). In other words, the processing speed of partial product addition is about twice as fast.
- the decoder 30 performs decoding in units of two bits, and the selectors 32, 33, 33, 33, 33, 33, 33, 33, 33, 33 There are provided four rows of 33 and 32 arrays.
- the actual logic in FIG. 23 can be easily understood by referring to the logic in FIG. 19, and is not shown. ⁇ Error correction by lidoso-Romon code ⁇
- FIG. 24 shows an example of a typical flow chart of the error correction processing using the Reed-Solomon code.
- the error correction processing flow is as follows: Syndrome operation (S 1), input operation (Euclidean algorithm) S 2, Chien search (error position search) S 3, error value calculation S for input data 4 and correction S5.
- the syndrome operation S 1 calculates a coefficient of a syndrome polynomial using a series of received codes as inputs. Here, if the coefficients of the syndrome polynomial are all zero, it is understood that there is no error in the received code. If it is determined that there is no error, the processing after S2 is omitted and the processing ends. If you find an error, start the correction process.
- an error locator polynomial and an error numerical polynomial are calculated from the syndrome polynomial by a step operation S2.
- the position of the error and the number of errors are obtained.
- the numerical value of the error is calculated based on the position (S 4), the error is corrected S 5, and the process is terminated.
- the Reed-Solomon code is defined using the number of Galois fields, and the above-described addition and multiplication on the Galois field are frequently used in the processing of the syndrome operation S1, the Euclidean operation S2, and the Chien search S3. Is done.
- the Galois multiplier can be used for such multiplication.
- FIG. 25 is a block diagram showing an example of a circuit for performing a syndrome operation, a leak operation, and a Chien search.
- Each circuit block is provided with two Galois multipliers 40 and an adder 41.
- the Galois multiplier 40 has any configuration described with reference to FIGS. 1 to 24.
- the circuits for performing the syndrome operation, the Euclidean operation, and the Chien search have their own hardware and are configured as one semiconductor integrated circuit.
- Primitive polynomials are commonly given to the respective Galois multipliers 40 from the coefficient setting means 3.
- X a and X b are a multiplier and a multiplicand. Therefore, when different primitive polynomials are set in different systems, the coefficients of the primitive polynomial can be set arbitrarily.
- FIG 26 shows a block diagram of an example of a microphone processor specialized in error correction using the read'Solomon code.
- the microprocessor 50 shown in the figure includes a program memory 55 storing an operation program of the microprocessor 50, and a control unit 5 which decodes an instruction fetched from the program memory 55 and generates a control signal. 1, an operation unit 52 controlled by the control signal, an interface unit 53 for interfacing the operation unit 52 with the outside, and a memory unit 54 used as a work area of the operation unit 52 And a single semiconductor substrate such as single crystal silicon.
- the operation unit 52 has a Galois multiplier 56, an adder 57, a register 58, and the like.
- the Galois multiplier 5 6 is used for Galois multiplication between the elements of the Galois field GF (2 n ), and the Galois field GF (the coefficient of the two elements and the Galois field GF).
- the original coefficient of (2 n ) and the coefficient of primitive polynomial are input, and the calculation of the coefficient for obtaining the Galois multiplication result is performed on a plurality of different primitive polynomials by the same hardware. It has any of the configurations described in Fig. 1 to Fig. 24.
- the coefficients of the primitive polynomial are provided from the control unit 51 according to a program, for example.
- the microprocessor 50 executes, for example, the syndrome calculation, the Euclidean calculation, and the Chien search in accordance with the operation program stored in the program memory 55. That is, Sof Twe The functions equivalent to those in Fig. 25 are realized by the software.
- FIG. 27 is a block diagram of a disk drive system used for recording information on a storage medium and reproducing recorded information.
- the storage media handled by the disk drive system shown in the figure is not particularly limited, but is both the MO and DVD media 60.
- the medium 60 is driven to rotate by the disk drive 61.
- the pickup section 62 includes a pickup for M0 and a pickup for DVD, and includes an actuator for focusing and tracking.
- the servo control of the pickup is performed by the servo circuit 64.
- the information read from the pickup is amplified by the preamplifier 63, the high-frequency signal is given to the encoding / decoding processing section 67, and the servo error signals for tracking and intelligent focusing are sent to the servo circuit 64. Given to.
- the write signal to the medium 60 is supplied from the encoding / decoding processing section 67 to the pickup section 62 via the driver 65.
- the control unit 66 is interfaced with a host system (not shown), and controls the entire disk drive system.
- the encoding / decoding processing unit 67 is interfaced with a host system (not shown), and decodes information read from the medium 60 and encodes information to be written to the medium 60.
- a parity for error correction is generated. Error correction is performed in decoding. Error correction at the time of decoding is performed by the error correction unit 68.
- the error correction unit 68 includes any one of the Galois multipliers described with reference to FIGS.
- the error correction processing unit 68 uses a primitive polynomial selected from a plurality of types of primitive polynomials.
- the error correction processing section 68 can be constituted by the microprocessor 50 or the like.
- the servo circuit 64 performs servo control according to the type of medium. Servo circuit 64 is used to recognize the type of medium. First, at the beginning of the training period, a tracking and focusing servo for M0 is performed. Since the depth of focus and the track pitch differ depending on the type of the medium 60, the tracking and focusing servo errors actually exceed the allowable range when a DVD is mounted.
- the servo circuit 64 When detecting this state, the servo circuit 64 recognizes that the mounted medium is a DVD. If the servo error is within the allowable range, the mounted medium is recognized as MO. In this sense, the servo circuit 64 in the system shown in FIG. 27 is an example of a medium recognizing means.
- the medium recognition result by the servo circuit 64 is given to the selector 69 as an automatic switching signal 71.
- the selector 69 is supplied with a manual switching signal 72 via the switch 70.
- the selector 69 selects either the automatic switching signal 71 or the manual switching signal 72 according to the operation mode of the system.
- the selected switching signal selects a primitive polynomial to be supplied to the error correction processing unit 68.
- Primitive polynomial is normalized to the MO, an x 8 + x 5 + x 3 + x 2 + 1, primitive polynomial that is standardized on a DVD, x 8 + x 4 + x 3 + x 2 + Is one.
- the switching signal 73 selected by the selector 69 indicates ⁇
- the former primitive polynomial is supplied to the error correction processor 68
- the latter primitive polynomial is supplied to the error correction processor 68.
- FIG. 28 shows a block diagram of a satellite broadcast receiving apparatus used for reproducing information from broadcast media.
- the broadcast media handled by the satellite broadcast receiving apparatus shown in the figure is not particularly limited, but broadcasts A and A from representative broadcast stations 80 and 81 are shown.
- Broadcast A, ⁇ uses geostationary satellite 82 It can be received by the satellite-side transmitting / receiving device 89.
- the satellite transmission / reception device 89 receives the broadcasts A and B with the tuner 83.
- the broadcast to be received by the tuner 83 can be selected by the switch 84.
- the video signal and the audio signal received by the tuner 83 are encoded by the encoding processing unit 85, subjected to error correction, and given to the image forming unit 88 for reproduction.
- Error correction at the time of decoding is performed by the error correction processing unit 86.
- the error correction processing unit 86 includes any one of the Galois multipliers described with reference to FIGS. 1 to 24, and performs error correction using the read-Solomon code using the Galois multiplier and the adder. Do.
- the error correction processing unit 86 uses a primitive polynomial selected from a plurality of types of primitive polynomials.
- the error correction processing unit 86 can be constituted by the microprocessor 50 or the like.
- the selection of the primitive polynomial is synchronized with the tuning by the switch 84.
- the primitive polynomial used for each broadcasting station is different. Therefore, by switching the switch 84 for switching the broadcast by the receiver, the error correction can be performed using the same Galois multiplier on the same system even in the broadcast with different primitive polynomials.
- the number of Galois bits to be multiplied is not limited to 4 bits or 8 bits, but may be other values.
- the location is not limited to MO or DVD, but may be another medium such as CD-ROM.
- the present invention provides a Galois multiplier and a CD-ROM used for encoding or decoding a Reed-Solomon code defined using the number of Galois fields.
- a Galois multiplier and a CD-ROM used for encoding or decoding a Reed-Solomon code defined using the number of Galois fields.
- Error correction processing in a recording information reproduction device or information recording / reproduction device for recording media such as DVD (Digital Video Disc M0 (Magnet Optics)
- a data processing system such as a satellite communication terminal
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Abstract
A semiconductor integrated circuit including a Galois multiplier which enables multiplication using a plurality of different primitive polynominals. The semiconductor integrated circuit (1) includes a Galois multiplier (2) which is used for Galois multiplication of the elements of a Galois field GF(2n). The coefficients (5, 4) of the elements of the Galois field GF(2n) which are the multiplier and the multiplicand and the coefficients (6) of the primitive polynominals are inputted to the Galois multiplier. The coefficients are arithmetically operated for different primitive polynominals with the same hardware to obtain Galois multiplication results. A coefficient setting means (3) which supplies the coefficients of the primitive polynominals of the Galois field GF(2n) is provided. With this constitution, the Galois multiplier can perform multiplication on the Galois field corresponding to the primitive polynominals supplied by the coefficient setting means. The semiconductor integrated circuit, therefore, can be versatilely applied to encoding or decoding of the error correction codes of the different Galois fields which are defined for the different primitive polynominals respectively.
Description
明 細 書 半導体集積回路及びデ一タ処理システム Description: Semiconductor integrated circuit and data processing system
技術分野 Technical field
本発明は、ガロア体上の乗算に利用されるガロア乗算器を含む半導体 集積回路に係り、例えば、ガロア体の数を用いて定義されたリー ドソロ モン符号による誤り訂正のための符号化又は復号化に用いられるガ口 ァ乗算器、 更には、 C D— R 0 M (Compact Di sc-Read Onl y Memory)、 D V D ( Di gi tal Vi deo Di sc) , M 0 (Magnet Opti cs)などの記録媒体に 対する記録情報再生装置若しくは情報記録再生装置、さらには衛星通信 端末装置などのデータ処理システムにおける誤り訂正処理に適用して 有効な技術に関するものである。 背景技術 The present invention relates to a semiconductor integrated circuit including a Galois multiplier used for multiplication on a Galois field, for example, encoding or decoding for error correction using a Read-Solomon code defined using the number of Galois fields. Multiplier used for multiplexing, and recording of CD-R0M (Compact Disc-Read Only Memory), DVD (Digital Video Desc), M0 (Magnet Optics), etc. The present invention relates to a technology effective when applied to error correction processing in a data processing system such as a recorded information reproducing apparatus or information recording / reproducing apparatus for a medium, and a satellite communication terminal apparatus. Background art
例えば前記記録情報再生装置若しくは情報記録再生装置には、記録媒 体で生じた読み出しの誤りを訂正できる符号語が用いられている。符号 語は、 ガロア体と呼ばれる特殊な数の集合と、 それと共に定義された特 殊な演算によって定義することができる。符号の誤り訂正は、ガロア体 の数と上記演算を用いたデータ処理によって行われる。最も多用されて いる符号語にはリ一 ドソロモン符号があり、特に誤りがー部に集中しや すいデータ蓄積系(データ記録系)又は通信系の誤り訂正符号に用いら れている。 リー ドソロモン符号は、ガロア体の数を用いて定義されてお り、 ガロア体上の演算によって符号化又は復号化処理が行われる。 この 符号化又は復号化の処理にはガロア体上の加算や乗算が多用される。 For example, a code word capable of correcting a reading error occurring in a recording medium is used in the recording information reproducing device or the information recording / reproducing device. A codeword can be defined by a special set of numbers called the Galois field and special operations defined with it. Code error correction is performed by data processing using the number of Galois fields and the above operation. The most frequently used codeword is a lead-Solomon code, which is particularly used for an error correction code in a data storage system (data recording system) or a communication system in which errors are easily concentrated in a part. Lead-Solomon codes are defined using the number of Galois fields, and encoding or decoding is performed by operations on the Galois field. For this encoding or decoding processing, addition and multiplication on Galois fields are frequently used.
ここで、ガロア体の数の集合は原始多項式で定義され、数の集合を定
義する基礎となる多項式によって、複数種類の定義が可能である。同時 に、ガロア体上の演算も原始多項式によって異なる定義がなされる。現 在、リ一 ドソロモン符号で用いられるガロア体を定義する原始多項式は、 M 0や D V Dなどの媒体毎に別々の規格が定められている。 また、蓄積 系、通信系では符号語が連続的に読み出し又は受信されており、誤り訂 正を含む読み取り又は受信データに対する処理に許される時間には制 限がある。換言すれば、 リアルタイム性を損なうことなく高速に誤り訂 正などの処理を行わなければならない。 Here, the set of numbers in the Galois field is defined by a primitive polynomial, and the set of numbers is defined. Multiple types of definitions are possible depending on the underlying polynomial to be defined. At the same time, operations on Galois fields are defined differently depending on the primitive polynomial. At present, different standards are defined for primitive polynomials that define Galois fields used in lead Solomon codes for each medium such as M0 and DVD. Further, in the storage system and communication system, codewords are continuously read or received, and there is a limit to the time allowed for reading or processing of received data including error correction. In other words, processing such as error correction must be performed at high speed without impairing the real-time performance.
このため、従来は、誤り訂正などに用いられるガロア体上の乗算器な どは、これが適用されるシステムの規格に適合した原始多項式に対して 専用化されたハ一 ドウエアで構成されていた。 For this reason, conventionally, multipliers on Galois fields used for error correction and the like have been composed of hardware dedicated to primitive polynomials conforming to the standard of the system to which the multipliers are applied.
しかしながら、特定の原始多項式に専用化されたガロア乗算器は、異 なる原始多項式を用いたシステムには適用できない。 したがって、原始 多項式の規格が異なる M Oと D V Dの双方に対応できる情報記録再生 装置においては、 M Oと D V Dのそれぞれに対して別々にガロア乗算器 を搭載しなければならない。 However, a Galois multiplier dedicated to a particular primitive polynomial cannot be applied to systems using different primitive polynomials. Therefore, in an information recording / reproducing apparatus that can support both MO and DV with different primitive polynomial standards, Galois multipliers must be separately mounted for each of MO and DVD.
尚、リ— ドソロモン符号を用いた誤り訂正について記載された文献の 例として、 特開平 5— 2 6 8 1 0 1号公報、 電子情報通信学会論文誌 A Vo1 . J73-A No .2 PP261〜268 ( 1990年 2月) 「光ディスク用誤り訂正 LSIj がある。 As examples of documents describing error correction using a lead-Solomon code, see Japanese Patent Application Laid-Open No. 5-268011, IEICE Transactions on Electronics, Information and Communication Engineers A Vo1. J73-A No. 2 PP261- 268 (February 1990) "There is an error correction LSIj for optical disks.
ここで、本明細書による以下の記述の理解を容易化するために、ガ口 ァ体及びガロア乗算について基本的な事項を予め説明する。 Here, in order to facilitate understanding of the following description according to the present specification, basic matters regarding the Gabor field and the Galois multiplication will be described in advance.
有限個の元の集合で四則演算が自由に行えて、その集合の中で閉じて いる構成になっているものをガロア体(Gal oi s Fi el d )と言う。体とは、 四則演算が自由に行える元の集まりとその計算規則という意味である。 また、 ガロア体では、 原始多項式が定義され、 この原始多項式の根とし
てガロア数が定義される。いいかえれば原始多項式がゼロになることを 満足するような数の集合がガロア体である。 A Galois field is a Galois field in which a finite number of element sets are free to perform the four arithmetic operations and are in a closed configuration. The field means a set of elements that can freely perform the four arithmetic operations and its calculation rules. In the Galois field, a primitive polynomial is defined. The Galois number is defined. In other words, a set of numbers that satisfies that the primitive polynomial is zero is a Galois field.
誤り訂正は、 ガロア数を四則演算して行われる。誤り訂正処理には、 通信系のモデルを示す第 3 4図、蓄積系のモデルを示す第 3 5図のよう に、送信側(記録側)での誤り訂正符号と受信側(再生側;)での誤り訂正復 号がある。誤り訂正は、符号と復号を組み合わせて成り立つものである。 最も基本的なガロア体 GF( p )の四則演算を説明する。ガロア体 GF(p) では、 0 , 1 , 2, · ■ · P- 1の元に対して mod p の計算法を使う。 ここ での mod は、 modulo (剰余)の略であり、 pは素数である。 Error correction is performed by performing arithmetic operations on Galois numbers. As shown in Fig. 34 showing the model of the communication system and Fig. 35 showing the model of the storage system, the error correction process uses the error correction code on the transmitting side (recording side) and the receiving side (reproducing side; Error correction decoding. Error correction is achieved by combining code and decoding. The four basic arithmetic operations of the most basic Galois field GF (p) will be described. In the Galois field GF (p), mod p is used for the elements of 0, 1, 2,. Here, mod is an abbreviation for modulo (remainder), and p is a prime number.
例えば mod p の算法で行う加算、 乗算は、 普通に計算を行い、 結果 が P以上になったら Pで割って余りを結果とすればよい。 For example, addition and multiplication by the mod p algorithm are performed as usual, and if the result is greater than or equal to P, the remainder can be obtained by dividing by P.
減算は、 0から p-1 までの元 a, bに対して、 a — b = a — b + p mod P( Pを加えても pの剰余は 0である。 )のように適当に pを加算して普 通に計算し、 さらに pで割って余りを採る。 The subtraction is performed appropriately for elements a and b from 0 to p-1 such that a — b = a — b + p mod P (the remainder of p is 0 even if P is added.) , Calculate as usual, and divide by p to get the remainder.
除算は、 以下のように行う。 mod Pの除算においては、 0以外の任意 の元 a に対して、 a * x = 1 mod ρ となる元 x が存在する。 本明細 書中において記号 *は積を意味する。 前記 X は、 X 二 1/a : a—1 mod p を意味する。 当該 X を a の乗法逆元といい、 a—1と表す。 a による割り 算は、 a の乗法逆元 a—1を乗ずることである。 Division is performed as follows. In the division of mod P, for any element other than 0, there is an element x such that a * x = 1 mod ρ. In this specification, the symbol * means a product. The X means X 2 1 / a: a- 1 mod p. This X is called the multiplicative inverse of a, and is expressed as a- 1 . Division by a is the multiplication of a by the multiplicative inverse a- 1 .
例えば、 ガロア体 GF(2) mod2 での加算の例を示すと、 1+0=1 mod 2 、 For example, in the case of addition in the Galois field GF (2) mod2, 1 + 0 = 1 mod2,
1+1=0 mod2 となり、 これは e x O R ( Exclusive OR:排他的論理和) で 演算することができる。 また、 ガロア体 GF(2) mod 2 での乗算の例を 示すと、 1 · 0=0 mod 2 、 1 · 1=1 mod2 となり、 これは A N D (論理積) で演算することができる。 1 + 1 = 0 mod2, which can be calculated by exOR (Exclusive OR). In addition, when an example of the multiplication in the Galois field GF (2) mod 2 is shown, 1 · 0 = 0 mod 2 and 1 · 1 = 1 mod2, which can be calculated by AND (logical product).
ガロア体 GF(p)を更に発展させたものにガロア体 GF(2 m)がある。 前 記ガロア体 GF(2)では、 0と 1 の 2種類の元がありその間で四則演算が
行えた。 これに対してガロア体 GF(2m)では、 2m個の元があり、 その元 の間で自由に四則演算が行える。 2m個の元は、 GF(2)上の m次元べク 卜 ルまたは GF(2)上の m— 1 次以下の多項式で表すことができる。前者を べク トル表示、 後者を多項式表示と言う。 ガロア体 GF(2)上のべク トル や多項式でガロア体 GF(2 m)の元を表現すことができるので、 GF(2 m) を GF(2)の拡大体もと言う。 例えばガロア体 GF(2 3)の元は第 3 6図の ように 23 = 8個ある。 べク 卜ル表現は、 多項式での各次数の係数と考 えることができる。 The Galois field GF (p) is a further development of the Galois field GF (2 m ). In the Galois field GF (2), there are two types of elements, 0 and 1, between which the four arithmetic operations are performed. I did it. In the Galois field GF (2 m ), on the other hand, there are 2 m elements, and the four arithmetic operations can be performed freely between those elements. The 2 m elements can be represented by m-dimensional vectors on GF (2) or polynomials of degree m−1 or less on GF (2). The former is called vector display, and the latter is called polynomial display. Since the elements of the Galois field GF (2 m ) can be expressed by vectors and polynomials on the Galois field GF (2), GF (2 m ) is called an extension field of GF (2). For example, there are 2 3 = 8 elements in the Galois field GF (2 3 ) as shown in Fig. 36. The vector representation can be considered as a coefficient of each order in a polynomial.
そして、 ガロア体 GF(2 m)の元 0〜x i ( i =0,1,2,3 · . )に対して mod x 3 + x + 1 を計算した場合、 その解が周期的に繰り返される。 このときの mod の多項式(x 3 + x + 1 )を原始多項式という。 これは、 どのような高次の多項式であっても mod X 3 + X + 1 で計算すれば第 3 6図又は第 3 9図の A 部に示されるような元の集合にもどることに なる。例えば第 3 6図の元で四則演算を行った場合も、演算結果はその 元の集合内で閉じることになる。例えば、元が 4ビッ 卜のガロア体 GF(2 4)にあっては、 原始多項式が 2種類有ることが知られている。 元が 8 ビッ 卜のガロア体 GF(28)にあっては、 原始多項式が 1 6通り有ること が知られている。 原始多項式に応じて元の集合は異なる。 Then, when mod x 3 + x + 1 is calculated for the elements 0 to xi (i = 0, 1, 2, 3,..) Of the Galois field GF (2 m ), the solution is repeated periodically. . The polynomial (x 3 + x + 1) of mod at this time is called a primitive polynomial. This means that any higher-order polynomial, if calculated with mod X 3 + X + 1, will return to the original set as shown in part A of Figure 36 or Figure 39 . For example, if the four arithmetic operations are performed under the conditions in Fig. 36, the operation results will be closed within the original set. For example, it is known that there are two primitive polynomials in the Galois field GF (2 4 ) whose element is 4 bits. It is known that there are 16 primitive polynomials in the 8-bit Galois field GF (2 8 ). The original set differs depending on the primitive polynomial.
前記ガロア体 GF(2m)の元の間の加算は、べク トル表示の加算(多項式 の加算)で定義する。 つまりべク トルの要素(多項式の同じ次数の係数) の加算である。 ただし、 要素あるいは係数は GF(2)の元である。 その加 算は mod 2の計算で行えばよい。 減算も同様である。 The addition between the elements of the Galois field GF (2 m ) is defined by the addition of vectors (addition of polynomials). That is, the addition of the vector elements (coefficients of the same order of the polynomial). However, the elements or coefficients are elements of GF (2). The addition may be performed by mod 2 calculation. The same applies to subtraction.
前記ガロア体 GF(2 m)の元の間の乗算は、 普通に多項式乗算を行い、 その結果が原始多項式の最高次数以上になったら原始多項式で割り算 をして、 その余りを結果とする。 除算は、 0以外の任意の元 a、 b に対 して a/bを行う場合、 b*x = 1 となる X ( = 1 /b ) をユークリッ ド
互除法を用いて求め、 Xが求まったら、 a*xで乗算を行って結果を得 ることができる。 The multiplication between the elements of the Galois field GF (2 m ) is usually performed by polynomial multiplication, and when the result is equal to or higher than the highest degree of the primitive polynomial, the result is divided by the primitive polynomial, and the remainder is the result. When a / b is performed on any element a or b other than 0, the division is X (= 1 / b) where b * x = 1. When X is found using the algorithm, the result can be obtained by multiplying by a * x.
ここで、 ガロア体 G F ( 23) mod x 3 + x + 1 での加算と乗算の例 を示す。 加算の例をべク トル表示で示すと、 G F ( 23)の元(0 1 0 )と (0 1 1 )の加算は、 (0 1 0 ) + (0 1 1 ) = (00 1 )とされる。 1 + 1 二 0、 1 + 0二 1 だからである。加算の例を多項式表示で示すと、 G F (23)の元 Xと x+1 の加算は、 Here, an example of addition and multiplication in the Galois field GF (2 3 ) mod x 3 + x + 1 is shown. If an example of addition is shown in vector display, the addition of the element (0 1 0) and (0 1 1) of GF (2 3 ) is (0 1 0) + (0 1 1) = (00 1) It is said. 1 + 1 2 0, 1 + 0 2 1 To show an example of addition in polynomial notation, the addition of the element X and x + 1 in GF (2 3 ) is
x+x + 1 =x ( 1 + 1 )+1 =1 mod(x 3 + x + 1 )とされる。 x + x + 1 = x ( 1 + 1) are +1 = 1 mod (x 3 + x + 1).
乗算の例を多項式表示で示すと、 G F ( 23)の元 2と +1 の乗算 は、 By way of example of a multiplication by a polynomial, then the original 2 and the multiplication of +1 GF (2 3), the
X 2*(χ+1 ) =χ 3 + χ 2=(χ + 1 )+χ 2 (V χ 3=-(χ + 1 )=χ + 1 ) X 2 * (χ + 1) = χ 3 + χ 2 = ( χ + 1) + χ 2 (V χ 3 =-(χ + 1) = χ + 1)
二 χ 2 + χ + 1 mod ( χ 3 + χ + 1 ) 2 χ 2 + χ + 1 mod (χ 3 + χ + 1)
とされる。 この乗算結果から明らかなように、乗算結果には、 原始多項 式よりも次数の高いものは存在しない。 It is said. As is clear from the multiplication result, there is no multiplication result having a higher order than the primitive polynomial.
以上の説明から理解されるように、 前記ガロア体 GF(2 m)の元の間の 加算は、 多項式の同じ次数の係数の加算であり、 その係数は GF(2)の元 であるから、 同じ次数の係数加算では mod 2の計算を行えばよい。 前記 ガロア体 GF(2 m)の元の間の乗算は普通に多項式乗算を行った後、 その 結果が原始多項式の最高次数以上になつたら原始多項式で割り算をし て、 その余りを結果とすればよい。乗算における同じ次数の係数の加算 に対しては上記の通り mod 2の計算で行えばよい。 As can be understood from the above description, the addition between the elements of the Galois field GF (2 m ) is the addition of the coefficients of the same order of the polynomial, and the coefficients are elements of GF (2). For addition of coefficients of the same order, the calculation of mod 2 may be performed. In the multiplication between the elements of the Galois field GF (2 m ), after performing a polynomial multiplication as usual, if the result exceeds the highest order of the primitive polynomial, divide by the primitive polynomial, and the remainder is the result. I just need. The addition of coefficients of the same order in multiplication may be performed by the calculation of mod 2 as described above.
ここで更に、 4 ビッ 卜のガロア体 GF(2 4)を例として、 元の間の乗算 について詳述する。 Here, the multiplication between elements will be described in detail by taking a 4-bit Galois field GF (2 4 ) as an example.
エラー訂正では前述の通りガロア体と呼ばれる数値体系を用い、乗算 と加算を中心にした演算を頻繁に行う。 この数値体系では、ある数の集 合に対し四則演算が定義され、四則演算の結果の数は元の数の集合に含
まれるという特徴がある。 ここでは、 4 ビッ 卜のガロア体 GF(2 4)のガ ロア数の定義と演算について述べる。ガロア体では、原始多項式が定義 され、 この原始多項式の根としてガロア数が定義される。 4ビッ 卜のガ ロア体 GF(24 )では以下の 2個の原始多項式が存在する。 As described above, error correction uses a numerical system called the Galois field, and frequently performs operations mainly on multiplication and addition. In this numerical system, four arithmetic operations are defined for a set of numbers, and the number of results of the four arithmetic operations is included in the original set of numbers. There is a feature that you can wear. Here, we describe moths lower number of defined operations 4 bits Bok Galois field GF (2 4). In the Galois field, a primitive polynomial is defined, and the Galois number is defined as the root of the primitive polynomial. 4 bits Bok moth lower body GF (2 4) In the following two primitive polynomials exist.
(式 1) 原始多項式 1 : x4+ x1† 1 (Equation 1) primitive polynomial 1: x 4 + x 1 † 1
(式 2) 原始多項式 2 : x+ x3+ 1 (Equation 2) the primitive polynomial 2: x + x 3 + 1
上記原始多項式がゼ口になることを満足するような数の集合がガ口ァ 体である。 A set of numbers that satisfies that the above primitive polynomial is a Zeguchi is a Gaguchi field.
ガロア体の数は前述のように多項式表現でき、 4ビッ 卜のガロア体 GF(24)では The number of Galois fields can be represented by a polynomial as described above, and in the 4-bit Galois field GF (2 4 )
(式 3) Xa = a3x3+ a2x2+ a,x1+ a0x° (Equation 3) Xa = a 3 x 3 + a 2 x 2 + a, x 1 + a 0 x °
と表現することができる。 ただし、 xQ=1、 anは 0又は 1と表現される。 加算は Can be expressed as However, x Q = 1, a n is expressed as 0 or 1. Addition is
(式 4) Xa = a3x3+ a2x2+ a x a0x° (Equation 4) Xa = a 3 x 3 + a 2 x 2 + axa 0 x °
(式 5) Xb = b3x3+ b2x2+ b,x,+ b0x° (Equation 5) Xb = b 3 x 3 + b 2 x 2 + b, x, + b 0 x °
として As
(式 6) Xa+Xb = (a3+ b3) x3+(a2+ b2) x2+(a,+ b,) x'+(a0i b。) x° となる。 ここで、 The (Equation 6) Xa + Xb = (a 3 + b 3) x 3 + (a 2 + b 2) x 2 + (a, + b,) x '+ (a 0 ib.) X °. here,
(式 7) (a3, a2, a,, a0) = ( 1, 0, 1, 0 ) (Equation 7) (a 3 , a 2 , a, a 0 ) = (1, 0, 1, 0)
(式 8) (b3, b2, b,, b0) 二 ( 0, 1, 1, 1 ) (Equation 8) (b 3 , b 2 , b ,, b 0 ) 2 (0, 1, 1, 1)
とすると、 上式の a„、 bnに対するガロア体の加算の定義は以下に示す ように Then, the definition of addition of Galois field to a „and b n in the above equation is as shown below.
0 + 0 = 0, 0 + 1 = 1, 0 + 0 = 0, 0 + 1 = 1,
1 + 0 = 1, 1 + 1 = 0 1 + 0 = 1, 1 + 1 = 0
の e x O Rであるから、 Since it is e x OR of
(式 9) Xa+Xb = (1 + 0) x3+(0 + 1) x2+(1 + 1) x1+(0 + 1) x°
= x3+ x2+ x° (Equation 9) Xa + Xb = (1 + 0) x 3 + (0 + 1) x 2 + (1 + 1) x 1 + (0 + 1) x ° = x 3 + x 2 + x °
二 x3+ x2+ 1 2 x 3 + x 2 + 1
となる。 Becomes
—方、 乗算は通常の乗算と違い、 ガロア体 G F (2 4)の原始多項式に よって乗算結果が異なる。 —On the other hand, multiplication differs from ordinary multiplication in that the result of multiplication differs depending on the primitive polynomial of the Galois field GF (2 4 ).
上記のガロア数 Xa、 Xbの乗算は The above multiplication of Galois numbers Xa and Xb is
(式 10) Xa * Xb = (a3b3) x6+(a3b2+a2b3)
x4 (Equation 10) Xa * Xb = (a 3 b 3 ) x 6 + (a 3 b 2 + a 2 b 3 ) x 4
+(a3b。+a2bl+a1b2+a。b3) x3+(a2b0+a1b1+a0b2) x2 +( a^o+aobj x' + (a。b。) x° + (a 3 b. + a 2 b l + a 1 b 2 + a.b 3 ) x 3 + (a 2 b 0 + a 1 b 1 + a 0 b 2 ) x 2 + (a ^ o + aobj x '+ (a.b.) x °
となる (第 2 9図参照)。 ここで、 (See Fig. 29). here,
(a3) aつ a a。 = ( 1, 0, 1 , 0 ) (a 3) One aa. = (1, 0, 1, 0)
(b3, b2, b b0) = ( 0, 1, 1】 1 ) (b 3 , b 2 , bb 0 ) = (0, 1, 1) 1)
とすると、 Then
(式 11) Xa * Xb = (1*0) x6+(1*1+0*0) x5+(1*1+0*1+1*0) x4 (Equation 11) Xa * Xb = (1 * 0) x 6 + (1 * 1 + 0 * 0) x 5 + (1 * 1 + 0 * 1 + 1 * 0) x 4
+(1*1+0*1+1*1+0*0) x3+(0*1 + 1*1+0*1 ) x2 + (1 * 1 + 0 * 1 + 1 * 1 + 0 * 0) x 3 + (0 * 1 + 1 * 1 + 0 * 1) x 2
+( 1*1+0*1) x1 + (0*1) x° + (1 * 1 + 0 * 1) x 1 + (0 * 1) x °
となる。 上式の a n、 b nに対するガロア体の乗算の定義は以下に示す ように Becomes The definition of the Galois field multiplication of a n and b n in the above equation is as follows:
0 * 0 = 0, 0 * 1 = 0, 0 * 0 = 0, 0 * 1 = 0,
1 * 0 = 0, 1 * 1 = 1 1 * 0 = 0, 1 * 1 = 1
の A N Dであるから、 Because of A N D
(式 12) Xa * Xb =χ5+χ4+χ2+χ1 (Equation 12) Xa * Xb = χ 5 + χ4 + χ 2 + χ 1
となる (第 3 0図参照)。 ここで、 原始多項式 1 を採用した場合には、 (式 13) x4+ x1i 1= 0 または X4 = x1+ 1 (See Figure 30). Here, when primitive polynomial 1 is adopted, (Equation 13) x 4 + x 1 i 1 = 0 or X 4 = x 1 + 1
であるから、 Because
(式 M) Xa * Xb = x4 x1 + x4 + x2 + x1
二 (x'+ 1) x1† (x1+ 1)+x2+ x1 (Formula M) Xa * Xb = x 4 x 1 + x 4 + x 2 + x 1 Two (x '+ 1) x 1 † (x 1 + 1) + x 2 + x 1
= x2+ x'+ x1+ 1+ x2 + x1 = x 2 + x '+ x 1 + 1+ x 2 + x 1
二 x1+ 1 Two x 1 + 1
となる。 Becomes
一方原始多項式 2を採用した場合には、 On the other hand, when primitive polynomial 2 is adopted,
(式 15) x + x3+ 1= 0 または X4 = x3+ 1 (Equation 15) x + x 3 + 1 = 0 or X 4 = x 3 + 1
であるから、 Because
(式 16) Xa * Xb = x4x1+x4+x2+ x1 (Equation 16) Xa * Xb = x 4 x 1 + x 4 + x 2 + x 1
: (x3+ 1 ) x1+ (x3+ 1 )+x2+ x1 : (X 3 + 1) x 1 + (x 3 + 1) + x 2 + x 1
= x4+ x1+ x3+ 1+ x2 + x1 = x 4 + x 1 + x 3 + 1 + x 2 + x 1
= (x3+ 1 )+ x1+ x3+ 1+ x2 + x1 = (x 3 + 1) + x 1 + x 3 + 1 + x 2 + x 1
二 X2 Two X 2
となる。 Becomes
このように、 採用する原始多項式によって乗算結果は異なる。 第 37図に は原始多項式 1の場合のガロア体が示され、 第 38図には原始多項式 2の場 合のガロア体が示される。 第 37図及び第 38図では、 元毎に、 x 3, X 2 , X 1 , x °の係数を示して、 ガロア体 G F(24)を表現している。 As described above, the multiplication result differs depending on the primitive polynomial employed. Fig. 37 shows a Galois field for the primitive polynomial 1, and Fig. 38 shows a Galois field for the primitive polynomial 2. In FIGS. 37 and 38, the Galois field GF (2 4 ) is expressed by showing the coefficients of x 3 , X 2 , X 1 , and x ° for each element.
4ビッ 卜のガロア体 G F(2 4)では、 上記 2種類の原始多項式が存在 し、 どの原始多項式を採用するかはシステムによって任意である。 この ため、従来の専用ハ— ドワイヤー ドのガロア乗算器の構成では異なるシ ステムに同一のガロア乗算器を用いることができない。従来は、 システ ム毎に(異なる原始多項式毎に)ガロア乗算器の再設計が必要であった c 従来のハー ドワイヤー ドの乗算器は、 (式 10) を (式 13) 又は (式 15)の原始多項式で直接変形して論理を構成することができる。(式 13) の原始多項式を用いた場合に (式 10) は以下のようになる。 In the 4-bit Galois field GF (2 4 ), there are two types of primitive polynomials, and which primitive polynomial is adopted is arbitrary depending on the system. For this reason, the configuration of the conventional dedicated hard-wired Galois multiplier cannot use the same Galois multiplier in different systems. Conventionally, Galois multipliers had to be redesigned for each system (for each different primitive polynomial). C Conventional hardwired multipliers replace (Equation 10) with (Equation 13) or (Equation 15). Can be directly transformed by the primitive polynomial of to form logic. When the primitive polynomial of (Equation 13) is used, (Equation 10) becomes as follows.
Xa*Xb 二 (a3b3) x6+(a,b2+a2b3)
x4
+ (a3b0+a2b1+a1b2+a0b3) x3+(a2b0+a1bl+a0b2) x2 + ( a^o+aobj xHCaobo) x° Xa * Xb two (a 3 b 3 ) x 6 + (a, b 2 + a 2 b 3 ) x 4 + (a 3 b 0 + a 2 b 1 + a 1 b 2 + a 0 b 3 ) x 3 + (a 2 b 0 + a 1 b l + a 0 b 2 ) x 2 + (a ^ o + aobj xHCaobo) x °
= (a3b3) x4 x2+(a3b2+a2b3) x4 x1+(a3bl+a2b2+alb3) x4 + (a3b0+a2b1+a1b2+a0b3) x3+(a2b0+alb1+a0b2) x2 +( a^o+aobj x1 + (a。b。) x° = (a 3 b 3 ) x 4 x 2 + (a 3 b 2 + a 2 b 3 ) x 4 x 1 + (a 3 b l + a 2 b 2 + a l b 3 ) x 4 + (a 3 b 0 + a 2 b 1 + a 1 b 2 + a 0 b 3 ) x 3 + (a 2 b 0 + a l b 1 + a 0 b 2 ) x 2 + (a ^ o + aobj x 1 + ( a.b.) x °
= (a3b3)(xl + 1 )x2+(a3b2+a2b3)(x1 + 1 )x1 = (a 3 b 3 ) (x l + 1) x 2 + (a 3 b 2 + a 2 b 3 ) (x 1 + 1) x 1
+ (a3bl+a2b2+a1b3) (,x' + 1 ) + (a 3 b l + a 2 b 2 + a 1 b 3 ) (, x '+ 1)
+ (a3b0+a2b1+a1b2+a0b3) x +(a2b0+a1b1+a0b2) x2
+ (a 3 b 0 + a 2 b 1 + a 1 b 2 + a 0 b 3 ) x + (a 2 b 0 + a 1 b 1 + a 0 b 2 ) x 2
二 (a3b3+a3b0+a2b1+a1b2+a0b3)x3 2 (a 3 b3 + a 3 b 0 + a 2 b 1 + a 1 b 2 + a 0 b 3 ) x 3
+ (a3b3+a3b2+a2b3+a2b。+a1b1+a。b2) x2 + (a 3 b 3 + a 3 b 2 + a 2 b 3 + a 2 b. + a 1 b 1 + a.b 2 ) x 2
+ ( a3b2+a2b3+ a3bl+a2b2+alb3+alb0+a0b1 ) x1 + ( a3b1+a2b2+alb3+a0b0) x° + (a 3 b 2 + a 2 b 3 + a 3 b l + a 2 b 2 + a l b3 + a l b 0 + a 0 b 1 ) x 1 + (a 3 b 1 + a 2 b 2 + a l b 3 + a 0 b 0 ) x °
従来のハ— ドワイヤー ドのガロア乗算器は、例えば上式を直接に論理 回路で構成する方法を採っていた。すなわち、専用ハー ドウェアのガ口 ァ乗算器は、第 3 1 図に示される論理を、第 3 2図に示される専用論理 回路によって構成する。 このため、 (式 15) に示される別の原始多項 式を採用するシステムでは、別の論理構成の乗算器を再設計する必要が あった。 これを避けるために、 それぞれの原始多項式に対応する複数個 の乗算器を同一ハー ドウエア上に搭載することも考えられるが、この場 合は回路規模が増大する。 The conventional hardwired Galois multiplier employs, for example, a method in which the above equation is directly constituted by a logic circuit. In other words, the dedicated hardware multiplier forms the logic shown in FIG. 31 by the dedicated logic circuit shown in FIG. For this reason, in a system employing another primitive polynomial shown in (Equation 15), it was necessary to redesign a multiplier having another logic configuration. To avoid this, it is conceivable to mount multiple multipliers corresponding to each primitive polynomial on the same hardware, but in this case, the circuit scale increases.
ガロア乗算器は、上述の特定の原始多項式に即したハー ドワイヤー ド の論理構成による以外に、べき表現による乗算方法を採用することも可 能である。すなわち、第 3 9図に示されるガロア体に対する表現を第 4 0図に示されるべキ表現とすることができ、 原始多項式 x 3 + x+ 1 の 根を X = ひとすることで、 X 1 (i=1〜6) を、 ひ1 で表現できる。
べキ表現による乗算は、 元のベキ数を整数加算し、 これを 7 (=23_ 1 )で割ったときの剰余で定義される。 The Galois multiplier can adopt a multiplication method based on a power expression, in addition to the above-described hardwired logical configuration based on the specific primitive polynomial. That is, the expression for the Galois field shown in FIG. 39 can be made the power expression shown in FIG. 40, and the root of the primitive polynomial x 3 + x + 1 is reduced by X = X 1 ( i = 1~6 a), it can be expressed by the ratio 1. Multiplication by a power expression is defined as the remainder when the original power number is added to an integer and this is divided by 7 (= 2 3 _ 1).
例えば前記多項式表現での G F ( 23)の元 X 2と x +1 との乗算を べキ表現で行う。 For example, the multiplication of the element X 2 of GF (2 3 ) in the above polynomial expression and x + 1 is performed by a power expression.
x 2= ひ 2 , X +1二 ひ 3であるから、 x 2 = HI 2 , X +1 2 HI 3
X 2*( X +1 ) 二ひ 2 *ひ 3二ひ ( 2 +3 )mod 2に 1 =ひ 5 X 2 * (X +1) 2 2 * 3 3 2 (2 +3) mod 2 1 = 5
となり、 第 40図からひ 5に対応する多項式をさがすと、 X 2 + X + 1Next, the search for polynomial corresponding to FIG. 40 Karahi 5, X 2 + X + 1
(べク トル表示では、 ( 1 1 1 ))が求まる。 ((1 1 1)) is obtained in the vector display.
べキ表現での乗算は、上述のように机上では容易に行うことができる が、 回路を組む場合は R OMを用いて行うことになる。例えば、 第 3 3 図には、公知ではないが、 R OMを用いてべキ表現での乗算を行うため のガロア乗算器の一例が示される。 ガロア数 αη , ひ mに相当するべク トル表現のデータが第 1 、第 2のガロア数デコー ド論理でデコ一 ドされ る。第 1 、 第 2の R OMには前記第 1 、第 2のガロア数デコ一 ド論理に よるデコー ド結果に応じたガロア数の指数 (べキ数) n, mが予じめ格 納され、デコー ド結果に従って指数が第 1 、第 2の R〇Mから読出され る。双方の R OMから読出された指数 n , mは加算され、 その加算結果 がエンコーダでエンコー ドされる。エンコーダの出力を受ける第 3の R は、指数 + nの値に応じたガロア数ひ m + nのべク トル表現データ が予じめ格納されており、ェンコ一 ドの結果に応じたガロア数 am + nの べク トル表現デ一夕が出力される。 Multiplication in power expression can be easily performed on a desk as described above, but when a circuit is built, it is performed using ROM. For example, FIG. 33 shows an example of a Galois multiplier, which is not publicly known, for performing multiplication in a power expression using a ROM. The vector representation data corresponding to the Galois numbers α η and m is decoded by the first and second Galois number decoding logic. In the first and second ROMs, exponents (power numbers) n and m of Galois numbers according to the decoding result by the first and second Galois number decoding logic are stored in advance. The exponent is read from the first and second R〇M according to the decoding result. The exponents n and m read from both ROMs are added, and the addition result is encoded by the encoder. The third R receiving the output of the encoder stores the Galois number according to the value of the exponent + n and the vector representation data of m + n in advance, and the Galois number according to the result of the encoding. The vector representation of am + n is output.
べキ表現による乗算手法を採用した第 3 3図に示されるガロア乗算 器は、数種類の R OMを持たなければならないから、ガロア乗算器の回 路規模は大きくなる。 また、 R OMを用いた場合は原始多項式が変われ ば、 それに応じて R 0 Mの記憶データを書き換えればよいが、ガロア体 のビッ 卜数 Nが大き〈なっていく と R〇M容量が 2 N倍で増え、 回路規
摸が益々増えてしまう。 しかも、異なる原始多項式に適用する場合に、The Galois multiplier shown in Fig. 33, which employs the power multiplication method, must have several types of ROMs, so the circuit size of the Galois multiplier becomes large. In addition, when the OM is used, if the primitive polynomial changes, the stored data of R0M may be rewritten accordingly, but as the number of bits N in the Galois field increases, the R〇M capacity becomes 2 N times increase, circuit rule There are more and more models. Moreover, when applied to different primitive polynomials,
R O Mのデータを書き換えるには比較的長い時間も必要である。 Rewriting data in ROM requires a relatively long time.
本発明は、上記事情に鑑みてなされたものであり、 R O Mを用いる場 合に比べて回路規模が小さく、複数の異なる原始多項式を用いた乗算を 可能にするガロア乗算器を含む半導体集積回路を提供することにある。 本発明の別の目的は、複数の異なる原始多項式に関する符号語を用い た複数種類の情報に対する誤り訂正を行う回路規模を小さ〈すること ができる、情報記録系や情報通信系などに適用されるデータ処理システ ムを提供することにある。 The present invention has been made in view of the above circumstances, and has a semiconductor integrated circuit including a Galois multiplier that has a smaller circuit size than that using a ROM and enables multiplication using a plurality of different primitive polynomials. To provide. Another object of the present invention is applied to an information recording system, an information communication system, and the like, which can reduce a circuit scale for performing error correction on a plurality of types of information using codewords related to a plurality of different primitive polynomials. To provide a data processing system.
本発明の前記ならびにその他の目的と新規な特徴は本明細書の以下 の記述から明らかにされるであろう。 発明の開示 The above and other objects and novel features of the present invention will become apparent from the following description of the present specification. Disclosure of the invention
本発明に係る半導体集積回路は、 ガロア体 G F ( 2 n )の元と元との間 のガロア乗算に用いられるガロア乗算器を含み、前記ガロア乗算器は、 乗数とされるガロア体 G F ( 2 n )の元の係数と、 被乗数とされるガロア 体 G F ( 2 n )の元の係数と、 原始多項式の係数とを入力し、 ガロア乗算 結果を得るための前記係数の演算を、複数の異なる原始多項式に対して、 同一ハー ドウエアで行う。 前記ガロア乗算器に前記ガロア体 G F ( 2 n ) の原始多項式の係数を与える係数設定手段が設けられている。 A semiconductor integrated circuit according to the present invention includes a Galois multiplier used for Galois multiplication between elements of a Galois field GF ( 2n ), wherein the Galois multiplier is a Galois field GF (2 n ), the original coefficient of the Galois field GF (2 n ), which is the multiplicand, and the coefficient of a primitive polynomial. The same hardware is used for primitive polynomials. The Galois multiplier is provided with coefficient setting means for giving a primitive polynomial coefficient of the Galois field GF ( 2n ).
これによれば、前記ガロア乗算器は、前記係数設定手段から与えられ る原始多項式に応じたガロア体上の乗算を行うことができる。したがつ て、上記半導体集積回路は、原始多項式毎に定義される異なったガロア 体による誤り訂正符号などに対する符号化又は復号化処理に汎用的に 利用することが可能である。 According to this, the Galois multiplier can perform multiplication on the Galois field in accordance with the primitive polynomial given from the coefficient setting means. Therefore, the semiconductor integrated circuit can be generally used for encoding or decoding of an error correction code or the like based on different Galois fields defined for each primitive polynomial.
前記係数設定手段は、原始多項式の係数を書き換え可能に記憶し、記
憶した原始多項式の係数を前記ガロア乗算器に出力するレジスタなど の記憶手段とすることができる。 また、 前記係数設定手段は、複数種類 の原始多項式の係数を記憶し、記憶した係数の中から選択された係数を 前記ガロア乗算器に出力する R O Mなどの手段とすることができる。 前記ガロア乗算器は部分積加算部と補正項加算部とを有し、前記部分 積加算部は、乗数と被乗数の部分積毎の乗数の係数と被乗数の係数との 部分積加算を行い、前記補正項加算部は、部分積加算部によって得られ た n + 1 次以上の部分積の係数を n次以下の部分積の係数に補正する 演算を行うように構成することができる。原始多項式の係数は前記係数 設定手段により予め設定されている。補正項加算部は、 そのように予め 設定された原始多項式の係数を予め入力しており、部分積加算部による 部分積加算結果を入力することにより、即座に補正演算を行うことがで さる。 The coefficient setting means stores the coefficients of the primitive polynomial in a rewritable manner, and It may be storage means such as a register for outputting the stored coefficients of the primitive polynomial to the Galois multiplier. Further, the coefficient setting unit may be a unit such as a ROM that stores a plurality of types of primitive polynomial coefficients and outputs a coefficient selected from the stored coefficients to the Galois multiplier. The Galois multiplier includes a partial product adder and a correction term adder, and the partial product adder performs partial product addition of a multiplier coefficient and a multiplicand coefficient for each partial product of the multiplier and the multiplicand. The correction term adding unit can be configured to perform an operation of correcting the coefficient of the partial product of order n + 1 or more obtained by the partial product adding unit to the coefficient of the partial product of order n or less. The coefficients of the primitive polynomial are set in advance by the coefficient setting means. The correction term addition unit has previously input the coefficients of the primitive polynomial set in advance in such a manner, and can immediately perform the correction operation by inputting the partial product addition result by the partial product addition unit.
具体的には、前記補正項加算部は、部分積加算部によって得られた n + 1次以上の部分積の係数を n次以下の部分積の係数に補正するため の補正情報を原始多項式の係数に基づいて予め演算する第 1 の論理演 算回路と、前記部分積加算部によって得られた n + 1 次以上の部分積の 係数毎に当該係数と対応する補正情報との積を採る第 2の論理演算回 路と、夫々の第 2の論理演算回路の出力を加算する第 3の論理演算回路 とから構成することができる。 これは、前記高次の項を低次の項に置き換 える方式として、 原始多項式の係数の演算を、 乗数、 被乗数の係数の演 算に対して予め独立に行うようにしたものであるから、ガロア乗算処理 を高速化するための補正項加算部の一つの基本型として位置付けるこ とができる。 Specifically, the correction term addition unit calculates correction information for correcting the coefficient of the partial product of n + 1 or higher order obtained by the partial product addition unit to the coefficient of the partial product of nth or lower order by using a primitive polynomial. A first logical operation circuit that calculates in advance based on the coefficient; and a second logic operation circuit that obtains, for each coefficient of the n + 1 or higher order partial product obtained by the partial product addition unit, a product of the coefficient and the corresponding correction information. It can be composed of two logical operation circuits and a third logical operation circuit that adds the outputs of the respective second logical operation circuits. This is because, as a method of replacing the higher-order terms with lower-order terms, the calculation of the coefficients of the primitive polynomial is performed in advance independently of the calculation of the coefficients of the multiplier and the multiplicand. Thus, it can be positioned as one basic type of the correction term adder for speeding up the Galois multiplication.
補正項加算部には、高次の項の次数を下げる手法として、原始多項式 の係数と乗数、被乗数の係数との部分積演算を行いながら、 逐次、 1 次
毎に次数を下げる構成を採用することができる。これを実現する補正項 加算部は、 n個の単位回路の配列を n - 1列備え、列方向の単位回路の 次数は 1 から 2 n— 2とされ、第 1列目の配列は n個目が次数 2 n - 2 とされ、 2列目の配列は n個目が次数 2 n— 3とされ、順次次数を下げ て n— 1列目の配列は n個目が次数 nとされる。前記配列の各列の単位 回路は、列毎に共通の入力として前列の配列の最上位の単位回路の出力 とそれに対応する部分積加算の値との第 1のガロア和を受け、この共通 の入力と各列の単位回路に共通に入力される原始多項式の係数とを受 けて論理積を生成すると共に、当該論理積の値と前列の同一次数位置の 単位回路の出力との第 2 のガロア和を生成して出力とする機能を有す る。 1 列目の単位回路は、夫々に前記共通の入力として部分積加算の最 上位である次数 2 n - 1 の値が供給されると共に、前記第 2のガロア和 を生成することなく出力を生成する。 2列目及びそれよりも下位の配列 の単位回路は前記共通の入力として一つ前の配列の最上位の単位回路 の出力とそれに対応する部分積加算の値との前記第 1 のガロア和を受 けて出力を生成する。そして、 n _ 1列目の n個の単位回路の出力を補 正項加算の出力とする。当該補正項加算の出力と部分積加算の下位 nビ ッ 卜とのガロア和が乗算結果とされる。 The correction term adder uses a method to reduce the order of the higher-order terms, performing partial product operations of the coefficients of the primitive polynomial and the coefficients of the multiplier and the multiplicand. A configuration in which the order is reduced every time can be adopted. The correction term adder that realizes this is provided with an array of n unit circuits of n-1 columns, the order of the unit circuits in the column direction is from 1 to 2 n-2, and the array of the first column is n The order is 2 n-2, the n-th array in the second column is the order 2 n— 3, and the order is reduced sequentially. The n-th array in the n-th column is the n-th order. . The unit circuit of each column of the array receives, as a common input for each column, a first Galois sum of the output of the uppermost unit circuit of the array of the preceding column and the value of the partial product addition corresponding thereto, and A logical product is generated by receiving the input and a coefficient of a primitive polynomial commonly input to the unit circuits of each column, and a second logical product of the value of the logical product and the output of the unit circuit at the same order position in the preceding column is obtained. It has a function to generate Galois sums and output them. Each of the unit circuits in the first column is supplied with the value of the order 2 n−1, which is the highest order of partial product addition, as the common input, and generates an output without generating the second Galois sum. I do. The unit circuits of the second column and the lower array are used as the common input as the first Galois sum of the output of the uppermost unit circuit of the immediately preceding array and the corresponding partial product addition value. Receives and produces output. Then, the outputs of the n unit circuits in the n_1st column are output as the correction term additions. The Galois sum of the output of the correction term addition and the lower n bits of the partial product addition is used as the multiplication result.
また、前記補正項加算部による演算処理を更に高速化した補正項加算 部は、 n個の単位回路の配列を n - 1列備え、列方向の単位回路の次数 は 1 から 2 n— 2とされ、第 1列目の配列は n個目が次数 2 n— 2とさ れ、 2列目の配列は n個目が次数 2 n— 3とされ、順次次数を下げて n - 1列目の配列は n個目が次数 nとされる。配列の各列の次数 n + 1 以 上の単位回路は、配列毎に共通の入力として対応するビッ 卜位置の部分 積加算の値を受け、この共通の入力と各列の単位回路に入力される nビ ッ 卜の原始多項式の係数をデコー ドした信号とを受けて積を生成する
と共に、前列の同一次数位置の単位回路からの出力と前記積との第 1の ガロア和を生成して出力する機能を有し、前記各列の次数 n + 1 以上の 単位回路のうち、配列の最上位位置の単位回路の出力は、それに対応す る部分積加算の値と共に第 2のガロア和を生成する。前記配列の各列の 次数 n以下の単位回路は、共通の入力として前記第 2のガロア和を受け、 この共通の入力と各列の単位回路に入力される原始多項式の対応され る係数とを受けて積を生成すると共に、前列の同一次数位置の単位回路 からの出力と前記積との第 3 のガロア和を生成して出力とする機能を 有する。 1列目の単位回路は次数 n + 1 以上と次数 n以下に共通の入力 として部分積加算の最上位次数 2 n一 1 の値が入力されて出力を生成 し、 2列目以下の単位回路では次数 n + 1以上に共通の入力は対応する 部分積加算の値とされ、同じく 2列目以下の単位回路では次数 n以下に 共通の入力は対応する前記第 2のガロア和の値とされる。 n— 1列目の n個の単位回路の出力が補正項加算の出力とされる。当該補正項加算の 出力と部分積加算の下位 nビッ 卜とのガロア和が乗算結果とされる。 n ビッ 卜の原始多項式の係数をデコー ドするデコ一 ド論理は、次数 n + 1 以上の部分積加算結果と原始多項式の係数とによる補正情報の生成論 理を簡素化して、 ゲー ト直列段数を少なくする。 Further, the correction term adder, which further speeds up the arithmetic processing by the correction term adder, includes an array of n unit circuits in n-1 columns, and the order of the unit circuits in the column direction is 1 to 2 n−2. In the array in the first column, the n-th array has the order 2 n—2, and in the array in the second column, the n-th array has the order 2 n— 3. The n-th array has the degree n. Unit circuits of order n + 1 or higher in each column of the array receive the value of the partial product addition at the corresponding bit position as a common input for each array, and are input to this common input and the unit circuit in each column. Generates a product by receiving the signal obtained by decoding the coefficients of the n-bit primitive polynomial And a function of generating and outputting the first Galois sum of the output from the unit circuit at the same order position in the front row and the product, and among the unit circuits of the order n + 1 or more in each column, the array The output of the unit circuit at the uppermost position generates a second Galois sum with the corresponding partial product addition value. A unit circuit of order n or less in each column of the array receives the second Galois sum as a common input, and calculates the common input and a corresponding coefficient of a primitive polynomial input to the unit circuit of each column. In addition to receiving and generating a product, a third Galois sum of the output from the unit circuit at the same order position in the front row and the product is output. The unit circuit in the first column receives the value of the highest order 2 n-1 1 of partial product addition as a common input for the order n + 1 or more and the order n or less and generates an output.The unit circuit in the second column or less In this case, the input common to the order n + 1 or more is the corresponding partial product addition value, and the input common to the order n or less is the corresponding value of the second Galois sum in the unit circuits in the second column and below. You. n — The output of the n unit circuits in the first column is the output of the correction term addition. The Galois sum of the output of the correction term addition and the lower n bits of the partial product addition is used as the multiplication result. Decoding logic that decodes the coefficients of n-bit primitive polynomials simplifies the logic of generating correction information based on partial product addition results of degree n + 1 or more and coefficients of primitive polynomials, and reduces the number of gate series stages. Less.
前記補正項加算部は、限定した複数の原始多項式を扱う場合に、複数 の原始多項式で共通に係数をゼロとする次数に関するハ— ドウエアを 省略して構成することができる。 すなわち、 ガロア体 G F ( 2 n )のビッ 卜数 nが決まると、それに対応される原始多項式は数種類に限定され、 このとき、全ての原始多項式で係数が常にゼロになる次数の部分ではそ のハ一 ドウエアを省略できる。 これは、 ゲー 卜直列段数の低減による演 算処理の高速化を促進する。 When handling a limited plurality of primitive polynomials, the correction term adder can be configured by omitting hardware relating to an order whose coefficient is commonly set to zero among a plurality of primitive polynomials. In other words, once the number of bits n of the Galois field GF (2 n ) is determined, the primitive polynomials corresponding to it are limited to several types.At this time, in the order where the coefficient is always zero in all primitive polynomials, Hardware can be omitted. This promotes faster arithmetic processing by reducing the number of gate series stages.
前記部分積加算部は、乗数の隣接する 2ビッ 卜のガロア和を n— 1 ビ
ッ 卜生成し、さらに被乗数の連続する 2ビッ ト毎をデコ一ドして 2ビッ 卜毎に 4つの出力を生成し、部分積の列数を 1 / 2とし、部分積の各列 の各ビッ 卜位置の入力として隣接する乗数のビッ 卜値、乗数の隣接する 2ビッ 卜のガロア和、及びゼロの 4つの入力を有し、上記デコ— ドされ た 4つの出力により入力を選択し、選択された入力と前列の部分積との ガロア和を出力として後列に出力するように構成することができる。こ のようなセレクタ方式で部分積加算を行う構成によっても、信号経路の ゲー 卜直列段数を低減でき、 演算処理の高速化を実現する。 The partial product adder calculates the Galois sum of adjacent two bits of the multiplier as n−1 bits. , And further decodes every two consecutive bits of the multiplicand to generate four outputs for every two bits.The number of columns of the partial product is set to 1/2, and each column of the partial product is output. The input of the bit position has four inputs: a bit value of an adjacent multiplier, a Galois sum of two adjacent bits of the multiplier, and zero, and selects an input based on the four outputs decoded as described above. The Galois sum of the selected input and the partial product of the front row can be output to the back row as an output. Even with such a configuration in which partial product addition is performed by the selector method, the number of gate series stages in the signal path can be reduced, and high-speed arithmetic processing is realized.
データ処理システムは、 ガロア体 G F ( 2 n )の元と元との間のガロア 乗算に用いられるガロア乗算器と、前記ガロア乗算器の原始多項式を再 設定可能にする設定手段とを含む。 このとき、 前記ガロア乗算器は、 乗 数とされるガロア体 G F ( 2 n )の元の係数と、 被乗数とされるガロア体 G F ( 2 n )の元の係数と、 原始多項式の係数とを入力し、 ガロア乗算結 果を得るための前記係数の演算を、複数の異なる原始多項式に対して、 同一ハー ドウエアで行う。前記原始多項式の係数は前記設定手段から与 えられるように構成することができる。 The data processing system includes a Galois multiplier used for Galois multiplication between elements of a Galois field GF ( 2n ), and setting means for enabling a primitive polynomial of the Galois multiplier to be reset. In this case, the Galois multiplier, and the original coefficients of the Galois field GF (2 n) which is the number of multiplication, and the original coefficients of the Galois field GF (2 n) which is the multiplicand, and a coefficient of a primitive polynomial The input and the calculation of the coefficients for obtaining the Galois multiplication result are performed on the same hardware for a plurality of different primitive polynomials. The coefficients of the primitive polynomial may be provided from the setting means.
前記設定手段は、設定すべき原始多項式を、選択スィツチの操作状態 に従つて決定するように構成することができる。 The setting means may be configured to determine a primitive polynomial to be set in accordance with an operation state of a selection switch.
別のデータ処理システムは、情報記録媒体の種類を認識する認識手段 と、複数種類の情報記録媒体をアクセス可能なアクセス手段と、ァクセ ス手段によつて前記情報記録媒体から読み取られた記録情報の誤り訂 正に用いられる誤り訂正回路とを含む。 このとき、前記ガロア乗算器は、 ガロア体 G F ( 2 n )の元と元との間のガロア乗算に用いられ、 乗数とさ れるガロア体 G F ( 2 n )の元の係数と、 被乗数とされるガロア体 G F ( 2 n )の元の係数と、 原始多項式の係数とを入力し、 ガロア乗算結果を得 るための前記係数の演算を、複数の異なる原始多項式に対して、同一ハ
一ドウエアで行う。前記原始多項式の係数は前記認識手段による情報記 録媒体の種類の認識結果に従って決定されるように構成することがで きる。 これによれば、 リードソロモン符号のような誤り訂正符号の定義 に用いられる原始多項式が異なる M 0と D V Dの双方の記録媒体を扱 うシステムにおいて、記録情報の再生と情報記録に際して何れの記録媒 体に対しても前記ガロア乗算器を共通に用いることができ、システムの 小型化に寄与する。 Another data processing system includes a recognizing unit that recognizes the type of the information recording medium, an access unit that can access a plurality of types of information recording media, and a recording unit that reads the recording information read from the information recording medium by the access unit. Error correction circuit used for error correction. In this case, the Galois multiplier is used for Galois multiplication between the original and the original Galois field GF (2 n), and the original coefficients of the Galois field GF (2 n) which is a multiplier, is the multiplicand The original coefficients of the Galois field GF (2 n ) and the coefficients of the primitive polynomial are input, and the calculation of the coefficients for obtaining the result of the Galois multiplication is the same for a plurality of different primitive polynomials. This is done with one hardware. The primitive polynomial coefficient may be determined according to the result of recognition of the type of the information recording medium by the recognition means. According to this, in a system that handles both M0 and DVD recording media having different primitive polynomials used for defining an error correction code such as a Reed-Solomon code, either of the recording media is used for reproducing the recorded information and for recording the information. The Galois multiplier can also be used in common for the body, which contributes to the miniaturization of the system.
更に別のデータ処理システムは、フェッチした命令を解読して制御信 号を生成する制御手段と、前記制御信号によって制御される演算手段と、 前記演算手段を外部とィン夕フェースさせるインタフェース手段とを 有する。 このとき、 前記演算手段は、 ガロア体 G F ( 2 n )の元と元との 間のガロア乗算に用いられるガロア乗算器を含み、前記ガロア乗算器は、 乗数とされるガロア体 G F (2 n )の元の係数と、 被乗数とされるガロア 体 G F ( 2 n )の元の係数と、 原始多項式の係数とを入力し、 ガロア乗算 結果を得るための前記係数の演算を、複数の異なる原始多項式に対して、 同一ハー ドウエアで行うガロア乗算器を含み、前記原始多項式の係数は 前記制御手段の制御によって決定されるように構成することができる。 このデータ処理システムは、単一の半導体基板に形成されたマイクロプ 口セッサとして構成することができる。 図面の簡単な説明 Still another data processing system includes control means for decoding a fetched instruction to generate a control signal, arithmetic means controlled by the control signal, and interface means for interfacing the arithmetic means with the outside. It has. At this time, the arithmetic means includes a Galois multiplier used for Galois multiplication between elements of the Galois field GF (2 n ), and the Galois multiplier is a Galois field GF (2 n ), The original coefficient of the Galois field GF (2 n ), which is the multiplicand, and the coefficient of the primitive polynomial, and the calculation of the coefficient to obtain the Galois multiplication result is performed by a plurality of different primitives. A Galois multiplier that performs the same hardware with respect to the polynomial may be included, and a coefficient of the primitive polynomial may be determined by control of the control unit. This data processing system can be configured as a microprocessor formed on a single semiconductor substrate. BRIEF DESCRIPTION OF THE FIGURES
第 1 図は複数種類の原始多項式の乗算を同一ハー ドウエアで可能に したガロア乗算器を概念的に示した説明図、 Fig. 1 is an explanatory diagram conceptually showing a Galois multiplier that enables multiplication of multiple types of primitive polynomials with the same hardware.
第 2図は部分積加算と補正項加算の第 1 の計算例を示す説明図、 第 3図は第 2図の計算例で示される論理を部分積と補正項に分けて 実現したガロア乗算器の一例論理回路図、
第 4図は部分積加算と補正項加算の第 2の計算例を示す説明図、 第 5図は第 4図の計算例で示される論理を部分積と補正項に分けて 実現したガロア乗算器の一例論理回路図、 Fig. 2 is an explanatory diagram showing the first calculation example of partial product addition and correction term addition, and Fig. 3 is a Galois multiplier realized by dividing the logic shown in the calculation example of Fig. 2 into a partial product and a correction term. Example logic circuit diagram, Fig. 4 is an explanatory diagram showing a second calculation example of partial product addition and correction term addition, and Fig. 5 is a Galois multiplier that realizes the logic shown in the calculation example of Fig. 4 by dividing it into a partial product and a correction term. Example logic circuit diagram,
第 6図は部分積加算と補正項加算の第 3の計算例を示す説明図、 第 7図は第 6図の計算例で示される論理を部分積と補正項に分けて 実現したガロア乗算器の一例論理回路図、 Fig. 6 is an explanatory diagram showing a third calculation example of partial product addition and correction term addition, and Fig. 7 is a Galois multiplier that implements the logic shown in the calculation example of Fig. 6 by dividing it into a partial product and a correction term. Example logic circuit diagram,
第 8図は 2種類有る 4次式の原始多項式における双方の原始多項式 では X 2の係数 C 2がゼロであることを考慮した場合の部分積加算と補 正項加算の計算例を示す説明図、 FIG. 8 is an explanatory diagram showing a calculation example of a partial product adding a complement Seiko addition in the case of considering that the coefficients C 2 both primitive polynomial in X 2 is zero at the primitive polynomial of the two there quartic ,
第 9図は第 8図の計算例で示される論理を部分積と補正項に分けて 実現したガロア乗算器の一例論理回路図、 Fig. 9 is an example logic circuit diagram of a Galois multiplier realized by dividing the logic shown in the calculation example of Fig. 8 into partial products and correction terms,
第 1 0図は第 6図及び第 7図の論理を 8 ビッ 卜のガロア体に適用し た場合のガロア乗算器の一例論理回路図、 FIG. 10 is an example logic circuit diagram of a Galois multiplier when the logic of FIGS. 6 and 7 is applied to an 8-bit Galois field,
第 1 1 図は第 1 0図の構成に対して更に高速化を図ったガロア乗算 器の一例論理回路図、 FIG. 11 is a logic circuit diagram of an example of a Galois multiplier which is further speeded up from the configuration of FIG. 10,
第 1 2図は第 3図などに具体的に示した部分積加算と補正項加算に 分けてガロア乗算を行うガロア乗算器の構成を機能的に示した説明図、 第 1 3図は補正項加算部において原始多項式の係数を予めデコー ド して補正項加算部に供給するガロア乗算器の構成を機能的に示した説 明図、 Fig. 12 is an explanatory diagram that functionally shows the configuration of a Galois multiplier that performs Galois multiplication by dividing into the partial product addition and the correction term addition specifically shown in Fig. 3, etc., and Fig. 13 is the correction term. Explanatory diagram functionally showing the configuration of a Galois multiplier that decodes the coefficients of a primitive polynomial in an adder in advance and supplies the decoded data to a correction term adder.
第 1 4図は第 7図の 4ビッ 卜の回路構成を第 1 3図のデコ— ド方式 に展開した場合の補正項加算部及びデコーダの構成を具体的に示した 説明図、 FIG. 14 is an explanatory diagram specifically showing the configurations of the correction term adder and the decoder when the 4-bit circuit configuration of FIG. 7 is expanded to the decoding system of FIG.
第 1 5図は第 1 4図のデコーダを用いた補正項の展開例を示す説明 図、 FIG. 15 is an explanatory diagram showing an example of expansion of a correction term using the decoder of FIG. 14,
第 1 6図は 8ビッ 卜のガロア乗算器にデコ—ド方式を適用した場合
の補正項加算部及びデコーダの構成を具体的に示した説明図、 Fig. 16 shows the case where the decoding method is applied to an 8-bit Galois multiplier. Explanatory diagram specifically showing the configuration of the correction term addition unit and the decoder of
第 1 7図は第 1 6図のデコーダを用いた補正項の展開例を示す説明 図、 FIG. 17 is an explanatory diagram showing an example of expansion of a correction term using the decoder of FIG. 16,
第 1 8図は部分積加算部の入力と補正項加算部の入力の双方にデコ ーダを設けて更に処理の高速化を図ったガロア乗算器を機能的に示す 説明図、 FIG. 18 is an explanatory diagram functionally showing a Galois multiplier in which a decoder is provided for both the input of the partial product addition unit and the input of the correction term addition unit to further speed up the processing;
第 1 9図は部分積加算部における演算処理を更に高速化するための セレクタ方式による構成を論理的に示した説明図、 FIG. 19 is an explanatory diagram logically showing a configuration based on a selector system for further accelerating the arithmetic processing in the partial product addition unit.
第 2 0図は第 1 9図に示されるセレクタ方式を 4ビッ トのガロア乗 算器に適用したときの部分積加算部の論理回路図、 FIG. 20 is a logic circuit diagram of a partial product adder when the selector method shown in FIG. 19 is applied to a 4-bit Galois multiplier.
第 2 1 図は第 2 0図の部分積加算部に適用される第 1 のセレクタの 一例回路図、 FIG. 21 is a circuit diagram of an example of a first selector applied to the partial product adder of FIG. 20,
第 2 2図は第 2 0図の部分積加算部に適用される第 2のセレクタの 一例回路図、 FIG. 22 is a circuit diagram of an example of a second selector applied to the partial product adder of FIG. 20,
第 2 3図は第 1 9図および第 2 0のセレクタ方式を 8ビッ 卜のガロ ァ乗算器に拡張した場合における部分積加算部の論理回路図、 FIG. 23 is a logic circuit diagram of the partial product adder when the selector system of FIGS. 19 and 20 is extended to an 8-bit Galois multiplier,
第 2 4図はリ一 ド 'ソロモン誤り訂正復号処理の一例フローチヤ一 卜、 第 2 5図はシンド口—厶演算、 ュ―クリ ツ ド演算及びチェンサーチ の各回路の内部構成を概略的に示したプロック図、 FIG. 24 is a flow chart showing an example of the read'Solomon error correction decoding process, and FIG. 25 is a schematic diagram showing the internal configuration of each of the circuits for the sindom operation, the leak operation and the Chien search. Block diagram shown,
第 2 6図は第 2 4図に示されるリ一 ド 'ソロモン誤り訂正復号処理を 行うプロセッサのブロック図、 FIG. 26 is a block diagram of a processor for performing the read 'Solomon error correction decoding process shown in FIG. 24,
第 2 7図は D V Dなどの蓄積メディアに対する情報記録又は情報再 生を行うデータ処理システムの一例プロック図、 Fig. 27 is a block diagram of an example of a data processing system that records or reproduces information on storage media such as DVDs.
第 2 8図は衛星放送などの通信系に利用されるデータ処理システム の一例ブロック図、 Figure 28 is an example block diagram of a data processing system used for communication systems such as satellite broadcasting.
第 2 9図は多項式表現されたガロア数の乗算計算例を示す説明図、
第 3 0図は乗数と被乗数の各次数の係数に数値を入れてガロア数の 乗算を行ったときの計算例を示す説明図、 FIG. 29 is an explanatory diagram showing an example of multiplication calculation of a Galois number represented by a polynomial expression. FIG. 30 is an explanatory diagram showing a calculation example when a numerical value is inserted in the coefficient of each order of the multiplier and the multiplicand and the Galois number is multiplied,
第 3 1 図は原始多項式が X4=X 1 + 1のときの乗算計算例を示す説明 図である。 FIG. 31 is an explanatory diagram showing an example of multiplication calculation when the primitive polynomial is X 4 = X 1 +1.
第 3 2図は原始多項式が X4=X 1 + 1のときの専用ハー ドウェアのガ ロア乗算回路の論理構成の一例を示すを論理回路図、 3 Fig. 2 logic circuit diagram of an example of a logical configuration of moths lower multiplying circuits dedicated hardware when primitive polynomial is X 4 = X 1 + 1,
第 3 3図は R 0M方式によるガロア乗算回路の一例を示すプロック 図、 FIG. 33 is a block diagram showing an example of a Galois multiplier circuit based on the R0M method.
第 3 4図はガロア体による誤り訂正を採用した通信系モデルの説明 図、 Fig. 34 is an explanatory diagram of a communication system model that employs Galois field error correction.
第 3 5図はガロア体による誤り訂正を採用した蓄積系モデルの説明 図、 Fig. 35 is an explanatory diagram of a storage model that adopts error correction by Galois field,
第 3 6図はガロア体 G F(23)の元を示す説明図、 FIG. 36 is an explanatory diagram showing elements of the Galois field GF (2 3 ),
第 3 7図は原始多項式 X 4 + X 1 + 1 の場合におけるガロア体 G F ( 24 )の元を示す説明図、 Fig. 37 is an explanatory diagram showing the elements of the Galois field GF (2 4 ) in the case of the primitive polynomial X 4 + X 1 + 1,
第 3 8図は原始多項式 X 4 + X 3 + 1 の場合におけるガロア体 G F ( 24)の元を示す説明図、 Fig. 38 is an explanatory diagram showing the elements of the Galois field GF (2 4 ) in the case of the primitive polynomial X 4 + X 3 + 1,
第 3 9図はガロア体 G F ( 24;)の元に対するべク 卜ル表現と多項式 表現の例を示す説明図、 3 9 FIG Galois field GF; explanatory view showing an example of a base click Bokuru representation and polynomial representation of the original, (2 4)
第 4 0図はガロア体 G F ( 24 )の元に対する多項式表現とべキ表現 の例を示す説明図である。 発明を実施するための最良の形態 4 0 is an explanatory diagram showing an example of a polynomial representation preparative base key representation of the original Galois field GF (2 4). BEST MODE FOR CARRYING OUT THE INVENTION
《汎用ガロア乗算器を含む半導体集積回路》 << Semiconductor integrated circuit including general-purpose Galois multiplier >>
第 1 図には本発明に係る半導体集積回路の一例が示される。同図に示 される半導体集積回路 1 は代表的に示されたガロア乗算器 2及び係数
設定手段 3を含み、単結晶シリコンのような 1個の半導体基板に、例え ば公知の C M O S集積回路製造技術により形成されている。 FIG. 1 shows an example of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 1 shown in FIG. 1 includes a Galois multiplier 2 and a coefficient It includes the setting means 3 and is formed on one semiconductor substrate such as single crystal silicon, for example, by a known CMOS integrated circuit manufacturing technique.
前記ガロア乗算器 2及び係数設定手段 3は、 ガロア体 G F ( 2 n )の元 と元との間のガロア乗算に用いられる。前記ガロア乗算器 2は、乗数と されるガロア体 G F ( 2 n )の元の係数 ( nビッ ト) 4と、 被乗数とされ るガロア体 G F ( 2 n )の元の係数 ( nビッ ト) 5と、 原始多項式の係数 ( nビッ 卜) 6とを入力し、ガロア乗算結果を得るための前記係数の演 算を、複数の異なる原始多項式に対して、 同一ハー ドウエアで行う。前 記係数設定手段 3は、 前記ガロア乗算器 2に前記ガロア体 G F ( 2 "の 原始多項式の係数を与える回路である。 The Galois multiplier 2 and the coefficient setting means 3 are used for Galois multiplication between elements of the Galois field GF ( 2n ). The Galois multiplier 2, and the original coefficients of the Galois field GF that is a multiplier (2 n) (n bits) 4, the original coefficients of the multiplicand and is Ru Galois field GF (2 n) (n bits) 5 and the coefficient (n bits) 6 of the primitive polynomial are input, and the operation of the coefficient for obtaining the Galois multiplication result is performed for a plurality of different primitive polynomials with the same hardware. The coefficient setting means 3 is a circuit that provides the Galois multiplier 2 with the coefficients of the primitive polynomial of the Galois field GF (2 ".
前記係数設定手段 3は、原始多項式の係数を書き換え可能に記憶し、 記憶した原始多項式の係数を前記ガロア乗算器 2に出力するレジスタ などの記憶手段とすることができる。 また、 前記係数設定手段 3は、 複 数種類の原始多項式の係数を記憶し、記憶した係数の中から選択された 係数を前記ガロア乗算器 2に出力する R O Mなどの手段とすることが できる。係数設定手段 3に対する原始多項式の係数設定又は原始多項式 の係数選択は、半導体集積回路 1 の内部から信号線 7で与えられ、或い は半導体集積回路の外部から信号線 8で与えることができる。 The coefficient setting unit 3 may be a storage unit such as a register that stores the coefficients of the primitive polynomial in a rewritable manner and outputs the stored coefficients of the primitive polynomial to the Galois multiplier 2. Further, the coefficient setting means 3 may be a means such as a ROM which stores a plurality of types of primitive polynomial coefficients and outputs a coefficient selected from the stored coefficients to the Galois multiplier 2. The coefficient setting of the primitive polynomial or the coefficient selection of the primitive polynomial for the coefficient setting means 3 can be given from inside the semiconductor integrated circuit 1 via a signal line 7 or from outside the semiconductor integrated circuit via a signal line 8.
この半導体集積回路 1 によれば、前記ガロア乗算器 2は、前記係数設 定手段 3から与えられる原始多項式の係数に応じたガロア体上の乗算 を行うことができる。 したがって、 上記半導体集積回路 1 は、 原始多項 式毎に定義される異なったガロア体による誤り訂正符号などに対する 符号化又は復号化処理に汎用的に利用することが可能である。半導体集 積回路 1 を例えば M O又は D V D向けのシステムに適用する場合にも、 ガロア乗算器を再設計することを要しない。 According to the semiconductor integrated circuit 1, the Galois multiplier 2 can perform multiplication on the Galois field according to the coefficients of the primitive polynomial given from the coefficient setting means 3. Therefore, the semiconductor integrated circuit 1 can be generally used for encoding or decoding of an error correction code or the like using a different Galois field defined for each primitive polynomial. Even when the semiconductor integrated circuit 1 is applied to a system for, for example, MO or DVD, it is not necessary to redesign the Galois multiplier.
例えば M 0及び D V Dの双方に対して情報記録及び記録情報再生を
行うデータ処理システムに前記半導体集積回路 1 を適用する場合にも、 単一の半導体集積回路 1 を M 0及び D V Dの双方に対する誤り訂正符 号の符号化及び復号化処理に利用することができる。例えば N種類の原 始多項式を用いるガロア乗算器を必要とするデータ処理システムを想 定した場合、各々の原始多項式に個別に対応する専用ハー ドウヱァとし てのハ一 ドワイヤー ドロジックによって個々のガロア乗算器を構成す る場合と、前記半導体集積回路 1 を用いてそのデータ処理システムを構 成する場合とを比較すると、システム全体として必要なガロア乗算器の 回路規模は、 前者に対して後者は約 1 / Nで済み、 対応すべき原始多項 式の種類が増えれば増える程、 回路規模縮小の効果は大きくなる。 《ガロア乗算器の第 1 の例》 For example, information recording and recorded information reproduction for both M0 and DVD Even when the semiconductor integrated circuit 1 is applied to a data processing system to be performed, the single semiconductor integrated circuit 1 can be used for encoding and decoding error correction codes for both M0 and DVD. For example, assuming a data processing system that requires Galois multipliers using N types of primitive polynomials, individual Galois multipliers using hardwired logic as dedicated hardware individually corresponding to each primitive polynomial When the data processing system is configured using the semiconductor integrated circuit 1, the circuit size of the Galois multiplier required for the entire system is about 1 unit for the former. / N, and the more primitive polynomials that need to be supported, the greater the effect of circuit scale reduction. 《First example of Galois multiplier》
前記乗算の (式 10) から (式 16) で示したように、 n ビッ 卜のガ口 ァ数の乗算では、 (n+1) ビッ 卜以上の次数に対しては、 原始多項式に より高次の項から順に次数を下げて、 最終結果を得ることができる。 例えばガロア体 G F (2 4 )の全ての原始多項式の乗算を可能とするに は、 前記(式 13)、 (式 15)の原始多項式を一般的な形で表現しておく必 要がある。 これを、 (式 17) に示す。 As shown in (Equation 10) to (Equation 16) of the above multiplication, in the multiplication of the n-bit GaP number, the higher the order of (n + 1) bits, the higher the primitive polynomial. The order can be reduced in order from the next term to get the final result. For example, in order to enable multiplication of all primitive polynomials in the Galois field GF (2 4 ), the primitive polynomials in (Equation 13) and (Equation 15) need to be expressed in a general form. This is shown in (Equation 17).
(式 17) X4 二 C3X + C2X2+ CTX1† C0X° (Equation 17) X 4 2 C 3 X + C 2 X 2 + CTX 1 † C 0 X °
ガロア体 G F (24)の 4ビッ 卜のガロア数 Xa (式 4)と Xb (式 5)に対す る多項式乗算結果を次数毎に整理した状態は第 2図の部分積加算の欄 に示されている。 この部分積加算の欄の記載からも明らかなように、当 該多項式乗算では、 次数 X 6、 x 5、 X 4が高次の項であるので、 (式 17) を用いて、 それら高次の次数を下げると (式 ) 〜 (式 20) のよ うになる。 4 bits Bok Galois number Xa (Equation 4) and Xb state that organizes polynomial multiplication result against the (Equation 5) for each degree of Galois field GF (2 4) is shown in the column of partial product addition of the second view Have been. As is clear from the description of the partial product addition column, in the polynomial multiplication, since the orders X 6 , x 5 , and X 4 are higher-order terms, the higher-order terms are calculated using (Equation 17). When the order of is reduced, it becomes as shown in (Equation) to (Equation 20).
(式 18) X6 = X4 X2 = (c3x3+ c2x2+ c^1† c。x。)x2 (Equation 18) X 6 = X 4 X 2 = (c 3 x 3 + c 2 x 2 + c ^ 1 † c. X.) X 2
= C3X5+ C2X + 。 3+ C0X'
= C3 (C3X3+ C2X2+ CTX1+ C0X°) X1 = C 3 X 5 + C 2 X +. 3 + C 0 X ' = C 3 (C 3 X 3 + C 2 X 2 + CTX 1 + C 0 X °) X 1
+ C2 (C3X3+ C2X2+ CTX1† C0X°)+ CTX3† C0X2 + C 2 (C 3 X 3 + C 2 X 2 + CTX 1 † C 0 X °) + CTX 3 † C 0 X 2
二 C3 (C3X + C2X3+ C,X2+ CQX1 ) Two C 3 (C 3 X + C 2 X 3 + C, X 2 + CQX 1 )
+ C2 (C3XJ+ C2X2+ CTX1+ C0X°)+ C,X3+ C0X2 + C 2 (C 3 X J + C 2 X 2 + CTX 1 + C 0 X °) + C, X 3 + C 0 X 2
二 C3 (C3(C3X3+ C2X2+ C ]+ C0X° )+ C2X3+ CTX2+ C0X' ) + c2 (c3x3+ C2X2+ c,x1+ c x。)+ c,x3+ C0X2 Two C 3 (C 3 (C 3 X 3 + C 2 X 2 + C] + C 0 X °) + C 2 X 3 + CTX 2 + C 0 X ') + c 2 (c 3 x 3 + C 2 X 2 + c, x 1 + cx.) + C, x 3 + C 0 X 2
+ c2c3x3+ C2X2+ C^TX1† C2C0X°+ CTXH C0X2 + c 2 c 3 x 3 + C 2 X 2 + C ^ TX 1 † C 2 C 0 X ° + CTXH C 0 X 2
= (c3 + cj x3+ (c2 + C0+ 030,+ C3C2) X2 + (c3c0+ 3C^ 2C^ ) X1 = (c 3 + cj x 3 + (c 2 + C 0 + 0 3 0, + C 3 C 2 ) X 2 + (c 3 c 0 + 3 C ^ 2 C ^) X 1
+ (c2c0 + C3C0) x° + (c 2 c 0 + C 3 C 0 ) x °
(式 19) X5 = X4 X1 = (C3X3+ C2X2+ CQX^X1 (Equation 19) X 5 = X 4 X 1 = (C 3 X 3 + C 2 X 2 + CQX ^ X 1
二 C3X4+ C2X3+ C,X2+ CQX1 2 C 3 X 4 + C 2 X 3 + C, X 2 + CQX 1
= c3 (c3x3+ c2x2+ c,x1+ c0x°) + c2x3+ c,x2+ C0X1 = c 3 (c 3 x 3 + c 2 x 2 + c, x 1 + c 0 x °) + c 2 x 3 + c, x 2 + C 0 X 1
= C3 X3+ C3C2X2+ CgC!X1† c3c x° + C2X3+ c,x2+ C0X1 二 (c3+ c2) xJ+ (c + c3c2) x2+ (c0+ C3C! ) x1+ C3C0 x° (式 20) x4 = c3x3+ c2x2+ c x1+ c0x° = C 3 X 3 + C 3 C 2 X 2 + CgC! X 1 † c 3 cx ° + C 2 X 3 + c, x 2 + C 0 X 1 two (c 3 + c 2 ) x J + (c + c 3 c 2 ) x 2 + (c 0 + C 3 C!) x 1 + C 3 C 0 x ° (Equation 20) x 4 = c 3 x 3 + c 2 x 2 + cx 1 + c 0 x °
前記 (式 17) 〜 (式 20) を前記 (式 10) に代入すると、 (式 21)を得 る By substituting (Equation 17) to (Equation 20) into (Equation 10), (Equation 21) is obtained.
(式 21) Xa * Xb = (a3b3)((c3 + c )x3+(c2 + c + cic + c3c2)x2 (Equation 21) Xa * Xb = (a 3 b 3) ((c 3 + c) x 3 + (c 2 + c + c i c + c 3 c 2) x 2
+ (C3C0+ 030!+ CjC, ) x1+ (c2c0 + C3C0) x° ) + (C 3 C 0 + 0 3 0! + CjC,) x 1 + (c 2 c 0 + C 3 C 0 ) x °)
+ (a3b2+a2b3) ( (c3+ c2) x°+ (c, + c3c2) x2+ (c0+ CgC, ) x,+ c3c0 x°) + (a3b1+a2b2+a1b3)(c3x3+ c2x2+ ο,χ^ c0x°) + (a 3 b 2 + a 2 b 3 ) ((c 3 + c 2 ) x ° + (c, + c 3 c 2 ) x 2 + (c 0 + CgC,) x, + c 3 c 0 x °) + (a 3 b 1 + a 2 b 2 + a 1 b 3 ) (c 3 x 3 + c 2 x 2 + ο, χ ^ c 0 x °)
+(a3bo+a2b,+a1b2+a0b3)x3+(a2b0+alb1+aob2)x2 + (a 3 b o + a 2 b, + a 1 b 2 + a 0 b 3 ) x 3 + (a 2 b 0 + a l b 1 + a o b 2 ) x 2
+ ( a^o+aob x1 + (a0b0)x° + (a ^ o + aob x 1 + (a 0 b 0 ) x °
前記 (式 21)の意味は、 上記より明らかであろうが、 更に付言すれば、 多項
式乗算によって得られる部分積の高次の項 x 6、 X 5、 X 4の係数を(式 17) の原始多項式の一般形を用いて、 部分積の低次の項 X 3、 X 2、 X 1、 X 0に 置き換えたものである。 第 2図の補正項加算の欄に示される計算式は、 前記 高次の項 X 6、 x 5、 X 4を低次の項 X 3、 x 2、 x 1、 x °に置き換えた式 である。 そのような置き換えのための演算を補正項加算、 補正項加算によつ て得られた低次の項 x 3、 x 2、 X 1、 x °を補正項と称する。第 2図の部分 積加算の欄に例示されるように、 2個のガロア数の多項式乗算を部分積加算、 それによつて得られる各項を部分積という。 The meaning of the above (Equation 21) will be clear from the above, but it is further added that Using the general form of the primitive polynomial of (Equation 17), the higher-order terms x 6 , X 5 , and X 4 of the partial product obtained by the equation multiplication are calculated using the lower-order terms X 3 , X 2 , It is replaced with X 1 and X 0 . The calculation formula shown in the column of correction term addition in FIG. 2 is a formula in which the higher-order terms X 6 , x 5 , and X 4 are replaced with lower-order terms X 3 , x 2 , x 1 , and x °. is there. Correction term added to operations for such replacement, the correction term was collected using cowpea in addition low-order sections x 3, x 2, X 1 , x ° is referred to as a correction term. As exemplified in the column of partial product addition in FIG. 2, a polynomial multiplication of two Galois numbers is called partial product addition, and each term obtained by that is called a partial product.
前記 (式 21) の説明から理解されるように、 ガロア数の乗算を汎用 的に行うには、 (式 21) の原始多項式の係数 c。 〜 c 3に、 必要な原始 多項式の係数を設定すれば、任意の原始多項式に対する乗算結果が得ら れる。 あるいは、 (式 21) の各次数の係数となる値をあらかじめ c。〜 c 3の間の論理演算により求めておき、 これらの値を設定することによ り、 任意の原始多項式に対する乗算結果が得られる。 As can be understood from the description of the above (Equation 21), in order to multiply the Galois number for general purpose, the coefficient c of the primitive polynomial of (Equation 21) is used. In ~ c 3, by setting the coefficient of the necessary primitive polynomial multiplication result for any primitive polynomial is obtained, et al. Alternatively, a value that is a coefficient of each order of (Equation 21) is set in advance c. Leave obtained by logical operation between ~ c 3, Ri by the setting these values, the multiplication result for any primitive polynomial is obtained.
前記 (式 14) 、 (式 16) で行った乗算を(式 21)に当てはめてみる。 乗数 ( : X a) の係数を (a3, a2, a,, a0) = ( 1 , 0, 1 , 0 )、 被乗数 ( : X b) の係数を (b3, b2, b b0) = ( 0, 1, 1, 1 )、 と するとき、 The multiplications performed in (Equation 14) and (Equation 16) will be applied to (Equation 21). Multiplier: coefficients (X a) (a 3, a 2, a ,, a 0) = (1, 0, 1, 0), the multiplicand (: X b) the coefficient of (b 3, b 2, bb 0 ) = (0, 1, 1, 1),
前記原始多項式 1 ( : x4+ x1+ 1= 0) の係数は、 前記 (式 17) の一 般形に対応させると、 The primitive polynomial 1: coefficients of (x 4 + x 1 + 1 = 0) is made to correspond to one般形of the equation (17),
(c3, c2 c, c0) = ( 0, 0, 1, 1 )、 (c 3 , c 2 c, c 0 ) = (0, 0, 1, 1),
であるから、 前記(式 21)に上記各係数を代入すれば、 乗算は以下のよ うになる。 Therefore, if the above coefficients are substituted into the above (Equation 21), the multiplication is as follows.
Xa * Xb =(1*0) ((0 +0) χ3+(0 +1+0+0)χ2+ (0+0+0)χ1+ (0+0)χ°) Xa * Xb = (1 * 0) ((0 +0) χ 3 + (0 + 1 + 0 + 0) χ 2 + (0 + 0 + 0) χ 1 + (0 + 0) χ °)
+(1*1+0*0) ((0+0) χ3+ (1 +0) χ2+ (1+0) χ1+ 0χ°)+ (1 * 1 + 0 * 0) ((0 + 0) χ 3 + (1 +0) χ 2 + (1 + 0) χ 1 + 0χ °)
+ (1*1+0*1+1*0)(0χ3+0χ2+1χ1 + 1χ°)
+(1*1+0*1+1*1+0*0)x3+(0*1+1*1+0*1 )xz + (1 * 1 + 0 * 1 + 1 * 0) (0χ 3 + 0χ 2 + 1χ 1 + 1χ °) + (1 * 1 + 0 * 1 + 1 * 1 + 0 * 0) x 3 + (0 * 1 + 1 * 1 + 0 * 1) x z
+(1*1+0*1) x1+(0*1)x° + (1 * 1 + 0 * 1) x 1 + (0 * 1) x °
二 x1 + 1 Two x 1 + 1
上記と同一の乗数 ( : X a) 及び被乗数 ( : X b) にっき、 原始多項 式 2 ( : x4+ x3+ 1= 0) の係数 (c3, c2, c,, c0) = ( 1, 0, 0, 1 )に対 して、 (式 21)を適用し、 当該 (式 21) に各係数を代入すると、 乗算は以 下のようになる。 With the same multiplier (: X a) and multiplicand (: X b) as above, the coefficients (c 3 , c 2 , c ,, c 0 ) of primitive polynomial 2 (: x 4 + x 3 + 1 = 0 ) Applying (Equation 21) to = (1, 0, 0, 1) and substituting each coefficient into (Equation 21), the multiplication is as follows.
Xa*Xb 二 (1*0) ((1+0) x3+ ( 0+1 +0 + 0 )x2+( 1 +0 + 0 )x1 + ( 0+1 )x°) Xa * Xb 2 (1 * 0) ((1 + 0) x 3 + (0 + 1 +0 + 0) x 2 + (1 +0 + 0) x 1 + (0 + 1) x °)
+ (1氺 1+0* 0) ((1+0) x3+ (0 +0) x2+ (1+0) xH 1x°) +(1 * 1+0* 1+1 * 0) (IxHOx Ox^lx0) + (1 氺 1 + 0 * 0) ((1 + 0) x 3 + (0 +0) x 2 + (1 + 0) xH 1x °) + (1 * 1 + 0 * 1 + 1 * 0) (IxHOx Ox ^ lx 0 )
+ (1氺 1+0 * 1+1氺 1+0 * 0)x3 + (0 * 1+1氺 1+0氺 1 )x2 + (1 * 1+0* 1 ) x^CO* 1 )x° + (1 氺 1 + 0 * 1 + 1 氺 1 + 0 * 0) x 3 + (0 * 1 + 1 氺 1 + 0 氺 1) x 2 + (1 * 1 + 0 * 1) x ^ CO * 1) x °
: X2 : X 2
このことより、 (式 14) 、 (式 16) と同じ結果が得られることがわか る。 This shows that the same results as (Equation 14) and (Equation 16) can be obtained.
第 3図には上記手法に従った論理を有するガロア乗算器 2の具体例 が示される。 ガロア乗算器 2は、部分積加算部 1 1 、補正項加算部 1 2 及び出力加算部 1 3によって構成される。前記部分積加算部 1 1 は、ガ ロア体 G F (2 n)の乗数と被乗数の部分積毎の乗数の係数と被乗数の係 数との部分積加算を行う。具体的には第 2図の部分積加算の欄に示され る論理をそのまま実現している。前記補正項加算部 1 2は、前記部分積 加算部 1 1 によって得られた π + 1 次以上の部分積の係数を n次以下 の部分積の係数に補正する演算を行う。具体的には第 2図の補正項加算 の欄に示される論理をそのまま実現している。出力加算部 1 3は前記補 正項加算部 1 2の出力と前記部分積加算部 1 1 の下位 nビッ 卜の部分 積係数とのガロア和( 2ビッ 卜のガロア体に対する加算処理と同じ) を
演算する。具体的には対応する次数の係数を排他的論理和で加算して出 力 ο 0〜ο 3を得る。 FIG. 3 shows a specific example of the Galois multiplier 2 having the logic according to the above method. The Galois multiplier 2 includes a partial product adder 11, a correction term adder 12, and an output adder 13. The partial product adder 11 performs partial product addition of a multiplier coefficient and a multiplicand coefficient for each partial product of the Galois field GF (2 n ) and the multiplicand. Specifically, the logic shown in the column of partial product addition in FIG. 2 is realized as it is. The correction term addition unit 12 performs an operation of correcting the coefficient of the π + 1 or higher order partial product obtained by the partial product addition unit 11 into the coefficient of the nth order or lower partial product. Specifically, the logic shown in the column of correction term addition in FIG. 2 is realized as it is. The output adder 13 is a Galois sum of the output of the correction term adder 12 and the lower n-bit partial product coefficient of the partial product adder 11 (similar to the addition process for a 2-bit Galois field) To Calculate. Specifically, the outputs ο 0 to ο 3 are obtained by adding the coefficients of the corresponding orders by exclusive OR.
前述の通り、 前記ガロア体 GF(2 n)の元の間の乗算は、 多項式の加算 で定義され、 多項式の係数は GF(2)の元であるから、 係数の加算、 乗算 は mod 2の計算で行えばよいので、 部分積加算部 1 1 、 補正項加算部 1 2及び加算出力部 1 3はアンドゲー 卜 ( A N D素子) と排他的論理和ゲ — 卜 ( e x O R ) を用いて構成されている。 As described above, the multiplication between the elements of the Galois field GF (2 n ) is defined by addition of a polynomial, and the coefficients of the polynomial are elements of GF (2). Since the calculation can be performed, the partial product addition unit 11, the correction term addition unit 12, and the addition output unit 13 are configured by using an AND gate and an exclusive OR gate (ex OR). ing.
第 3図において、前記補正項加算部 1 2は、第 1 乃至第 3の論理演算 回路に分類することができる。第 1 の論理演算回路は、部分積加算部 1 1 によって得られた n + 1 次以上の部分積の係数を n次以下の部分積 の係数に補正するための補正情報を原始多項式の係数 c 3〜c。に基づ いて予め演算する論理回路であり、ゲ一 卜列 1 2 G , 1 2 Eによって構 成される。前記第 2の論理演算回路は、前記部分積加算部 1 1 によって 得られた n + 1 次以上の部分積の係数毎に当該係数と対応する補正情 報との積を採る論理回路であり、 ゲ— 卜列 1 2 B , 1 2 D , 1 2 Fによ つて構成される。前記第 3の論理演算回路は、夫々の第 2の論理演算回 路の出力を加算する論理回路であり、 ゲ一 卜列 1 2 A, 1 2 Cによって 構成される。 In FIG. 3, the correction term adding section 12 can be classified into first to third logical operation circuits. The first logical operation circuit converts the correction information for correcting the coefficient of the partial product of order n + 1 or higher obtained by the partial product adder 11 into the coefficient of the partial product of order n or less into the coefficient c of the primitive polynomial. 3 to c. This is a logic circuit that calculates in advance on the basis of, and is composed of gate rows 12G and 12E. The second logic operation circuit is a logic circuit that takes, for each coefficient of the n + 1 or higher-order partial product obtained by the partial product addition unit 11, a product of the coefficient and the corresponding correction information, It is composed of gate rows 12B, 12D, and 12F. The third logical operation circuit is a logical circuit for adding the outputs of the respective second logical operation circuits, and is constituted by gate arrays 12A and 12C.
この構成によれば、 ゲ— 卜列 1 2 G , 1 2 Eによって構成される第 1 の論理演算回路の出力は原始多項式の係数 C 3〜C。によって予め演算 されているから、部分積加算部による部分積加算結果を入力することに より、 即座に補正項加算演算の結果を得ることができる。 According to this configuration, the output of the first logical operation circuit constituted by the gate trains 12 G and 12 E has the coefficients C 3 to C of the primitive polynomial. , The result of the correction term addition operation can be immediately obtained by inputting the result of the partial product addition by the partial product addition unit.
第 3図の構成に利用されるゲ一 卜数は、部分積加算部 1 1 が 2 5個、 補正項加算部 1 2が 3 5個、 出力加算部 1 3が 4個であり、全体として 64個の A N D素子及び e x 0 Rが必要とされる。 また、第 3図におい て、丸で囲んだ数字は、 e X 0 Rと A N D素子のそれぞれの信号伝達時
間を 1 とした場合に入力から当該数字が付されている地点までの所要 伝達時間を意味する。 クリティカルパスは出力ビッ 卜 o 3を得るための 経路とされる。 尚、 ゲー ト列 1 2 G , 1 2 Eによって構成される第 1 の 論理演算回路の出力は原始多項式の係数 C3〜C。によって予め演算さ れているから、ゲー ト列 1 2 Fの出力が確定するまでの伝達時間は②に されている。 The number of gates used in the configuration of Fig. 3 is 25 for the partial product adder 11, 11 for the correction term adder 12, and 4 for the output adder 13. 64 AND elements and exOR are required. In Fig. 3, the circled numbers indicate the signal transmission of each of eXOR and the AND element. When the interval is set to 1, it means the required transmission time from the input to the point marked with the number. The critical path is a path for obtaining the output bit Bok o 3. The outputs of the first logical operation circuit composed of the gate arrays 12 G and 12 E are the primitive polynomial coefficients C 3 to C 3 . , The transmission time until the output of the gate train 12F is determined is set to ②.
《ガロア乗算器の第 2の例》 《Second example of Galois multiplier》
ガロア乗算器 2における補正項加算の論理は、規則性が増せば、それ を構成するための論理ゲー 卜のレイァゥ 卜が簡単になる。 また、ゲ一 卜 直列段数が少なくなれば補正加算の演算処理を高速化できる。 If the regularity of the logic of the correction term addition in the Galois multiplier 2 increases, the layout of the logic gates for constructing the logic becomes simple. In addition, if the number of gate series stages is reduced, the arithmetic processing of correction and addition can be sped up.
補正項加算部の別の例を説明する。 前記 (式 18) 〜 (式 20) の演算 において補正項の演算を規則的に行う論理構成について説明する。ここ でも上記同様の 4ビッ 卜のガロア数を一例とする。 前記次数が X6, X 5 , X 4の高次の項に対する低次の項への置き換えのための別の展開を (式 22) 〜 (式 24) に示す。 Another example of the correction term adding unit will be described. A description will be given of a logical configuration in which the operations of the correction terms are regularly performed in the operations of (Equation 18) to (Equation 20). Here, the 4-bit Galois number as described above is taken as an example. (Equation 22) to (Equation 24) show other expansions for replacing higher-order terms of X 6 , X 5 , and X 4 with lower-order terms.
(式 22) X6 = X4 X2 二 (c3x3+ c2x2+ c,x1+ c0x°)x2 (Equation 22) X 6 = X 4 X 2 (c 3 x 3 + c 2 x 2 + c, x 1 + c 0 x °) x 2
= C3X5+ C2X4+ C,X3+ C0X' = C 3 X 5 + C 2 X 4 + C, X 3 + C 0 X '
= c3 (c3x4+ c2x3+ c,x2+ c0x1 ) + c2 x4+ c,xd+ C0X2 = c 3 (c 3 x 4 + c 2 x 3 + c, x 2 + c 0 x 1 ) + c 2 x 4 + c, x d + C 0 X 2
: ( C3+ C2 ) X4+ C3 (C2X3+ CTX2+ CQX1 ) + c,x3+ C0X2 二 (c3+ c2 ) (c3x3+ c2x2+ c^x] + c0x°) : (C 3 + C 2) X 4 + C 3 (C 2 X 3 + CTX 2 + CQX 1) + c, x 3 + C 0 X 2 two (c 3 + c 2) ( c 3 x 3 + c 2 x 2 + c ^ x ] + c 0 x °)
+ c3 (c2x3+ c,x2+ C0X1 ) + ο,χ3+ C0X2 + c 3 (c 2 x 3 + c, x 2 + C 0 X 1 ) + ο, χ 3 + C 0 X 2
(式 23) χδ = x4 x1 = (c3x3+ c2x2+ c,x1+ c0x°)x1 (Equation 23) δ δ = x 4 x 1 = (c 3 x 3 + c 2 x 2 + c, x 1 + c 0 x °) x 1
= c3x4+ c2x3+ c,x2+ c0x1 = c 3 x 4 + c 2 x 3 + c, x 2 + c 0 x 1
= C3 (C3X3+ C2X2+ C,X1+ C0X°) + C2X3+ C,X2+ CQX1 (式 24) x4 : c3x3+ c2x2+ c,x1+ c0x° = C 3 (C 3 X 3 + C 2 X 2 + C, X 1 + C 0 X °) + C 2 X 3 + C, X 2 + CQX 1 (Equation 24) x 4 : c 3 x 3 + c 2 x 2 + c, x 1 + c 0 x °
前記 (式 22) 〜 (式 24) を前記 (式 10) に代入して整理すると、 第
4 図の補正項加算の欄に示される計算式を得ることができる。 これは前記同 様、 前記高次の項 X 6、 X 5、 X 4を低次の項 X 3、 X 2、 x 1、 x °に置き 換えた式になる。 Substituting the above (Equation 22) to (Equation 24) into the above (Equation 10) and rearranging, 4 The calculation formula shown in the column for adding correction terms in the figure can be obtained. This is an expression in which the higher-order terms X 6 , X 5 , and X 4 are replaced with lower-order terms X 3 , X 2 , x 1 , and x °, as described above.
第 5図には第 4 図の補正項加算の欄に記載された論理を実現した補 正項加算部 1 4が示される。この補正項加算部 1 4の論理構成から明ら かなように、排他的論理和ゲー 卜とアンドゲ— 卜の配列は第 3図に比べ て規則的になっている。従って、第 3図に比べて第 5図の方が半導体集 積回路のレイァゥ 卜設計を容易化できる。 FIG. 5 shows a correction term adder 14 that realizes the logic described in the column of correction term addition in FIG. As is apparent from the logical configuration of the correction term adding unit 14, the arrangement of the exclusive OR gate and the AND gate is more regular than that in FIG. Therefore, the layout design of the semiconductor integrated circuit in FIG. 5 can be easier than that in FIG.
第 5図の補正項加算部 1 4において前記第 1 の論理回路は、ゲ— 卜列 1 4 G , 1 4 Eによって構成される。前記第 2の論理演算回路は、 ゲー 卜列 1 4 B , 1 4 D , 1 4 Fによって構成される。前記第 3の論理演算 回路は、 ゲ一 卜列 1 4 A , 1 4 Cによって構成される。 In the correction term adding unit 14 in FIG. 5, the first logic circuit is constituted by gate rows 14G and 14E. The second logical operation circuit is constituted by gate rows 14B, 14D, and 14F. The third logical operation circuit is constituted by gate rows 14A and 14C.
第 5図の構成に利用されるゲ一 卜数は、部分積加算部 1 1及び出力加 算部 1 3が第 3図の構成と同じであるが、補正項加算部 1 2は 3 9個の ゲ一 卜を用いており、全体として 6 8個の A N D素子及び e x 0 Rが必 要とされる。 また、 第 5図において、 丸で囲んだ数字は、 e X 0 Rと A D素子のそれぞれの信号伝達時間を 1 とした場合に入力から当該数 字が付されている地点までの所要伝達時間を意味する。クリティカルパ スは出力ビッ 卜 o 3を得るための経路とされる。 したがって、 第 5図に 示されるガロア乗算器は演算速度の点では第 3図の構成と実質的に変 わりないが、前述の通り、補正項加算部 1 4のレイアウ トという点で優 れている。 The number of gates used in the configuration of FIG. 5 is the same as that of FIG. 3 for the partial product adder 11 and the output adder 13, but the correction term adder 12 has 39 In this case, 68 AND elements and exOR are required as a whole. In Fig. 5, the circled numbers indicate the required transmission time from the input to the point where the number is given, assuming that the signal transmission time of each of eXOR and the AD element is 1. means. Critical paths are the paths for output bit Bok o 3. Therefore, the Galois multiplier shown in FIG. 5 is not substantially different from the configuration in FIG. 3 in terms of the operation speed, but is superior in the layout of the correction term adder 14 as described above. I have.
《ガロア乗算器の第 3の例》 《Third example of Galois multiplier》
ガロア乗算器の前記二つの例は、 前記高次の項 X 6、 χ 5、 X 4を低次 の項 x 3、 x 2、 x 1、 x °に置き換える方式として、 原始多項式の係数 c nの演算を、乗数、被乗数の係数 a n、 b nの演算に対して予め独立に行
うようにした。 ここでは、 高次の項 X 3、 X 2、 x 1、 x °の次数を下げ る手法として、 原始多項式の係数 c nと乗数、 被乗数の係数 a n、 b n の演算を行いながら、逐次、 1次毎に次数を下げる構成について説明す る o The two examples of the Galois multiplier are based on a method of replacing the higher-order terms X 6 , χ 5 , and X 4 with lower-order terms x 3 , x 2 , x 1 , and x ° as coefficients of a primitive polynomial c n The calculation of the multiplier and the multiplicand coefficients an and b n I did it. Here, as a method of lowering the order of the higher-order terms X 3 , X 2 , x 1 , and x °, the coefficients c n and the multiplier of the primitive polynomial and the coefficients a n and b n of the multiplicand are calculated successively. Explain the configuration to reduce the order for each order o
前記 (式 18) 〜 (式 20) の X 6、 x 5、 X 4の夫々の項の次数を一つ だけ下げると When the order of each of the terms X 6 , x 5 , and X 4 in (Equation 18) to (Equation 20) is reduced by one,
(式 25) x6= c3x5+ c2x,+ c,x3+ c0x2 (Equation 25) x 6 = c 3 x 5 + c 2 x , + c, x 3 + c 0 x 2
(式 26) x5二 c3x4+ c2x3+ c,x2+ c0x1 (Equation 26) x 5 2 c 3 x 4 + c 2 x 3 + c, x 2 + c 0 x 1
(式 27) x4= c3x3+ c2x2+ c,x1+ c0x° (Equation 27) x 4 = c 3 x 3 + c 2 x 2 + c, x 1 + c 0 x °
となる。 これらを前記 (式 10) に代入して逐次、 次数を下げると (式 28) Xa*Xb = (a3b3)(c3x5+ c2x4+ c,x3+ c0x2) Becomes Substituting these into (Equation 10) above and sequentially reducing the order, (Equation 28) Xa * Xb = (a 3 b 3 ) (c 3 x 5 + c 2 x 4 + c, x 3 + c 0 x 2 )
+(a3b2+a2b3) x5 + (a 3 b 2 + a 2 b 3 ) x 5
+ (a3bl+a2b2+a1b3) x4 + (a 3 b l + a 2 b 2 + a 1 b 3 ) x 4
+ (a3b0+a2bl+a1b2+a0b3) x3+(a2b0+a1bl+a0b2) x2 + ( a +aobJ x1 + (a。b。) x° + (a 3 b 0 + a 2 b l + a 1 b 2 + a 0 b 3 ) x 3 + (a 2 b 0 + a 1 b l + a 0 b 2 ) x 2 + (a + aobJ x 1 + (a.b.) x °
二((a3b3)c3+(a3b2+a2b3) ) ( c3x4+ c2x3+ c,x2+ c。x,) + (a3b3) (c2x4+ c,x3+ c。x2) Two ((a 3 b 3) c 3 + (a 3 b 2 + a 2 b 3)) (c 3 x 4 + c 2 x 3 + c, x 2 + c.x,) + (a 3 b 3 ) (c 2 x 4 + c, x 3 + c. x 2 )
+ (a3b1+a2b2+a1b3 ) x4 + (a 3 b 1 + a 2 b 2 + a 1 b 3 ) x 4
+ (a3b0+a2b1+a1b2+a0b3) x3 + (a2b0+alb1+a0b2) x2 + ( a^o+aob! ) x1 + (a0b0) x° + (a 3 b 0 + a 2 b 1 + a 1 b 2 + a 0 b 3 ) x 3 + (a 2 b 0 + a l b 1 + a 0 b 2 ) x 2 + (a ^ o + aob !) x 1 + (a 0 b 0 ) x °
=( ( (a3b3)c3+(a3b2+a2b3) )c3+(a3b3 )C2 = (((a 3 b 3 ) c 3 + (a 3 b 2 + a 2 b 3 )) c 3 + (a 3 b 3 ) C2
+ (a3bl+a2b2+a1b3 ) )x4 + (a 3 b l + a 2 b 2 + a 1 b 3 )) x 4
+( (a3b3)c3+(a3b2+a2b3) )( c2x3+ c,x2+ c。x1) +(a3b3) (c,x3+ c0x2) + ((a 3 b 3 ) c 3 + (a 3 b 2 + a 2 b 3 )) (c 2 x 3 + c, x 2 + c.x 1 ) + (a 3 b 3 ) (c, x 3 + c 0 x 2 )
+ (a3b0+a2b1+alb2+aob3) x3 + (a2b0+alb1+a0b2 ) x2 + ( a^o+aob x1 + (a0b0) x°
二(((a3b3)c3 + (a3b2+a2b3) )c3+(a3b3)c2 + (A 3 b 0 + a 2 b 1 + a l b 2 + a o b 3) x 3 + (a 2 b 0 + a l b 1 + a 0 b 2) x 2 + (a ^ o + aob x 1 + (a 0 b 0 ) x ° Two (((a 3 b 3 ) c 3 + (a 3 b 2 + a 2 b 3 )) c 3 + (a 3 b 3 ) c 2
+ (a3b1+a2b2+alb3 ) ) (c3x3+ c2x2+ c,x1+ c0x°) +((a3b3)c3+(a3b2+a2b3))( c2x3+ c,x2+ c。x1) + (a3b3) (c,x3+ c。x2) + (a 3 b 1 + a 2 b 2 + a l b 3 )) (c 3 x 3 + c 2 x 2 + c, x 1 + c 0 x °) + ((a 3 b 3 ) c 3 + (a 3 b 2 + a 2 b 3 )) (c 2 x 3 + c, x 2 + c.x 1 ) + (a 3 b 3 ) (c, x 3 + c.x 2 )
+(a3b0+a2b1+a1b2+a0b3) x3 + (a 3 b 0 + a 2 b 1 + a 1 b 2 + a 0 b 3 ) x 3
+ (a2b0+a1b1+a0b2 ) x2 + (a 2 b 0 + a 1 b 1 + a 0 b 2 ) x 2
+ ( a^o+aob! ) x1 + (a0b0) x° + (a ^ o + aob!) x 1 + (a 0 b 0 ) x °
となる。上記式の内容を整理すると、第 6図の補正項加算の欄に記載の 内容になる。 この論理を論理回路で実現すると、第 7図の補正項加算部 1 5を実現することができる。 Becomes By rearranging the contents of the above equation, the contents are as described in the column for adding correction terms in Fig. 6. If this logic is realized by a logic circuit, the correction term adding unit 15 in FIG. 7 can be realized.
すなわち、 第 7図において補正項加算部 1 5は、 ガロア体 G F ( 2 n )、 特に n = 4の場合の 4ビヅ 卜のガロア数に対するガロア乗算に適用さ れる場合を一例としている。 これに即して説明すると、補正項加算部 1 5は、 n (= 4 ) 個の単位回路 1 5 Aの配列を n— 1 (= 3 ) 列備え、 列方向の単位回路 1 5 Aの次数は 1 から 2 n— 2 (= 6 ) とされ、 第 1 列目の配列は n ( = 4 ) 個目が次数 2 n - 2 (= 6 ) とされ、 2列目の 配列は n ( = 4 ) 個目が次数 2 n - 3 (= 5 ) とされ、 順次、 次数を下 げて n— 1 (= 3 ) 列目の配列は n ( = 4 ) 個目が次数 n ( = 4 ) とさ れる。前記配列の各列の単位回路は、列毎に共通の入力として前列の配 列の最上位の単位回路の出力とそれに対応する部分積加算の値との排 他的論理和ゲー 卜 ( e X 0 R ) 1 5 Bによるガロア和を受け、 この共通 の入力と各列の単位回路に共通に入力される n ( = 4 ) ビッ 卜の原始多 項式の係数 C 3〜C。とを受けてアン ドゲー ト 1 5 Cによる論理積を生 成すると共に、当該論理積の値と前列の同一次数位置の単位回路の出力 との排他的論理和ゲー卜 ( e X 0 R ) 1 5 Dによるガロア和を生成して 出力とする機能を有する。 1列目の単位回路は、夫々に前記共通の入力
として部分積加算の最上位である次数 2 n— 1 ( = 7 )の値が入力され る、 前記排他的論理和ゲ一 卜 (排他的論理和回路) 1 5 Dを有しない。 2列目及びそれよりも下位の配列の単位回路は、前記共通の入力として、 一つ前の配列の最上位の単位回路の出力とそれに対応する部分積加算 の値との前記排他的論理和ゲ一 卜 ( e x O R ) 1 5 Bによるガロア和を 受けて、 出力を生成する。各配列の最下位の単位回路は、 前記排他的論 理和ゲー ト 1 5 Dを有しない。このように構成された補正項加算部 1 5 は、 n - 1 ( = 3 ) 列目の n (二 4 ) 個の単位回路の出力を補正項加算 の出力とし、 当該補正項加算の出力と部分積加算の下位 n (二 4 ) ビッ 卜とのガロア和を得て、 乗算結果とする。 That is, in FIG. 7, an example is shown in which the correction term adder 15 is applied to Galois field multiplication with respect to the Galois field GF (2 n ), particularly the 4-bit Galois number when n = 4. Explaining this, the correction term adder 15 has an array of n (= 4) unit circuits 15 A in n−1 (= 3) columns, and the column-wise unit circuit 15 A The order is from 1 to 2 n— 2 (= 6), the array in the first column is n (= 4), the order is 2 n-2 (= 6), and the array in the second column is n ( = 4) -th order is 2 n-3 (= 5), and the array of the n- 1 (= 3) -th column is sequentially reduced in order. ). The unit circuit in each column of the array is an exclusive OR gate (e X) of the output of the uppermost unit circuit of the array in the preceding column and the corresponding partial product addition value as a common input for each column. 0 R) Receives the Galois sum of 15 B, and this common input and n (= 4) bits of the primitive polynomial coefficients C 3 to C that are commonly input to the unit circuits of each column. In response to this, an AND gate is generated by the AND gate 15 C, and an exclusive OR gate (eXOR) 1 of the value of the AND and the output of the unit circuit at the same order position in the front row is generated. It has a function to generate Galois sum by 5D and output it. The unit circuits in the first column have the common input The exclusive OR gate (exclusive OR circuit) 15D to which the value of the order 2 n−1 (= 7), which is the highest order of the partial product addition, is input. The unit circuits of the second column and lower arrays are the exclusive OR of the output of the uppermost unit circuit of the immediately preceding array and the corresponding partial product addition value as the common input. Gate (ex OR) Generates output by receiving Galois sum by 15B. The lowest unit circuit of each array does not have the exclusive OR gate 15D. The correction term adder 15 configured in this way uses the outputs of the n (2 4) unit circuits in the n-1 (= 3) column as the output of the correction term addition, and outputs the output of the correction term addition and Obtain the Galois sum with the lower n (2 4) bits of the partial product addition and obtain the multiplication result.
この補正項加算部 1 5の論理構成から明らかなように、排他的論理和 ゲ— 卜とアン ドゲ一 卜の配列は第 5図に比べて格段に規則的になって いる。従って、第 5図に比べて第 7図の方が半導体集積回路のレイァゥ 卜設計を容易化できる。 As is clear from the logical configuration of the correction term adder 15, the arrangement of the exclusive OR gate and the AND gate is much more regular than in FIG. Therefore, the layout design of the semiconductor integrated circuit in FIG. 7 can be easier than that in FIG.
第 7図の構成において、部分積加算部 1 1及び出力加算部 1 3は第 5 図の構成と同じである力 補正項加算部 1 5は 2 0個のゲ— 卜で構成さ れ、全体として 4 9個の A N D素子及び e x 0 Rで実現されている。 ま た、 第 7図において、 丸で囲んだ数字は、 前記同様に、 e X 0 Rと A N D素子のそれぞれの信号伝達時間を 1 とした場合に入力から当該数字 が付されている地点までの所要伝達時間を意味する。クリティカルパス は出力ビッ 卜 o 3を得るための経路とされ、 その時間は第 5図よりも長 〈なっている。 したがって、第 7図に示されるガロア乗算器は演算速度 の点では第 5図の構成よりも劣るが、補正項加算部 1 5のレイアウ トと いう点では格段に優れている。 In the configuration of FIG. 7, the partial product adder 11 and the output adder 13 are the same as those in FIG. 5. The force correction term adder 15 is composed of 20 gates. This is realized by 49 AND elements and exOR. Also, in FIG. 7, the numbers enclosed by circles are, as described above, the distance from the input to the point where the number is attached when the signal transmission time of each of the eXOR and the AND element is set to 1. Means the required transmission time. The critical path is a path for obtaining the output bit Bok o 3, that time has become <length than the fifth FIG. Therefore, the Galois multiplier shown in FIG. 7 is inferior to the configuration of FIG. 5 in terms of operation speed, but is much better in terms of the layout of the correction term adder 15.
《ガロア乗算器の第 4の例》 《Fourth example of Galois multiplier》
今まで説明したガロア乗算器は乗数及び被乗数のビッ 卜数に対して
原始多項式を一切限定していない前記 (式 17 ) に示されるような一般 式を用いてその論理を構成した。 しかしながら、例えば 4ビッ 卜のガロ ァ体 G F ( 2 4 )の原始多項式は 2種類であることが知られているから、 原始多項式を完全一般式とする論理構成には無駄がある。そこで、使用 可能な範囲で原始多項式を限定すれば、いくつかの次数の係数を常にゼ 口にすることができる場合が有り、 これによつて、 その係数に関する補 正項加算部のハー ドウエアを部分的に省略でき、少ない論理規模でガ口 ァ乗算器を構成できるようになる。これまで説明してきた 4ビッ 卜のガ ロア数の例では、 原始多項式として前記(式 13 )、 (式 15 )があり、 両方 の原始多項式を扱う場合でも次数 X 2の係数 c 2はゼロである。 したが つて、例えば第 6図及び第 7図における補正項加算若しくは補正項加算 部 1 5の c 2に関連する論理は実質的に不要である。 The Galois multipliers described so far are based on the number of bits in the multiplier and multiplicand. The logic was constructed using the general formula as shown in the above (Equation 17) which does not limit the primitive polynomial at all. However, for example, from a primitive polynomial of 4 bits Bok Gallo § body GF (2 4) are known to be two types, there is a waste in the logical structure of the primitive polynomial and complete formula. Therefore, if the primitive polynomial is limited to the extent that it can be used, some order coefficients may always be zero, which may make the hardware of the correction term adder for those coefficients inefficient. It can be partially omitted, and it becomes possible to configure a Gaa multiplier with a small logical scale. In the example of 4-bit Bok moth lower numbers described so far, examples of the primitive polynomial (Equation 13), (Equation 15) There is, coefficients c 2 of degree X 2 even when dealing with both primitive polynomial is zero is there. Was but connexion, for example, logic associated with the correction term addition or c 2 correction term addition section 1 5 in FIG. 6 and FIG. 7 is substantially unnecessary.
第 8図には、 前記(式 17 )の原始多項式の一般形において、 次数 X 2の 係数 c 2がゼロである場合を想定したときの、 補正項加算部の論理が補 正項加算の欄に示される。第 9図には、 その論理を実現した補正項加算 部 1 6の構成が示される。 The FIG. 8, in the general form of the primitive polynomial (Equation 17), when assuming a case coefficients c 2 of degree X 2 is zero, the logic of the correction term addition portion of the auxiliary Seiko addition field Is shown in FIG. 9 shows a configuration of the correction term adder 16 that realizes the logic.
このような構成により、補正項加算部 1 6の論理規模が縮小され、ゲ 一卜直列段数も少なくなり、 レイァゥ 卜の容易化、演算処理速度の増強、 の双方を促進することができる。第 9図は、第 7図の構成を更に発展さ せた構造を一例として示しているが、 第 2図及び第 3図、 そして、 第 4 図及び第 5図の構成に対しても、 c 2に関連する論理を省略して、 上記 同様の改善を施すことが可能である。 With such a configuration, the logical scale of the correction term adding unit 16 is reduced, the number of gate serial stages is reduced, and both simplification of the layout and enhancement of the arithmetic processing speed can be promoted. FIG. 9 shows, as an example, a structure obtained by further developing the configuration of FIG. 7, but also for the configurations of FIGS. 2 and 3, and FIGS. 4 and 5, c It is possible to omit the logic related to 2 and make the same improvement as above.
《ガロア乗算器の第 5の例》 《Fifth example of Galois multiplier》
第 1 0図には第 6図及び第 7図の論理構成を 8 ビッ 卜のガロア数の 乗算に拡張したガロア乗算器の例が示される。第 1 0図の例では、部分 積加算部 1 1 X及び補正項加算部 1 5 Xは共に同じ単位回路 1 9を用
いている。 単位回路 1 9は、 第 1 0図に例示されるように、 入力 P , A に対して論理積を採るアンドゲ一 卜 1 7、このアンドゲ一卜の出力と入 力 Bに対して排他的論理和を採る排他的論理和ゲ— 卜 1 8とによって 構成される。 G Dは回路の接地電位であり、 論理値 " 0 " の信号を供 給する。 FIG. 10 shows an example of a Galois multiplier in which the logical configuration of FIGS. 6 and 7 is extended to multiplication of an 8-bit Galois number. In the example of Fig. 10, the partial product adder 11X and the correction term adder 15X both use the same unit circuit 19. Have been. As shown in FIG. 10, the unit circuit 19 is an AND gate 17 which takes a logical product of the inputs P and A, and an exclusive logic is provided for the output of the AND gate and the input B. Exclusive OR gate 18 for taking the sum. GD is the ground potential of the circuit and supplies a signal with a logical value of "0".
第 1 0図の構成によれば極めて規則的なゲ— 卜配置によってガロア 乗算器を実現できる。第 1 0図において、 丸で囲んだ数字は、 e X 0 R と A N D素子のそれぞれの信号伝達時間を 1 とした場合に入力から当 該数字が付されている地点までの所要伝達時間を意味する。クリティカ ルパスは出力ビッ ト o 7得るための経路とされる。 According to the configuration of FIG. 10, a Galois multiplier can be realized by a very regular gate arrangement. In Fig. 10, the circled numbers mean the required transmission time from the input to the point marked with the number, assuming that the signal transmission time of each of eXOR and the AND element is 1. I do. Critical path is a path for obtaining the output bit o 7.
第 1 1 図には第 1 0図の実施例の高速化を図った実施例が示される。 第 1 0図の例では、乗算出力を得るまでの遅延時間は比較的長い。 これ は主に、 補正項加算部 1 5 Xは、 原始多項式の係数 c nと乗数、 被乗数 の係数 a n、 b nの演算を行いながら、 逐次、 1 次毎に次数を下げる構 成を採用し、 このとき、配列の最上位の単位回路 1 9の出力を排他的論 理和ゲ— 卜 1 5 Bを介して次段の単位回路 1 9に共通に与える信号を 形成するからである。第 1 1 図のガロア乗算器では、補正項加算部 1 5 Yにおける各列の駆動入力信号 D k ( k二 2 ~ 8 ) の高速化を図ってい る o FIG. 11 shows an embodiment for increasing the speed of the embodiment of FIG. In the example of FIG. 10, the delay time until the multiplication output is obtained is relatively long. This is mainly because the correction term adder 15 X employs a configuration in which the order is reduced successively and linearly while calculating the coefficient c n of the primitive polynomial and the multipliers a n and b n of the multiplicand. At this time, a signal which is commonly applied to the output of the uppermost unit circuit 19 of the array via the exclusive OR gate 15B is provided to the next unit circuit 19. In the Galois multiplier of FIG. 11, the speed of the drive input signal D k (k 2 2 to 8) of each column in the correction term adder 15 Y is increased.o
すなわち、第 1 0図の構成は、 各列の駆動入力信号 D kは、 前の配列 の駆動入力信号 D k-1 が単位回路 1 .9のアンドゲ— 卜 1 7と排他的論 理和ゲ— ト 1 8、そして排他的論理和ゲ— 卜 1 5 Bを通過して形成され る。第 1 1図では、 そのような排他的論理和ゲー 卜 1 5 Bを廃止した。 第 1 0図のようにアンドゲー 卜 1 7、排他的論理和ゲ— 卜 1 8の各々に おける信号伝達時間を 1 とすると、信号 D kと信号 D k- 1 と間の遅延時 間は 2となる。 これを短縮するために第 1 1 図では、 各列の C7信号を
受ける単位回路 1 9 A, 1 9 Bと、補正項加算の最終配列の単位回路 1 9 B , 1 9 Aに排他的論理和回路 1 8 A, 1 8 Cとセレクタ回路 1 8 B との組み合わせを採用し、 第 1 0図の K n、 Z n信号を受ける排他的論 理和回路 1 3 A、 そして前記排他的論理和回路 1 5 Bを省略した。 セレクタ回路 1 8 Bの選択信号は、各列の駆動入力信号 D kとする。 信号 C 7、 D 8信号を受ける単位回路 1 9 Aと信号 C 0、 D 2信号を受 ける単位回路 1 9 Aは排他的論理和回路 1 8 Aとその一方の入力と出 力を選択するセレクタ回路 1 8 Bによって構成される。信号 C 7とその 他の D k信号を受ける単位回路 1 8 Bと最終列の Z 2〜Z 8を出力する 単位回路 1 9 Bは、排他的論理和回路 1 8 Aとその一方の入力と出力を 選択するセレクタ回路 1 8 Bに加えて当該セレク夕回路 1 8 B出力と 前列からの出力との排他的論理和を採る排他的論理和回路 1 8 Cを通 過して信号出力を行う。 That is, in the configuration of FIG. 10, the drive input signal Dk of each column is obtained by exclusive-ORing the drive input signal Dk-1 of the previous array with the AND gate 17 of the unit circuit 1.9. — Formed through gate 18 and exclusive OR gate 15B. In Fig. 11, such an exclusive OR gate 15B has been abolished. Assuming that the signal transmission time in each of the AND gate 17 and the exclusive OR gate 18 is 1 as shown in FIG. 10, the delay time between the signal Dk and the signal Dk-1 is 2 Becomes To shorten this, Figure 11 shows that the C7 signal in each column is Receiving unit circuit 19 A, 19 B and unit circuit 19 B, 19 A in the final array of correction term addition Combining exclusive OR circuit 18 A, 18 C with selector circuit 18 B The exclusive OR circuit 13A for receiving the Kn and Zn signals in FIG. 10 and the exclusive OR circuit 15B in FIG. 10 are omitted. The selection signal of the selector circuit 18B is a drive input signal Dk of each column. The unit circuit 19 A receiving the signals C 7 and D 8 and the unit circuit 19 A receiving the signals C 0 and D 2 select the exclusive OR circuit 18 A and its one input and output It is composed of a selector circuit 18B. A unit circuit 18B that receives the signal C7 and other Dk signals and outputs Z2 to Z8 in the last column is a unit circuit 19B, which is an exclusive OR circuit 18A and one of its inputs. In addition to the selector circuit 18B that selects the output, the signal is output through an exclusive OR circuit 18C that takes the exclusive OR of the output of the selector circuit 18B and the output from the front row. .
前記セレクタ回路 1 8 Bの伝達時間は、アンドゲー 卜や排他的論理和 回路に比べて速く、 その伝達時間は 0.5程度で信号伝達を行うことが 可能である。 したがって、本実施例の信号 D kと信号 D k-1 と間の遅延 時間は、 C 7、 D 8信号を受ける単位回路 1 9 Aで 0. 5、 C 7とその 他の D k信号を受ける単位回路 1 9 Bでは 1 . 5となる。 その結果、 第 1 1 図に示されるように、乗算出力を得るまでの全体の遅延時間は 1 3 となり、第 1 0図の遅延時間 2 1 に比べ、 3 8%の高速化が可能となる 利点がある。 The transmission time of the selector circuit 18B is faster than that of an AND gate or an exclusive OR circuit, and the transmission time is about 0.5, so that signal transmission can be performed. Therefore, the delay time between the signal Dk and the signal Dk-1 in this embodiment is 0.5, C7 and other Dk signals in the unit circuit 19A receiving the signals C7 and D8. The receiving unit circuit 19 B is 1.5. As a result, as shown in Fig. 11, the total delay time until obtaining the multiplication output is 13 and it is possible to speed up by 38% compared to the delay time 2 1 in Fig. 10. There are advantages.
《ガロア乗算器の第 6の例》 << Sixth example of Galois multiplier >>
今まで説明したガロア乗算器は第 1 2図に示されるように、少な〈 と も、 部分積加算部 1 1 ( 1 1 X ) と、 補正項加算部 1 2 ( 1 4 , 1 5 , 1 6 , 1 5 X , 1 5 Y ) とを有し、 前記補正項加算部に出力加算機能が 無い場合には、 更に出力加算部 1 3 ( 1 3 X ) を備える。補正項加算部
には係数設定手段によって原始多項式の係数が与えられる。 As shown in FIG. 12, the Galois multipliers described so far have a small number of <and a partial product adder 1 1 (1 1 X) and a correction term adder 1 2 (1 4, 15, 1). 6, 15X, 15Y), and when the correction term adding section does not have an output adding function, an output adding section 13 (13X) is further provided. Correction term adder Is given a coefficient of a primitive polynomial by coefficient setting means.
第 1 3図にはデコ一ダを介して原始多項式の係数を供給可能にした ガロア乗算器の例が示される。 すなわち、 原始多項式をデコー ドし、 デ コード結果を補正項加算部 2 1 に供給するデコーダ 2 0を追加する。 第 1 4図には第 1 3図のデコーダ 2 0及び補正項加算部 2 1 の一例 が示される。第 1 4図には第 7図の構成に対してデコーダを追加した時 の構成が示されている。第 1 4図において補正項加算部 2 1 は、ガロア 体 G F ( 2 n)、 特に n二 4の場合の 4ビヅ 卜のガロア数に対するガロア 乗算に適用される場合を一例としている。 これに即して説明すると、補 正項加算部 2 1 は、 n ( = 4 ) 個の単位回路 2 1 A , 2 1 Bの配列を n - 1 (= 3 ) 列備え、 単位回路 2 1 A, 2 1 Bの列方向の次数は 1 から 2门ー 2 (ニ 6 ) とされ、 第 1列目の配列は n ( = 4 ) 個目が次数 2 n — 2 (= 6 ) とされ、 2列目の配列は n ( = 4 )個目が次数 2 n— 3 (= 5 ) とされ、 j頃次、 次数を下げて n _ 1 (= 3 )列目の配列は n (二 4 ) 個目が次数 n (二 4 ) とされる。 配列の各列の次数 n + 1 (= 5 ) 以上 の単位回路 2 1 Bは、配列毎に共通の入力として対応するビッ 卜位置の 部分積加算の値 G 4, G 3を受け、 この共通の入力と各列の単位回路に 入力される n ( = 4 ) ビッ 卜の原始多項式の係数をデコ一 ドした信号と を受けてアンドゲー ト 2 1 Cで積を生成すると共に、前列の同一次数位 置の単位回路 2 1 Bからの出力と前記積とを受けて排他的論理和回路 2 1 Dで第 1のガロア和を生成して出力する機能を有し、前記各列の次 数 n + 1 (= 5 ) 以上の単位回路 2 1 Bのうち、 配列の最上位位置の単 位回路 2 1 Bの出力は、 それに対応する部分積加算の値 G 3 , G 2と共 に排他的論理和回路 2 1 Eで第 2のガロア和を生成する。 FIG. 13 shows an example of a Galois multiplier that can supply the coefficients of a primitive polynomial via a decoder. That is, a decoder 20 that decodes the primitive polynomial and supplies the decoded result to the correction term adder 21 is added. FIG. 14 shows an example of the decoder 20 and the correction term adder 21 shown in FIG. FIG. 14 shows the configuration when a decoder is added to the configuration of FIG. In FIG. 14, an example is shown in which the correction term adder 21 is applied to Galois multiplication of a Galois field GF (2 n ), in particular, a 4-bit Galois number in the case of n24. Explaining this, the correction term adder 2 1 has an array of n (= 4) unit circuits 21 A and 21 B in n-1 (= 3) columns, and the unit circuit 2 1 The order in the column direction of A, 2 1 B is from 1 to 2 门 2 (d 6), and the array in the first column is the order 2 n — 2 (= 6) for the n (= 4) th array In the array of the second column, the order of n (= 4) is 2 n—3 (= 5). 4) The n-th order is the order n (2 4). The unit circuits 21 B having the order of n + 1 (= 5) or more in each column of the array receive the partial product addition values G 4 and G 3 of the corresponding bit positions as common inputs for each array, and And a signal obtained by decoding the coefficients of n (= 4) bits of primitive polynomials input to the unit circuits of each column, and a product is generated by AND gate 21C, and the same order of the front column is generated. The exclusive OR circuit 21D receives the output from the unit circuit 21B at the position and the product and generates and outputs a first Galois sum, and the order n of each column is provided. Of the unit circuits 2 1 B of +1 or more (= 5) or more, the output of the unit circuit 2 1 B at the highest position in the array is exclusive with the corresponding partial product addition values G 3 and G 2 The second Galois sum is generated by the OR circuit 21E.
前記配列の各列の次数 n以下の単位回路 2 1 Aは、共通の入力として 前記第 2のガロア和を受け、この共通の入力と各列の単位回路 2 1 Aに
入力される原始多項式の対応される係数とを受けてァンドゲー ト 2 1 Fで積を生成すると共に、前列の同一次数位置の単位回路 2 1 Aからの 出力と前記積とを受けて排他的論理和回路 2 1 Gで第 3 のガロア和を 生成して出力とする機能を有する。 The unit circuit 21A having an order n or less of each column of the array receives the second Galois sum as a common input, and receives the common input and the unit circuit 21A of each column. In response to the input coefficients of the primitive polynomial and the corresponding coefficients, a product is generated by an AND gate 21F, and an exclusive logic is generated by receiving the output from the unit circuit 21A at the same order position in the front row and the product. It has the function of generating and outputting the third Galois sum by the sum circuit 21G.
1 列目の単位回路は次数 n + 1 以上と次数 n以下に共通の入力とし て部分積加算の最上位次数 2 n— 1 の値 (G4) が入力されて出力を生 成し、 2列目以下の単位回路では次数 n + 1 以上に共通の入力は対応す る部分積加算の値 (G 3) とされ、 同じく 2列目以下の単位回路では次 数 n以下に共通の入力は、対応する前記排他的論理和回路 2 1 Eから出 力される第 3のガロア和とされる。 In the unit circuit in the first column, the value (G 4 ) of the highest order 2 n−1 of partial product addition is input as a common input for the order n + 1 or more and the order n or less, and an output is generated. In the unit circuits below the column, the input common to the order n + 1 or more is the corresponding partial product addition value (G 3 ). Similarly, for the unit circuit below the second column, the input common to the order n or less is Is the third Galois sum output from the corresponding exclusive OR circuit 21E.
n - 1 (= 3 ) 列目の n (= 4 ) 個の単位回路 2 1 Aの出力が補正項 加算の出力とされ、 当該補正項加算の出力と部分積加算の下位 n (= 4 ) ビッ トとのガロア和が乗算結果とされる。 The output of n (= 4) unit circuits 2 1 A in the n-1 (= 3) column is the output of the correction term addition, and the output of the correction term addition and the lower n (= 4) of the partial product addition The Galois sum with the bit is the result of the multiplication.
第 1 5図には第 7図のノー ド D 2, D 3, D4の信号論理と第 1 4図の 同じノー ド D2, D 3, D 4の信号論理との相違点が示される。展開前の 関係式から明らかなように、 第 7図の構成ではノ一 D 3の値はその前 段のノ一 ド D 4の値に依存し、 ノー ド D 2の値はそれよりも前段のノ― ド D 3, D4の値に依存している。 これに対し、 第 1 4図の構成に応ず る展開後の関係式によれば、 ノー ド D 3の値はその前のノ一 ド D 4の値 に依存せず、 ノー ド D 2の値はそれよりも前段のノー ド D 3, D4の値に 依存しない論理構成とされる。第 1 5図の展開後の関係式は、代入法に より式の右辺から D 3 , D 4を消去したものである。 第 1 5図の展開後 の関係式から明らかなように、 デコーダ 20を用いれば、 理論上、補正 項加算部 2 1 のノー ド D 2, D 3の値は夫々の後段のノ一 ドの確定に時 間的な影響を及ぼさないことが理解されるであろう。従って、第 1 4図 の補正項加算部 2 1及びデコーダ 20を採用したガロア乗算器は、第 7
図に比べ演算処理の高速化を実現できる。すなわち、補正項加算部 2 1 におけるクリティカルパスの出力 Z 4の信号伝達時間は⑦とされ、 第 7 図の場合の⑧に対して短くされている。尚、丸付き数字は前述と同じ意 味である。 FIG. 15 shows the differences between the signal logic of nodes D 2 , D 3 and D 4 in FIG. 7 and the signal logic of the same nodes D 2 , D 3 and D 4 in FIG. . As is clear from the relational expression before the expansion, in the configuration of FIG. 7, the value of the node D 3 depends on the value of the node D 4 in the preceding stage, and the value of the node D 2 is in the preceding stage. It depends on the values of the nodes D 3 and D 4 . On the other hand, according to the expanded relation corresponding to the configuration in FIG. 14, the value of the node D 3 does not depend on the value of the preceding node D 4 but the value of the node D 2 Is a logical configuration that does not depend on the values of the preceding nodes D 3 and D 4 . Relationship after deployment of the first 5 diagrams are those from the right side expression of more substitution method was erased D 3, D 4. As is clear from the relational expression after the expansion in FIG. 15, if the decoder 20 is used, the values of the nodes D 2 and D 3 of the correction term adder 21 are theoretically the values of the nodes at the subsequent stage. It will be appreciated that it has no time effect on the confirmation. Therefore, the Galois multiplier employing the correction term adder 21 and the decoder 20 shown in FIG. The calculation processing can be performed at a higher speed than in the figure. That is, the critical path output Z 4 signal transmission time of the correction term addition unit 2 1 is a ⑦, are shorter than ⑧ in the case of Figure 7. The numbers with circles have the same meaning as described above.
第 1 6図には第 1 0図の補正項加算部の構成に対してデコーダ 2 2 を採用した例が示される。 第 1 7図には第 1 0図のノー ド D 2〜D 8の 信号論理と第 1 4図の同じノー ド D2~D 8の信号論理との相違点が示 される。第 1 4図及び第 1 5図の場合と同様に、デコーダ 2 2を用いれ ば、 理論上、 補正項加算部 2 3のノー ド D 2〜D 8の値は夫々の後段の ノー ドの確定に時間的な影響を及ぼさないことが理解されるであろう。 従って、第 1 6図の補正項加算部 2 3及びデコーダ 2 2を採用したガ口 ァ乗算器は、第 1 0図に比べ演算処理の高速化を実現できる。すなわち、 補正項加算部 2 3におけるクリティカルパスの出力 Z 8の信号伝達時 間は⑪とされ、第 1 0図の場合の⑳に対して約半分に減少されている。 尚、 丸付き数字は前述と同じ意味である。 FIG. 16 shows an example in which a decoder 22 is employed for the configuration of the correction term adder of FIG. The first 7 Figure differs from the signal logic of the same node D 2 ~ D 8 of the signal logic and the first 4 view of nodes D 2 to D 8 of the first 0 diagram is shown. As in the case of FIGS. 14 and 15, if the decoder 22 is used, the values of the nodes D 2 to D 8 of the correction term adder 23 are theoretically determined by the nodes at the subsequent stages. It has no effect on the time. Therefore, the Gaa multiplier employing the correction term adder 23 and the decoder 22 shown in FIG. 16 can realize a higher speed of the arithmetic processing as compared with FIG. That is, during the time of signal transmission of the output Z 8 of the critical path in the correction term addition unit 2 3 is a ⑪, is reduced to about half of the ⑳ in the case of the first 0 FIG. The circled numbers have the same meaning as described above.
《ガロア乗算器の第 7の例》 << Seventh example of Galois multiplier >>
第 1 8図には部分積加算部及び補正項加算部をさらに高速化したガ ロア乗算器のプロック図が示される。同図に示されるガロア乗算器は、 nビッ 卜の被乗数をデコーダ 3 0でデコ一 ドして部分積加算部 3 1 に 供給し、部分積加算部 3 1 の出力をデコーダ 2 6でデコ一 ドして補正項 加算部 2 5に与える。 FIG. 18 shows a block diagram of a Galois multiplier in which the partial product adder and the correction term adder are further speeded up. In the Galois multiplier shown in the figure, the n-bit multiplicand is decoded by the decoder 30 and supplied to the partial product adder 31. The output of the partial product adder 31 is decoded by the decoder 26. To the correction term adder 25.
第 1 9図には第 1 8図の構成に対応される部分積加算部 3 1 の論理 構成が示される。 第 1 9図の ( 1 ) 欄及び ( 2 ) 欄に示されるように、 X a*X bの部分積の係数を、 次数毎に、 b。, t^ , b 2 J b 3で整理す る。 そして前記 ( 2 ) 欄の係数を被乗数 x 3 , X 2の係数 b 3, b 2のデ コー ド結果にしたがって選択し、 同様に前記 ( 1 )欄の係数を被乗数 X
1 , x °の係数 b b。のデコー ド結果にしたがって選択する。 その前 言己 ( 1 ) 欄及び ( 2 ) 欄の夫々における選択態様は第 1 9図の ( 3 ) 欄 に示されている。 FIG. 19 shows the logical configuration of the partial product adder 31 corresponding to the configuration of FIG. As shown in columns (1) and (2) of Fig. 19, the coefficient of the partial product of Xa * Xb is calculated for each degree by b. , T ^, organized in b 2 J b 3. Then, the coefficients in column (2) are selected according to the decoding results of the coefficients b 3 and b 2 of the multiplicand x 3 and X 2 , and the coefficients in column (1) are similarly calculated by the multiplicand X 1 , x ° coefficient bb. Select according to the decoding result of. Before that, the manner of selection in each of columns (1) and (2) is shown in column (3) of FIG.
第 20図には第 1 9図の論理を具体的に実現したデコーダ 3 0及び 部分積加算部 3 1 の一例が示される。 デコーダ 3 0は被乗数 b。, b 1 , b2 ) b 3の各ビッ 卜を反転及び非反転信号に変換する。 部分積加算部 3 1 は、 セレクタ 3 2, 3 3 , 3 3 , 3 3 , 3 2の配列を 2列有し、 各 配列のセレクタは、前記第 1 9図の ( 3 )欄の論理に従って入力を選択 する。 FIG. 20 shows an example of the decoder 30 and the partial product adder 31 that specifically realize the logic of FIG. Decoder 30 is multiplicand b. , B 1 , b 2) Convert each bit of b 3 into inverted and non-inverted signals. The partial product adder 31 has two arrays of selectors 32, 33, 33, 33, 33, 32, and the selector of each array is in accordance with the logic in the column (3) in FIG. Select input.
前記セレクタ 3 2の一例は第 2 1 図に示され、前記セレクタ 3 3の一 例は第 2 2図に示される。第 2 0図に示される丸付き数字は排他的論理 和ゲー 卜とアンドゲ一 卜の夫々の信号伝達時間を 1 、ィンバ一夕の信号 伝達時間を 0. 5とした場合、入力からその地点までの信号伝達遅延時 間を示す。 第 7図の部分積加算部 1 1 における出力 K 4までの伝達時間 は④であり、 これに比べて第 2 0図の構成では出力 Κ 4までの信号伝達 時間を③に短縮できる。 この伝達時間の短縮率は、乗数及び被乗数のビ ッ ト数(ガロア数のビヅ 卜数) を増やせばさらに顕著になる。例えば、 第 2 3図に示される 8ビッ 卜のガロア数を演算対象とするガロア乗算 器の部分積加算部 3 1 に第 20図の構成を適用した場合、第 1 0の構成 では Κ 8の出力を得るまでの遅延時間が⑧であるのに対し、 ⑤まで短縮 できる (約半分( 5/8 )に短縮できる) 。 すなわち部分積加算の演算処 理速度は約 2倍早くなる。第 2 3図の部分積加算部 3 1 においても、デ コーダ 3 0は 2ビッ 卜づっデコ一 ドを行い、 セレクタ 3 2 , 3 3 , 3 3 , 33 , 3 3 , 3 3 , 3 3, 3 3 , 3 2の配列が 4列設けられている。 第 2 3図の実際の論理については第 1 9の論理を参照すれば容易に理解 することができるから、 図示を省略してある。
《リ一ドソ · ロモン符号による誤り訂正》 An example of the selector 32 is shown in FIG. 21 and an example of the selector 33 is shown in FIG. The circled numbers shown in Fig. 20 indicate that the signal transmission time of each of the exclusive OR gate and AND gate is 1 and that the signal transmission time of Imba overnight is 0.5, from the input to that point. This shows the signal transmission delay time. The transmission time to the output K 4 in the partial product addition unit 11 in FIG. 7 is ④, and the signal transmission time to the output Κ 4 can be reduced to ③ in the configuration of FIG. This reduction rate of the transmission time becomes more remarkable when the number of bits of the multiplier and the multiplicand (the number of bits of the Galois number) is increased. For example, the second 3 when applying 8 to the partial-product addition unit 3 first Galois multiplier which candidate operation Galois number of bits Bok FIG. 20 of the configuration shown in FIG., The first 0 in the structure of kappa 8 The delay time until the output is obtained is ⑧, but it can be reduced to ((about half (5/8)). In other words, the processing speed of partial product addition is about twice as fast. Also in the partial product adder 31 shown in FIG. 23, the decoder 30 performs decoding in units of two bits, and the selectors 32, 33, 33, 33, 33, 33, 33, 33 There are provided four rows of 33 and 32 arrays. The actual logic in FIG. 23 can be easily understood by referring to the logic in FIG. 19, and is not shown. 《Error correction by lidoso-Romon code》
第 2 4図にはリー ド ·ソロモン符号による誤り訂正処理の代表的なフ ローチヤ一 卜の一例が示される。誤り訂正の処理フローは、入力データ に対するシンドロ一厶演算 ( S 1 ) 、 ュ一クリ ツ ド演算 (ュ一クリツ ド 互除法) S 2、 チェンサーチ (誤り位置検索) S 3、 誤り数値計算 S 4 及び訂正 S 5から成る。前記シンドロ一厶演算 S 1 は、一連の受信符号 を入力とし、 シンドローム多項式の係数を算出する。 ここで、 シンドロ ーム多項式の係数が、全てゼロであれば受信符号に誤りがないことが分 かる。誤りがないことが分かった場合は S 2以下の処理を省略して終了 する。誤りがあることが分かった場合は、 訂正処理を始める。最初にュ ークリツ ド演算 S 2により、シンドローム多項式から誤り位置多項式と 誤り数値多項式を算出する。誤り位置多項式の根を、チェンサーチ S 3 で求めることによって誤りの位置と誤りの数が求められる。このとき、 誤りの数が規定数以上になった場合には、符号の訂正能力を上回る誤り が発生していることが分かる。 このときは、訂正不能であることを出力 し、以下の処理を省略して終了する。誤りの位置と誤りの数が適切に求 められた場合には、 それをもとにして、 誤りの数値を計算し ( S 4 ) 、 誤り訂正 S 5を行って処理を終了する。 FIG. 24 shows an example of a typical flow chart of the error correction processing using the Reed-Solomon code. The error correction processing flow is as follows: Syndrome operation (S 1), input operation (Euclidean algorithm) S 2, Chien search (error position search) S 3, error value calculation S for input data 4 and correction S5. The syndrome operation S 1 calculates a coefficient of a syndrome polynomial using a series of received codes as inputs. Here, if the coefficients of the syndrome polynomial are all zero, it is understood that there is no error in the received code. If it is determined that there is no error, the processing after S2 is omitted and the processing ends. If you find an error, start the correction process. First, an error locator polynomial and an error numerical polynomial are calculated from the syndrome polynomial by a step operation S2. By finding the root of the error locator polynomial in Chien search S 3, the position of the error and the number of errors are obtained. At this time, if the number of errors exceeds the specified number, it can be understood that an error has occurred that exceeds the code correction capability. At this time, it outputs that the correction is not possible and skips the following processing and ends. If the position of the error and the number of errors are properly obtained, the numerical value of the error is calculated based on the position (S 4), the error is corrected S 5, and the process is terminated.
リード ' ソロモン符号はガロア体の数を用いて定義されており、前記 シンドロ—ム演算 S 1 、ユークリツ ド演算 S 2及びチェンサーチ S 3の 処理では、前述したガロア体上の加算及び乗算が多用される。そのよう な乗算に前記ガロア乗算器を用いることができる。 The Reed-Solomon code is defined using the number of Galois fields, and the above-described addition and multiplication on the Galois field are frequently used in the processing of the syndrome operation S1, the Euclidean operation S2, and the Chien search S3. Is done. The Galois multiplier can be used for such multiplication.
第 2 5図にはシンドローム演算、ュ―クリヅ ド演算及びチェンサーチ を行う回路の一例ブロック図が示される。各回路ブロックには 2個のガ ロア乗算器 4 0と加算器 4 1 が設けられている。ガロア乗算器 4 0は第 1 図から第 2 4図に基づいて説明した何れかの構成を有する。この例に
従えば、 シンドローム演算、 ユークリッ ド演算及び チェンサーチを行 う回路は夫々固有のハー ドウエアを有して、 1個の半導体集積回路とし て構成される。夫々のガロア乗算器 4 0には係数設定手段 3から原始多 項式が共通に与えられる。 X a , X bは乗数, 被乗数である。 したがつ て、異なったシステムで異なった原始多項式を設定する場合、原始多項 式の係数を任意に設定することができる。 FIG. 25 is a block diagram showing an example of a circuit for performing a syndrome operation, a leak operation, and a Chien search. Each circuit block is provided with two Galois multipliers 40 and an adder 41. The Galois multiplier 40 has any configuration described with reference to FIGS. 1 to 24. In this example Accordingly, the circuits for performing the syndrome operation, the Euclidean operation, and the Chien search have their own hardware and are configured as one semiconductor integrated circuit. Primitive polynomials are commonly given to the respective Galois multipliers 40 from the coefficient setting means 3. X a and X b are a multiplier and a multiplicand. Therefore, when different primitive polynomials are set in different systems, the coefficients of the primitive polynomial can be set arbitrarily.
第 2 6図にはリー ド 'ソロモン符号による誤り訂正に特化したマイク 口プロセッサの一例プロック図が示される。同図に示されるマイクロプ 口セッサ 5 0は、マイクロプロセッサ 5 0の動作プログラムが格納され たプログラムメモリ 5 5と、プログラムメモリ 5 5からフェッチした命 令を解読して制御信号を生成する制御部 5 1 と、前記制御信号によって 制御される演算部 5 2と、前記演算部 5 2を外部とイ ンタフェースさせ るインタフェース部 5 3と、演算部 5 2のワーク領域などとして利用さ れるメモリ部 5 4とを、単結晶シリコンのような 1個の半導体基板に儲 えて構成される。 Figure 26 shows a block diagram of an example of a microphone processor specialized in error correction using the read'Solomon code. The microprocessor 50 shown in the figure includes a program memory 55 storing an operation program of the microprocessor 50, and a control unit 5 which decodes an instruction fetched from the program memory 55 and generates a control signal. 1, an operation unit 52 controlled by the control signal, an interface unit 53 for interfacing the operation unit 52 with the outside, and a memory unit 54 used as a work area of the operation unit 52 And a single semiconductor substrate such as single crystal silicon.
前記演算部 5 2はガロア乗算器 5 6、加算器 5 7及びレジスタ 5 8な どを有する。 ガロア乗算器 5 6は、 ガロア体 G F ( 2 n )の元と元との間 のガロア乗算に用いられ、 乗数とされるガロア体 G F ( 2 つの元の係数 と、 被乗数とされるガロア体 G F ( 2 n )の元の係数と、 原始多項式の係 数とを入力し、 ガロア乗算結果を得るための前記係数の演算を、複数の 異なる原始多項式に対して、同一ハ— ドウエアで行う、前記第 1 図から 第 2 4図で説明した何れかの構成を有する。前記原始多項式の係数は、 例えばプログラムにしたがつて前記制御部 5 1 から与えられる。 The operation unit 52 has a Galois multiplier 56, an adder 57, a register 58, and the like. The Galois multiplier 5 6 is used for Galois multiplication between the elements of the Galois field GF (2 n ), and the Galois field GF (the coefficient of the two elements and the Galois field GF The original coefficient of (2 n ) and the coefficient of primitive polynomial are input, and the calculation of the coefficient for obtaining the Galois multiplication result is performed on a plurality of different primitive polynomials by the same hardware. It has any of the configurations described in Fig. 1 to Fig. 24. The coefficients of the primitive polynomial are provided from the control unit 51 according to a program, for example.
このマイクロプロセッサ 5 0は、プログラムメモリ 5 5に格納されて いる動作プログラムに従って、例えば前記シンドローム演算、ユークリ ッ ド演算及びチェンサーチの各処理を実行する。すなわち、 ソフ トゥェ
ァによって第 2 5図と等価な機能を実現する。 The microprocessor 50 executes, for example, the syndrome calculation, the Euclidean calculation, and the Chien search in accordance with the operation program stored in the program memory 55. That is, Sof Twe The functions equivalent to those in Fig. 25 are realized by the software.
第 2 7図には蓄積メディアに対する情報記録と記録情報再生に用い られるディスク ドライブシステムのブロック図が示される。同図に示さ れるディスク ドライブシステムが扱う蓄積メディアは、特に制限されな いが M Oと D V Dの双方の媒体 6 0とされる。媒体 6 0はディスクモ一 夕 6 1 で回転駆動される。 ピックアップ部 6 2は、特に制限されないが M 0用のピックアップと D V D用のピックアツプを有し、フオーカシン グ及びトラッキング用のァクチエータを備える。ピックアップのサ一ボ 制御はサーボ回路 6 4が行う。ピックアップから読み取られた情報はプ リアンプ 6 3で増幅され、高周波信号は符号化 '復号化処理部 6 7に与 えられ、 トラッキング及びフ才一カシングの各サーボエラー信号はサ一 ボ回路 6 4に与えられる。媒体 6 0への書き込み信号は符号化 .復号化 処理部 6 7から ドライバ 6 5を経てピックアップ部 6 2に与えられる。 制御部 6 6は図示を省略するホス 卜システムとインタフェースされ、デ イスク ドライブシステム全体の制御を行う。符号化 ·復号化処理部 6 7 は、 図示を省略するホス 卜システムとインタフェースされ、媒体 6 0か ら読み取られた情報の復号化、媒体 6 0へ書き込むべき情報の符号化を 行う。符号化に際しては誤り訂正のためのパリティ一を生成する。復号 化においては誤り訂正を行う。復号化に際しての誤り訂正は誤り訂正部 6 8が行う。誤り訂正部 6 8は、第 1 図から第 2 4図で説明した何れか のガロア乗算器を含み、 当該ガロア乗算器や加算器を用いて、 リー ド - ソロモン符号による誤り訂正を行う。誤り訂正処理部 6 8は、複数種類 の原始多項式の中から選ばれた原始多項式を用いる。誤り訂正処理部 6 8は前記マイクロプロセッサ 5 0などによつて構成することができる。 第 2 7図の構成において、前記サーボ回路 6 4は媒体の種類に応じた サ一ボ制御を行う。サーボ回路 6 4は、媒体の種類を認識するために、
先ず、 卜レーニング期間の最初に、 M0のためのトラッキング及びフォ —カシングサーボを行う。媒体 60の種類によって、焦点深度及びトラ ックピッチが違うので、 実際、 D V Dが装着されている場合には、 トラ ヅキング及びフオーカシングのサ一ボエラーが許容範囲を超える。この 状態を検出したとき、サ一ボ回路 64は装着媒体が D V Dであることを 認識する。サーボエラーが許容範囲に入る場合、装着媒体は MOと認識 する。 この意味において、第 27図のシステムにおいて前記サ―ボ回路 64は媒体認識手段の一例とされる。 FIG. 27 is a block diagram of a disk drive system used for recording information on a storage medium and reproducing recorded information. The storage media handled by the disk drive system shown in the figure is not particularly limited, but is both the MO and DVD media 60. The medium 60 is driven to rotate by the disk drive 61. Although not particularly limited, the pickup section 62 includes a pickup for M0 and a pickup for DVD, and includes an actuator for focusing and tracking. The servo control of the pickup is performed by the servo circuit 64. The information read from the pickup is amplified by the preamplifier 63, the high-frequency signal is given to the encoding / decoding processing section 67, and the servo error signals for tracking and intelligent focusing are sent to the servo circuit 64. Given to. The write signal to the medium 60 is supplied from the encoding / decoding processing section 67 to the pickup section 62 via the driver 65. The control unit 66 is interfaced with a host system (not shown), and controls the entire disk drive system. The encoding / decoding processing unit 67 is interfaced with a host system (not shown), and decodes information read from the medium 60 and encodes information to be written to the medium 60. At the time of encoding, a parity for error correction is generated. Error correction is performed in decoding. Error correction at the time of decoding is performed by the error correction unit 68. The error correction unit 68 includes any one of the Galois multipliers described with reference to FIGS. 1 to 24, and performs error correction using a lead-Solomon code using the Galois multiplier and the adder. The error correction processing unit 68 uses a primitive polynomial selected from a plurality of types of primitive polynomials. The error correction processing section 68 can be constituted by the microprocessor 50 or the like. In the configuration shown in FIG. 27, the servo circuit 64 performs servo control according to the type of medium. Servo circuit 64 is used to recognize the type of medium. First, at the beginning of the training period, a tracking and focusing servo for M0 is performed. Since the depth of focus and the track pitch differ depending on the type of the medium 60, the tracking and focusing servo errors actually exceed the allowable range when a DVD is mounted. When detecting this state, the servo circuit 64 recognizes that the mounted medium is a DVD. If the servo error is within the allowable range, the mounted medium is recognized as MO. In this sense, the servo circuit 64 in the system shown in FIG. 27 is an example of a medium recognizing means.
サーボ回路 64による媒体認識結果は自動切換え信号 7 1 としてセ レクタ 69に与えられる。またセレクタ 69にはスィッチ 70を介して 手動切換え信号 7 2が与えられる。セレクタ 69は、 システムの動作モ - ドに応じて、自動切換え信号 7 1又は手動切換え信号 7 2の何れか一 方を選択する。選択された切換え信号は、誤り訂正処理部 68に供給す べき原始多項式を選択する。 The medium recognition result by the servo circuit 64 is given to the selector 69 as an automatic switching signal 71. The selector 69 is supplied with a manual switching signal 72 via the switch 70. The selector 69 selects either the automatic switching signal 71 or the manual switching signal 72 according to the operation mode of the system. The selected switching signal selects a primitive polynomial to be supplied to the error correction processing unit 68.
MOに規格化されている原始多項式は、 x8+ x 5 + x 3+ x2+ 1で あり、 D V Dに規格化されている原始多項式は、 x8 + x 4 + x 3 + x 2 + 1である。セレクタ 69で選択された切換え信号 73が ΜΟを意味す るときは前者の原始多項式が誤り訂正処理部 68に供給され、 D V Dの ときは後者の原始多項式が誤り訂正処理部 68に供給される。 Primitive polynomial is normalized to the MO, an x 8 + x 5 + x 3 + x 2 + 1, primitive polynomial that is standardized on a DVD, x 8 + x 4 + x 3 + x 2 + Is one. When the switching signal 73 selected by the selector 69 indicates ΜΟ, the former primitive polynomial is supplied to the error correction processor 68, and in the case of DVD, the latter primitive polynomial is supplied to the error correction processor 68.
これにより、原始多項式が異なる媒体 60に対してハー ドウエア同一 のガロア乗算器を用いて誤り訂正処理を行うことができる。原始多項式 の切換えを自動で行うことができ、 また、 手動切換えも可能になる。 第 28図には放送メディアに対する情報再生に用いられる衛星放送 受信装置のプロック図が示される。同図に示される衛星放送受信装置が 扱う放送メディアは、特に制限されないが、代表的に示された放送局 8 0 , 8 1 からの放送 A, Βとされる。前記放送 A, Βは静止衛星 82を
介して衛星方送受信装置 8 9で受信することができる。衛星方送受信装 置 8 9は、 放送 A , Bなどをチューナ 8 3で受信する。チューナ 8 3で 受信すべき放送はスィツチ 8 4で選択できる。チューナ 8 3で受信され た映像信号及び音声信号は、符号化処理部 8 5で符号化され、誤り訂正 が施された後、 画像形成部 8 8に与えられて再生される。 As a result, error correction processing can be performed on media 60 having different primitive polynomials using the same Galois multiplier in hardware. The switching of primitive polynomials can be performed automatically, and manual switching is also possible. FIG. 28 shows a block diagram of a satellite broadcast receiving apparatus used for reproducing information from broadcast media. The broadcast media handled by the satellite broadcast receiving apparatus shown in the figure is not particularly limited, but broadcasts A and A from representative broadcast stations 80 and 81 are shown. Broadcast A, Β uses geostationary satellite 82 It can be received by the satellite-side transmitting / receiving device 89. The satellite transmission / reception device 89 receives the broadcasts A and B with the tuner 83. The broadcast to be received by the tuner 83 can be selected by the switch 84. The video signal and the audio signal received by the tuner 83 are encoded by the encoding processing unit 85, subjected to error correction, and given to the image forming unit 88 for reproduction.
復号化に際しての誤り訂正は誤り訂正処理部 8 6が行う。誤り訂正処 理部 8 6は、第 1 図から第 2 4図で説明した何れかのガロア乗算器を含 み、 当該ガロア乗算器や加算器を用いて、 リー ド ' ソロモン符号による 誤り訂正を行う。誤り訂正処理部 8 6は、複数種類の原始多項式の中か ら選ばれた原始多項式を用いる。誤り訂正処理部 8 6は前記マイクロプ 口セッサ 5 0などによって構成することができる。 Error correction at the time of decoding is performed by the error correction processing unit 86. The error correction processing unit 86 includes any one of the Galois multipliers described with reference to FIGS. 1 to 24, and performs error correction using the read-Solomon code using the Galois multiplier and the adder. Do. The error correction processing unit 86 uses a primitive polynomial selected from a plurality of types of primitive polynomials. The error correction processing unit 86 can be constituted by the microprocessor 50 or the like.
原始多項式の選択はスィツチ 8 4による選局に同期される。この例で は、 放送局毎に用いる原始多項式が相違されている。 したがって、放送 を切換えるスィッチ 8 4を受信者が切り換えることにより、原始多項式 が異なる放送においても同一システム上で同一のガロア乗算器を用い て誤り訂正処理を行うことができる。 The selection of the primitive polynomial is synchronized with the tuning by the switch 84. In this example, the primitive polynomial used for each broadcasting station is different. Therefore, by switching the switch 84 for switching the broadcast by the receiver, the error correction can be performed using the same Galois multiplier on the same system even in the broadcast with different primitive polynomials.
以上本発明者によってなされた発明を実施例に基づいて具体的に説 明したが、本発明はそれに限定されるものではなく、 その要旨を逸脱し ない範囲において種々変更可能であることは言うまでもない。 Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it is needless to say that various modifications can be made without departing from the gist of the invention. .
例えば、乗算対象とされるガロア数のビッ 卜数は 4ビッ 卜又は 8ビヅ 卜に限定されずそれ以外であってもよい。また前記場位置は M Oや D V Dに限定されず C D - R O Mなどその他の媒体であってもよい。 産業上の利用可能性 For example, the number of Galois bits to be multiplied is not limited to 4 bits or 8 bits, but may be other values. The location is not limited to MO or DVD, but may be another medium such as CD-ROM. Industrial applicability
以上のように、本発明はガロア体の数を用いて定義されたリ一 ドソロ モン符号の符号化又は復号化に用いられるガロア乗算器、 C D— R O M
(Compact Disc-Read Only Memory)^ D V D (Digital Video Disc M 0 (Magnet Optics)などの記録媒体に対する記録情報再生装置若しくは 情報記録再生装置、さらには衛星通信端末などのデータ処理システムに おける誤り訂正処理などに広く適用することができる。
As described above, the present invention provides a Galois multiplier and a CD-ROM used for encoding or decoding a Reed-Solomon code defined using the number of Galois fields. (Compact Disc-Read Only Memory) ^ Error correction processing in a recording information reproduction device or information recording / reproduction device for recording media such as DVD (Digital Video Disc M0 (Magnet Optics)), and in a data processing system such as a satellite communication terminal It can be widely applied.
Claims
1 . ガロア体 G F ( 2つの元と元との間のガロア乗算に用いられるガ口 ァ乗算器を含み、 1. Galois field G F (including a Galois multiplier used for Galois multiplication between two elements,
前記ガロア乗算器は、乗数とされるガロア体 G F ( 2 n )の元の係数と、 被乗数とされるガロア体 G F ( 2 n )の元の係数と、 原始多項式の係数と を入力し、 ガロア乗算結果を得るための前記係数の演算を、複数の異な る原始多項式に対して、同一ハ一 ドウエアで行うガロア乗算器を含み、 更に、 前記ガロア乗算器に前記ガロア体 G F ( 2 n )の原始多項式の係 数を与える係数設定手段を含んで成るものであることを特徴とする半 導体集積回路。 The Galois multiplier inputs the original coefficients of the Galois field GF that is a multiplier (2 n), and the original coefficients of the Galois field GF (2 n) which is the multiplicand, and a coefficient of a primitive polynomial, the Galois The Galois multiplier includes a Galois multiplier that performs the calculation of the coefficient to obtain a multiplication result for a plurality of different primitive polynomials with the same hardware, and further includes the Galois multiplier with the Galois field GF (2 n ). A semiconductor integrated circuit comprising coefficient setting means for giving a coefficient of a primitive polynomial.
2 . 前記係数設定手段は、 原始多項式の係数を書き換え可能に記憶し、 記憶した原始多項式の係数を前記ガロア乗算器に出力する記憶手段で あることを特徴とする請求の範囲第 1項記載の半導体集積回路。 2. The coefficient setting means according to claim 1, wherein the coefficient setting means is a storage means for rewritably storing coefficients of a primitive polynomial, and outputting the stored coefficients of the primitive polynomial to the Galois multiplier. Semiconductor integrated circuit.
3 . 前記係数設定手段は、複数種類の原始多項式の係数を記憶し、記憶 した係数の中から選択された係数を前記ガロア乗算器に出力するもの であることを特徴とする請求の範囲第 1項記載の半導体集積回路。3. The coefficient setting means according to claim 1, wherein the coefficient setting means stores coefficients of a plurality of types of primitive polynomials and outputs a coefficient selected from the stored coefficients to the Galois multiplier. 13. A semiconductor integrated circuit according to claim 1.
4 . 前記ガロア乗算器は部分積加算部と補正項加算部とを有し、 前記部分積加算部は、乗数と被乗数の部分積毎の乗数の係数と被乗数 の係数との部分積加算を行い、 4. The Galois multiplier has a partial product adder and a correction term adder, and the partial product adder performs partial product addition of a multiplier coefficient and a multiplicand coefficient for each partial product of the multiplier and the multiplicand. ,
前記補正項加算部は、部分積加算部によって得られた n + 1次以上の 部分積の係数を n次以下の部分積の係数に補正する演算を行うもので あることを特徴とする請求の範囲第 1項記載の半導体集積回路。 The correction term adding unit performs an operation of correcting a coefficient of a partial product of n + 1 or higher order obtained by the partial product adding unit to a coefficient of a partial product of nth or lower order. 2. The semiconductor integrated circuit according to claim 1.
5 . 前記補正項加算部は、部分積加算部によって得られた n + 1 次以上 の部分積の係数を n次以下の部分積の係数に補正するための補正情報 を原始多項式の係数に基づいて予め演算する第 1 の論理演算回路と、前
記部分積加算部によって得られた n + 1 次以上の部分積の係数毎に当 該係数と対応する補正情報との積を採る第 2の論理演算回路と、夫々の 第 2の論理演算回路の出力を加算する第 3の論理演算回路とから成る ものであることを特徴とする請求の範囲第 4項記載の半導体集積回路。 5. The correction term adding unit calculates correction information for correcting the coefficient of the partial product of degree n + 1 or higher obtained by the partial product addition unit into the coefficient of partial product of degree n or less based on the coefficient of the primitive polynomial. A first logical operation circuit that pre-calculates A second logical operation circuit that takes a product of the coefficient and the corresponding correction information for each coefficient of the n + 1 or higher order partial product obtained by the partial product adder, and a second logical operation circuit 5. The semiconductor integrated circuit according to claim 4, further comprising a third logical operation circuit for adding the outputs of the first and second logic circuits.
6 . 前記補正項加算部は、 n個の単位回路の配列を n— 1列備え、 列方 向の単位回路の次数は 1 から 2 n— 2とされ、第 1列目の配列は n個目 が次数 2 n— 2とされ、 2列目の配列は n個目が次数 2 n— 3とされ、 順次次数を下げて n— 1 列目の配列は n個目が次数 nとされ、前記配列 の各列の単位回路は、列毎に共通の入力として前列の配列の最上位の単 位回路の出力とそれに対応する部分積加算の値との第 1 のガロア和を 受け、この共通の入力と各列の単位回路に共通に入力される原始多項式 の係数とを受けて論理積を生成すると共に、当該論理積の値と前列の同6. The correction term adder includes n-1 arrays of n unit circuits, and the order of the unit circuits in the column direction is from 1 to 2 n-2, and the array of the first column is n The order is 2 n—2 in the array, the n-th array in the second column is the order 2 n—3, the order is lowered sequentially, and the n-th array in the n-th column is the n-th order, The unit circuit of each column of the array receives, as a common input for each column, a first Galois sum of the output of the highest-order unit circuit of the array of the previous column and the corresponding partial product addition value, Of the primitive polynomial and the coefficient of the primitive polynomial commonly input to the unit circuits of each column, and generates a logical product.
—次数位置の出力との第 2のガロア和を生成して出力とする機能を有 し、 1列目の単位回路は夫々に前記共通の入力として部分積加算の最上 位である次数 2 n - 1 の値が供給されると共に、前記第 2のガロア和を 生成することなく出力を生成し、 2列目及びそれよりも下位の配列の単 位回路は前記共通の入力として一つ前の配列の最上位の単位回路の出 力とそれに対応する部分積加算の値との前記第 1 のガロア和を受けて 出力を生成し、 n— 1列目の n個の単位回路の出力を補正項加算の出力 とし、当該補正項加算の出力は部分積加算の下位 nビッ 卜とのガロア和 が採られて乗算結果とされるものであることを特徴とする請求の範囲 第 4項記載の半導体集積回路。 —Has the function of generating and outputting a second Galois sum with the output of the order position, and the unit circuits in the first column each have the highest order of partial product addition 2 n − The value of 1 is supplied and the output is generated without generating the second Galois sum, and the unit circuits of the second column and the lower array are used as the common input in the previous array. Receiving the first Galois sum of the output of the uppermost unit circuit and the value of the partial product addition corresponding to the output, generates an output, and corrects the outputs of the n unit circuits in the n-1st column. 5. The semiconductor according to claim 4, wherein an output of the addition is obtained, and an output of the correction term addition is obtained as a multiplication result by taking a Galois sum with lower n bits of the partial product addition. Integrated circuit.
7 . 前記補正項加算部は、 n個の単位回路の配列を n— 1列備え、 列方 向の単位回路の次数は 1 から 2 n— 2とされ、第 1列目の配列は n個目 が次数 2 n— 2とされ、 2列目の配列は n個目が次数 2 n— 3とされ、 順次次数を下げて n― 1列目の配列は n個目が次数 nとされ、
配列の各列の次数 n + 1以上の単位回路は、配列毎に共通の入力とし て対応するビッ 卜位置の部分積加算の値を受け、この共通の入力と各列 の単位回路に入力される nビッ 卜の原始多項式の係数をデコ— ドした 信号とを受けて積を生成すると共に、前列の同一次数位置の単位回路か らの出力と前記積との第 1のガロア和を生成して出力する機能を有し、 前記各配列の次数 n + 1以上の単位回路の内、配列の最上位位置の単位 回路の出力は、それに対応する部分積加算の値と共に第 2のガロア和を 生成し、 7. The correction term adder has n-1 arrays of n unit circuits, the order of the unit circuits in the column direction is 1 to 2 n-2, and the array of the first column is n The order is 2 n—2 in the array, the n-th array in the second column is the order 2 n—3, the order is reduced in order, and the n-th array in the n-th column is the n-th order, Unit circuits of order n + 1 or more in each column of the array receive the value of the partial product addition at the corresponding bit position as a common input for each array, and are input to this common input and the unit circuit of each column. A signal obtained by decoding the coefficients of the n-bit primitive polynomial to generate a product, and generate a first Galois sum of the output from the unit circuit at the same order position in the front row and the product. The output of the unit circuit at the highest position of the array among the unit circuits of order n + 1 or more of each array is the second Galois sum together with the corresponding partial product addition value. Generate
前記配列の各列の次数 n以下の単位回路は、共通の入力として前記第 2のガロア和を受け、 この共通の入力と各列の単位回路に入力される原 始多項式の対応される係数とを受けて積を生成すると共に、前列の同一 次数位置の単位回路からの出力と前記積との第 3 のガロア和を生成し て出力とする機能を有し、 A unit circuit of order n or less of each column of the array receives the second Galois sum as a common input, and the common input and a corresponding coefficient of a primitive polynomial input to the unit circuit of each column. And a function of generating a third Galois sum of the output from the unit circuit at the same order position in the front row and the product, and generating an output,
1 列目の単位回路は次数 n + 1 以上と次数 n以下に共通の入力とし て部分積加算の最上位次数 2 n - 1 の値が入力されて出力を生成し、 2 列目以下の単位回路では次数 n + 1 以上に共通の入力は対応する部分 積加算の値とされ、同じく 2列目以下の単位回路では次数 n以下に共通 の入力は対応する前記第 2のガロア和の値とされ、 The unit circuit in the first column receives the value of the highest order 2 n-1 of the partial product addition as a common input for the order n + 1 or more and the order n or less and generates an output. In the circuit, the input common to the order n + 1 or more is the value of the corresponding partial product addition, and the input common to the order n or less in the unit circuit in the second column and below is the value of the corresponding second Galois sum And
n - 1 列目の n個の単位回路の出力が補正項加算の出力とされ、当該 補正項加算の出力は部分積加算の下位 nビッ 卜とのガロア和が採られ て乗算結果とされるものであることを特徴とする請求の範囲第 4項記 載の半導体集積回路。 The output of the n unit circuits in the n-1st column is the output of the correction term addition, and the output of the correction term addition is the result of multiplication by taking the Galois sum with the lower n bits of the partial product addition 5. The semiconductor integrated circuit according to claim 4, wherein:
8 . 前記補正項加算部は、 限定した複数の原始多項式を扱う場合に、複 数の原始多項式で共通に係数をゼロとする次数に関するハー ドウエア が省略されて成るものであることを特徴とする請求の範囲第 4項記載 の半導体集積回路。
8. The correction term adding unit is characterized in that, when handling a limited plurality of primitive polynomials, hardware relating to an order having a coefficient commonly set to zero in a plurality of primitive polynomials is omitted. The semiconductor integrated circuit according to claim 4.
9 . 前記部分積加算部は、乗数の隣接する 2ビッ 卜のガロア和を n— 1 ビッ 卜生成し、さらに被乗数の連続する 2ビッ 卜毎をデコ一ドして 2ビ ヅ 卜毎に 4つの出力を生成し、部分積の列数を 1 / 2とし、部分積の各 列の各ビッ 卜位置の入力として隣接する乗数のビッ 卜値、乗数の隣接す る 2ビッ 卜のガロア和、及びゼロの 4つの入力を有し、上記デコー ドさ れた 4つの出力により入力を選択し、選択された入力と前列の部分積と のガロア和を出力として後列に出力することを特徴とする請求の範囲 第 4項記載の半導体集積回路。 9. The partial product adder generates n−1 bits of the Galois sum of adjacent two bits of the multiplier, and further decodes every two consecutive bits of the multiplicand to obtain 4 bits for each two bits. , The number of columns of the partial product is set to 1/2, the bit values of adjacent multipliers, the Galois sum of adjacent two bits of the multipliers as inputs for each bit position of each column of the partial product, And zero, and the input is selected based on the four decoded outputs, and the Galois sum of the selected input and the partial product of the preceding column is output to the succeeding column as an output. A semiconductor integrated circuit according to claim 4.
1 0 . ガロア体 G F ( 2 n )の元と元との間のガロア乗算に用いられるガ ロア乗算器と、前記ガロア乗算器の原始多項式を設定可能にする設定手 段とを含み、 10. A Galois multiplier used for Galois multiplication between elements of the Galois field GF (2 n ), and a setting means for setting a primitive polynomial of the Galois multiplier,
前記ガロア乗算器は、乗数とされるガロア体 G F ( 2 n )の元の係数と、 被乗数とされるガロア体 G F ( 2 n )の元の係数と、 原始多項式の係数と を入力し、ガロア乗算結果を得るための前記係数の演算を、複数の異な る原始多項式に対して同一ハー ドウエアで行い、前記原始多項式の係数 は前記設定手段から与えられるものであることを特徴とするデータ処 システム。 The Galois multiplier inputs the original coefficients of the Galois field GF that is a multiplier (2 n), and the original coefficients of the Galois field GF (2 n) which is the multiplicand, and a coefficient of a primitive polynomial, the Galois A data processing system for calculating the coefficient for obtaining a multiplication result for a plurality of different primitive polynomials with the same hardware, and wherein the coefficient of the primitive polynomial is given from the setting means; .
1 1 . 前記設定手段は、 設定すべき原始多項式を、選択スィッチの操作 状態に従って決定するものであることを特徴とする請求の範囲第 1 0 項記載のデータ処理システム。 11. The data processing system according to claim 10, wherein said setting means determines a primitive polynomial to be set in accordance with an operation state of a selection switch.
1 2 . 情報記録媒体の種類を認識する認識手段と、複数種類の情報記録 媒体をアクセス可能なアクセス手段と、アクセス手段によって前記情報 記録媒体から読み取られた記録情報の誤り訂正に用いられる誤り訂正 回路とを含むデータ処理システムであって、 1 2. Recognition means for recognizing the type of information recording medium, access means capable of accessing a plurality of types of information recording media, and error correction used for error correction of recorded information read from the information recording medium by the access means A data processing system comprising:
前記ガロア乗算器は、 ガロア体 G F ( 2 n )の元と元との間のガロア乗 算に用いられ、 乗数とされるガロア体 G F ( 2 n )の元の係数と、 被乗数
とされるガロア体 G F (2 n )の元の係数と、 原始多項式の係数とを入力 し、ガロア乗算結果を得るための前記係数の演算を、複数の異なる原始 多項式に対して、同一ハードウエアで行い、ガロア乗算器に与えられる 前記原始多項式の係数は前記認識手段による情報記録媒体の種類の認 識結果に従って決定されるものであることを特徴とするデータ処理シ ス丁厶。 The Galois multiplier is used for Galois multiplication between the original and the original Galois field GF (2 n), and the original coefficients of the Galois field GF (2 n) which is the multiplier, multiplicand The original coefficient of the Galois field GF (2 n ) and the coefficient of the primitive polynomial are input, and the calculation of the coefficient for obtaining the Galois multiplication result is performed on the same hardware for a plurality of different primitive polynomials. Wherein the coefficient of the primitive polynomial given to the Galois multiplier is determined according to the result of recognition of the type of information recording medium by the recognition means.
1 3 . フェッチした命令を解読して制御信号を生成する制御手段と、前 記制御信号によって制御される演算手段と、前記演算手段を外部とイン タフエースさせるインタフェース手段とを有するデータ処理システム であって、 13. A data processing system comprising: control means for decoding a fetched instruction to generate a control signal; arithmetic means controlled by the control signal; and interface means for interfacing the arithmetic means with the outside. hand,
前記演算手段は、 ガロア体 G F ( 2 n )の元と元との間のガロア乗算に 用いられるガロア乗算器を含み、 The arithmetic means includes a Galois multiplier used for Galois multiplication between elements of a Galois field GF (2 n ),
前記ガロア乗算器は、乗数とされるガロア体 G F ( 2 n )の元の係数と、 被乗数とされるガロア体 G F ( 2 n )の元の係数と、 原始多項式の係数と を入力し、 ガロア乗算結果を得るための前記係数の演算を、複数の異な る原始多項式に対して、同一ハー ドウェアで行い、ガロア乗算器に与え られる前記原始多項式の係数は前記制御手段の制御によって決定され るものであることを特徴とするデータ処理システム。 The Galois multiplier inputs the original coefficients of the Galois field GF that is a multiplier (2 n), and the original coefficients of the Galois field GF (2 n) which is the multiplicand, and a coefficient of a primitive polynomial, the Galois The operation of the coefficient for obtaining the multiplication result is performed on a plurality of different primitive polynomials by the same hardware, and the coefficient of the primitive polynomial given to the Galois multiplier is determined by the control of the control means. A data processing system, characterized in that:
1 4 .単一の半導体基板に形成されたマイクロプロセッサであることを 特徴とする請求の範囲第 1 3項記載のデータ処理システム。
14. The data processing system according to claim 13, wherein the microprocessor is a microprocessor formed on a single semiconductor substrate.
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KR20140034677A (en) * | 2012-09-12 | 2014-03-20 | 삼성전자주식회사 | Galois field calculating circuit and memory device |
KR20140034678A (en) * | 2012-09-12 | 2014-03-20 | 삼성전자주식회사 | Error check and correction circuit and semiconductor memory |
KR102027949B1 (en) | 2012-09-12 | 2019-10-02 | 삼성전자주식회사 | Error check and correction circuit and semiconductor memory |
KR102064857B1 (en) | 2012-09-12 | 2020-02-11 | 삼성전자주식회사 | Galois field calculating circuit and memory device |
KR20140039980A (en) * | 2012-09-24 | 2014-04-02 | 삼성전자주식회사 | Error bit search circuit, error check and correction circuit therewith, and memory device therewith |
KR102021560B1 (en) | 2012-09-24 | 2019-09-16 | 삼성전자주식회사 | Error bit search circuit, error check and correction circuit therewith, and memory device therewith |
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