WO1998055965A1

WO1998055965A1 - Apparatus and method for optimizing memory usage while processing graphics images

Info

Publication number: WO1998055965A1
Application number: PCT/US1998/007798
Authority: WO
Inventors: Charles Chungyohl Lee
Original assignee: Oak Technology, Inc.
Priority date: 1997-06-04
Filing date: 1998-04-20
Publication date: 1998-12-10

Abstract

A novel apparatus and method is disclosed to optimize and reduce the amount of memory required for processing of anti-aliased graphics images while preserving the quality of the displayed image. An approximation buffer is used to store the subpixel color information and the memory reduction is achieved by reducing the number of bits used to store subpixel color information. An input scaler apparatus scales the input pixel color value to a range represented by the reduced number of bits used to store subpixel color information. Approximation computation apparatus computes the approximated subpixel color values and writes them to the subpixel storage locations in the approximation buffer. Approximation buffer stores subpixel color values using a reduced number of bits than prior art techniques. Pixel color computation apparatus retrieves subpixel values from the approximation buffer and averages them to determine the pixel color value. Finally, output scaler apparatus reverses the scaling effect introduced by the input scaler apparatus. The computed pixel value is stored in the frame buffer by the graphics chip and then displayed on a CRT display device.

Description

APPARATUS AND METHOD FOR OPTIMIZING MEMORY USAGE WHILE

PROCESSING GRAPHICS IMAGES

INTRODUCTION

Technical Field

The present invention relates to processing of graphical images, and more particularly to a novel apparatus and method for optimizing memory usage during the processing of graphics images.

Background

Computer graphics using 2-D and 3-D imaging is used today in many different areas of industry, business, education, entertainment and home applications. Additionally, many graphics applications also use "anti-aliasing" techniques to improve the quality of displayed images. Anti-aliasing involves the application of techniques to remove "jaggies" or "staircasing" artifacts introduced in an image due to the aliasing phenomenon. Aliasing occurs when discrete signals are used to represent continuous signals Anti-aliasing techniques, such as "supersampling," strive to "smooth out" the discontinuities between the discrete sample values and thus improve the overall quality of the displayed image FIG. 1 depicts a typical computer graphics system 100 for generation and display of 2-D and 3-D graphics images. Computer graphics system 100 includes CPU 102, graphics chip 104, system memory 110 and peripheral and storage devices 112. System bus 114, which is typically a PCI bus, provides the communication interface between CPU 102, graphics chip 104, system memory 110 and peripheral and storage devices 112. Graphics chip 104 is also coupled to local memory 106 which is used for storing image data and to cathode ray tube (CRT) display 108 which is used for displaying the graphics images. Graphics chip 104 accepts commands from CPU 102 over system bus 114 and is responsible for processing the digital images to be displayed on CRT 108. Processing of graphics images, for both 2-D and 3-D images, includes performing anti-aliasing and image rendering. Images processed by graphics chip 104 are drawn into a "frame buffer" which may reside either in local memory 106 or in system memory 1 10. Graphics chip 104 then periodically reads the frame buffer, a scanline at a time, and sends the display data to CRT 108 to be displayed on screen. A typical 3-D graphics image is composed of a collection of planar polygons.

Graphics chip 104 draws the 3-D image one polygon at a time and one pixel of the polygon at a time. The images are drawn into the frame buffer before being displayed on CRT 108. FIG. 2 depicts a section of the frame buffer for a typical 3-D graphics image composed of a collection of planar polygons 114a,b. As shown in FIG. 2, the frame buffer stores information for each pixel 116-1, 116-2, . . . 116-n to be displayed on CRT 108, where "n" represents the total number of pixels to be displayed. For example, for a standard 320x240 CRT screen, the frame buffer stores information for each of the 320x240 pixels.

For each pixel, graphics chip 104 determines the correct color information associated with that pixel. The color information includes information corresponding to the red (R), green (G) and blue (B) components of the pixel color. In general, a specified number of bits are allocated to store information for each of the color components for the pixel. For example, the RGB888 format uses 8 bits to store color information for each of the red (R), green (G) and blue (B) components for a given pixel. The frame buffer is thus basically an array of memory elements storing color information for each pixel that is to be displayed on the screen. The amount of memory required for the frame buffer is determined by the resolution of the display device and the format used for storing pixel color information. For example, for a screen resolution of 320x240 pixels, and using the RGB888 format, the frame buffer requires 1,843,200 bits of memory (320 * 240 * 3 * 8). As stated earlier, graphics chip 104 is also responsible for performing anti-aliasing on the digital image. The "supersampling" method is a commonly used technique for performing anti-aliasing. For purposes of anti-aliasing, each pixel is further subdivided into "N" subpixels, where "N" is a number greater than one. It is common for each pixel to be subdivided into 16 subpixels (117-1, 117-2, . . ., 117-16) as shown in FIG. 3. For each polygon to be drawn, RGB color information is computed for each subpixel and written to a "subpixel color buffer." FIG. 4 depicts a prior art computer graphics system for generation and display of anti-aliased images in which frame buffer 122 and subpixel color buffer 120 are stored in local memory 106 coupled to graphics chip 104. In alternate embodiments subpixel color buffer 120 and frame buffer 122 may also be stored in system memory 1 10. Graphics chip 104 computes the RGB color information for each subpixel and writes the subpixel color information into subpixel color buffer 120. FIG. 5 depicts a portion of subpixel color buffer 120 with two polygons 114a and 114b drawn into subpixel color buffer 120 where each pixel is subdivided into 16 subpixels. Thus, if the RGB888 format is used, subpixel color buffer 120 stores a 24-bit (3 * 8) color value for each subpixel.

Typically, the same RGB888 value is written into all of the subpixels storage locations corresponding to a pixel that is contained within a polygon. If only a portion of the pixel is contained within a polygon, for example pixel 124 in FIG. 5, then only those subpixels contained in the polygon are given the RGB 888 value for the polygon pixel color. Thus, in FIG. 5, pixel 124 will have some subpixels storing RGB888 values from polygon 114a, while the other subpixels will store RGB888 values from polygon 114b. After all the polygons of a 3-D image have been drawn into subpixel color buffer

120, graphics chip 104 then averages all of the subpixel color values for a pixel to compute a single pixel color value to be stored in frame buffer 122. This averaged pixel value stored in frame buffer 122 then gets displayed on CRT display device 108. The reason for using subpixel color buffer 120 is that the averaging performed by graphics chip 104 for determining the color for a single pixel results in anti-aliasing, which improves the quality of the displayed image. Since subpixel color buffer 120 stores subpixel information for each subpixel, it requires extensive memory storage resources. For example, for a computer graphics system with screen resolution 320x240 pixels and which subdivides a pixel into 16 subpixels and uses the RGB888 format, the total number of memory bits required for subpixel color buffer 120 is:

= (Number of pixels per screen) * (Number of memory bits required for each pixel) = (Number of pixels per screen) *

[(RGB color bits per subpixel) * (Number of subpixels per pixel)] = (Number of pixels per screen) *

[(Red color bits + green color bits + blue color bits) * (Number of subpixels per pixel)] = (340 * 240) * [(8 + 8 + 8) * 16] = (340 * 240) * (384) = 29, 491,200 memory bits

As can be seen, this is a substantial amount of memory. Thus, a major disadvantage of prior art graphics systems for processing and displaying anti-aliased images is that a substantial amount of memory is required for processing of 2-D or 3-D graphical images. The increased memory requirement directly translates to increased costs of the graphics systems. Increased memory requirements also inhibit efforts to improve the quality of the graphics by using a display device with greater resolution or by increasing the number of subpixels per pixel since the aforementioned techniques further increase the amount of memory required. It would be desirable to provide a graphics system architecture and method which enables processing of anti-aliased images using reduced amounts of memory without affecting the quality of the displayed image.

SUMMARY

In view of the foregoing it is an objective of the present invention to perform 2-D and 3-D graphics processing using less memory than prior art graphics systems. It is also an objective of the present invention to preserve the quality of the 2-D or 3-D anti-aliased graphics images while performing processing using reduced memory resources. It is a further objective of this invention to minimize the occurrence of artifacts in the displayed anti-aliased graphics images.

The present invention achieves the above goals and objectives by providing a novel apparatus and method which reduces the amount of memory required for processing and displaying anti-aliased images. Memory savings are achieved by using a reduced number of bits to store subpixel information related to the anti-aliased image.

In the preferred embodiment of the present invention, a graphics chip is coupled to an input sealer apparatus, an approximation computation apparatus, an approximation buffer, pixel color computation apparatus and an output sealer apparatus. The input sealer apparatus scales the input pixel color value to a range represented by the reduced number of bits used to store subpixel information. The approximation computation apparatus computes the approximated subpixel color values and writes them to the subpixel storage locations in the approximation buffer. The subpixel color values are represented using a reduced number of bits than prior art techniques. The pixel color computation apparatus retrieves subpixel values from the approximation buffer and averages them to determine the pixel color value. Finally, the output sealer apparatus reverses the scaling effect introduced by the input sealer apparatus. The computed pixel value is stored in the frame buffer by the graphics chip and then displayed on a CRT display device.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional features of the invention will be readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which:

FIG. 1 is a block diagram depicting a typical computer graphics system for generating and displaying anti-aliased digital images.

FIG. 2 illustrates a section of the frame buffer for a 3-D image comprising of planar polygons. FIG. 3 depicts an enlarged view of a pixel subdivided into sixteen subpixels for purposes of anti-aliasing.

FIG. 4 is a block diagram depicting a prior art graphics system for processing anti- aliased images. FIG. 5 depicts a section of the subpixel color buffer for a 3-D image comprising of planar polygons in which each pixel is subdivided into sixteen subpixels.

FIG. 6 is a block diagram depicting an embodiment of the present invention for processing and displaying anti-aliased graphics images.

FIG. 7 depicts a flow chart showing the steps involved in processing of 3-D anti- aliased images in accordance with the teachings of the present invention.

FIG. 8 depicts an enlarged view of a pixel, comprising of sixteen subpixels, which is owned by two different polygons.

FIG. 9 depicts an enlarged view of a pixel showing the pattern of subpixels whose increment flag bit is set. FIG. 10 depicts an enlarged view of a pixel showing the pattern of subpixels whose increment flag bit is set using subpixel scrambling performed by the scrambling logic.

FIG. 11a, lib, and 12 depict an example of pixel-level of scrambling in accordance with the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

In accordance with the teachings of the present invention, a novel apparatus and method is taught which reduces the amount of memory required for processing and displaying anti-aliased images. In particular, the present invention provides a novel apparatus and method for storage of subpixel color information which requires less memory to store the subpixel color information as compared to prior art graphics system architectures.

Since anti-aliasing presents greater benefits for 3-D images as compared to 2-D images, the present invention will be described in context of 3-D graphics processing. However, it should be apparent to those skilled in the art that the present invention applies to processing of both 2-D and 3-D graphics images. Furthermore, for purposes of describing the present invention, it will be assumed that color information for each pixel is received by the graphics chip in the RGB888 format, i.e. 8 bits are used to store information for each color component. It should be apparent to those skilled in the art that other color formats may also be used. Additionally, it will be assumed that for antialiasing purposes each pixel is subdivided into sixteen subpixels. It should be apparent to those skilled in the art that alternate techniques employing more or less number of subpixels per pixel are also encompassed within the scope of the present invention.

FIG. 6 depicts an embodiment of a computer graphics system 130 constructed in accordance with the teachings of the present invention. As shown in FIG. 6, computer graphics system 130 comprises CPU 132, graphics chip 134, CRT display device 136, system memory 133, local memory 140 comprising of approximation buffer 142 (which replaces the subpixel color buffer of prior art systems) for storing subpixel information and frame buffer 144 for storing pixel information, input sealer apparatus 146, approximation computation apparatus 148 comprising of scrambling logic 150, pixel color computation apparatus 152 and output sealer apparatus 154. System bus 138, which is typically a PCI bus, provides the communication interface between CPU 132, graphics chip 134 and system memory 133.

Graphics chip 134 takes commands from CPU 102 over system bus 138 and along with input sealer apparatus 146, approximation computation apparatus 148, approximation buffer 142, frame buffer 144, pixel color computation apparatus 152 and output sealer apparatus 154, is responsible for processing and displaying 3-D anti-aliased images on CRT 136. Although in the embodiment shown in FIG. 6, approximation buffer 142 and frame buffer 144 reside in local memory 140, in alternate embodiments they may reside in system memory 133. Furthermore, in alternate embodiments local memory 140 may be integrated with graphics chip 134. The processed 3-D images are drawn into frame buffer 144. Graphics chip 134 then periodically reads frame buffer 144, a scanline at a time, and sends the display data to CRT 136 to be displayed.

The present invention reduces the amount of memory required for 3-D anti-aliased graphics by storing subpixel information using a reduced number of bits than prior art techniques. Thus, rather than storing subpixel information in the standard RGB888 format, the present invention uses less than eight bits to store color information for each of the color components of the subpixel. In general, the number of bits required to store subpixel color information is given by the following equation: P = M - (log₂(N)) where,

P = number of bits required to store subpixel color information, M = number of bits used to store pixel color information, N = number of subpixels per pixel. The present invention requires Thus, forN = 16, and M = 8, the number of bits required to store color information for each color component of the subpixel is: P = 8 - (log-base-2(16))

P = 8 - 4

P = 4 bits Thus, only four bits are required to store the subpixel color component information as compared to 8-bits in prior art graphics systems. The subpixel information is thus stored in approximation buffer 142 in RGB444 instead of RGB888 format, i.e. only four bits instead of eight bits are used to store color information for each subpixel color component. Flowchart 160 depicted in FIG. 7 describes the steps involved in accordance with the teachings of the present invention. Graphics chip 134 receives pixel color information in RGB888 format. At step 162, input sealer apparatus 146 scales the input pixel RGB888 value into a range suitable for storage as RGB444 in approximation buffer 142. At step 164, approximation computation apparatus 148 approximates the scaled RGB888 pixel color received from input scaling apparatus 146 to a subpixel color for each subpixel in RGB444 format. Additionally, rather than storing the same color component value into each of the subpixel locations, different color component values are stored in the subpixel locations in approximation buffer 142. At step 166, approximation computation apparatus 148 writes the subpixel information into approximation buffer 142. At step 168, pixel color computation apparatus 152 retrieves the subpixel information stored in approximation buffer 142. Pixel color computation apparatus 152 averages the subpixel colors in RGB444 format to determine the pixel color in RGB888 format. The pixel color value is then forwarded to output sealer apparatus 154. At step 170, output sealer apparatus 154 reverses the scaling effect introduced by input sealer apparatus 146. The resultant output RGB888 pixel color value is written to frame buffer 144 and then displayed on CRT 136. Input Sealer Apparatus 146

Input sealer apparatus 146 receives pixel information in RGB888 format and scales the input information to a value which falls within the range of values represented by the number of bits used to store the subpixel information. Scaling is performed by multiplying the input pixel value with a "input scaling factor." The numerator of the input scaling factor denotes the maximum value that can be represented by the number of bits used to store subpixel color component information in approximation buffer 142, while the denominator denotes the maximum value that is representable by the number of bits used to store the pixel color component information. Thus, if the input pixel color value is in RGB888 format and RGB444 format is used to store the subpixel color information, input sealer apparatus 146 scales the RGB888 pixel value to range representable by RGB444 format The maximum representable value for an 8-bit number is OxFF (hexadecimal format) or 255 (decimal format). Thus, the range of each color component represented in RGB888 format is 0 to 255. The maximum representable value for a 4-bit number is OxF (hexadecimal format) or 15 (decimal format). Since each pixel is subdivided into sixteen subpixels, the maximum value that can be represented by approximation buffer color storage is:

= (Maximum value represented by 4 bits) * (Number of subpixels per pixel) = 15 * 16 = 240 (OxFO in hexadecimal format)

Thus, the range of each color component represented in RGB444 format is 0 to 240. Since the input color range in RGB888 format is 0 to 255, the input scaling factor is (240/255). Input sealer apparatus 146 thus multiplies each input pixel color component by the input scaling factor (240/255). For example, the scaling down operation for the BLUE (B) color component of the input pixel having a value of 0x56 is as follows:

= (8 bit input pixel color component value) * (Input scaling factor) = 0x56 * (240/255) = 86 * (240/255) = 81 (rounded) (decimal format)

= 0x51 (hexadecimal format) The 0x51 blue pixel color component value is then forwarded to approximation computation apparatus 148.

Approximation Computation Apparatus 148 Approximation computation apparatus 148 receives a scaled input pixel color component value from input sealer apparatus 146. Approximation computation apparatus 148 uses the scaled input pixel color component value to generate subpixel color component values to be stored in the subpixel color storage locations in approximation buffer 142. In prior art techniques, the color component values for each of the subpixels are the same as the color component value of pixel. For example, if the blue pixel color component had a value of 0x56, that same value would be written into all of the subpixel locations for that particular color component However, in accordance with the teachings of the present invention, approximation computation apparatus 148 computes different color component values for the subpixel color components. Approximation computation apparatus 148 computes these values in a manner such that the average of all the subpixel values approximates the desired final color, while using fewer bits of storage in approximation buffer 142.

Approximation computation apparatus 148 computes these values by dividing each pixel color component value into a most significant bits (MSBs) portion and a least significant bits (LSBs) portion. The MSB portion is the "base value" and the MSB portion incremented by one is the "incremented value." Approximation computation apparatus 148 then computes the "increment flag" bits for each of the subpixels based on the value of the LSB portion. The "increment flag" is either SET or CLEAR. The total number of subpixels having a SET "increment flag" equals the value of the LSB portion. If the "increment flag" for a particular subpixel is SET, then the "incremented value" of the color component is assigned to that subpixel and stored in approximation buffer 142. If the "increment flag" for a particular subpixel is CLEAR, then the "base value" is assigned to the subpixel and stored in approximation buffer 148.

For example, assume that the input pixel has a 8-bit blue color component value of 0x17. Then, assuming that there are sixteen subpixels per pixel, the blue color component values for each subpixel are computed as follows: Pixel blue component value = 0x17 (8-bit value) MSB portion = Oxl (4-bit value)

Thus, Base Value = 0x1; and

Incremented Value = 0x1 + 1 = 0x2 LSB portion = 0x7 (4-bit value) Thus, exactly 7 of the 16 subpixels will have their "increment flags" SET, while the "increment flag" for the other 9 subpixels will be CLEAR. For each SET increment flag, the base value of 0x1 (4 bit value) will be assigned to that subpixel. For each CLEAR increment flag, the incremented value of 0x2 (4 bit value) will be assigned to that subpixel. The method can thus stores subpixel information in RGB444 format rather than RGB888 format.

The above described method assures that when pixel color computation apparatus

152 reads the subpixel color values from approximation buffer 148 and averages them to determine the pixel color component value, the actual correct pixel color is obtained. For example, in the above example, the initial value of 0x17 is retrieved by pixel color computation apparatus 152 by performing the following calculation:

Pixel component value = Sum of all the subpixel values

= (0x2 * 7) + (0x1 * 9) = 0x17

= Correct value of the pixel color component As can be seen, there is no loss of information even though the RGB888 format pixel color has been stored in RGB444 format subpixel color. Thus, the present invention reduces the amount of memory required for subpixel information storage while processing 3-D anti- aliased images without degradation of image quality.

The above method employed by approximation computation apparatus 148 produces no artifacts for pixels displayed on the screen which are wholly owned by a single non-transparent polygon, for example, pixel 126 in FIG. 5 which is entirely owned by polygon 114-a. However, if a pixel is owned by multiple polygons, for example, pixel 124 which is owned by polygon 114a and 114b, or if the polygon is a partially transparent polygon, the approximation method performed by approximation computation apparatus 148 may introduce artifacts in the displayed image. Scrambling logic 150 which is part of approximation computation apparatus 148 minimizes the visual discrepancies caused by such artifacts. Scrambling logic 150 performs "subpixel scrambling" to reduce errors introduced due to a pixel being owned by multiple polygons and performs "chain scrambling" to reduce the errors where the pixel is part of a partially transparent polygon.

Pixel owned by multiple polygons — "Subpixel scrambling" FIG. 8 depicts an enlarged view of pixel 124 of FIG. 5. As shown in FIG. 8, pixel

124 is owned by polygon 114a and 114b with the six shaded subpixels belonging to polygon 114a and the other ten non-shaded subpixels belonging to polygon 114b. Since only six pixels are owned by polygon 114a, when polygon 114a is drawn by the graphics chip hardware, only those six subpixels are touched by the drawing hardware. This poses a problem because the approximation method used by approximation computation apparatus 148 relies on the fact that the subpixel information is written to all sixteen subpixels.

FIG. 9 depicts illustrates the pattern of subpixels generated by approximation computation apparatus 148 using the approximation method for a pixel blue color value of 0x17. The shaded subpixels in FIG. 9 represent the subpixels whose increment flag bit is SET. As shown, to store a value of 0x17, the increment flag bit is SET for seven subpixels and CLEAR for the other nine subpixels. The base value of 0x1 is written to each subpixel with the increment flag CLEAR and the incremented value of 0x2 is written to each subpixel whose increment flag bit is SET. From FIG. 9, the pixel color for the six subpixels touched by polygon 114a can be computed as:

Pixel color = (Sum of subpixel values for subpixels owned by polygon 114a)

(Number of subpixels touched by polygon 114a) = ((5 * 0x2) + (1 * 0x1)76 = 0xlD

This color approximation is off from the actual value of 0x17 by six and would introduce an unwanted artifact in the displayed image.

Scrambling logic 150 minimizes the errors introduced by the above situation by storing as close a value to the actual value as possible within the constraint of six subpixels. Scrambling logic 150 accomplishes this by SETTING the increment flag bits in a "scrambled" pattern such that the SET increment flag bits are evenly distributed among the available subpixels. FIG. 10 illustrates the scrambled subpixel pattern for storing a pixel blue color value of 0x17. From FIG. 10, the pixel color for the six subpixels touched by polygon 114a can be computed as:

Pixel color = (Sum of subpixel values for subpixels owned by polygon 114a) (Number of subpixels touched by polygon 114a)

= ((3 * 0x2) + (3 * 0xl)/6

= 0x18

Thus, the final answer is only off by 1. Thus, by performing subpixel scrambling, scrambling logic 150 greatly reduces errors produced when a pixel is owned by multiple polygons.

Pixel belonging to a partially transparent polygon -- "Chain scrambling"

A common technique for drawing transparent polygons is to draw them with subpixel "holes" in the pixels. For example, for a pixel subdivided into sixteen subpixels, the drawing hardware will touch only eight of the sixteen subpixels, thus leaving "holes" in the remaining eight subpixels. Such a polygon when drawn on the screen appears to be 50% transparent, as the objects behind the polygon are seen with 50% color intensity, while the polygon itself is seen with 50% color intensity.

Leaving subpixel "holes" poses a problem for the calculation method used by the approximation computation apparatus 148, because it reduces the number of subpixels available for accurately storing the subpixel color values. In addition to "subpixel scrambling", scrambling logic 150 performs "pixel-level scrambling" to reduce any perceived color errors for transparent polygons. Scrambling logic 150 performs "pixel- level scrambling" by rotating the subpixel colors stored in a group of N pixels on-screen, such that the errors at any particular pixel are "evened out" among the group of N pixels. Consequently, when looking at the group of "N" pixels, the errors tend to cancel each other out. This technique works for either one transparent polygon, or multiple transparent polygons overlapping each other.

For example, takeN=16 (N=32,64,8 or some other convenient number could have been chosen instead). Also, say the polygon is 25% transparent. Then, the following scenario can occur:

Say we have the pattern of increment flag bits, due to the particular color of the pixel, as shown in Fig 11a. Also, say that for transparency value =25%, the blank spots depicted in Fig l ib denote subpixel "holes" corresponding to this transparency value.

Then, just by the way the SET (opaque) subpixels align with the SET increment flag bits, we effectively write a color of the polygon that has 4 out of 12 subpixels with incremented colors. Note (4/12=0.333). Ideally, we want to draw a color that has 7 out of 16 subpixels with incremented colors (7/16=0.438). Thus, for this particular pixel, we have some fractional color inaccuracy.

For such scenarios, locally within one pixel, there can be color errors, but pixel- level scrambling spreads out the errors such that among a group of N pixels, the errors tend to cancel each other out: one way of doing pixel-level scrambling rotates the 16 increment flag bits differently for a group of 16 pixels on-screen, in the following manner, as depicted in Fig 12.

For a group of 16 pixels on-screen, pixel #1 will have rotation=0 (i.e., have the original increment flag bit pattern), pixel #2 will have rotation=l (same pattern as pixel #1 , but rotated once according to the diagram above), pixel #3 will have rotation=2, and so on. Note after rotation=15, one more rotation (i.e., rotation=16) will result in the original pattern (i.e., rotation=16 is same as rotation=0).

Notice, then, that no matter what the original pattern of increment flag bits is, and no matter what the subpixel hole pattern is, all of the increment flag bits eventually get used exactly the same number of times among the 16 pixels on-screen. As such, whatever color error occurs locally at any given pixel tends to get offset by opposite color errors at some other pixel within the group of 16 pixels.

This particular example used N=16, and a simple rotation pattern for the "pixel- level scrambling". However, it should be pointed out that other values of N and other scrambling patterns are possible using the same methodology.

As described above, the present invention reduces the amount of memory required for the subpixel information storage while processing 3-D anti-aliased images with minimal degradation of image quality. Furthermore, scrambling logic 150 minimizes the occurrence of artifacts in the displayed 3-D anti-aliased graphics image.

Approximation Buffer 142 Approximation buffer 142 replaces the subpixel color buffer of prior art graphics systems. Subpixel color information is stored in approximation buffer 142 using less memory bits than prior art techniques. Consequently, approximation buffer requires significantly smaller memory than a traditional subpixel color buffer. Although, the embodiment of the present invention depicted in FIG. 6 shows approximation buffer 142 residing in local memory 140, in alternate embodiments approximation buffer 142 may also reside in system memory 133.

Pixel Color Computation Apparatus 152 Pixel color computation apparatus 152 retrieves subpixel information stored in approximation buffer 142 and averages the subpixel values to compute a pixel color component value. For example, for a pixel value of 0x17 stored as 0x1 in nine subpixel locations and 0x2 in seven subpixel locations, pixel color computation apparatus 152 computes the pixel color component value as follows: Pixel component value = Sum of all the subpixel values

= (0x2 * 7) + (0xl * 9) = 0x17 The computed pixel value is then forwarded to output sealer apparatus 154 to undo the scaling effects introduced by input sealer apparatus 146.

Output Sealer Apparatus 154

Output sealer apparatus 154 reverses the scaling effects introduced by input sealer apparatus 146. In essence, output sealer apparatus 154 scales the pixel value from the range represented by the number of bits used to store subpixel color information to the range represented by the number of bits used to store pixel color information. This is performed by multiplying the pixel value with an "output scaling factor." The output scaling factor is the inverse of the input scaling factor computed by input sealer apparatus 146. For example, if the pixel color is stored in RGB888 format and the subpixel information is stored in RGB444 format, the output scaling factor is (255/240), where the numerator denotes the maximum value that can be represented by the number of bits used to store pixel color component information and the denominator denotes the maximum value that is representable by the number of bits used to store the subpixel color component information. The product of the multiplication represents the pixel value in RGB888 format and is stored in frame buffer 144. Graphics chip 134 then periodically reads frame buffer 144, a scanline at a time, and displays the pixel on CRT display 136.

Alternate Embodiments

The present invention applies to processing of 2-D and 3-D graphics images. The present invention has been described above with reference to an architecture in which the pixel color is represented in RGB888 format, the subpixel information is stored in RGB444 format and each pixel is subdivided into sixteen subpixels. However, the scope of the present invention is not limited to the above architecture. It should be obvious to those skilled in the art that the present invention can work with a wide variety of architectures using different color format schemes and having varying number of subpixels per pixel. In general, the higher the number of subpixels per pixel, the higher the relative benefit of the present invention in reducing the required storage. It should also be obvious to those skilled in the art that various components of the present invention, namely input sealer apparatus 146, approximation computation apparatus 148, pixel color computation apparatus 152 and output sealer apparatus 154 may be implemented either in hardware or as software modules residing in system memory 133 and executed by CPU 132 or by graphics chip 134. In alternate embodiments hardware implementations of the components of the present invention may be integrated with the graphics chip hardware. Additionally, even though in the previous description of the present invention approximation buffer 142 and frame buffer 144 resided in local memory 140, in alternate embodiments approximation buffer 142 and frame buffer 144 may reside in system memory 133 accessed via bus 138.

Advantages of the present invention

The present invention reduces the amount of memory required for processing 2-D or 3-D anti-aliased images. The present invention achieves this by reducing the number of bits required for the storage of subpixel color information. In general, the memory required to store subpixel color information can be represented by the following equation: Required subpixel storage = (Size of screen) * (Number of subpixels per pixel)

* (Number of bits required RGB subpixel storage) Using the above equation, for a prior art system using RGB888 format, having 16 subpixels per pbcel and displaying the image on a screen of size 320x240, the size of subpixel color buffer memory required to store subpixel information can be computed as follows: Required subpixel storage = (320 * 240) * (16) * (3 * 8)

= 29,491,200 bits of memory (prior art system) In general, the number of bits required to store subpixel color information in accordance with the teachings of the present invention are given by the following equation: P = M - (log₂(N)) where,

P = number of bits required to store subpixel color information, M = number of bits used to store pixel color information, N = number of subpixels per pixel. The present invention requires Thus, for N = 16, and M = 8, the number of bits required to store color information for each color component of the subpixel is: P = 8 - (log-base-2(16))

P = 8 - 4

P = 4 bits

Consequently, the size of the approximation buffer is: = (320 * 240) * 16 * (3 * 4)

= 14,745,600 memory bits (present invention) Thus, the present invention provides memory savings of approximately 50% over prior art techniques. In general, the relative benefit of the present invention in reducing memory storage is directly proportional to the number of subpixels per pixel. This in turn translates to significant cost savings for the graphics system.

The invention now being fully described, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the spirit or scope of the appended claims. All publications and patent applications mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference.

Claims

WHAT IS CLAIMED IS

1. A method for processing digital graphics images, said method comprising the steps of: receiving pixel color information for a pixel, said pixel color information requiring "M" bits of storage; subdividing said pixel into a plurality of subpixels; deriving subpixel color information from said pixel color information for each subpixel of said plurality of subpixels, said subpixel color information using "P" bits of storage, wherein the value of "P" is less than the value of "M"; storing said subpixel color information in an approximation buffer; computing anti-aliased pixel color information from said subpixel color information stored in said approximation buffer for said plurality of subpixels; and storing said anti-aliased pbcel color information into a frame buffer to be displayed on screen.

2. The method of claim 1, wherein said step of deriving said subpixel color information from said pixel color information comprises the steps of: computing a scaled pixel color information value by scaling down said pixel color information from a range representable by said "M" bits to a range representable by said "F' bits; apportioning said scaled pixel color information value into a most significant bits portion and a least significant bits portion; computing a base subpixel color value corresponding to the value of said most significant bits portion; computing an incremented subpixel color value by incrementing said base subpixel color value by one; assigning said incremented subpixel color value to a number of subpixels comprising said plurality of subpixels, said number of subpixels corresponding to the value of said least significant bits portion; and assigning said base subpixel color value to remaining subpixels of said plurality of subpixels.

3. The method of claim 2, wherein said step of computing said scaled pixel color information value by scaling down said pixel color information comprises the steps of: computing an input sealer factor using the following equation: Input scaler = RangeP/RangeM where,

Input scaler = value of said input sealer factor, RangeP = maximum range of values representable by said "P" bits, RangeM = maximum range of values representable by said "M" bits; and multiplying said pbcel color information by said input sealer factor to produce said scaled pixel color information value.

4. The method of claim 2, wherein said step of assigning said incremented subpixel color value to said number of subpbcels comprising said plurality of subpixels is performed in a scrambled manner at a subpixel level.

5. The method of claim 2, wherein said step of assigning said incremented subpixel color value to said number of subpbcels comprising said plurality of subpixels is perfo╧Çned by scrambling said incremented subpixel color value at a pixel-level as well.

6. The method of claim 1, wherein said step of computing said anti-aliased pixel color information from said subpixel color information stored in said approximation buffer for said plurality of subpixels comprises the steps of: reading said subpixel color information for each of said plurality of subpixels from said approximation buffer; computing an approximated pixel color information value by aggregating said subpixel color information for said plurality of subpixels; and computing said anti-aliased pixel color information by scaling up said approximated pixel color information value from a range representable by said "P" bits to a range representable by said "M" bits.

7. The method of claim 6, wherein said step of computing said anti-aliased pixel color information by scaling up said approximated pixel color information value comprises the steps of: computing an output sealer factor using the following equation: Output_scaler = RangeM/RangeP where,

Output_scaler = value of said output sealer factor, RangeM = maximum range of values representable by said "M" bits, RangeP = maximum range of values representable by said "P" bits; and multiplying said approximated pixel color information value by said output sealer factor to produce said anti-aliased pixel color information

8. A image processor for processing pixel color information for a pixel, said pixel color information requiring "M" bits of storage, said image processor comprising: a memory buffer including an approximation buffer and a frame buffer; and a graphics processor coupled to said memory buffer to process said pixel color information, said graphics processor configured to: subdivide said pixel into a plurality of subpixels, said graphics processor configured to store subpixel color information in said approximation buffer for each subpbcel of said plurality of subpixels using "P" bits of storage wherein value of "P" is less than value of "M"; compute anti-aliased pixel color information from said subpixel color information stored in said approximation buffer; and store said anti-aliased pixel color information into said frame buffer.

9. The image processor of claim 8, wherein said graphics processor further comprises of: an input sealer apparatus configured to receive said pixel color information, said input sealer apparatus configured to transform said pixel color information from a range representable by said "M" bits to a scaled pixel color information value falling within a range representable by said "P" bits; an approximation computation apparatus coupled to said input sealer apparatus and to said approximation buffer, said approximation computation apparatus configured to: receive said scaled pixel color information value from said input sealer apparatus; apportion said scaled pixel color information value into a most significant bits portion and a lest significant bits portion; compute a base subpixel color value corresponding to value of said most significant bits portion; compute an incremented subpixel color value corresponding to the value of said most significant bits portion; assign said incremented subpixel color value to a number of subpixels comprising said plurality of subpixels, said number of subpixels corresponding to the value of said least significant bits portion; assign said base subpixel color value to remaining subpixels of said plurality of subpixels; and store said subpixel color information in said approximation buffer; a pixel color computation apparatus coupled to said approximation buffer, said pbcel color computation apparatus configured to read said subpixel color information from said approximation buffer for each of said plurality of subpixels, said pixel color computation apparatus configured to compute an approximated pixel color information value by aggregating said subpbcel color information values for said plurality of subpixels; and an output sealer apparatus coupled to said pixel color computation apparatus, said output sealer apparatus configured to compute said anti-aliased pixel color information by scaling up said approximated pixel color information value from a range representable by said "P" bits to a range representable by said "M" bits.

10. The image processor of claim 9, wherein said input sealer apparatus is further configured to: compute an input sealer factor using equation:

Input_scaler = RangeP RangeM where, Input scaler = value of said input sealer factor, RangeP = maximum range of values representable by said "P" bits, RangeM = maximum range of values representable by said "M" bits; and multiply said pixel color information by said input sealer factor to produce said scaled pbcel color information value.

11. The image processor of claim 9, wherein said output sealer apparatus is further configured to: compute an output sealer factor using the equation: Output scaler = RangeM/RangeP where,

Output_scaler = value of said output sealer factor, RangeM = maximum range of values representable by said "M' bits, RangeP = maximum range of values representable by said "P" bits; and multiply said approximated pixel color information value by said output sealer factor to produce said anti-aliased pixel color information.

12. The image processor of claim 9, wherein said approximation computation apparatus is further configured to assign said incremented subpixel value to said number of subpixels comprising said plurality of subpixels in a scrambled manner.

13. The image processor of claim 9, wherein said approximation computation apparatus is further configured to assign said incremented subpixel value to said number of subpbcels comprising said plurality of subpixels by rotating said incremented subpixel value in a chain of said subpixels.