WO1998026509B1 - Method and apparatus for high-speed data transfer that minimizes conductors - Google Patents
Method and apparatus for high-speed data transfer that minimizes conductorsInfo
- Publication number
- WO1998026509B1 WO1998026509B1 PCT/US1997/021594 US9721594W WO9826509B1 WO 1998026509 B1 WO1998026509 B1 WO 1998026509B1 US 9721594 W US9721594 W US 9721594W WO 9826509 B1 WO9826509 B1 WO 9826509B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- cell
- cell bus
- switching fabric
- conductors
- set forth
- Prior art date
Links
- 239000004020 conductor Substances 0.000 title claims abstract 20
- 239000004744 fabric Substances 0.000 claims abstract 25
- 230000005540 biological transmission Effects 0.000 claims abstract 7
- 238000011144 upstream manufacturing Methods 0.000 claims 1
- 230000003287 optical Effects 0.000 abstract 1
Abstract
A cell bus (270), which reduces the number of conductors required to transfer data in a telecommunications switching fabric, contains a plurality of conductors, Data[X:0], for transmitting information. A cell bus interface (110) generates a cell bus frame that includes a plurality of words 'X' bits in length, of both data and control information that includes, in part, routing information for the data. As a result of encapsulating data and control information into a cell bus frame for transmission on the Data[X:0] conductors, the number of conductors required to transmit data is reduced. An asynchronous transfer mode (ATM) switching fabric (200), which includes a plurality of cell buses configures in a point to point fashion between a cell routing unit (CRU)/ATM filter bank interface unit (AFIU) (220, 240) and a plurality of optical line units (OLUs) is also disclosed.
Claims
1. A switching fabric comprising: at least one switch; a plurality of line units; a cell bus comprising a plurality of conductors that electrically couple a switch to a plurality of line cards in said switching fabric, said cell bus for transmitting a cell of a predetermined size; and said switching fabric comprising a minimum bandwidth requirement that specifies delivery of a predetermined numbers of said cells per unit of time to said line cards via said cell bus, said switching fabric including a plurality of control parameters that control flow of said cells from said switch to said line cards; and cell bus interface for transmitting a cell bus frame on said cell bus, said cell bus frame comprising said cell and said control parameters, such that a maximum size of a cell bus frame permits transmission of said cell and said control parameters on said conductors to meet said minimum bandwidth requirement, whereby encapsulating said control parameters for said switching fabric into said cell bus frame reduces the number of conductors in said switching fabric.
2. The switching fabric as set forth in claim 1 , wherein said cell bus further comprises: a cell clock line for conducting a cell clock that provides timing for said cell bus; and a cell sync line for conducting a cell sync signal that delineates between said cell bus frames.
3. The switching fabric as set forth in claim 1 , wherein said cell bus comprises a point to point bus between said switch and said line cards.
4, The switching fabric as set forth in claim 1 , wherein said cell bus 37 comprises a bus shared among a plurality of cell bus interfaces.
5. The switching fabric as set forth in claim 1 , wherein said control parameter further comprises a check sum to validate said cell bus frame.
6. The switching fabric as set forth in claim 1 , wherein said cell bus interface comprises circuitry for transmitting and receiving data for bi- directional transmission of data on said bus.
7. The switching fabric as set forth in claim 1, wherein said cell comprises an asynchronous transfer mode (ATM) cell of 53 bytes.
8. The switching fabric as set forth in claim 1, wherein said control parameter comprises an idle bit that indicates an active cell bus frame.
9. A method for reducing a number of conductors required on a switching fabric, said method comprising the steps of: generating a cell bus comprising a plurality of conductors that electrically couple a switch to a plurality of line cards in a switching fabric, said cell bus for transmitting a cell of a predetermined size and said switching fabric comprising a minimum bandwidth requirement that specifies delivery of a predetermined numbers of said cells per unit of time to said line cards via said cell bus, said switching fabric including a plurality of control parameters that control flow of said cells from said switch to said line cards; and generating a cell bus frame for transmission on said cell bus, said cell bus frame comprising said cell and said control parameters, such that a maximum size of a cell bus frame permits transmission of said cell and said control parameters on said conductors to meet said minimum bandwidth requirement, whereby encapsulating said control parameters for said switching fabric into said cell bus frame reduces the number of conductors in said switching fabric.
10. A line card for a telecommunications device comprising: a plurality of conductors that electrically couple said line card to a switch in a switching fabric, said conductors for transmitting a cell of a predetermined size; and said switching fabric comprising a minimum bandwidth requirement that specifies delivery of a predetermined number of said cells per unit of time to said line card via said conductors, said switching fabric including a plurality of control parameters that control flow of said cells from said switch to said line card; and a cell bus interface, coupled to said conductors, for transmitting a cell bus frame on said conductors, said cell bus frame comprising said cell and said control parameters, such that a maximum size of a cell bus frame permits transmission of said cell and said control parameters on said conductors to meet said minimum bandwidth requirement, whereby encapsulating said control parameters for said switching fabric into said cell bus frame reduces the number of conductors in said line card.
11. The line card as set forth in claim 10, wherein line card further comprises a cell bus interface for generating said cell bus frame for transmission upstream.
12. The line card as set forth in claim 10, wherein said conductors further comprise: a cell clock line for receiving a cell clock that provides timing for said cell bus frame; and a cell sync line for receiving a cell sync signal that delineates between said cell bus frames.
13. The line card as set forth in claim 10, wherein said control parameter further comprises a check sum to validate said cell bus frame.
14. The line card as set forth in claim 10, wherein said cell comprises an asynchronous transfer mode (ATM) cell of 53 bytes. 39
15. The line card as set forth in claim 10, wherein said control parameter comprises an idle bit that indicates an active cell bus frame.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU78511/98A AU7851198A (en) | 1996-11-27 | 1997-11-26 | Method and apparatus for high-speed data transfer that minimizes conductor |
| CA002273044A CA2273044A1 (en) | 1996-11-27 | 1997-11-26 | Method and apparatus for high-speed data transfer that minimizes conductors |
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US3204596P | 1996-11-27 | 1996-11-27 | |
| US3189896P | 1996-11-27 | 1996-11-27 | |
| US3182896P | 1996-11-27 | 1996-11-27 | |
| US60/031,828 | 1996-11-27 | ||
| US60/032,045 | 1996-11-27 | ||
| US60/031,898 | 1996-11-27 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO1998026509A2 WO1998026509A2 (en) | 1998-06-18 |
| WO1998026509A3 WO1998026509A3 (en) | 1998-11-19 |
| WO1998026509B1 true WO1998026509B1 (en) | 1999-01-14 |
Family
ID=27363967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1997/021594 WO1998026509A2 (en) | 1996-11-27 | 1997-11-26 | Method and apparatus for high-speed data transfer that minimizes conductors |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6091729A (en) |
| AU (1) | AU7851198A (en) |
| CA (1) | CA2273044A1 (en) |
| TW (1) | TW382868B (en) |
| WO (1) | WO1998026509A2 (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6362908B1 (en) * | 1998-12-02 | 2002-03-26 | Marconi Communications, Inc. | Multi-service adaptable optical network unit |
| US6826187B1 (en) * | 1999-05-07 | 2004-11-30 | Cisco Technology, Inc. | Interfacing between a physical layer and a bus |
| US20020071321A1 (en) * | 2000-11-29 | 2002-06-13 | International Business Machines Corporation | System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories |
| US6785734B1 (en) * | 2000-04-10 | 2004-08-31 | International Business Machines Corporation | System and method for processing control information from a general through a data processor when a control processor of a network processor being congested |
| EP1158735A1 (en) * | 2000-05-24 | 2001-11-28 | Motorola, Inc. | TDMA bus interface, system for communicating data, and method |
| US7047196B2 (en) | 2000-06-08 | 2006-05-16 | Agiletv Corporation | System and method of voice recognition near a wireline node of a network supporting cable television and/or video delivery |
| EP1170907B1 (en) * | 2000-07-05 | 2005-09-28 | Roke Manor Research Limited | Improvements in or relating to switching devices |
| US20020040391A1 (en) * | 2000-10-04 | 2002-04-04 | David Chaiken | Server farm formed of systems on a chip |
| US20040213188A1 (en) * | 2001-01-19 | 2004-10-28 | Raze Technologies, Inc. | Backplane architecture for use in wireless and wireline access systems |
| GB0031839D0 (en) | 2000-12-29 | 2001-02-14 | Marconi Comm Ltd | A multi-service digital cross-connect |
| US6963569B1 (en) | 2000-12-29 | 2005-11-08 | Cisco Technology, Inc. | Device for interworking asynchronous transfer mode cells |
| US6839882B2 (en) * | 2001-06-01 | 2005-01-04 | Virtual Silicon Technology, Inc. | Method and apparatus for design of integrated circuits |
| US7464180B1 (en) | 2001-10-16 | 2008-12-09 | Cisco Technology, Inc. | Prioritization and preemption of data frames over a switching fabric |
| US8145787B1 (en) | 2001-10-16 | 2012-03-27 | Cisco Technology, Inc. | Adaptive bandwidth utilization over fabric links |
| US7347866B2 (en) | 2003-03-10 | 2008-03-25 | Boston Scientific Scimed, Inc. | Medical stent and related methods |
| US7408878B2 (en) * | 2003-06-10 | 2008-08-05 | Cisco Technology, Inc. | System packet interface |
| US7668202B2 (en) * | 2003-10-10 | 2010-02-23 | Nokia Corporation | Communications bus having low latency interrupts and control signals, hotpluggability error detection and recovery, bandwidth allocation, network integrity verification, protocol tunneling and discoverability features |
| US9183713B2 (en) | 2011-02-22 | 2015-11-10 | Kelly Research Corp. | Perimeter security system |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5452330A (en) * | 1992-07-06 | 1995-09-19 | Digital Equipment Corporation | Bus-oriented switching system for asynchronous transfer mode |
| AU6172694A (en) * | 1993-02-09 | 1994-08-29 | Dsc Communications Corporation | High-speed packet bus |
| ES2187535T3 (en) * | 1993-09-20 | 2003-06-16 | Transwitch Corp | ASYNCHRON DATA TRANSFER SYSTEM AND ORIGIN TRAFFIC CONTROL. |
| US5453979A (en) * | 1994-01-27 | 1995-09-26 | Dsc Communications Corporation | Method and apparatus for generating route information for asynchronous transfer mode cell processing |
| US5619500A (en) * | 1994-09-01 | 1997-04-08 | Digital Link Corporation | ATM network interface |
| US5631908A (en) * | 1995-03-28 | 1997-05-20 | Digital Equipment Corporation | Method and apparatus for generating and implementing smooth schedules for forwarding data flows across cell-based switches |
| US5729546A (en) * | 1995-06-21 | 1998-03-17 | Cisco Systems, Inc. | Expandable communication cell bus for multiplexing and concentrating communication cell traffic onto high speed lines |
| US5864539A (en) * | 1996-05-06 | 1999-01-26 | Bay Networks, Inc. | Method and apparatus for a rate-based congestion control in a shared memory switch |
| US5926475A (en) * | 1996-09-20 | 1999-07-20 | Cisco Technology, Inc. | Method and apparatus for ensuring ATM cell order in multiple cell transmission lane switching system |
| US6009092A (en) * | 1996-12-24 | 1999-12-28 | International Business Machines Corporation | LAN switch architecture |
-
1997
- 1997-11-26 CA CA002273044A patent/CA2273044A1/en not_active Abandoned
- 1997-11-26 WO PCT/US1997/021594 patent/WO1998026509A2/en active Application Filing
- 1997-11-26 US US08/979,383 patent/US6091729A/en not_active Expired - Fee Related
- 1997-11-26 AU AU78511/98A patent/AU7851198A/en not_active Abandoned
- 1997-11-27 TW TW086117871A patent/TW382868B/en not_active IP Right Cessation
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